1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#if !defined (_soc21_ENUM_HEADER)
24#define _soc21_ENUM_HEADER
25
26#ifndef _DRIVER_BUILD
27#ifndef GL_ZERO
28#define GL__ZERO BLEND_ZERO
29#define GL__ONE BLEND_ONE
30#define GL__SRC_COLOR BLEND_SRC_COLOR
31#define GL__ONE_MINUS_SRC_COLOR BLEND_ONE_MINUS_SRC_COLOR
32#define GL__DST_COLOR BLEND_DST_COLOR
33#define GL__ONE_MINUS_DST_COLOR BLEND_ONE_MINUS_DST_COLOR
34#define GL__SRC_ALPHA BLEND_SRC_ALPHA
35#define GL__ONE_MINUS_SRC_ALPHA BLEND_ONE_MINUS_SRC_ALPHA
36#define GL__DST_ALPHA BLEND_DST_ALPHA
37#define GL__ONE_MINUS_DST_ALPHA BLEND_ONE_MINUS_DST_ALPHA
38#define GL__SRC_ALPHA_SATURATE BLEND_SRC_ALPHA_SATURATE
39#define GL__CONSTANT_COLOR BLEND_CONSTANT_COLOR
40#define GL__ONE_MINUS_CONSTANT_COLOR BLEND_ONE_MINUS_CONSTANT_COLOR
41#define GL__CONSTANT_ALPHA BLEND_CONSTANT_ALPHA
42#define GL__ONE_MINUS_CONSTANT_ALPHA BLEND_ONE_MINUS_CONSTANT_ALPHA
43#endif
44#endif
45
46/*******************************************************
47 * Chip Enums
48 *******************************************************/
49
50/*
51 * DSM_DATA_SEL enum
52 */
53
54typedef enum DSM_DATA_SEL {
55DSM_DATA_SEL_DISABLE = 0x00000000,
56DSM_DATA_SEL_0 = 0x00000001,
57DSM_DATA_SEL_1 = 0x00000002,
58DSM_DATA_SEL_BOTH = 0x00000003,
59} DSM_DATA_SEL;
60
61/*
62 * DSM_ENABLE_ERROR_INJECT enum
63 */
64
65typedef enum DSM_ENABLE_ERROR_INJECT {
66DSM_ENABLE_ERROR_INJECT_FED_IN = 0x00000000,
67DSM_ENABLE_ERROR_INJECT_SINGLE = 0x00000001,
68DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE = 0x00000002,
69DSM_ENABLE_ERROR_INJECT_UNCORRECTABLE_LIMITED = 0x00000003,
70} DSM_ENABLE_ERROR_INJECT;
71
72/*
73 * DSM_SELECT_INJECT_DELAY enum
74 */
75
76typedef enum DSM_SELECT_INJECT_DELAY {
77DSM_SELECT_INJECT_DELAY_NO_DELAY = 0x00000000,
78DSM_SELECT_INJECT_DELAY_DELAY_ERROR = 0x00000001,
79} DSM_SELECT_INJECT_DELAY;
80
81/*
82 * DSM_SINGLE_WRITE enum
83 */
84
85typedef enum DSM_SINGLE_WRITE {
86DSM_SINGLE_WRITE_DIS = 0x00000000,
87DSM_SINGLE_WRITE_EN = 0x00000001,
88} DSM_SINGLE_WRITE;
89
90/*
91 * ENUM_NUM_SIMD_PER_CU enum
92 */
93
94typedef enum ENUM_NUM_SIMD_PER_CU {
95NUM_SIMD_PER_CU = 0x00000004,
96} ENUM_NUM_SIMD_PER_CU;
97
98/*
99 * GATCL1RequestType enum
100 */
101
102typedef enum GATCL1RequestType {
103GATCL1_TYPE_NORMAL = 0x00000000,
104GATCL1_TYPE_SHOOTDOWN = 0x00000001,
105GATCL1_TYPE_BYPASS = 0x00000002,
106} GATCL1RequestType;
107
108/*
109 * GL0V_CACHE_POLICIES enum
110 */
111
112typedef enum GL0V_CACHE_POLICIES {
113GL0V_CACHE_POLICY_MISS_LRU = 0x00000000,
114GL0V_CACHE_POLICY_MISS_EVICT = 0x00000001,
115GL0V_CACHE_POLICY_HIT_LRU = 0x00000002,
116GL0V_CACHE_POLICY_HIT_EVICT = 0x00000003,
117} GL0V_CACHE_POLICIES;
118
119/*
120 * GL1_CACHE_POLICIES enum
121 */
122
123typedef enum GL1_CACHE_POLICIES {
124GL1_CACHE_POLICY_MISS_LRU = 0x00000000,
125GL1_CACHE_POLICY_MISS_EVICT = 0x00000001,
126GL1_CACHE_POLICY_HIT_LRU = 0x00000002,
127GL1_CACHE_POLICY_HIT_EVICT = 0x00000003,
128} GL1_CACHE_POLICIES;
129
130/*
131 * GL1_CACHE_STORE_POLICIES enum
132 */
133
134typedef enum GL1_CACHE_STORE_POLICIES {
135GL1_CACHE_STORE_POLICY_BYPASS = 0x00000000,
136} GL1_CACHE_STORE_POLICIES;
137
138/*
139 * GL2_CACHE_POLICIES enum
140 */
141
142typedef enum GL2_CACHE_POLICIES {
143GL2_CACHE_POLICY_LRU = 0x00000000,
144GL2_CACHE_POLICY_STREAM = 0x00000001,
145GL2_CACHE_POLICY_NOA = 0x00000002,
146GL2_CACHE_POLICY_BYPASS = 0x00000003,
147} GL2_CACHE_POLICIES;
148
149/*
150 * Hdp_SurfaceEndian enum
151 */
152
153typedef enum Hdp_SurfaceEndian {
154HDP_ENDIAN_NONE = 0x00000000,
155HDP_ENDIAN_8IN16 = 0x00000001,
156HDP_ENDIAN_8IN32 = 0x00000002,
157HDP_ENDIAN_8IN64 = 0x00000003,
158} Hdp_SurfaceEndian;
159
160/*
161 * MTYPE enum
162 */
163
164typedef enum MTYPE {
165MTYPE_C_RW_US = 0x00000000,
166MTYPE_RESERVED_1 = 0x00000001,
167MTYPE_C_RO_S = 0x00000002,
168MTYPE_UC = 0x00000003,
169MTYPE_C_RW_S = 0x00000004,
170MTYPE_RESERVED_5 = 0x00000005,
171MTYPE_C_RO_US = 0x00000006,
172MTYPE_RESERVED_7 = 0x00000007,
173} MTYPE;
174
175/*
176 * PERFMON_COUNTER_MODE enum
177 */
178
179typedef enum PERFMON_COUNTER_MODE {
180PERFMON_COUNTER_MODE_ACCUM = 0x00000000,
181PERFMON_COUNTER_MODE_ACTIVE_CYCLES = 0x00000001,
182PERFMON_COUNTER_MODE_MAX = 0x00000002,
183PERFMON_COUNTER_MODE_DIRTY = 0x00000003,
184PERFMON_COUNTER_MODE_SAMPLE = 0x00000004,
185PERFMON_COUNTER_MODE_CYCLES_SINCE_FIRST_EVENT = 0x00000005,
186PERFMON_COUNTER_MODE_CYCLES_SINCE_LAST_EVENT = 0x00000006,
187PERFMON_COUNTER_MODE_CYCLES_GE_HI = 0x00000007,
188PERFMON_COUNTER_MODE_CYCLES_EQ_HI = 0x00000008,
189PERFMON_COUNTER_MODE_INACTIVE_CYCLES = 0x00000009,
190PERFMON_COUNTER_MODE_RESERVED = 0x0000000f,
191} PERFMON_COUNTER_MODE;
192
193/*
194 * PERFMON_SPM_MODE enum
195 */
196
197typedef enum PERFMON_SPM_MODE {
198PERFMON_SPM_MODE_OFF = 0x00000000,
199PERFMON_SPM_MODE_16BIT_CLAMP = 0x00000001,
200PERFMON_SPM_MODE_16BIT_NO_CLAMP = 0x00000002,
201PERFMON_SPM_MODE_32BIT_CLAMP = 0x00000003,
202PERFMON_SPM_MODE_32BIT_NO_CLAMP = 0x00000004,
203PERFMON_SPM_MODE_RESERVED_5 = 0x00000005,
204PERFMON_SPM_MODE_RESERVED_6 = 0x00000006,
205PERFMON_SPM_MODE_RESERVED_7 = 0x00000007,
206PERFMON_SPM_MODE_TEST_MODE_0 = 0x00000008,
207PERFMON_SPM_MODE_TEST_MODE_1 = 0x00000009,
208PERFMON_SPM_MODE_TEST_MODE_2 = 0x0000000a,
209} PERFMON_SPM_MODE;
210
211/*
212 * RMI_CID enum
213 */
214
215typedef enum RMI_CID {
216RMI_CID_CC = 0x00000000,
217RMI_CID_FC = 0x00000001,
218RMI_CID_CM = 0x00000002,
219RMI_CID_DC = 0x00000003,
220RMI_CID_Z = 0x00000004,
221RMI_CID_S = 0x00000005,
222RMI_CID_TILE = 0x00000006,
223RMI_CID_ZPCPSD = 0x00000007,
224} RMI_CID;
225
226/*
227 * ReadPolicy enum
228 */
229
230typedef enum ReadPolicy {
231CACHE_LRU_RD = 0x00000000,
232CACHE_STREAM_RD = 0x00000001,
233CACHE_NOA = 0x00000002,
234RESERVED_RDPOLICY = 0x00000003,
235} ReadPolicy;
236
237/*
238 * SDMA_PERFMON_SEL enum
239 */
240
241typedef enum SDMA_PERFMON_SEL {
242SDMA_PERFMON_SEL_CYCLE = 0x00000000,
243SDMA_PERFMON_SEL_IDLE = 0x00000001,
244SDMA_PERFMON_SEL_REG_IDLE = 0x00000002,
245SDMA_PERFMON_SEL_RB_EMPTY = 0x00000003,
246SDMA_PERFMON_SEL_RB_FULL = 0x00000004,
247SDMA_PERFMON_SEL_RB_WPTR_WRAP = 0x00000005,
248SDMA_PERFMON_SEL_RB_RPTR_WRAP = 0x00000006,
249SDMA_PERFMON_SEL_RB_WPTR_POLL_READ = 0x00000007,
250SDMA_PERFMON_SEL_RB_RPTR_WB = 0x00000008,
251SDMA_PERFMON_SEL_RB_CMD_IDLE = 0x00000009,
252SDMA_PERFMON_SEL_RB_CMD_FULL = 0x0000000a,
253SDMA_PERFMON_SEL_IB_CMD_IDLE = 0x0000000b,
254SDMA_PERFMON_SEL_IB_CMD_FULL = 0x0000000c,
255SDMA_PERFMON_SEL_EX_IDLE = 0x0000000d,
256SDMA_PERFMON_SEL_SRBM_REG_SEND = 0x0000000e,
257SDMA_PERFMON_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f,
258SDMA_PERFMON_SEL_WR_BA_RTR = 0x00000010,
259SDMA_PERFMON_SEL_MC_WR_IDLE = 0x00000011,
260SDMA_PERFMON_SEL_MC_WR_COUNT = 0x00000012,
261SDMA_PERFMON_SEL_RD_BA_RTR = 0x00000013,
262SDMA_PERFMON_SEL_MC_RD_IDLE = 0x00000014,
263SDMA_PERFMON_SEL_MC_RD_COUNT = 0x00000015,
264SDMA_PERFMON_SEL_MC_RD_RET_STALL = 0x00000016,
265SDMA_PERFMON_SEL_MC_RD_NO_POLL_IDLE = 0x00000017,
266SDMA_PERFMON_SEL_SEM_IDLE = 0x0000001a,
267SDMA_PERFMON_SEL_SEM_REQ_STALL = 0x0000001b,
268SDMA_PERFMON_SEL_SEM_REQ_COUNT = 0x0000001c,
269SDMA_PERFMON_SEL_SEM_RESP_INCOMPLETE = 0x0000001d,
270SDMA_PERFMON_SEL_SEM_RESP_FAIL = 0x0000001e,
271SDMA_PERFMON_SEL_SEM_RESP_PASS = 0x0000001f,
272SDMA_PERFMON_SEL_INT_IDLE = 0x00000020,
273SDMA_PERFMON_SEL_INT_REQ_STALL = 0x00000021,
274SDMA_PERFMON_SEL_INT_REQ_COUNT = 0x00000022,
275SDMA_PERFMON_SEL_INT_RESP_ACCEPTED = 0x00000023,
276SDMA_PERFMON_SEL_INT_RESP_RETRY = 0x00000024,
277SDMA_PERFMON_SEL_NUM_PACKET = 0x00000025,
278SDMA_PERFMON_SEL_CE_WREQ_IDLE = 0x00000027,
279SDMA_PERFMON_SEL_CE_WR_IDLE = 0x00000028,
280SDMA_PERFMON_SEL_CE_SPLIT_IDLE = 0x00000029,
281SDMA_PERFMON_SEL_CE_RREQ_IDLE = 0x0000002a,
282SDMA_PERFMON_SEL_CE_OUT_IDLE = 0x0000002b,
283SDMA_PERFMON_SEL_CE_IN_IDLE = 0x0000002c,
284SDMA_PERFMON_SEL_CE_DST_IDLE = 0x0000002d,
285SDMA_PERFMON_SEL_CE_AFIFO_FULL = 0x00000030,
286SDMA_PERFMON_SEL_CE_INFO_FULL = 0x00000033,
287SDMA_PERFMON_SEL_CE_INFO1_FULL = 0x00000034,
288SDMA_PERFMON_SEL_CE_RD_STALL = 0x00000035,
289SDMA_PERFMON_SEL_CE_WR_STALL = 0x00000036,
290SDMA_PERFMON_SEL_GFX_SELECT = 0x00000037,
291SDMA_PERFMON_SEL_RLC0_SELECT = 0x00000038,
292SDMA_PERFMON_SEL_RLC1_SELECT = 0x00000039,
293SDMA_PERFMON_SEL_PAGE_SELECT = 0x0000003a,
294SDMA_PERFMON_SEL_CTX_CHANGE = 0x0000003b,
295SDMA_PERFMON_SEL_CTX_CHANGE_EXPIRED = 0x0000003c,
296SDMA_PERFMON_SEL_CTX_CHANGE_EXCEPTION = 0x0000003d,
297SDMA_PERFMON_SEL_DOORBELL = 0x0000003e,
298SDMA_PERFMON_SEL_F32_L1_WR_VLD = 0x0000003f,
299SDMA_PERFMON_SEL_CE_L1_WR_VLD = 0x00000040,
300SDMA_PERFMON_SEL_CPF_SDMA_INVREQ = 0x00000041,
301SDMA_PERFMON_SEL_SDMA_CPF_INVACK = 0x00000042,
302SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ = 0x00000043,
303SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK = 0x00000044,
304SDMA_PERFMON_SEL_UTCL2_SDMA_INVREQ_ALL = 0x00000045,
305SDMA_PERFMON_SEL_SDMA_UTCL2_INVACK_ALL = 0x00000046,
306SDMA_PERFMON_SEL_UTCL2_RET_XNACK = 0x00000047,
307SDMA_PERFMON_SEL_UTCL2_RET_ACK = 0x00000048,
308SDMA_PERFMON_SEL_UTCL2_FREE = 0x00000049,
309SDMA_PERFMON_SEL_SDMA_UTCL2_SEND = 0x0000004a,
310SDMA_PERFMON_SEL_DMA_L1_WR_SEND = 0x0000004b,
311SDMA_PERFMON_SEL_DMA_L1_RD_SEND = 0x0000004c,
312SDMA_PERFMON_SEL_DMA_MC_WR_SEND = 0x0000004d,
313SDMA_PERFMON_SEL_DMA_MC_RD_SEND = 0x0000004e,
314SDMA_PERFMON_SEL_GPUVM_INV_HIGH = 0x0000004f,
315SDMA_PERFMON_SEL_GPUVM_INV_LOW = 0x00000050,
316SDMA_PERFMON_SEL_L1_WRL2_IDLE = 0x00000051,
317SDMA_PERFMON_SEL_L1_RDL2_IDLE = 0x00000052,
318SDMA_PERFMON_SEL_L1_WRMC_IDLE = 0x00000053,
319SDMA_PERFMON_SEL_L1_RDMC_IDLE = 0x00000054,
320SDMA_PERFMON_SEL_L1_WR_INV_IDLE = 0x00000055,
321SDMA_PERFMON_SEL_L1_RD_INV_IDLE = 0x00000056,
322SDMA_PERFMON_SEL_META_L2_REQ_SEND = 0x00000057,
323SDMA_PERFMON_SEL_L2_META_RET_VLD = 0x00000058,
324SDMA_PERFMON_SEL_SDMA_UTCL2_RD_SEND = 0x00000059,
325SDMA_PERFMON_SEL_UTCL2_SDMA_RD_RTN = 0x0000005a,
326SDMA_PERFMON_SEL_SDMA_UTCL2_WR_SEND = 0x0000005b,
327SDMA_PERFMON_SEL_UTCL2_SDMA_WR_RTN = 0x0000005c,
328SDMA_PERFMON_SEL_META_REQ_SEND = 0x0000005d,
329SDMA_PERFMON_SEL_META_RTN_VLD = 0x0000005e,
330SDMA_PERFMON_SEL_TLBI_SEND = 0x0000005f,
331SDMA_PERFMON_SEL_TLBI_RTN = 0x00000060,
332SDMA_PERFMON_SEL_GCR_SEND = 0x00000061,
333SDMA_PERFMON_SEL_GCR_RTN = 0x00000062,
334SDMA_PERFMON_SEL_UTCL1_TAG_DELAY_COUNTER = 0x00000063,
335SDMA_PERFMON_SEL_MMHUB_TAG_DELAY_COUNTER = 0x00000064,
336} SDMA_PERFMON_SEL;
337
338/*
339 * SDMA_PERF_SEL enum
340 */
341
342typedef enum SDMA_PERF_SEL {
343SDMA_PERF_SEL_CYCLE = 0x00000000,
344SDMA_PERF_SEL_IDLE = 0x00000001,
345SDMA_PERF_SEL_REG_IDLE = 0x00000002,
346SDMA_PERF_SEL_RB_EMPTY = 0x00000003,
347SDMA_PERF_SEL_RB_FULL = 0x00000004,
348SDMA_PERF_SEL_RB_WPTR_WRAP = 0x00000005,
349SDMA_PERF_SEL_RB_RPTR_WRAP = 0x00000006,
350SDMA_PERF_SEL_RB_WPTR_POLL_READ = 0x00000007,
351SDMA_PERF_SEL_RB_RPTR_WB = 0x00000008,
352SDMA_PERF_SEL_RB_CMD_IDLE = 0x00000009,
353SDMA_PERF_SEL_RB_CMD_FULL = 0x0000000a,
354SDMA_PERF_SEL_IB_CMD_IDLE = 0x0000000b,
355SDMA_PERF_SEL_IB_CMD_FULL = 0x0000000c,
356SDMA_PERF_SEL_EX_IDLE = 0x0000000d,
357SDMA_PERF_SEL_SRBM_REG_SEND = 0x0000000e,
358SDMA_PERF_SEL_EX_IDLE_POLL_TIMER_EXPIRE = 0x0000000f,
359SDMA_PERF_SEL_MC_WR_IDLE = 0x00000010,
360SDMA_PERF_SEL_MC_WR_COUNT = 0x00000011,
361SDMA_PERF_SEL_MC_RD_IDLE = 0x00000012,
362SDMA_PERF_SEL_MC_RD_COUNT = 0x00000013,
363SDMA_PERF_SEL_MC_RD_RET_STALL = 0x00000014,
364SDMA_PERF_SEL_MC_RD_NO_POLL_IDLE = 0x00000015,
365SDMA_PERF_SEL_SEM_IDLE = 0x00000018,
366SDMA_PERF_SEL_SEM_REQ_STALL = 0x00000019,
367SDMA_PERF_SEL_SEM_REQ_COUNT = 0x0000001a,
368SDMA_PERF_SEL_SEM_RESP_INCOMPLETE = 0x0000001b,
369SDMA_PERF_SEL_SEM_RESP_FAIL = 0x0000001c,
370SDMA_PERF_SEL_SEM_RESP_PASS = 0x0000001d,
371SDMA_PERF_SEL_INT_IDLE = 0x0000001e,
372SDMA_PERF_SEL_INT_REQ_STALL = 0x0000001f,
373SDMA_PERF_SEL_INT_REQ_COUNT = 0x00000020,
374SDMA_PERF_SEL_INT_RESP_ACCEPTED = 0x00000021,
375SDMA_PERF_SEL_INT_RESP_RETRY = 0x00000022,
376SDMA_PERF_SEL_NUM_PACKET = 0x00000023,
377SDMA_PERF_SEL_CE_WREQ_IDLE = 0x00000025,
378SDMA_PERF_SEL_CE_WR_IDLE = 0x00000026,
379SDMA_PERF_SEL_CE_SPLIT_IDLE = 0x00000027,
380SDMA_PERF_SEL_CE_RREQ_IDLE = 0x00000028,
381SDMA_PERF_SEL_CE_OUT_IDLE = 0x00000029,
382SDMA_PERF_SEL_CE_IN_IDLE = 0x0000002a,
383SDMA_PERF_SEL_CE_DST_IDLE = 0x0000002b,
384SDMA_PERF_SEL_CE_AFIFO_FULL = 0x0000002e,
385SDMA_PERF_SEL_CE_INFO_FULL = 0x00000031,
386SDMA_PERF_SEL_CE_INFO1_FULL = 0x00000032,
387SDMA_PERF_SEL_CE_RD_STALL = 0x00000033,
388SDMA_PERF_SEL_CE_WR_STALL = 0x00000034,
389SDMA_PERF_SEL_GFX_SELECT = 0x00000035,
390SDMA_PERF_SEL_RLC0_SELECT = 0x00000036,
391SDMA_PERF_SEL_RLC1_SELECT = 0x00000037,
392SDMA_PERF_SEL_PAGE_SELECT = 0x00000038,
393SDMA_PERF_SEL_CTX_CHANGE = 0x00000039,
394SDMA_PERF_SEL_CTX_CHANGE_EXPIRED = 0x0000003a,
395SDMA_PERF_SEL_CTX_CHANGE_EXCEPTION = 0x0000003b,
396SDMA_PERF_SEL_DOORBELL = 0x0000003c,
397SDMA_PERF_SEL_RD_BA_RTR = 0x0000003d,
398SDMA_PERF_SEL_WR_BA_RTR = 0x0000003e,
399SDMA_PERF_SEL_F32_L1_WR_VLD = 0x0000003f,
400SDMA_PERF_SEL_CE_L1_WR_VLD = 0x00000040,
401SDMA_PERF_SEL_CPF_SDMA_INVREQ = 0x00000041,
402SDMA_PERF_SEL_SDMA_CPF_INVACK = 0x00000042,
403SDMA_PERF_SEL_UTCL2_SDMA_INVREQ = 0x00000043,
404SDMA_PERF_SEL_SDMA_UTCL2_INVACK = 0x00000044,
405SDMA_PERF_SEL_UTCL2_SDMA_INVREQ_ALL = 0x00000045,
406SDMA_PERF_SEL_SDMA_UTCL2_INVACK_ALL = 0x00000046,
407SDMA_PERF_SEL_UTCL2_RET_XNACK = 0x00000047,
408SDMA_PERF_SEL_UTCL2_RET_ACK = 0x00000048,
409SDMA_PERF_SEL_UTCL2_FREE = 0x00000049,
410SDMA_PERF_SEL_SDMA_UTCL2_SEND = 0x0000004a,
411SDMA_PERF_SEL_DMA_L1_WR_SEND = 0x0000004b,
412SDMA_PERF_SEL_DMA_L1_RD_SEND = 0x0000004c,
413SDMA_PERF_SEL_DMA_MC_WR_SEND = 0x0000004d,
414SDMA_PERF_SEL_DMA_MC_RD_SEND = 0x0000004e,
415SDMA_PERF_SEL_GPUVM_INV_HIGH = 0x0000004f,
416SDMA_PERF_SEL_GPUVM_INV_LOW = 0x00000050,
417SDMA_PERF_SEL_L1_WRL2_IDLE = 0x00000051,
418SDMA_PERF_SEL_L1_RDL2_IDLE = 0x00000052,
419SDMA_PERF_SEL_L1_WRMC_IDLE = 0x00000053,
420SDMA_PERF_SEL_L1_RDMC_IDLE = 0x00000054,
421SDMA_PERF_SEL_L1_WR_INV_IDLE = 0x00000055,
422SDMA_PERF_SEL_L1_RD_INV_IDLE = 0x00000056,
423SDMA_PERF_SEL_META_L2_REQ_SEND = 0x00000057,
424SDMA_PERF_SEL_L2_META_RET_VLD = 0x00000058,
425SDMA_PERF_SEL_SDMA_UTCL2_RD_SEND = 0x00000059,
426SDMA_PERF_SEL_UTCL2_SDMA_RD_RTN = 0x0000005a,
427SDMA_PERF_SEL_SDMA_UTCL2_WR_SEND = 0x0000005b,
428SDMA_PERF_SEL_UTCL2_SDMA_WR_RTN = 0x0000005c,
429SDMA_PERF_SEL_META_REQ_SEND = 0x0000005d,
430SDMA_PERF_SEL_META_RTN_VLD = 0x0000005e,
431SDMA_PERF_SEL_TLBI_SEND = 0x0000005f,
432SDMA_PERF_SEL_TLBI_RTN = 0x00000060,
433SDMA_PERF_SEL_GCR_SEND = 0x00000061,
434SDMA_PERF_SEL_GCR_RTN = 0x00000062,
435SDMA_PERF_SEL_CGCG_FENCE = 0x00000063,
436SDMA_PERF_SEL_CE_CH_WR_REQ = 0x00000064,
437SDMA_PERF_SEL_CE_CH_WR_RET = 0x00000065,
438SDMA_PERF_SEL_F32_CH_WR_REQ = 0x00000066,
439SDMA_PERF_SEL_F32_CH_WR_RET = 0x00000067,
440SDMA_PERF_SEL_CE_OR_F32_CH_RD_REQ = 0x00000068,
441SDMA_PERF_SEL_CE_OR_F32_CH_RD_RET = 0x00000069,
442SDMA_PERF_SEL_RB_CH_RD_REQ = 0x0000006a,
443SDMA_PERF_SEL_RB_CH_RD_RET = 0x0000006b,
444SDMA_PERF_SEL_IB_CH_RD_REQ = 0x0000006c,
445SDMA_PERF_SEL_IB_CH_RD_RET = 0x0000006d,
446SDMA_PERF_SEL_WPTR_CH_RD_REQ = 0x0000006e,
447SDMA_PERF_SEL_WPTR_CH_RD_RET = 0x0000006f,
448SDMA_PERF_SEL_UTCL1_UTCL2_REQ = 0x00000070,
449SDMA_PERF_SEL_UTCL1_UTCL2_RET = 0x00000071,
450SDMA_PERF_SEL_CMD_OP_MATCH = 0x00000072,
451SDMA_PERF_SEL_CMD_OP_START = 0x00000073,
452SDMA_PERF_SEL_CMD_OP_END = 0x00000074,
453SDMA_PERF_SEL_CE_BUSY = 0x00000075,
454SDMA_PERF_SEL_CE_BUSY_START = 0x00000076,
455SDMA_PERF_SEL_CE_BUSY_END = 0x00000077,
456SDMA_PERF_SEL_F32_PERFCNT_TRIGGER = 0x00000078,
457SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_START = 0x00000079,
458SDMA_PERF_SEL_F32_PERFCNT_TRIGGER_END = 0x0000007a,
459SDMA_PERF_SEL_CE_CH_WRREQ_SEND = 0x0000007b,
460SDMA_PERF_SEL_CH_CE_WRRET_VALID = 0x0000007c,
461SDMA_PERF_SEL_CE_CH_RDREQ_SEND = 0x0000007d,
462SDMA_PERF_SEL_CH_CE_RDRET_VALID = 0x0000007e,
463} SDMA_PERF_SEL;
464
465/*
466 * TCC_CACHE_POLICIES enum
467 */
468
469typedef enum TCC_CACHE_POLICIES {
470TCC_CACHE_POLICY_LRU = 0x00000000,
471TCC_CACHE_POLICY_STREAM = 0x00000001,
472} TCC_CACHE_POLICIES;
473
474/*
475 * TCC_MTYPE enum
476 */
477
478typedef enum TCC_MTYPE {
479MTYPE_NC = 0x00000000,
480MTYPE_WC = 0x00000001,
481MTYPE_CC = 0x00000002,
482} TCC_MTYPE;
483
484/*
485 * UTCL0FaultType enum
486 */
487
488typedef enum UTCL0FaultType {
489UTCL0_XNACK_SUCCESS = 0x00000000,
490UTCL0_XNACK_RETRY = 0x00000001,
491UTCL0_XNACK_PRT = 0x00000002,
492UTCL0_XNACK_NO_RETRY = 0x00000003,
493} UTCL0FaultType;
494
495/*
496 * UTCL0RequestType enum
497 */
498
499typedef enum UTCL0RequestType {
500UTCL0_TYPE_NORMAL = 0x00000000,
501UTCL0_TYPE_SHOOTDOWN = 0x00000001,
502UTCL0_TYPE_BYPASS = 0x00000002,
503} UTCL0RequestType;
504
505/*
506 * UTCL1FaultType enum
507 */
508
509typedef enum UTCL1FaultType {
510UTCL1_XNACK_SUCCESS = 0x00000000,
511UTCL1_XNACK_RETRY = 0x00000001,
512UTCL1_XNACK_PRT = 0x00000002,
513UTCL1_XNACK_NO_RETRY = 0x00000003,
514} UTCL1FaultType;
515
516/*
517 * UTCL1RequestType enum
518 */
519
520typedef enum UTCL1RequestType {
521UTCL1_TYPE_NORMAL = 0x00000000,
522UTCL1_TYPE_SHOOTDOWN = 0x00000001,
523UTCL1_TYPE_BYPASS = 0x00000002,
524} UTCL1RequestType;
525
526/*
527 * VMEMCMD_RETURN_ORDER enum
528 */
529
530typedef enum VMEMCMD_RETURN_ORDER {
531VMEMCMD_RETURN_OUT_OF_ORDER = 0x00000000,
532VMEMCMD_RETURN_IN_ORDER = 0x00000001,
533VMEMCMD_RETURN_IN_ORDER_READ = 0x00000002,
534} VMEMCMD_RETURN_ORDER;
535
536/*
537 * WritePolicy enum
538 */
539
540typedef enum WritePolicy {
541CACHE_LRU_WR = 0x00000000,
542CACHE_STREAM = 0x00000001,
543CACHE_NOA_WR = 0x00000002,
544CACHE_BYPASS = 0x00000003,
545} WritePolicy;
546
547/*******************************************************
548 * CNVC_CFG Enums
549 *******************************************************/
550
551/*
552 * CNVC_BYPASS enum
553 */
554
555typedef enum CNVC_BYPASS {
556CNVC_BYPASS_DISABLE = 0x00000000,
557CNVC_BYPASS_EN = 0x00000001,
558} CNVC_BYPASS;
559
560/*
561 * CNVC_COEF_FORMAT_ENUM enum
562 */
563
564typedef enum CNVC_COEF_FORMAT_ENUM {
565CNVC_FIX_S2_13 = 0x00000000,
566CNVC_FIX_S3_12 = 0x00000001,
567} CNVC_COEF_FORMAT_ENUM;
568
569/*
570 * CNVC_ENABLE enum
571 */
572
573typedef enum CNVC_ENABLE {
574CNVC_DIS = 0x00000000,
575CNVC_EN = 0x00000001,
576} CNVC_ENABLE;
577
578/*
579 * CNVC_PENDING enum
580 */
581
582typedef enum CNVC_PENDING {
583CNVC_NOT_PENDING = 0x00000000,
584CNVC_YES_PENDING = 0x00000001,
585} CNVC_PENDING;
586
587/*
588 * COLOR_KEYER_MODE enum
589 */
590
591typedef enum COLOR_KEYER_MODE {
592FORCE_00 = 0x00000000,
593FORCE_FF = 0x00000001,
594RANGE_00 = 0x00000002,
595RANGE_FF = 0x00000003,
596} COLOR_KEYER_MODE;
597
598/*
599 * DENORM_TRUNCATE enum
600 */
601
602typedef enum DENORM_TRUNCATE {
603CNVC_ROUND = 0x00000000,
604CNVC_TRUNCATE = 0x00000001,
605} DENORM_TRUNCATE;
606
607/*
608 * FORMAT_CROSSBAR enum
609 */
610
611typedef enum FORMAT_CROSSBAR {
612FORMAT_CROSSBAR_R = 0x00000000,
613FORMAT_CROSSBAR_G = 0x00000001,
614FORMAT_CROSSBAR_B = 0x00000002,
615} FORMAT_CROSSBAR;
616
617/*
618 * PIX_EXPAND_MODE enum
619 */
620
621typedef enum PIX_EXPAND_MODE {
622PIX_DYNAMIC_EXPANSION = 0x00000000,
623PIX_ZERO_EXPANSION = 0x00000001,
624} PIX_EXPAND_MODE;
625
626/*
627 * PRE_CSC_MODE_ENUM enum
628 */
629
630typedef enum PRE_CSC_MODE_ENUM {
631PRE_CSC_BYPASS = 0x00000000,
632PRE_CSC_SET_A = 0x00000001,
633PRE_CSC_SET_B = 0x00000002,
634} PRE_CSC_MODE_ENUM;
635
636/*
637 * PRE_DEGAM_MODE enum
638 */
639
640typedef enum PRE_DEGAM_MODE {
641PRE_DEGAM_BYPASS = 0x00000000,
642PRE_DEGAM_ENABLE = 0x00000001,
643} PRE_DEGAM_MODE;
644
645/*
646 * PRE_DEGAM_SELECT enum
647 */
648
649typedef enum PRE_DEGAM_SELECT {
650PRE_DEGAM_SRGB = 0x00000000,
651PRE_DEGAM_GAMMA_22 = 0x00000001,
652PRE_DEGAM_GAMMA_24 = 0x00000002,
653PRE_DEGAM_GAMMA_26 = 0x00000003,
654PRE_DEGAM_BT2020 = 0x00000004,
655PRE_DEGAM_BT2100PQ = 0x00000005,
656PRE_DEGAM_BT2100HLG = 0x00000006,
657} PRE_DEGAM_SELECT;
658
659/*
660 * SURFACE_PIXEL_FORMAT enum
661 */
662
663typedef enum SURFACE_PIXEL_FORMAT {
664ARGB1555 = 0x00000001,
665RGBA5551 = 0x00000002,
666RGB565 = 0x00000003,
667BGR565 = 0x00000004,
668ARGB4444 = 0x00000005,
669RGBA4444 = 0x00000006,
670ARGB8888 = 0x00000008,
671RGBA8888 = 0x00000009,
672ARGB2101010 = 0x0000000a,
673RGBA1010102 = 0x0000000b,
674AYCrCb8888 = 0x0000000c,
675YCrCbA8888 = 0x0000000d,
676ACrYCb8888 = 0x0000000e,
677CrYCbA8888 = 0x0000000f,
678ARGB16161616_10MSB = 0x00000010,
679RGBA16161616_10MSB = 0x00000011,
680ARGB16161616_10LSB = 0x00000012,
681RGBA16161616_10LSB = 0x00000013,
682ARGB16161616_12MSB = 0x00000014,
683RGBA16161616_12MSB = 0x00000015,
684ARGB16161616_12LSB = 0x00000016,
685RGBA16161616_12LSB = 0x00000017,
686ARGB16161616_FLOAT = 0x00000018,
687RGBA16161616_FLOAT = 0x00000019,
688ARGB16161616_UNORM = 0x0000001a,
689RGBA16161616_UNORM = 0x0000001b,
690ARGB16161616_SNORM = 0x0000001c,
691RGBA16161616_SNORM = 0x0000001d,
692AYCrCb16161616_10MSB = 0x00000020,
693AYCrCb16161616_10LSB = 0x00000021,
694YCrCbA16161616_10MSB = 0x00000022,
695YCrCbA16161616_10LSB = 0x00000023,
696ACrYCb16161616_10MSB = 0x00000024,
697ACrYCb16161616_10LSB = 0x00000025,
698CrYCbA16161616_10MSB = 0x00000026,
699CrYCbA16161616_10LSB = 0x00000027,
700AYCrCb16161616_12MSB = 0x00000028,
701AYCrCb16161616_12LSB = 0x00000029,
702YCrCbA16161616_12MSB = 0x0000002a,
703YCrCbA16161616_12LSB = 0x0000002b,
704ACrYCb16161616_12MSB = 0x0000002c,
705ACrYCb16161616_12LSB = 0x0000002d,
706CrYCbA16161616_12MSB = 0x0000002e,
707CrYCbA16161616_12LSB = 0x0000002f,
708Y8_CrCb88_420_PLANAR = 0x00000040,
709Y8_CbCr88_420_PLANAR = 0x00000041,
710Y10_CrCb1010_420_PLANAR = 0x00000042,
711Y10_CbCr1010_420_PLANAR = 0x00000043,
712Y12_CrCb1212_420_PLANAR = 0x00000044,
713Y12_CbCr1212_420_PLANAR = 0x00000045,
714YCrYCb8888_422_PACKED = 0x00000048,
715YCbYCr8888_422_PACKED = 0x00000049,
716CrYCbY8888_422_PACKED = 0x0000004a,
717CbYCrY8888_422_PACKED = 0x0000004b,
718YCrYCb10101010_422_PACKED = 0x0000004c,
719YCbYCr10101010_422_PACKED = 0x0000004d,
720CrYCbY10101010_422_PACKED = 0x0000004e,
721CbYCrY10101010_422_PACKED = 0x0000004f,
722YCrYCb12121212_422_PACKED = 0x00000050,
723YCbYCr12121212_422_PACKED = 0x00000051,
724CrYCbY12121212_422_PACKED = 0x00000052,
725CbYCrY12121212_422_PACKED = 0x00000053,
726RGB111110_FIX = 0x00000070,
727BGR101111_FIX = 0x00000071,
728ACrYCb2101010 = 0x00000072,
729CrYCbA1010102 = 0x00000073,
730RGBE = 0x00000074,
731RGB111110_FLOAT = 0x00000076,
732BGR101111_FLOAT = 0x00000077,
733MONO_8 = 0x00000078,
734MONO_10MSB = 0x00000079,
735MONO_10LSB = 0x0000007a,
736MONO_12MSB = 0x0000007b,
737MONO_12LSB = 0x0000007c,
738MONO_16 = 0x0000007d,
739} SURFACE_PIXEL_FORMAT;
740
741/*
742 * XNORM enum
743 */
744
745typedef enum XNORM {
746XNORM_A = 0x00000000,
747XNORM_B = 0x00000001,
748} XNORM;
749
750/*******************************************************
751 * CNVC_CUR Enums
752 *******************************************************/
753
754/*
755 * CUR_ENABLE enum
756 */
757
758typedef enum CUR_ENABLE {
759CUR_DIS = 0x00000000,
760CUR_EN = 0x00000001,
761} CUR_ENABLE;
762
763/*
764 * CUR_EXPAND_MODE enum
765 */
766
767typedef enum CUR_EXPAND_MODE {
768CUR_DYNAMIC_EXPANSION = 0x00000000,
769CUR_ZERO_EXPANSION = 0x00000001,
770} CUR_EXPAND_MODE;
771
772/*
773 * CUR_INV_CLAMP enum
774 */
775
776typedef enum CUR_INV_CLAMP {
777CUR_CLAMP_DIS = 0x00000000,
778CUR_CLAMP_EN = 0x00000001,
779} CUR_INV_CLAMP;
780
781/*
782 * CUR_MODE enum
783 */
784
785typedef enum CUR_MODE {
786MONO_2BIT = 0x00000000,
787COLOR_24BIT_1BIT_AND = 0x00000001,
788COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002,
789COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003,
790COLOR_64BIT_FP_PREMULT = 0x00000004,
791COLOR_64BIT_FP_UNPREMULT = 0x00000005,
792} CUR_MODE;
793
794/*
795 * CUR_PENDING enum
796 */
797
798typedef enum CUR_PENDING {
799CUR_NOT_PENDING = 0x00000000,
800CUR_YES_PENDING = 0x00000001,
801} CUR_PENDING;
802
803/*
804 * CUR_ROM_EN enum
805 */
806
807typedef enum CUR_ROM_EN {
808CUR_FP_NO_ROM = 0x00000000,
809CUR_FP_USE_ROM = 0x00000001,
810} CUR_ROM_EN;
811
812/*******************************************************
813 * DSCL Enums
814 *******************************************************/
815
816/*
817 * COEF_RAM_SELECT_RD enum
818 */
819
820typedef enum COEF_RAM_SELECT_RD {
821COEF_RAM_SELECT_BACK = 0x00000000,
822COEF_RAM_SELECT_CURRENT = 0x00000001,
823} COEF_RAM_SELECT_RD;
824
825/*
826 * DSCL_MODE_SEL enum
827 */
828
829typedef enum DSCL_MODE_SEL {
830DSCL_MODE_SCALING_444_BYPASS = 0x00000000,
831DSCL_MODE_SCALING_444_RGB_ENABLE = 0x00000001,
832DSCL_MODE_SCALING_444_YCBCR_ENABLE = 0x00000002,
833DSCL_MODE_SCALING_YCBCR_ENABLE = 0x00000003,
834DSCL_MODE_LUMA_SCALING_BYPASS = 0x00000004,
835DSCL_MODE_CHROMA_SCALING_BYPASS = 0x00000005,
836DSCL_MODE_DSCL_BYPASS = 0x00000006,
837} DSCL_MODE_SEL;
838
839/*
840 * LB_ALPHA_EN enum
841 */
842
843typedef enum LB_ALPHA_EN {
844LB_ALPHA_DISABLE = 0x00000000,
845LB_ALPHA_ENABLE = 0x00000001,
846} LB_ALPHA_EN;
847
848/*
849 * LB_INTERLEAVE_EN enum
850 */
851
852typedef enum LB_INTERLEAVE_EN {
853LB_INTERLEAVE_DISABLE = 0x00000000,
854LB_INTERLEAVE_ENABLE = 0x00000001,
855} LB_INTERLEAVE_EN;
856
857/*
858 * LB_MEMORY_CONFIG enum
859 */
860
861typedef enum LB_MEMORY_CONFIG {
862LB_MEMORY_CONFIG_0 = 0x00000000,
863LB_MEMORY_CONFIG_1 = 0x00000001,
864LB_MEMORY_CONFIG_2 = 0x00000002,
865LB_MEMORY_CONFIG_3 = 0x00000003,
866} LB_MEMORY_CONFIG;
867
868/*
869 * OBUF_BYPASS_SEL enum
870 */
871
872typedef enum OBUF_BYPASS_SEL {
873OBUF_BYPASS_DIS = 0x00000000,
874OBUF_BYPASS_EN = 0x00000001,
875} OBUF_BYPASS_SEL;
876
877/*
878 * OBUF_IS_HALF_RECOUT_WIDTH_SEL enum
879 */
880
881typedef enum OBUF_IS_HALF_RECOUT_WIDTH_SEL {
882OBUF_FULL_RECOUT = 0x00000000,
883OBUF_HALF_RECOUT = 0x00000001,
884} OBUF_IS_HALF_RECOUT_WIDTH_SEL;
885
886/*
887 * OBUF_USE_FULL_BUFFER_SEL enum
888 */
889
890typedef enum OBUF_USE_FULL_BUFFER_SEL {
891OBUF_RECOUT = 0x00000000,
892OBUF_FULL = 0x00000001,
893} OBUF_USE_FULL_BUFFER_SEL;
894
895/*
896 * SCL_2TAP_HARDCODE enum
897 */
898
899typedef enum SCL_2TAP_HARDCODE {
900SCL_COEF_2TAP_HARDCODE_OFF = 0x00000000,
901SCL_COEF_2TAP_HARDCODE_ON = 0x00000001,
902} SCL_2TAP_HARDCODE;
903
904/*
905 * SCL_ALPHA_COEF enum
906 */
907
908typedef enum SCL_ALPHA_COEF {
909SCL_ALPHA_COEF_FIRST = 0x00000000,
910SCL_ALPHA_COEF_SECOND = 0x00000001,
911} SCL_ALPHA_COEF;
912
913/*
914 * SCL_AUTOCAL_MODE enum
915 */
916
917typedef enum SCL_AUTOCAL_MODE {
918AUTOCAL_MODE_OFF = 0x00000000,
919AUTOCAL_MODE_AUTOSCALE = 0x00000001,
920AUTOCAL_MODE_AUTOCENTER = 0x00000002,
921AUTOCAL_MODE_AUTOREPLICATE = 0x00000003,
922} SCL_AUTOCAL_MODE;
923
924/*
925 * SCL_BOUNDARY enum
926 */
927
928typedef enum SCL_BOUNDARY {
929SCL_BOUNDARY_EDGE = 0x00000000,
930SCL_BOUNDARY_BLACK = 0x00000001,
931} SCL_BOUNDARY;
932
933/*
934 * SCL_CHROMA_COEF enum
935 */
936
937typedef enum SCL_CHROMA_COEF {
938SCL_CHROMA_COEF_FIRST = 0x00000000,
939SCL_CHROMA_COEF_SECOND = 0x00000001,
940} SCL_CHROMA_COEF;
941
942/*
943 * SCL_COEF_FILTER_TYPE_SEL enum
944 */
945
946typedef enum SCL_COEF_FILTER_TYPE_SEL {
947SCL_COEF_LUMA_VERT_FILTER = 0x00000000,
948SCL_COEF_LUMA_HORZ_FILTER = 0x00000001,
949SCL_COEF_CHROMA_VERT_FILTER = 0x00000002,
950SCL_COEF_CHROMA_HORZ_FILTER = 0x00000003,
951} SCL_COEF_FILTER_TYPE_SEL;
952
953/*
954 * SCL_COEF_RAM_SEL enum
955 */
956
957typedef enum SCL_COEF_RAM_SEL {
958SCL_COEF_RAM_SEL_0 = 0x00000000,
959SCL_COEF_RAM_SEL_1 = 0x00000001,
960} SCL_COEF_RAM_SEL;
961
962/*
963 * SCL_SHARP_EN enum
964 */
965
966typedef enum SCL_SHARP_EN {
967SCL_SHARP_DISABLE = 0x00000000,
968SCL_SHARP_ENABLE = 0x00000001,
969} SCL_SHARP_EN;
970
971/*******************************************************
972 * CM Enums
973 *******************************************************/
974
975/*
976 * CMC_3DLUT_30BIT_ENUM enum
977 */
978
979typedef enum CMC_3DLUT_30BIT_ENUM {
980CMC_3DLUT_36BIT = 0x00000000,
981CMC_3DLUT_30BIT = 0x00000001,
982} CMC_3DLUT_30BIT_ENUM;
983
984/*
985 * CMC_3DLUT_RAM_SEL enum
986 */
987
988typedef enum CMC_3DLUT_RAM_SEL {
989CMC_RAM0_ACCESS = 0x00000000,
990CMC_RAM1_ACCESS = 0x00000001,
991CMC_RAM2_ACCESS = 0x00000002,
992CMC_RAM3_ACCESS = 0x00000003,
993} CMC_3DLUT_RAM_SEL;
994
995/*
996 * CMC_3DLUT_SIZE_ENUM enum
997 */
998
999typedef enum CMC_3DLUT_SIZE_ENUM {
1000CMC_3DLUT_17CUBE = 0x00000000,
1001CMC_3DLUT_9CUBE = 0x00000001,
1002} CMC_3DLUT_SIZE_ENUM;
1003
1004/*
1005 * CMC_LUT_2_CONFIG_ENUM enum
1006 */
1007
1008typedef enum CMC_LUT_2_CONFIG_ENUM {
1009CMC_LUT_2CFG_NO_MEMORY = 0x00000000,
1010CMC_LUT_2CFG_MEMORY_A = 0x00000001,
1011CMC_LUT_2CFG_MEMORY_B = 0x00000002,
1012} CMC_LUT_2_CONFIG_ENUM;
1013
1014/*
1015 * CMC_LUT_2_MODE_ENUM enum
1016 */
1017
1018typedef enum CMC_LUT_2_MODE_ENUM {
1019CMC_LUT_2_MODE_BYPASS = 0x00000000,
1020CMC_LUT_2_MODE_RAMA_LUT = 0x00000001,
1021CMC_LUT_2_MODE_RAMB_LUT = 0x00000002,
1022} CMC_LUT_2_MODE_ENUM;
1023
1024/*
1025 * CMC_LUT_NUM_SEG enum
1026 */
1027
1028typedef enum CMC_LUT_NUM_SEG {
1029CMC_SEGMENTS_1 = 0x00000000,
1030CMC_SEGMENTS_2 = 0x00000001,
1031CMC_SEGMENTS_4 = 0x00000002,
1032CMC_SEGMENTS_8 = 0x00000003,
1033CMC_SEGMENTS_16 = 0x00000004,
1034CMC_SEGMENTS_32 = 0x00000005,
1035CMC_SEGMENTS_64 = 0x00000006,
1036CMC_SEGMENTS_128 = 0x00000007,
1037} CMC_LUT_NUM_SEG;
1038
1039/*
1040 * CMC_LUT_RAM_SEL enum
1041 */
1042
1043typedef enum CMC_LUT_RAM_SEL {
1044CMC_RAMA_ACCESS = 0x00000000,
1045CMC_RAMB_ACCESS = 0x00000001,
1046} CMC_LUT_RAM_SEL;
1047
1048/*
1049 * CM_BYPASS enum
1050 */
1051
1052typedef enum CM_BYPASS {
1053NON_BYPASS = 0x00000000,
1054BYPASS_EN = 0x00000001,
1055} CM_BYPASS;
1056
1057/*
1058 * CM_COEF_FORMAT_ENUM enum
1059 */
1060
1061typedef enum CM_COEF_FORMAT_ENUM {
1062FIX_S2_13 = 0x00000000,
1063FIX_S3_12 = 0x00000001,
1064} CM_COEF_FORMAT_ENUM;
1065
1066/*
1067 * CM_DATA_SIGNED enum
1068 */
1069
1070typedef enum CM_DATA_SIGNED {
1071UNSIGNED = 0x00000000,
1072SIGNED = 0x00000001,
1073} CM_DATA_SIGNED;
1074
1075/*
1076 * CM_EN enum
1077 */
1078
1079typedef enum CM_EN {
1080CM_DISABLE = 0x00000000,
1081CM_ENABLE = 0x00000001,
1082} CM_EN;
1083
1084/*
1085 * CM_GAMMA_LUT_MODE_ENUM enum
1086 */
1087
1088typedef enum CM_GAMMA_LUT_MODE_ENUM {
1089BYPASS = 0x00000000,
1090RESERVED_1 = 0x00000001,
1091RAM_LUT = 0x00000002,
1092RESERVED_3 = 0x00000003,
1093} CM_GAMMA_LUT_MODE_ENUM;
1094
1095/*
1096 * CM_GAMMA_LUT_PWL_DISABLE_ENUM enum
1097 */
1098
1099typedef enum CM_GAMMA_LUT_PWL_DISABLE_ENUM {
1100ENABLE_PWL = 0x00000000,
1101DISABLE_PWL = 0x00000001,
1102} CM_GAMMA_LUT_PWL_DISABLE_ENUM;
1103
1104/*
1105 * CM_GAMMA_LUT_SEL_ENUM enum
1106 */
1107
1108typedef enum CM_GAMMA_LUT_SEL_ENUM {
1109RAMA = 0x00000000,
1110RAMB = 0x00000001,
1111} CM_GAMMA_LUT_SEL_ENUM;
1112
1113/*
1114 * CM_GAMUT_REMAP_MODE_ENUM enum
1115 */
1116
1117typedef enum CM_GAMUT_REMAP_MODE_ENUM {
1118BYPASS_GAMUT = 0x00000000,
1119GAMUT_COEF = 0x00000001,
1120GAMUT_COEF_B = 0x00000002,
1121} CM_GAMUT_REMAP_MODE_ENUM;
1122
1123/*
1124 * CM_LUT_2_CONFIG_ENUM enum
1125 */
1126
1127typedef enum CM_LUT_2_CONFIG_ENUM {
1128LUT_2CFG_NO_MEMORY = 0x00000000,
1129LUT_2CFG_MEMORY_A = 0x00000001,
1130LUT_2CFG_MEMORY_B = 0x00000002,
1131} CM_LUT_2_CONFIG_ENUM;
1132
1133/*
1134 * CM_LUT_2_MODE_ENUM enum
1135 */
1136
1137typedef enum CM_LUT_2_MODE_ENUM {
1138LUT_2_MODE_BYPASS = 0x00000000,
1139LUT_2_MODE_RAMA_LUT = 0x00000001,
1140LUT_2_MODE_RAMB_LUT = 0x00000002,
1141} CM_LUT_2_MODE_ENUM;
1142
1143/*
1144 * CM_LUT_4_CONFIG_ENUM enum
1145 */
1146
1147typedef enum CM_LUT_4_CONFIG_ENUM {
1148LUT_4CFG_NO_MEMORY = 0x00000000,
1149LUT_4CFG_ROM_A = 0x00000001,
1150LUT_4CFG_ROM_B = 0x00000002,
1151LUT_4CFG_MEMORY_A = 0x00000003,
1152LUT_4CFG_MEMORY_B = 0x00000004,
1153} CM_LUT_4_CONFIG_ENUM;
1154
1155/*
1156 * CM_LUT_4_MODE_ENUM enum
1157 */
1158
1159typedef enum CM_LUT_4_MODE_ENUM {
1160LUT_4_MODE_BYPASS = 0x00000000,
1161LUT_4_MODE_ROMA_LUT = 0x00000001,
1162LUT_4_MODE_ROMB_LUT = 0x00000002,
1163LUT_4_MODE_RAMA_LUT = 0x00000003,
1164LUT_4_MODE_RAMB_LUT = 0x00000004,
1165} CM_LUT_4_MODE_ENUM;
1166
1167/*
1168 * CM_LUT_CONFIG_MODE enum
1169 */
1170
1171typedef enum CM_LUT_CONFIG_MODE {
1172DIFFERENT_RGB = 0x00000000,
1173ALL_USE_R = 0x00000001,
1174} CM_LUT_CONFIG_MODE;
1175
1176/*
1177 * CM_LUT_NUM_SEG enum
1178 */
1179
1180typedef enum CM_LUT_NUM_SEG {
1181SEGMENTS_1 = 0x00000000,
1182SEGMENTS_2 = 0x00000001,
1183SEGMENTS_4 = 0x00000002,
1184SEGMENTS_8 = 0x00000003,
1185SEGMENTS_16 = 0x00000004,
1186SEGMENTS_32 = 0x00000005,
1187SEGMENTS_64 = 0x00000006,
1188SEGMENTS_128 = 0x00000007,
1189} CM_LUT_NUM_SEG;
1190
1191/*
1192 * CM_LUT_RAM_SEL enum
1193 */
1194
1195typedef enum CM_LUT_RAM_SEL {
1196RAMA_ACCESS = 0x00000000,
1197RAMB_ACCESS = 0x00000001,
1198} CM_LUT_RAM_SEL;
1199
1200/*
1201 * CM_LUT_READ_COLOR_SEL enum
1202 */
1203
1204typedef enum CM_LUT_READ_COLOR_SEL {
1205BLUE_LUT = 0x00000000,
1206GREEN_LUT = 0x00000001,
1207RED_LUT = 0x00000002,
1208} CM_LUT_READ_COLOR_SEL;
1209
1210/*
1211 * CM_LUT_READ_DBG enum
1212 */
1213
1214typedef enum CM_LUT_READ_DBG {
1215DISABLE_DEBUG = 0x00000000,
1216ENABLE_DEBUG = 0x00000001,
1217} CM_LUT_READ_DBG;
1218
1219/*
1220 * CM_PENDING enum
1221 */
1222
1223typedef enum CM_PENDING {
1224CM_NOT_PENDING = 0x00000000,
1225CM_YES_PENDING = 0x00000001,
1226} CM_PENDING;
1227
1228/*
1229 * CM_POST_CSC_MODE_ENUM enum
1230 */
1231
1232typedef enum CM_POST_CSC_MODE_ENUM {
1233BYPASS_POST_CSC = 0x00000000,
1234COEF_POST_CSC = 0x00000001,
1235COEF_POST_CSC_B = 0x00000002,
1236} CM_POST_CSC_MODE_ENUM;
1237
1238/*
1239 * CM_WRITE_BASE_ONLY enum
1240 */
1241
1242typedef enum CM_WRITE_BASE_ONLY {
1243WRITE_BOTH = 0x00000000,
1244WRITE_BASE_ONLY = 0x00000001,
1245} CM_WRITE_BASE_ONLY;
1246
1247/*******************************************************
1248 * DPP_TOP Enums
1249 *******************************************************/
1250
1251/*
1252 * CRC_CUR_SEL enum
1253 */
1254
1255typedef enum CRC_CUR_SEL {
1256CRC_CUR_0 = 0x00000000,
1257CRC_CUR_1 = 0x00000001,
1258} CRC_CUR_SEL;
1259
1260/*
1261 * CRC_INTERLACE_SEL enum
1262 */
1263
1264typedef enum CRC_INTERLACE_SEL {
1265CRC_INTERLACE_0 = 0x00000000,
1266CRC_INTERLACE_1 = 0x00000001,
1267CRC_INTERLACE_2 = 0x00000002,
1268CRC_INTERLACE_3 = 0x00000003,
1269} CRC_INTERLACE_SEL;
1270
1271/*
1272 * CRC_IN_CUR_SEL enum
1273 */
1274
1275typedef enum CRC_IN_CUR_SEL {
1276CRC_IN_CUR_0 = 0x00000000,
1277CRC_IN_CUR_1 = 0x00000001,
1278CRC_IN_CUR_2 = 0x00000002,
1279CRC_IN_CUR_3 = 0x00000003,
1280} CRC_IN_CUR_SEL;
1281
1282/*
1283 * CRC_IN_PIX_SEL enum
1284 */
1285
1286typedef enum CRC_IN_PIX_SEL {
1287CRC_IN_PIX_0 = 0x00000000,
1288CRC_IN_PIX_1 = 0x00000001,
1289CRC_IN_PIX_2 = 0x00000002,
1290CRC_IN_PIX_3 = 0x00000003,
1291CRC_IN_PIX_4 = 0x00000004,
1292CRC_IN_PIX_5 = 0x00000005,
1293CRC_IN_PIX_6 = 0x00000006,
1294CRC_IN_PIX_7 = 0x00000007,
1295} CRC_IN_PIX_SEL;
1296
1297/*
1298 * CRC_SRC_SEL enum
1299 */
1300
1301typedef enum CRC_SRC_SEL {
1302CRC_SRC_0 = 0x00000000,
1303CRC_SRC_1 = 0x00000001,
1304CRC_SRC_2 = 0x00000002,
1305CRC_SRC_3 = 0x00000003,
1306} CRC_SRC_SEL;
1307
1308/*
1309 * CRC_STEREO_SEL enum
1310 */
1311
1312typedef enum CRC_STEREO_SEL {
1313CRC_STEREO_0 = 0x00000000,
1314CRC_STEREO_1 = 0x00000001,
1315CRC_STEREO_2 = 0x00000002,
1316CRC_STEREO_3 = 0x00000003,
1317} CRC_STEREO_SEL;
1318
1319/*
1320 * TEST_CLK_SEL enum
1321 */
1322
1323typedef enum TEST_CLK_SEL {
1324TEST_CLK_SEL_0 = 0x00000000,
1325TEST_CLK_SEL_1 = 0x00000001,
1326TEST_CLK_SEL_2 = 0x00000002,
1327TEST_CLK_SEL_3 = 0x00000003,
1328TEST_CLK_SEL_4 = 0x00000004,
1329TEST_CLK_SEL_5 = 0x00000005,
1330TEST_CLK_SEL_6 = 0x00000006,
1331TEST_CLK_SEL_7 = 0x00000007,
1332} TEST_CLK_SEL;
1333
1334/*******************************************************
1335 * DC_PERFMON Enums
1336 *******************************************************/
1337
1338/*
1339 * PERFCOUNTER_ACTIVE enum
1340 */
1341
1342typedef enum PERFCOUNTER_ACTIVE {
1343PERFCOUNTER_IS_IDLE = 0x00000000,
1344PERFCOUNTER_IS_ACTIVE = 0x00000001,
1345} PERFCOUNTER_ACTIVE;
1346
1347/*
1348 * PERFCOUNTER_CNT0_STATE enum
1349 */
1350
1351typedef enum PERFCOUNTER_CNT0_STATE {
1352PERFCOUNTER_CNT0_STATE_RESET = 0x00000000,
1353PERFCOUNTER_CNT0_STATE_START = 0x00000001,
1354PERFCOUNTER_CNT0_STATE_FREEZE = 0x00000002,
1355PERFCOUNTER_CNT0_STATE_HW = 0x00000003,
1356} PERFCOUNTER_CNT0_STATE;
1357
1358/*
1359 * PERFCOUNTER_CNT1_STATE enum
1360 */
1361
1362typedef enum PERFCOUNTER_CNT1_STATE {
1363PERFCOUNTER_CNT1_STATE_RESET = 0x00000000,
1364PERFCOUNTER_CNT1_STATE_START = 0x00000001,
1365PERFCOUNTER_CNT1_STATE_FREEZE = 0x00000002,
1366PERFCOUNTER_CNT1_STATE_HW = 0x00000003,
1367} PERFCOUNTER_CNT1_STATE;
1368
1369/*
1370 * PERFCOUNTER_CNT2_STATE enum
1371 */
1372
1373typedef enum PERFCOUNTER_CNT2_STATE {
1374PERFCOUNTER_CNT2_STATE_RESET = 0x00000000,
1375PERFCOUNTER_CNT2_STATE_START = 0x00000001,
1376PERFCOUNTER_CNT2_STATE_FREEZE = 0x00000002,
1377PERFCOUNTER_CNT2_STATE_HW = 0x00000003,
1378} PERFCOUNTER_CNT2_STATE;
1379
1380/*
1381 * PERFCOUNTER_CNT3_STATE enum
1382 */
1383
1384typedef enum PERFCOUNTER_CNT3_STATE {
1385PERFCOUNTER_CNT3_STATE_RESET = 0x00000000,
1386PERFCOUNTER_CNT3_STATE_START = 0x00000001,
1387PERFCOUNTER_CNT3_STATE_FREEZE = 0x00000002,
1388PERFCOUNTER_CNT3_STATE_HW = 0x00000003,
1389} PERFCOUNTER_CNT3_STATE;
1390
1391/*
1392 * PERFCOUNTER_CNT4_STATE enum
1393 */
1394
1395typedef enum PERFCOUNTER_CNT4_STATE {
1396PERFCOUNTER_CNT4_STATE_RESET = 0x00000000,
1397PERFCOUNTER_CNT4_STATE_START = 0x00000001,
1398PERFCOUNTER_CNT4_STATE_FREEZE = 0x00000002,
1399PERFCOUNTER_CNT4_STATE_HW = 0x00000003,
1400} PERFCOUNTER_CNT4_STATE;
1401
1402/*
1403 * PERFCOUNTER_CNT5_STATE enum
1404 */
1405
1406typedef enum PERFCOUNTER_CNT5_STATE {
1407PERFCOUNTER_CNT5_STATE_RESET = 0x00000000,
1408PERFCOUNTER_CNT5_STATE_START = 0x00000001,
1409PERFCOUNTER_CNT5_STATE_FREEZE = 0x00000002,
1410PERFCOUNTER_CNT5_STATE_HW = 0x00000003,
1411} PERFCOUNTER_CNT5_STATE;
1412
1413/*
1414 * PERFCOUNTER_CNT6_STATE enum
1415 */
1416
1417typedef enum PERFCOUNTER_CNT6_STATE {
1418PERFCOUNTER_CNT6_STATE_RESET = 0x00000000,
1419PERFCOUNTER_CNT6_STATE_START = 0x00000001,
1420PERFCOUNTER_CNT6_STATE_FREEZE = 0x00000002,
1421PERFCOUNTER_CNT6_STATE_HW = 0x00000003,
1422} PERFCOUNTER_CNT6_STATE;
1423
1424/*
1425 * PERFCOUNTER_CNT7_STATE enum
1426 */
1427
1428typedef enum PERFCOUNTER_CNT7_STATE {
1429PERFCOUNTER_CNT7_STATE_RESET = 0x00000000,
1430PERFCOUNTER_CNT7_STATE_START = 0x00000001,
1431PERFCOUNTER_CNT7_STATE_FREEZE = 0x00000002,
1432PERFCOUNTER_CNT7_STATE_HW = 0x00000003,
1433} PERFCOUNTER_CNT7_STATE;
1434
1435/*
1436 * PERFCOUNTER_CNTL_SEL enum
1437 */
1438
1439typedef enum PERFCOUNTER_CNTL_SEL {
1440PERFCOUNTER_CNTL_SEL_0 = 0x00000000,
1441PERFCOUNTER_CNTL_SEL_1 = 0x00000001,
1442PERFCOUNTER_CNTL_SEL_2 = 0x00000002,
1443PERFCOUNTER_CNTL_SEL_3 = 0x00000003,
1444PERFCOUNTER_CNTL_SEL_4 = 0x00000004,
1445PERFCOUNTER_CNTL_SEL_5 = 0x00000005,
1446PERFCOUNTER_CNTL_SEL_6 = 0x00000006,
1447PERFCOUNTER_CNTL_SEL_7 = 0x00000007,
1448} PERFCOUNTER_CNTL_SEL;
1449
1450/*
1451 * PERFCOUNTER_CNTOFF_START_DIS enum
1452 */
1453
1454typedef enum PERFCOUNTER_CNTOFF_START_DIS {
1455PERFCOUNTER_CNTOFF_START_ENABLE = 0x00000000,
1456PERFCOUNTER_CNTOFF_START_DISABLE = 0x00000001,
1457} PERFCOUNTER_CNTOFF_START_DIS;
1458
1459/*
1460 * PERFCOUNTER_COUNTED_VALUE_TYPE enum
1461 */
1462
1463typedef enum PERFCOUNTER_COUNTED_VALUE_TYPE {
1464PERFCOUNTER_COUNTED_VALUE_TYPE_ACC = 0x00000000,
1465PERFCOUNTER_COUNTED_VALUE_TYPE_MAX = 0x00000001,
1466PERFCOUNTER_COUNTED_VALUE_TYPE_MIN = 0x00000002,
1467} PERFCOUNTER_COUNTED_VALUE_TYPE;
1468
1469/*
1470 * PERFCOUNTER_CVALUE_SEL enum
1471 */
1472
1473typedef enum PERFCOUNTER_CVALUE_SEL {
1474PERFCOUNTER_CVALUE_SEL_47_0 = 0x00000000,
1475PERFCOUNTER_CVALUE_SEL_15_0 = 0x00000001,
1476PERFCOUNTER_CVALUE_SEL_31_16 = 0x00000002,
1477PERFCOUNTER_CVALUE_SEL_47_32 = 0x00000003,
1478PERFCOUNTER_CVALUE_SEL_11_0 = 0x00000004,
1479PERFCOUNTER_CVALUE_SEL_23_12 = 0x00000005,
1480PERFCOUNTER_CVALUE_SEL_35_24 = 0x00000006,
1481PERFCOUNTER_CVALUE_SEL_47_36 = 0x00000007,
1482} PERFCOUNTER_CVALUE_SEL;
1483
1484/*
1485 * PERFCOUNTER_HW_CNTL_SEL enum
1486 */
1487
1488typedef enum PERFCOUNTER_HW_CNTL_SEL {
1489PERFCOUNTER_HW_CNTL_SEL_RUNEN = 0x00000000,
1490PERFCOUNTER_HW_CNTL_SEL_CNTOFF = 0x00000001,
1491} PERFCOUNTER_HW_CNTL_SEL;
1492
1493/*
1494 * PERFCOUNTER_HW_STOP1_SEL enum
1495 */
1496
1497typedef enum PERFCOUNTER_HW_STOP1_SEL {
1498PERFCOUNTER_HW_STOP1_0 = 0x00000000,
1499PERFCOUNTER_HW_STOP1_1 = 0x00000001,
1500} PERFCOUNTER_HW_STOP1_SEL;
1501
1502/*
1503 * PERFCOUNTER_HW_STOP2_SEL enum
1504 */
1505
1506typedef enum PERFCOUNTER_HW_STOP2_SEL {
1507PERFCOUNTER_HW_STOP2_0 = 0x00000000,
1508PERFCOUNTER_HW_STOP2_1 = 0x00000001,
1509} PERFCOUNTER_HW_STOP2_SEL;
1510
1511/*
1512 * PERFCOUNTER_INC_MODE enum
1513 */
1514
1515typedef enum PERFCOUNTER_INC_MODE {
1516PERFCOUNTER_INC_MODE_MULTI_BIT = 0x00000000,
1517PERFCOUNTER_INC_MODE_BOTH_EDGE = 0x00000001,
1518PERFCOUNTER_INC_MODE_LSB = 0x00000002,
1519PERFCOUNTER_INC_MODE_POS_EDGE = 0x00000003,
1520PERFCOUNTER_INC_MODE_NEG_EDGE = 0x00000004,
1521} PERFCOUNTER_INC_MODE;
1522
1523/*
1524 * PERFCOUNTER_INT_EN enum
1525 */
1526
1527typedef enum PERFCOUNTER_INT_EN {
1528PERFCOUNTER_INT_DISABLE = 0x00000000,
1529PERFCOUNTER_INT_ENABLE = 0x00000001,
1530} PERFCOUNTER_INT_EN;
1531
1532/*
1533 * PERFCOUNTER_INT_TYPE enum
1534 */
1535
1536typedef enum PERFCOUNTER_INT_TYPE {
1537PERFCOUNTER_INT_TYPE_LEVEL = 0x00000000,
1538PERFCOUNTER_INT_TYPE_PULSE = 0x00000001,
1539} PERFCOUNTER_INT_TYPE;
1540
1541/*
1542 * PERFCOUNTER_OFF_MASK enum
1543 */
1544
1545typedef enum PERFCOUNTER_OFF_MASK {
1546PERFCOUNTER_OFF_MASK_DISABLE = 0x00000000,
1547PERFCOUNTER_OFF_MASK_ENABLE = 0x00000001,
1548} PERFCOUNTER_OFF_MASK;
1549
1550/*
1551 * PERFCOUNTER_RESTART_EN enum
1552 */
1553
1554typedef enum PERFCOUNTER_RESTART_EN {
1555PERFCOUNTER_RESTART_DISABLE = 0x00000000,
1556PERFCOUNTER_RESTART_ENABLE = 0x00000001,
1557} PERFCOUNTER_RESTART_EN;
1558
1559/*
1560 * PERFCOUNTER_RUNEN_MODE enum
1561 */
1562
1563typedef enum PERFCOUNTER_RUNEN_MODE {
1564PERFCOUNTER_RUNEN_MODE_LEVEL = 0x00000000,
1565PERFCOUNTER_RUNEN_MODE_EDGE = 0x00000001,
1566} PERFCOUNTER_RUNEN_MODE;
1567
1568/*
1569 * PERFCOUNTER_STATE_SEL0 enum
1570 */
1571
1572typedef enum PERFCOUNTER_STATE_SEL0 {
1573PERFCOUNTER_STATE_SEL0_GLOBAL = 0x00000000,
1574PERFCOUNTER_STATE_SEL0_LOCAL = 0x00000001,
1575} PERFCOUNTER_STATE_SEL0;
1576
1577/*
1578 * PERFCOUNTER_STATE_SEL1 enum
1579 */
1580
1581typedef enum PERFCOUNTER_STATE_SEL1 {
1582PERFCOUNTER_STATE_SEL1_GLOBAL = 0x00000000,
1583PERFCOUNTER_STATE_SEL1_LOCAL = 0x00000001,
1584} PERFCOUNTER_STATE_SEL1;
1585
1586/*
1587 * PERFCOUNTER_STATE_SEL2 enum
1588 */
1589
1590typedef enum PERFCOUNTER_STATE_SEL2 {
1591PERFCOUNTER_STATE_SEL2_GLOBAL = 0x00000000,
1592PERFCOUNTER_STATE_SEL2_LOCAL = 0x00000001,
1593} PERFCOUNTER_STATE_SEL2;
1594
1595/*
1596 * PERFCOUNTER_STATE_SEL3 enum
1597 */
1598
1599typedef enum PERFCOUNTER_STATE_SEL3 {
1600PERFCOUNTER_STATE_SEL3_GLOBAL = 0x00000000,
1601PERFCOUNTER_STATE_SEL3_LOCAL = 0x00000001,
1602} PERFCOUNTER_STATE_SEL3;
1603
1604/*
1605 * PERFCOUNTER_STATE_SEL4 enum
1606 */
1607
1608typedef enum PERFCOUNTER_STATE_SEL4 {
1609PERFCOUNTER_STATE_SEL4_GLOBAL = 0x00000000,
1610PERFCOUNTER_STATE_SEL4_LOCAL = 0x00000001,
1611} PERFCOUNTER_STATE_SEL4;
1612
1613/*
1614 * PERFCOUNTER_STATE_SEL5 enum
1615 */
1616
1617typedef enum PERFCOUNTER_STATE_SEL5 {
1618PERFCOUNTER_STATE_SEL5_GLOBAL = 0x00000000,
1619PERFCOUNTER_STATE_SEL5_LOCAL = 0x00000001,
1620} PERFCOUNTER_STATE_SEL5;
1621
1622/*
1623 * PERFCOUNTER_STATE_SEL6 enum
1624 */
1625
1626typedef enum PERFCOUNTER_STATE_SEL6 {
1627PERFCOUNTER_STATE_SEL6_GLOBAL = 0x00000000,
1628PERFCOUNTER_STATE_SEL6_LOCAL = 0x00000001,
1629} PERFCOUNTER_STATE_SEL6;
1630
1631/*
1632 * PERFCOUNTER_STATE_SEL7 enum
1633 */
1634
1635typedef enum PERFCOUNTER_STATE_SEL7 {
1636PERFCOUNTER_STATE_SEL7_GLOBAL = 0x00000000,
1637PERFCOUNTER_STATE_SEL7_LOCAL = 0x00000001,
1638} PERFCOUNTER_STATE_SEL7;
1639
1640/*
1641 * PERFMON_CNTOFF_AND_OR enum
1642 */
1643
1644typedef enum PERFMON_CNTOFF_AND_OR {
1645PERFMON_CNTOFF_OR = 0x00000000,
1646PERFMON_CNTOFF_AND = 0x00000001,
1647} PERFMON_CNTOFF_AND_OR;
1648
1649/*
1650 * PERFMON_CNTOFF_INT_EN enum
1651 */
1652
1653typedef enum PERFMON_CNTOFF_INT_EN {
1654PERFMON_CNTOFF_INT_DISABLE = 0x00000000,
1655PERFMON_CNTOFF_INT_ENABLE = 0x00000001,
1656} PERFMON_CNTOFF_INT_EN;
1657
1658/*
1659 * PERFMON_CNTOFF_INT_TYPE enum
1660 */
1661
1662typedef enum PERFMON_CNTOFF_INT_TYPE {
1663PERFMON_CNTOFF_INT_TYPE_LEVEL = 0x00000000,
1664PERFMON_CNTOFF_INT_TYPE_PULSE = 0x00000001,
1665} PERFMON_CNTOFF_INT_TYPE;
1666
1667/*
1668 * PERFMON_STATE enum
1669 */
1670
1671typedef enum PERFMON_STATE {
1672PERFMON_STATE_RESET = 0x00000000,
1673PERFMON_STATE_START = 0x00000001,
1674PERFMON_STATE_FREEZE = 0x00000002,
1675PERFMON_STATE_HW = 0x00000003,
1676} PERFMON_STATE;
1677
1678/*******************************************************
1679 * HUBP Enums
1680 *******************************************************/
1681
1682/*
1683 * BIGK_FRAGMENT_SIZE enum
1684 */
1685
1686typedef enum BIGK_FRAGMENT_SIZE {
1687VM_PG_SIZE_4KB = 0x00000000,
1688VM_PG_SIZE_8KB = 0x00000001,
1689VM_PG_SIZE_16KB = 0x00000002,
1690VM_PG_SIZE_32KB = 0x00000003,
1691VM_PG_SIZE_64KB = 0x00000004,
1692VM_PG_SIZE_128KB = 0x00000005,
1693VM_PG_SIZE_256KB = 0x00000006,
1694VM_PG_SIZE_512KB = 0x00000007,
1695VM_PG_SIZE_1024KB = 0x00000008,
1696VM_PG_SIZE_2048KB = 0x00000009,
1697} BIGK_FRAGMENT_SIZE;
1698
1699/*
1700 * CHUNK_SIZE enum
1701 */
1702
1703typedef enum CHUNK_SIZE {
1704CHUNK_SIZE_1KB = 0x00000000,
1705CHUNK_SIZE_2KB = 0x00000001,
1706CHUNK_SIZE_4KB = 0x00000002,
1707CHUNK_SIZE_8KB = 0x00000003,
1708CHUNK_SIZE_16KB = 0x00000004,
1709CHUNK_SIZE_32KB = 0x00000005,
1710CHUNK_SIZE_64KB = 0x00000006,
1711} CHUNK_SIZE;
1712
1713/*
1714 * COMPAT_LEVEL enum
1715 */
1716
1717typedef enum COMPAT_LEVEL {
1718ADDR_GEN_ZERO = 0x00000000,
1719ADDR_GEN_ONE = 0x00000001,
1720ADDR_GEN_TWO = 0x00000002,
1721ADDR_RESERVED = 0x00000003,
1722} COMPAT_LEVEL;
1723
1724/*
1725 * DPTE_GROUP_SIZE enum
1726 */
1727
1728typedef enum DPTE_GROUP_SIZE {
1729DPTE_GROUP_SIZE_64B = 0x00000000,
1730DPTE_GROUP_SIZE_128B = 0x00000001,
1731DPTE_GROUP_SIZE_256B = 0x00000002,
1732DPTE_GROUP_SIZE_512B = 0x00000003,
1733DPTE_GROUP_SIZE_1024B = 0x00000004,
1734DPTE_GROUP_SIZE_2048B = 0x00000005,
1735} DPTE_GROUP_SIZE;
1736
1737/*
1738 * FORCE_ONE_ROW_FOR_FRAME enum
1739 */
1740
1741typedef enum FORCE_ONE_ROW_FOR_FRAME {
1742FORCE_ONE_ROW_FOR_FRAME_0 = 0x00000000,
1743FORCE_ONE_ROW_FOR_FRAME_1 = 0x00000001,
1744} FORCE_ONE_ROW_FOR_FRAME;
1745
1746/*
1747 * HUBP_BLANK_EN enum
1748 */
1749
1750typedef enum HUBP_BLANK_EN {
1751HUBP_BLANK_SW_DEASSERT = 0x00000000,
1752HUBP_BLANK_SW_ASSERT = 0x00000001,
1753} HUBP_BLANK_EN;
1754
1755/*
1756 * HUBP_IN_BLANK enum
1757 */
1758
1759typedef enum HUBP_IN_BLANK {
1760HUBP_IN_ACTIVE = 0x00000000,
1761HUBP_IN_VBLANK = 0x00000001,
1762} HUBP_IN_BLANK;
1763
1764/*
1765 * HUBP_MEASURE_WIN_MODE_DCFCLK enum
1766 */
1767
1768typedef enum HUBP_MEASURE_WIN_MODE_DCFCLK {
1769HUBP_MEASURE_WIN_MODE_DCFCLK_0 = 0x00000000,
1770HUBP_MEASURE_WIN_MODE_DCFCLK_1 = 0x00000001,
1771HUBP_MEASURE_WIN_MODE_DCFCLK_2 = 0x00000002,
1772HUBP_MEASURE_WIN_MODE_DCFCLK_3 = 0x00000003,
1773} HUBP_MEASURE_WIN_MODE_DCFCLK;
1774
1775/*
1776 * HUBP_NO_OUTSTANDING_REQ enum
1777 */
1778
1779typedef enum HUBP_NO_OUTSTANDING_REQ {
1780OUTSTANDING_REQ = 0x00000000,
1781NO_OUTSTANDING_REQ = 0x00000001,
1782} HUBP_NO_OUTSTANDING_REQ;
1783
1784/*
1785 * HUBP_SOFT_RESET enum
1786 */
1787
1788typedef enum HUBP_SOFT_RESET {
1789HUBP_SOFT_RESET_ON = 0x00000000,
1790HUBP_SOFT_RESET_OFF = 0x00000001,
1791} HUBP_SOFT_RESET;
1792
1793/*
1794 * HUBP_TTU_DISABLE enum
1795 */
1796
1797typedef enum HUBP_TTU_DISABLE {
1798HUBP_TTU_ENABLED = 0x00000000,
1799HUBP_TTU_DISABLED = 0x00000001,
1800} HUBP_TTU_DISABLE;
1801
1802/*
1803 * HUBP_VREADY_AT_OR_AFTER_VSYNC enum
1804 */
1805
1806typedef enum HUBP_VREADY_AT_OR_AFTER_VSYNC {
1807VREADY_BEFORE_VSYNC = 0x00000000,
1808VREADY_AT_OR_AFTER_VSYNC = 0x00000001,
1809} HUBP_VREADY_AT_OR_AFTER_VSYNC;
1810
1811/*
1812 * HUBP_VTG_SEL enum
1813 */
1814
1815typedef enum HUBP_VTG_SEL {
1816VTG_SEL_0 = 0x00000000,
1817VTG_SEL_1 = 0x00000001,
1818VTG_SEL_2 = 0x00000002,
1819VTG_SEL_3 = 0x00000003,
1820VTG_SEL_4 = 0x00000004,
1821VTG_SEL_5 = 0x00000005,
1822} HUBP_VTG_SEL;
1823
1824/*
1825 * H_MIRROR_EN enum
1826 */
1827
1828typedef enum H_MIRROR_EN {
1829HW_MIRRORING_DISABLE = 0x00000000,
1830HW_MIRRORING_ENABLE = 0x00000001,
1831} H_MIRROR_EN;
1832
1833/*
1834 * LEGACY_PIPE_INTERLEAVE enum
1835 */
1836
1837typedef enum LEGACY_PIPE_INTERLEAVE {
1838LEGACY_PIPE_INTERLEAVE_256B = 0x00000000,
1839LEGACY_PIPE_INTERLEAVE_512B = 0x00000001,
1840} LEGACY_PIPE_INTERLEAVE;
1841
1842/*
1843 * META_CHUNK_SIZE enum
1844 */
1845
1846typedef enum META_CHUNK_SIZE {
1847META_CHUNK_SIZE_1KB = 0x00000000,
1848META_CHUNK_SIZE_2KB = 0x00000001,
1849META_CHUNK_SIZE_4KB = 0x00000002,
1850META_CHUNK_SIZE_8KB = 0x00000003,
1851} META_CHUNK_SIZE;
1852
1853/*
1854 * META_LINEAR enum
1855 */
1856
1857typedef enum META_LINEAR {
1858META_SURF_TILED = 0x00000000,
1859META_SURF_LINEAR = 0x00000001,
1860} META_LINEAR;
1861
1862/*
1863 * MIN_CHUNK_SIZE enum
1864 */
1865
1866typedef enum MIN_CHUNK_SIZE {
1867NO_MIN_CHUNK_SIZE = 0x00000000,
1868MIN_CHUNK_SIZE_256B = 0x00000001,
1869MIN_CHUNK_SIZE_512B = 0x00000002,
1870MIN_CHUNK_SIZE_1024B = 0x00000003,
1871} MIN_CHUNK_SIZE;
1872
1873/*
1874 * MIN_META_CHUNK_SIZE enum
1875 */
1876
1877typedef enum MIN_META_CHUNK_SIZE {
1878NO_MIN_META_CHUNK_SIZE = 0x00000000,
1879MIN_META_CHUNK_SIZE_64B = 0x00000001,
1880MIN_META_CHUNK_SIZE_128B = 0x00000002,
1881MIN_META_CHUNK_SIZE_256B = 0x00000003,
1882} MIN_META_CHUNK_SIZE;
1883
1884/*
1885 * PIPE_ALIGNED enum
1886 */
1887
1888typedef enum PIPE_ALIGNED {
1889PIPE_UNALIGNED_SURF = 0x00000000,
1890PIPE_ALIGNED_SURF = 0x00000001,
1891} PIPE_ALIGNED;
1892
1893/*
1894 * PTE_BUFFER_MODE enum
1895 */
1896
1897typedef enum PTE_BUFFER_MODE {
1898PTE_BUFFER_MODE_0 = 0x00000000,
1899PTE_BUFFER_MODE_1 = 0x00000001,
1900} PTE_BUFFER_MODE;
1901
1902/*
1903 * PTE_ROW_HEIGHT_LINEAR enum
1904 */
1905
1906typedef enum PTE_ROW_HEIGHT_LINEAR {
1907PTE_ROW_HEIGHT_LINEAR_8L = 0x00000000,
1908PTE_ROW_HEIGHT_LINEAR_16L = 0x00000001,
1909PTE_ROW_HEIGHT_LINEAR_32L = 0x00000002,
1910PTE_ROW_HEIGHT_LINEAR_64L = 0x00000003,
1911PTE_ROW_HEIGHT_LINEAR_128L = 0x00000004,
1912PTE_ROW_HEIGHT_LINEAR_256L = 0x00000005,
1913PTE_ROW_HEIGHT_LINEAR_512L = 0x00000006,
1914PTE_ROW_HEIGHT_LINEAR_1024L = 0x00000007,
1915} PTE_ROW_HEIGHT_LINEAR;
1916
1917/*
1918 * ROTATION_ANGLE enum
1919 */
1920
1921typedef enum ROTATION_ANGLE {
1922ROTATE_0_DEGREES = 0x00000000,
1923ROTATE_90_DEGREES = 0x00000001,
1924ROTATE_180_DEGREES = 0x00000002,
1925ROTATE_270_DEGREES = 0x00000003,
1926} ROTATION_ANGLE;
1927
1928/*
1929 * SWATH_HEIGHT enum
1930 */
1931
1932typedef enum SWATH_HEIGHT {
1933SWATH_HEIGHT_1L = 0x00000000,
1934SWATH_HEIGHT_2L = 0x00000001,
1935SWATH_HEIGHT_4L = 0x00000002,
1936SWATH_HEIGHT_8L = 0x00000003,
1937SWATH_HEIGHT_16L = 0x00000004,
1938} SWATH_HEIGHT;
1939
1940/*
1941 * USE_MALL_FOR_CURSOR enum
1942 */
1943
1944typedef enum USE_MALL_FOR_CURSOR {
1945USE_MALL_FOR_CURSOR_0 = 0x00000000,
1946USE_MALL_FOR_CURSOR_1 = 0x00000001,
1947} USE_MALL_FOR_CURSOR;
1948
1949/*
1950 * USE_MALL_FOR_PSTATE_CHANGE enum
1951 */
1952
1953typedef enum USE_MALL_FOR_PSTATE_CHANGE {
1954USE_MALL_FOR_PSTATE_CHANGE_0 = 0x00000000,
1955USE_MALL_FOR_PSTATE_CHANGE_1 = 0x00000001,
1956} USE_MALL_FOR_PSTATE_CHANGE;
1957
1958/*
1959 * USE_MALL_FOR_STATIC_SCREEN enum
1960 */
1961
1962typedef enum USE_MALL_FOR_STATIC_SCREEN {
1963USE_MALL_FOR_STATIC_SCREEN_0 = 0x00000000,
1964USE_MALL_FOR_STATIC_SCREEN_1 = 0x00000001,
1965} USE_MALL_FOR_STATIC_SCREEN;
1966
1967/*
1968 * VMPG_SIZE enum
1969 */
1970
1971typedef enum VMPG_SIZE {
1972VMPG_SIZE_4KB = 0x00000000,
1973VMPG_SIZE_64KB = 0x00000001,
1974} VMPG_SIZE;
1975
1976/*
1977 * VM_GROUP_SIZE enum
1978 */
1979
1980typedef enum VM_GROUP_SIZE {
1981VM_GROUP_SIZE_64B = 0x00000000,
1982VM_GROUP_SIZE_128B = 0x00000001,
1983VM_GROUP_SIZE_256B = 0x00000002,
1984VM_GROUP_SIZE_512B = 0x00000003,
1985VM_GROUP_SIZE_1024B = 0x00000004,
1986VM_GROUP_SIZE_2048B = 0x00000005,
1987} VM_GROUP_SIZE;
1988
1989/*******************************************************
1990 * HUBPREQ Enums
1991 *******************************************************/
1992
1993/*
1994 * DFQ_MIN_FREE_ENTRIES enum
1995 */
1996
1997typedef enum DFQ_MIN_FREE_ENTRIES {
1998DFQ_MIN_FREE_ENTRIES_0 = 0x00000000,
1999DFQ_MIN_FREE_ENTRIES_1 = 0x00000001,
2000DFQ_MIN_FREE_ENTRIES_2 = 0x00000002,
2001DFQ_MIN_FREE_ENTRIES_3 = 0x00000003,
2002DFQ_MIN_FREE_ENTRIES_4 = 0x00000004,
2003DFQ_MIN_FREE_ENTRIES_5 = 0x00000005,
2004DFQ_MIN_FREE_ENTRIES_6 = 0x00000006,
2005DFQ_MIN_FREE_ENTRIES_7 = 0x00000007,
2006} DFQ_MIN_FREE_ENTRIES;
2007
2008/*
2009 * DFQ_NUM_ENTRIES enum
2010 */
2011
2012typedef enum DFQ_NUM_ENTRIES {
2013DFQ_NUM_ENTRIES_0 = 0x00000000,
2014DFQ_NUM_ENTRIES_1 = 0x00000001,
2015DFQ_NUM_ENTRIES_2 = 0x00000002,
2016DFQ_NUM_ENTRIES_3 = 0x00000003,
2017DFQ_NUM_ENTRIES_4 = 0x00000004,
2018DFQ_NUM_ENTRIES_5 = 0x00000005,
2019DFQ_NUM_ENTRIES_6 = 0x00000006,
2020DFQ_NUM_ENTRIES_7 = 0x00000007,
2021DFQ_NUM_ENTRIES_8 = 0x00000008,
2022} DFQ_NUM_ENTRIES;
2023
2024/*
2025 * DFQ_SIZE enum
2026 */
2027
2028typedef enum DFQ_SIZE {
2029DFQ_SIZE_0 = 0x00000000,
2030DFQ_SIZE_1 = 0x00000001,
2031DFQ_SIZE_2 = 0x00000002,
2032DFQ_SIZE_3 = 0x00000003,
2033DFQ_SIZE_4 = 0x00000004,
2034DFQ_SIZE_5 = 0x00000005,
2035DFQ_SIZE_6 = 0x00000006,
2036DFQ_SIZE_7 = 0x00000007,
2037} DFQ_SIZE;
2038
2039/*
2040 * DMDATA_VM_DONE enum
2041 */
2042
2043typedef enum DMDATA_VM_DONE {
2044DMDATA_VM_IS_NOT_DONE = 0x00000000,
2045DMDATA_VM_IS_DONE = 0x00000001,
2046} DMDATA_VM_DONE;
2047
2048/*
2049 * EXPANSION_MODE enum
2050 */
2051
2052typedef enum EXPANSION_MODE {
2053EXPANSION_MODE_ZERO = 0x00000000,
2054EXPANSION_MODE_CONSERVATIVE = 0x00000001,
2055EXPANSION_MODE_OPTIMAL = 0x00000002,
2056} EXPANSION_MODE;
2057
2058/*
2059 * FLIP_RATE enum
2060 */
2061
2062typedef enum FLIP_RATE {
2063FLIP_RATE_0 = 0x00000000,
2064FLIP_RATE_1 = 0x00000001,
2065FLIP_RATE_2 = 0x00000002,
2066FLIP_RATE_3 = 0x00000003,
2067FLIP_RATE_4 = 0x00000004,
2068FLIP_RATE_5 = 0x00000005,
2069FLIP_RATE_6 = 0x00000006,
2070FLIP_RATE_7 = 0x00000007,
2071} FLIP_RATE;
2072
2073/*
2074 * INT_MASK enum
2075 */
2076
2077typedef enum INT_MASK {
2078INT_DISABLED = 0x00000000,
2079INT_ENABLED = 0x00000001,
2080} INT_MASK;
2081
2082/*
2083 * PIPE_IN_FLUSH_URGENT enum
2084 */
2085
2086typedef enum PIPE_IN_FLUSH_URGENT {
2087PIPE_IN_FLUSH_URGENT_ENABLE = 0x00000000,
2088PIPE_IN_FLUSH_URGENT_DISABLE = 0x00000001,
2089} PIPE_IN_FLUSH_URGENT;
2090
2091/*
2092 * PRQ_MRQ_FLUSH_URGENT enum
2093 */
2094
2095typedef enum PRQ_MRQ_FLUSH_URGENT {
2096PRQ_MRQ_FLUSH_URGENT_ENABLE = 0x00000000,
2097PRQ_MRQ_FLUSH_URGENT_DISABLE = 0x00000001,
2098} PRQ_MRQ_FLUSH_URGENT;
2099
2100/*
2101 * ROW_TTU_MODE enum
2102 */
2103
2104typedef enum ROW_TTU_MODE {
2105END_OF_ROW_MODE = 0x00000000,
2106WATERMARK_MODE = 0x00000001,
2107} ROW_TTU_MODE;
2108
2109/*
2110 * SURFACE_DCC enum
2111 */
2112
2113typedef enum SURFACE_DCC {
2114SURFACE_IS_NOT_DCC = 0x00000000,
2115SURFACE_IS_DCC = 0x00000001,
2116} SURFACE_DCC;
2117
2118/*
2119 * SURFACE_DCC_IND_128B enum
2120 */
2121
2122typedef enum SURFACE_DCC_IND_128B {
2123SURFACE_DCC_IS_NOT_IND_128B = 0x00000000,
2124SURFACE_DCC_IS_IND_128B = 0x00000001,
2125} SURFACE_DCC_IND_128B;
2126
2127/*
2128 * SURFACE_DCC_IND_64B enum
2129 */
2130
2131typedef enum SURFACE_DCC_IND_64B {
2132SURFACE_DCC_IS_NOT_IND_64B = 0x00000000,
2133SURFACE_DCC_IS_IND_64B = 0x00000001,
2134} SURFACE_DCC_IND_64B;
2135
2136/*
2137 * SURFACE_DCC_IND_BLK enum
2138 */
2139
2140typedef enum SURFACE_DCC_IND_BLK {
2141SURFACE_DCC_BLOCK_IS_UNCONSTRAINED = 0x00000000,
2142SURFACE_DCC_BLOCK_IS_IND_64B = 0x00000001,
2143SURFACE_DCC_BLOCK_IS_IND_128B = 0x00000002,
2144SURFACE_DCC_BLOCK_IS_IND_64B_NO_128BCL = 0x00000003,
2145} SURFACE_DCC_IND_BLK;
2146
2147/*
2148 * SURFACE_FLIP_AWAY_INT_TYPE enum
2149 */
2150
2151typedef enum SURFACE_FLIP_AWAY_INT_TYPE {
2152SURFACE_FLIP_AWAY_INT_LEVEL = 0x00000000,
2153SURFACE_FLIP_AWAY_INT_PULSE = 0x00000001,
2154} SURFACE_FLIP_AWAY_INT_TYPE;
2155
2156/*
2157 * SURFACE_FLIP_EXEC_DEBUG_MODE enum
2158 */
2159
2160typedef enum SURFACE_FLIP_EXEC_DEBUG_MODE {
2161SURFACE_FLIP_EXEC_NORMAL_MODE = 0x00000000,
2162SURFACE_FLIP_EXEC_DEBUG_MODE_ENABLE = 0x00000001,
2163} SURFACE_FLIP_EXEC_DEBUG_MODE;
2164
2165/*
2166 * SURFACE_FLIP_INT_TYPE enum
2167 */
2168
2169typedef enum SURFACE_FLIP_INT_TYPE {
2170SURFACE_FLIP_INT_LEVEL = 0x00000000,
2171SURFACE_FLIP_INT_PULSE = 0x00000001,
2172} SURFACE_FLIP_INT_TYPE;
2173
2174/*
2175 * SURFACE_FLIP_IN_STEREOSYNC enum
2176 */
2177
2178typedef enum SURFACE_FLIP_IN_STEREOSYNC {
2179SURFACE_FLIP_NOT_IN_STEREOSYNC_MODE = 0x00000000,
2180SURFACE_FLIP_IN_STEREOSYNC_MODE = 0x00000001,
2181} SURFACE_FLIP_IN_STEREOSYNC;
2182
2183/*
2184 * SURFACE_FLIP_MODE_FOR_STEREOSYNC enum
2185 */
2186
2187typedef enum SURFACE_FLIP_MODE_FOR_STEREOSYNC {
2188FLIP_ANY_FRAME = 0x00000000,
2189FLIP_LEFT_EYE = 0x00000001,
2190FLIP_RIGHT_EYE = 0x00000002,
2191SURFACE_FLIP_MODE_FOR_STEREOSYNC_RESERVED = 0x00000003,
2192} SURFACE_FLIP_MODE_FOR_STEREOSYNC;
2193
2194/*
2195 * SURFACE_FLIP_STEREO_SELECT_DISABLE enum
2196 */
2197
2198typedef enum SURFACE_FLIP_STEREO_SELECT_DISABLE {
2199SURFACE_FLIP_STEREO_SELECT_ENABLED = 0x00000000,
2200SURFACE_FLIP_STEREO_SELECT_DISABLED = 0x00000001,
2201} SURFACE_FLIP_STEREO_SELECT_DISABLE;
2202
2203/*
2204 * SURFACE_FLIP_STEREO_SELECT_POLARITY enum
2205 */
2206
2207typedef enum SURFACE_FLIP_STEREO_SELECT_POLARITY {
2208SURFACE_FLIP_STEREO_SELECT_POLARITY_NOT_INVERT = 0x00000000,
2209SURFACE_FLIP_STEREO_SELECT_POLARITY_INVERT = 0x00000001,
2210} SURFACE_FLIP_STEREO_SELECT_POLARITY;
2211
2212/*
2213 * SURFACE_FLIP_TYPE enum
2214 */
2215
2216typedef enum SURFACE_FLIP_TYPE {
2217SURFACE_V_FLIP = 0x00000000,
2218SURFACE_I_FLIP = 0x00000001,
2219} SURFACE_FLIP_TYPE;
2220
2221/*
2222 * SURFACE_FLIP_VUPDATE_SKIP_NUM enum
2223 */
2224
2225typedef enum SURFACE_FLIP_VUPDATE_SKIP_NUM {
2226SURFACE_FLIP_VUPDATE_SKIP_NUM_0 = 0x00000000,
2227SURFACE_FLIP_VUPDATE_SKIP_NUM_1 = 0x00000001,
2228SURFACE_FLIP_VUPDATE_SKIP_NUM_2 = 0x00000002,
2229SURFACE_FLIP_VUPDATE_SKIP_NUM_3 = 0x00000003,
2230SURFACE_FLIP_VUPDATE_SKIP_NUM_4 = 0x00000004,
2231SURFACE_FLIP_VUPDATE_SKIP_NUM_5 = 0x00000005,
2232SURFACE_FLIP_VUPDATE_SKIP_NUM_6 = 0x00000006,
2233SURFACE_FLIP_VUPDATE_SKIP_NUM_7 = 0x00000007,
2234SURFACE_FLIP_VUPDATE_SKIP_NUM_8 = 0x00000008,
2235SURFACE_FLIP_VUPDATE_SKIP_NUM_9 = 0x00000009,
2236SURFACE_FLIP_VUPDATE_SKIP_NUM_10 = 0x0000000a,
2237SURFACE_FLIP_VUPDATE_SKIP_NUM_11 = 0x0000000b,
2238SURFACE_FLIP_VUPDATE_SKIP_NUM_12 = 0x0000000c,
2239SURFACE_FLIP_VUPDATE_SKIP_NUM_13 = 0x0000000d,
2240SURFACE_FLIP_VUPDATE_SKIP_NUM_14 = 0x0000000e,
2241SURFACE_FLIP_VUPDATE_SKIP_NUM_15 = 0x0000000f,
2242} SURFACE_FLIP_VUPDATE_SKIP_NUM;
2243
2244/*
2245 * SURFACE_INUSE_RAED_NO_LATCH enum
2246 */
2247
2248typedef enum SURFACE_INUSE_RAED_NO_LATCH {
2249SURFACE_INUSE_IS_LATCHED = 0x00000000,
2250SURFACE_INUSE_IS_NOT_LATCHED = 0x00000001,
2251} SURFACE_INUSE_RAED_NO_LATCH;
2252
2253/*
2254 * SURFACE_TMZ enum
2255 */
2256
2257typedef enum SURFACE_TMZ {
2258SURFACE_IS_NOT_TMZ = 0x00000000,
2259SURFACE_IS_TMZ = 0x00000001,
2260} SURFACE_TMZ;
2261
2262/*
2263 * SURFACE_UPDATE_LOCK enum
2264 */
2265
2266typedef enum SURFACE_UPDATE_LOCK {
2267SURFACE_UPDATE_IS_UNLOCKED = 0x00000000,
2268SURFACE_UPDATE_IS_LOCKED = 0x00000001,
2269} SURFACE_UPDATE_LOCK;
2270
2271/*******************************************************
2272 * HUBPRET Enums
2273 *******************************************************/
2274
2275/*
2276 * CROSSBAR_FOR_ALPHA enum
2277 */
2278
2279typedef enum CROSSBAR_FOR_ALPHA {
2280ALPHA_DATA_ONTO_ALPHA_PORT = 0x00000000,
2281Y_G_DATA_ONTO_ALPHA_PORT = 0x00000001,
2282CB_B_DATA_ONTO_ALPHA_PORT = 0x00000002,
2283CR_R_DATA_ONTO_ALPHA_PORT = 0x00000003,
2284} CROSSBAR_FOR_ALPHA;
2285
2286/*
2287 * CROSSBAR_FOR_CB_B enum
2288 */
2289
2290typedef enum CROSSBAR_FOR_CB_B {
2291ALPHA_DATA_ONTO_CB_B_PORT = 0x00000000,
2292Y_G_DATA_ONTO_CB_B_PORT = 0x00000001,
2293CB_B_DATA_ONTO_CB_B_PORT = 0x00000002,
2294CR_R_DATA_ONTO_CB_B_PORT = 0x00000003,
2295} CROSSBAR_FOR_CB_B;
2296
2297/*
2298 * CROSSBAR_FOR_CR_R enum
2299 */
2300
2301typedef enum CROSSBAR_FOR_CR_R {
2302ALPHA_DATA_ONTO_CR_R_PORT = 0x00000000,
2303Y_G_DATA_ONTO_CR_R_PORT = 0x00000001,
2304CB_B_DATA_ONTO_CR_R_PORT = 0x00000002,
2305CR_R_DATA_ONTO_CR_R_PORT = 0x00000003,
2306} CROSSBAR_FOR_CR_R;
2307
2308/*
2309 * CROSSBAR_FOR_Y_G enum
2310 */
2311
2312typedef enum CROSSBAR_FOR_Y_G {
2313ALPHA_DATA_ONTO_Y_G_PORT = 0x00000000,
2314Y_G_DATA_ONTO_Y_G_PORT = 0x00000001,
2315CB_B_DATA_ONTO_Y_G_PORT = 0x00000002,
2316CR_R_DATA_ONTO_Y_G_PORT = 0x00000003,
2317} CROSSBAR_FOR_Y_G;
2318
2319/*
2320 * DETILE_BUFFER_PACKER_ENABLE enum
2321 */
2322
2323typedef enum DETILE_BUFFER_PACKER_ENABLE {
2324DETILE_BUFFER_PACKER_IS_DISABLE = 0x00000000,
2325DETILE_BUFFER_PACKER_IS_ENABLE = 0x00000001,
2326} DETILE_BUFFER_PACKER_ENABLE;
2327
2328/*
2329 * MEM_PWR_DIS_MODE enum
2330 */
2331
2332typedef enum MEM_PWR_DIS_MODE {
2333MEM_POWER_DIS_MODE_ENABLE = 0x00000000,
2334MEM_POWER_DIS_MODE_DISABLE = 0x00000001,
2335} MEM_PWR_DIS_MODE;
2336
2337/*
2338 * MEM_PWR_FORCE_MODE enum
2339 */
2340
2341typedef enum MEM_PWR_FORCE_MODE {
2342MEM_POWER_FORCE_MODE_OFF = 0x00000000,
2343MEM_POWER_FORCE_MODE_LIGHT_SLEEP = 0x00000001,
2344MEM_POWER_FORCE_MODE_DEEP_SLEEP = 0x00000002,
2345MEM_POWER_FORCE_MODE_SHUT_DOWN = 0x00000003,
2346} MEM_PWR_FORCE_MODE;
2347
2348/*
2349 * MEM_PWR_STATUS enum
2350 */
2351
2352typedef enum MEM_PWR_STATUS {
2353MEM_POWER_STATUS_ON = 0x00000000,
2354MEM_POWER_STATUS_LIGHT_SLEEP = 0x00000001,
2355MEM_POWER_STATUS_DEEP_SLEEP = 0x00000002,
2356MEM_POWER_STATUS_SHUT_DOWN = 0x00000003,
2357} MEM_PWR_STATUS;
2358
2359/*
2360 * PIPE_INT_MASK_MODE enum
2361 */
2362
2363typedef enum PIPE_INT_MASK_MODE {
2364PIPE_INT_MASK_MODE_DISABLE = 0x00000000,
2365PIPE_INT_MASK_MODE_ENABLE = 0x00000001,
2366} PIPE_INT_MASK_MODE;
2367
2368/*
2369 * PIPE_INT_TYPE_MODE enum
2370 */
2371
2372typedef enum PIPE_INT_TYPE_MODE {
2373PIPE_INT_TYPE_MODE_DISABLE = 0x00000000,
2374PIPE_INT_TYPE_MODE_ENABLE = 0x00000001,
2375} PIPE_INT_TYPE_MODE;
2376
2377/*
2378 * PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE enum
2379 */
2380
2381typedef enum PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE {
2382PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000,
2383PIXCDC_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001,
2384} PIXCDC_MEM_PWR_LIGHT_SLEEP_MODE;
2385
2386/*******************************************************
2387 * CURSOR Enums
2388 *******************************************************/
2389
2390/*
2391 * CROB_MEM_PWR_LIGHT_SLEEP_MODE enum
2392 */
2393
2394typedef enum CROB_MEM_PWR_LIGHT_SLEEP_MODE {
2395CROB_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000,
2396CROB_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001,
2397CROB_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002,
2398} CROB_MEM_PWR_LIGHT_SLEEP_MODE;
2399
2400/*
2401 * CURSOR_2X_MAGNIFY enum
2402 */
2403
2404typedef enum CURSOR_2X_MAGNIFY {
2405CURSOR_2X_MAGNIFY_IS_DISABLE = 0x00000000,
2406CURSOR_2X_MAGNIFY_IS_ENABLE = 0x00000001,
2407} CURSOR_2X_MAGNIFY;
2408
2409/*
2410 * CURSOR_ENABLE enum
2411 */
2412
2413typedef enum CURSOR_ENABLE {
2414CURSOR_IS_DISABLE = 0x00000000,
2415CURSOR_IS_ENABLE = 0x00000001,
2416} CURSOR_ENABLE;
2417
2418/*
2419 * CURSOR_LINES_PER_CHUNK enum
2420 */
2421
2422typedef enum CURSOR_LINES_PER_CHUNK {
2423CURSOR_LINE_PER_CHUNK_1 = 0x00000000,
2424CURSOR_LINE_PER_CHUNK_2 = 0x00000001,
2425CURSOR_LINE_PER_CHUNK_4 = 0x00000002,
2426CURSOR_LINE_PER_CHUNK_8 = 0x00000003,
2427CURSOR_LINE_PER_CHUNK_16 = 0x00000004,
2428} CURSOR_LINES_PER_CHUNK;
2429
2430/*
2431 * CURSOR_MODE enum
2432 */
2433
2434typedef enum CURSOR_MODE {
2435CURSOR_MONO_2BIT = 0x00000000,
2436CURSOR_COLOR_24BIT_1BIT_AND = 0x00000001,
2437CURSOR_COLOR_24BIT_8BIT_ALPHA_PREMULT = 0x00000002,
2438CURSOR_COLOR_24BIT_8BIT_ALPHA_UNPREMULT = 0x00000003,
2439CURSOR_COLOR_64BIT_FP_PREMULT = 0x00000004,
2440CURSOR_COLOR_64BIT_FP_UNPREMULT = 0x00000005,
2441} CURSOR_MODE;
2442
2443/*
2444 * CURSOR_PERFMON_LATENCY_MEASURE_EN enum
2445 */
2446
2447typedef enum CURSOR_PERFMON_LATENCY_MEASURE_EN {
2448CURSOR_PERFMON_LATENCY_MEASURE_IS_DISABLED = 0x00000000,
2449CURSOR_PERFMON_LATENCY_MEASURE_IS_ENABLED = 0x00000001,
2450} CURSOR_PERFMON_LATENCY_MEASURE_EN;
2451
2452/*
2453 * CURSOR_PERFMON_LATENCY_MEASURE_SEL enum
2454 */
2455
2456typedef enum CURSOR_PERFMON_LATENCY_MEASURE_SEL {
2457CURSOR_PERFMON_LATENCY_MEASURE_MC_LATENCY = 0x00000000,
2458CURSOR_PERFMON_LATENCY_MEASURE_CROB_LATENCY = 0x00000001,
2459} CURSOR_PERFMON_LATENCY_MEASURE_SEL;
2460
2461/*
2462 * CURSOR_PITCH enum
2463 */
2464
2465typedef enum CURSOR_PITCH {
2466CURSOR_PITCH_64_PIXELS = 0x00000000,
2467CURSOR_PITCH_128_PIXELS = 0x00000001,
2468CURSOR_PITCH_256_PIXELS = 0x00000002,
2469} CURSOR_PITCH;
2470
2471/*
2472 * CURSOR_REQ_MODE enum
2473 */
2474
2475typedef enum CURSOR_REQ_MODE {
2476CURSOR_REQUEST_NORMALLY = 0x00000000,
2477CURSOR_REQUEST_EARLY = 0x00000001,
2478} CURSOR_REQ_MODE;
2479
2480/*
2481 * CURSOR_SNOOP enum
2482 */
2483
2484typedef enum CURSOR_SNOOP {
2485CURSOR_IS_NOT_SNOOP = 0x00000000,
2486CURSOR_IS_SNOOP = 0x00000001,
2487} CURSOR_SNOOP;
2488
2489/*
2490 * CURSOR_STEREO_EN enum
2491 */
2492
2493typedef enum CURSOR_STEREO_EN {
2494CURSOR_STEREO_IS_DISABLED = 0x00000000,
2495CURSOR_STEREO_IS_ENABLED = 0x00000001,
2496} CURSOR_STEREO_EN;
2497
2498/*
2499 * CURSOR_SURFACE_TMZ enum
2500 */
2501
2502typedef enum CURSOR_SURFACE_TMZ {
2503CURSOR_SURFACE_IS_NOT_TMZ = 0x00000000,
2504CURSOR_SURFACE_IS_TMZ = 0x00000001,
2505} CURSOR_SURFACE_TMZ;
2506
2507/*
2508 * CURSOR_SYSTEM enum
2509 */
2510
2511typedef enum CURSOR_SYSTEM {
2512CURSOR_IN_SYSTEM_PHYSICAL_ADDRESS = 0x00000000,
2513CURSOR_IN_GUEST_PHYSICAL_ADDRESS = 0x00000001,
2514} CURSOR_SYSTEM;
2515
2516/*
2517 * CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS enum
2518 */
2519
2520typedef enum CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS {
2521CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_0 = 0x00000000,
2522CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS_1 = 0x00000001,
2523} CURSOR_XY_POSITION_ROTATION_AND_MIRRORING_BYPASS;
2524
2525/*
2526 * DMDATA_DONE enum
2527 */
2528
2529typedef enum DMDATA_DONE {
2530DMDATA_NOT_SENT_TO_DIG = 0x00000000,
2531DMDATA_SENT_TO_DIG = 0x00000001,
2532} DMDATA_DONE;
2533
2534/*
2535 * DMDATA_MODE enum
2536 */
2537
2538typedef enum DMDATA_MODE {
2539DMDATA_SOFTWARE_UPDATE_MODE = 0x00000000,
2540DMDATA_HARDWARE_UPDATE_MODE = 0x00000001,
2541} DMDATA_MODE;
2542
2543/*
2544 * DMDATA_QOS_MODE enum
2545 */
2546
2547typedef enum DMDATA_QOS_MODE {
2548DMDATA_QOS_LEVEL_FROM_TTU = 0x00000000,
2549DMDATA_QOS_LEVEL_FROM_SOFTWARE = 0x00000001,
2550} DMDATA_QOS_MODE;
2551
2552/*
2553 * DMDATA_REPEAT enum
2554 */
2555
2556typedef enum DMDATA_REPEAT {
2557DMDATA_USE_FOR_CURRENT_FRAME_ONLY = 0x00000000,
2558DMDATA_USE_FOR_CURRENT_AND_FUTURE_FRAMES = 0x00000001,
2559} DMDATA_REPEAT;
2560
2561/*
2562 * DMDATA_UNDERFLOW enum
2563 */
2564
2565typedef enum DMDATA_UNDERFLOW {
2566DMDATA_NOT_UNDERFLOW = 0x00000000,
2567DMDATA_UNDERFLOWED = 0x00000001,
2568} DMDATA_UNDERFLOW;
2569
2570/*
2571 * DMDATA_UNDERFLOW_CLEAR enum
2572 */
2573
2574typedef enum DMDATA_UNDERFLOW_CLEAR {
2575DMDATA_DONT_CLEAR = 0x00000000,
2576DMDATA_CLEAR_UNDERFLOW_STATUS = 0x00000001,
2577} DMDATA_UNDERFLOW_CLEAR;
2578
2579/*
2580 * DMDATA_UPDATED enum
2581 */
2582
2583typedef enum DMDATA_UPDATED {
2584DMDATA_NOT_UPDATED = 0x00000000,
2585DMDATA_WAS_UPDATED = 0x00000001,
2586} DMDATA_UPDATED;
2587
2588/*******************************************************
2589 * HUBBUB_SDPIF Enums
2590 *******************************************************/
2591
2592/*
2593 * RESPONSE_STATUS enum
2594 */
2595
2596typedef enum RESPONSE_STATUS {
2597OKAY = 0x00000000,
2598EXOKAY = 0x00000001,
2599SLVERR = 0x00000002,
2600DECERR = 0x00000003,
2601EARLY = 0x00000004,
2602OKAY_NODATA = 0x00000005,
2603PROTVIOL = 0x00000006,
2604TRANSERR = 0x00000007,
2605CMPTO = 0x00000008,
2606CRS = 0x0000000c,
2607} RESPONSE_STATUS;
2608
2609/*******************************************************
2610 * HUBBUB_RET_PATH Enums
2611 *******************************************************/
2612
2613/*
2614 * DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE enum
2615 */
2616
2617typedef enum DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE {
2618DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_OFF = 0x00000000,
2619DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_1 = 0x00000001,
2620DCHUBBUB_DET_MEM_POWER_LIGHT_SLEEP_MODE_2 = 0x00000002,
2621} DCHUBBUB_DET_MEM_PWR_LIGHT_SLEEP_MODE;
2622
2623/*
2624 * DCHUBBUB_MEM_PWR_DIS_MODE enum
2625 */
2626
2627typedef enum DCHUBBUB_MEM_PWR_DIS_MODE {
2628DCHUBBUB_MEM_POWER_DIS_MODE_ENABLE = 0x00000000,
2629DCHUBBUB_MEM_POWER_DIS_MODE_DISABLE = 0x00000001,
2630} DCHUBBUB_MEM_PWR_DIS_MODE;
2631
2632/*
2633 * DCHUBBUB_MEM_PWR_MODE enum
2634 */
2635
2636typedef enum DCHUBBUB_MEM_PWR_MODE {
2637DCHUBBUB_MEM_POWER_MODE_OFF = 0x00000000,
2638DCHUBBUB_MEM_POWER_MODE_LIGHT_SLEEP = 0x00000001,
2639DCHUBBUB_MEM_POWER_MODE_DEEP_SLEEP = 0x00000002,
2640DCHUBBUB_MEM_POWER_MODE_SHUT_DOWN = 0x00000003,
2641} DCHUBBUB_MEM_PWR_MODE;
2642
2643/*******************************************************
2644 * MPC_CFG Enums
2645 *******************************************************/
2646
2647/*
2648 * MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET enum
2649 */
2650
2651typedef enum MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET {
2652MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2653MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2654} MPC_CFG_ADR_CFG_CUR_VUPDATE_LOCK_SET;
2655
2656/*
2657 * MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET enum
2658 */
2659
2660typedef enum MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET {
2661MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2662MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2663} MPC_CFG_ADR_CFG_VUPDATE_LOCK_SET;
2664
2665/*
2666 * MPC_CFG_ADR_VUPDATE_LOCK_SET enum
2667 */
2668
2669typedef enum MPC_CFG_ADR_VUPDATE_LOCK_SET {
2670MPC_CFG_ADR_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2671MPC_CFG_ADR_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2672} MPC_CFG_ADR_VUPDATE_LOCK_SET;
2673
2674/*
2675 * MPC_CFG_CFG_VUPDATE_LOCK_SET enum
2676 */
2677
2678typedef enum MPC_CFG_CFG_VUPDATE_LOCK_SET {
2679MPC_CFG_CFG_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2680MPC_CFG_CFG_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2681} MPC_CFG_CFG_VUPDATE_LOCK_SET;
2682
2683/*
2684 * MPC_CFG_CUR_VUPDATE_LOCK_SET enum
2685 */
2686
2687typedef enum MPC_CFG_CUR_VUPDATE_LOCK_SET {
2688MPC_CFG_CUR_VUPDATE_LOCK_SET_FALSE = 0x00000000,
2689MPC_CFG_CUR_VUPDATE_LOCK_SET_TRUE = 0x00000001,
2690} MPC_CFG_CUR_VUPDATE_LOCK_SET;
2691
2692/*
2693 * MPC_CFG_MPC_TEST_CLK_SEL enum
2694 */
2695
2696typedef enum MPC_CFG_MPC_TEST_CLK_SEL {
2697MPC_CFG_MPC_TEST_CLK_SEL_0 = 0x00000000,
2698MPC_CFG_MPC_TEST_CLK_SEL_1 = 0x00000001,
2699MPC_CFG_MPC_TEST_CLK_SEL_2 = 0x00000002,
2700MPC_CFG_MPC_TEST_CLK_SEL_3 = 0x00000003,
2701} MPC_CFG_MPC_TEST_CLK_SEL;
2702
2703/*
2704 * MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN enum
2705 */
2706
2707typedef enum MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN {
2708MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
2709MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
2710} MPC_CFG_TEST_DEBUG_INDEX_MPC_CFG_TEST_DEBUG_WRITE_EN;
2711
2712/*
2713 * MPC_CRC_CALC_INTERLACE_MODE enum
2714 */
2715
2716typedef enum MPC_CRC_CALC_INTERLACE_MODE {
2717MPC_CRC_INTERLACE_MODE_TOP = 0x00000000,
2718MPC_CRC_INTERLACE_MODE_BOTTOM = 0x00000001,
2719MPC_CRC_INTERLACE_MODE_BOTH_RESET_BOTTOM = 0x00000002,
2720MPC_CRC_INTERLACE_MODE_BOTH_RESET_EACH = 0x00000003,
2721} MPC_CRC_CALC_INTERLACE_MODE;
2722
2723/*
2724 * MPC_CRC_CALC_MODE enum
2725 */
2726
2727typedef enum MPC_CRC_CALC_MODE {
2728MPC_CRC_ONE_SHOT_MODE = 0x00000000,
2729MPC_CRC_CONTINUOUS_MODE = 0x00000001,
2730} MPC_CRC_CALC_MODE;
2731
2732/*
2733 * MPC_CRC_CALC_STEREO_MODE enum
2734 */
2735
2736typedef enum MPC_CRC_CALC_STEREO_MODE {
2737MPC_CRC_STEREO_MODE_LEFT = 0x00000000,
2738MPC_CRC_STEREO_MODE_RIGHT = 0x00000001,
2739MPC_CRC_STEREO_MODE_BOTH_RESET_RIGHT = 0x00000002,
2740MPC_CRC_STEREO_MODE_BOTH_RESET_EACH = 0x00000003,
2741} MPC_CRC_CALC_STEREO_MODE;
2742
2743/*
2744 * MPC_CRC_SOURCE_SELECT enum
2745 */
2746
2747typedef enum MPC_CRC_SOURCE_SELECT {
2748MPC_CRC_SOURCE_SEL_DPP = 0x00000000,
2749MPC_CRC_SOURCE_SEL_OPP = 0x00000001,
2750MPC_CRC_SOURCE_SEL_DWB = 0x00000002,
2751MPC_CRC_SOURCE_SEL_OTHER = 0x00000003,
2752} MPC_CRC_SOURCE_SELECT;
2753
2754/*
2755 * MPC_DEBUG_BUS1_DATA_SELECT enum
2756 */
2757
2758typedef enum MPC_DEBUG_BUS1_DATA_SELECT {
2759MPC_DEBUG_BUS1_DATA_SELECT_MPC_CFG = 0x00000000,
2760MPC_DEBUG_BUS1_DATA_SELECT_MPC_CONT = 0x00000001,
2761MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV1 = 0x00000002,
2762MPC_DEBUG_BUS1_DATA_SELECT_MPC_RSV = 0x00000003,
2763} MPC_DEBUG_BUS1_DATA_SELECT;
2764
2765/*
2766 * MPC_DEBUG_BUS2_DATA_SELECT enum
2767 */
2768
2769typedef enum MPC_DEBUG_BUS2_DATA_SELECT {
2770MPC_DEBUG_BUS2_DATA_SELECT_MPCC = 0x00000000,
2771MPC_DEBUG_BUS2_DATA_SELECT_MPCC_CONT = 0x00000001,
2772MPC_DEBUG_BUS2_DATA_SELECT_MPCC_MCM = 0x00000002,
2773MPC_DEBUG_BUS2_DATA_SELECT_RES = 0x00000003,
2774} MPC_DEBUG_BUS2_DATA_SELECT;
2775
2776/*
2777 * MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT enum
2778 */
2779
2780typedef enum MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT {
2781MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_DEBUG_ID = 0x00000000,
2782MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_DEBUG_ID = 0x00000001,
2783MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_OGAM_DEBUG_ID = 0x00000002,
2784MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPC_OCSC_DEBUG_ID = 0x00000003,
2785MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFR_DEBUG_DATA = 0x00000004,
2786MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_SFT_DEBUG_DATA = 0x00000005,
2787MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_RSV1 = 0x00000006,
2788MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT_MPCC_MCM_DEBUG_ID = 0x00000007,
2789} MPC_DEBUG_BUS_DIRECT_OUT_DATA_SELECT;
2790
2791/*
2792 * MPC_DEBUG_BUS_MPCC_BYTE_SELECT enum
2793 */
2794
2795typedef enum MPC_DEBUG_BUS_MPCC_BYTE_SELECT {
2796MPC_DEBUG_BUS_MPCC_BYTE0 = 0x00000000,
2797MPC_DEBUG_BUS_MPCC_BYTE1 = 0x00000001,
2798MPC_DEBUG_BUS_MPCC_BYTE2 = 0x00000002,
2799MPC_DEBUG_BUS_MPCC_BYTE3 = 0x00000003,
2800} MPC_DEBUG_BUS_MPCC_BYTE_SELECT;
2801
2802/*******************************************************
2803 * MPC_OCSC Enums
2804 *******************************************************/
2805
2806/*
2807 * MPC_OCSC_COEF_FORMAT enum
2808 */
2809
2810typedef enum MPC_OCSC_COEF_FORMAT {
2811MPC_OCSC_COEF_FORMAT_S2_13 = 0x00000000,
2812MPC_OCSC_COEF_FORMAT_S3_12 = 0x00000001,
2813} MPC_OCSC_COEF_FORMAT;
2814
2815/*
2816 * MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN enum
2817 */
2818
2819typedef enum MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN {
2820MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
2821MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
2822} MPC_OCSC_TEST_DEBUG_INDEX_MPC_OCSC_TEST_DEBUG_WRITE_EN;
2823
2824/*
2825 * MPC_OUT_CSC_MODE enum
2826 */
2827
2828typedef enum MPC_OUT_CSC_MODE {
2829MPC_OUT_CSC_MODE_0 = 0x00000000,
2830MPC_OUT_CSC_MODE_1 = 0x00000001,
2831MPC_OUT_CSC_MODE_2 = 0x00000002,
2832MPC_OUT_CSC_MODE_RSV = 0x00000003,
2833} MPC_OUT_CSC_MODE;
2834
2835/*
2836 * MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE enum
2837 */
2838
2839typedef enum MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE {
2840MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_BYPASS = 0x00000000,
2841MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_6BITS = 0x00000001,
2842MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_8BITS = 0x00000002,
2843MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_9BITS = 0x00000003,
2844MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_10BITS = 0x00000004,
2845MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_11BITS = 0x00000005,
2846MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_12BITS = 0x00000006,
2847MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_PASSTHROUGH = 0x00000007,
2848} MPC_OUT_DENORM_CONTROL_MPC_OUT_DENORM_MODE;
2849
2850/*
2851 * MPC_OUT_RATE_CONTROL_DISABLE_SET enum
2852 */
2853
2854typedef enum MPC_OUT_RATE_CONTROL_DISABLE_SET {
2855MPC_OUT_RATE_CONTROL_SET_ENABLE = 0x00000000,
2856MPC_OUT_RATE_CONTROL_SET_DISABLE = 0x00000001,
2857} MPC_OUT_RATE_CONTROL_DISABLE_SET;
2858
2859/*******************************************************
2860 * MPCC Enums
2861 *******************************************************/
2862
2863/*
2864 * MPCC_BG_COLOR_BPC enum
2865 */
2866
2867typedef enum MPCC_BG_COLOR_BPC {
2868MPCC_BG_COLOR_BPC_8bit = 0x00000000,
2869MPCC_BG_COLOR_BPC_9bit = 0x00000001,
2870MPCC_BG_COLOR_BPC_10bit = 0x00000002,
2871MPCC_BG_COLOR_BPC_11bit = 0x00000003,
2872MPCC_BG_COLOR_BPC_12bit = 0x00000004,
2873} MPCC_BG_COLOR_BPC;
2874
2875/*
2876 * MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY enum
2877 */
2878
2879typedef enum MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY {
2880MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_FALSE = 0x00000000,
2881MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY_TRUE = 0x00000001,
2882} MPCC_CONTROL_MPCC_ACTIVE_OVERLAP_ONLY;
2883
2884/*
2885 * MPCC_CONTROL_MPCC_ALPHA_BLND_MODE enum
2886 */
2887
2888typedef enum MPCC_CONTROL_MPCC_ALPHA_BLND_MODE {
2889MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA = 0x00000000,
2890MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_PER_PIXEL_ALPHA_COMBINED_GLOBAL_GAIN = 0x00000001,
2891MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_GLOBAL_ALPHA = 0x00000002,
2892MPCC_CONTROL_MPCC_ALPHA_BLND_MODE_UNUSED = 0x00000003,
2893} MPCC_CONTROL_MPCC_ALPHA_BLND_MODE;
2894
2895/*
2896 * MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE enum
2897 */
2898
2899typedef enum MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE {
2900MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_FALSE = 0x00000000,
2901MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE_TRUE = 0x00000001,
2902} MPCC_CONTROL_MPCC_ALPHA_MULTIPLIED_MODE;
2903
2904/*
2905 * MPCC_CONTROL_MPCC_BOT_GAIN_MODE enum
2906 */
2907
2908typedef enum MPCC_CONTROL_MPCC_BOT_GAIN_MODE {
2909MPCC_CONTROL_MPCC_BOT_GAIN_MODE_0 = 0x00000000,
2910MPCC_CONTROL_MPCC_BOT_GAIN_MODE_1 = 0x00000001,
2911} MPCC_CONTROL_MPCC_BOT_GAIN_MODE;
2912
2913/*
2914 * MPCC_CONTROL_MPCC_MODE enum
2915 */
2916
2917typedef enum MPCC_CONTROL_MPCC_MODE {
2918MPCC_CONTROL_MPCC_MODE_BYPASS = 0x00000000,
2919MPCC_CONTROL_MPCC_MODE_TOP_LAYER_PASSTHROUGH = 0x00000001,
2920MPCC_CONTROL_MPCC_MODE_TOP_LAYER_ONLY = 0x00000002,
2921MPCC_CONTROL_MPCC_MODE_TOP_BOT_BLENDING = 0x00000003,
2922} MPCC_CONTROL_MPCC_MODE;
2923
2924/*
2925 * MPCC_SM_CONTROL_MPCC_SM_EN enum
2926 */
2927
2928typedef enum MPCC_SM_CONTROL_MPCC_SM_EN {
2929MPCC_SM_CONTROL_MPCC_SM_EN_FALSE = 0x00000000,
2930MPCC_SM_CONTROL_MPCC_SM_EN_TRUE = 0x00000001,
2931} MPCC_SM_CONTROL_MPCC_SM_EN;
2932
2933/*
2934 * MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT enum
2935 */
2936
2937typedef enum MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT {
2938MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_FALSE = 0x00000000,
2939MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT_TRUE = 0x00000001,
2940} MPCC_SM_CONTROL_MPCC_SM_FIELD_ALT;
2941
2942/*
2943 * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL enum
2944 */
2945
2946typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL {
2947MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_NO_FORCE = 0x00000000,
2948MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_RESERVED = 0x00000001,
2949MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_LOW = 0x00000002,
2950MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL_FORCE_HIGH = 0x00000003,
2951} MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_FRAME_POL;
2952
2953/*
2954 * MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL enum
2955 */
2956
2957typedef enum MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL {
2958MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_NO_FORCE = 0x00000000,
2959MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_RESERVED = 0x00000001,
2960MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_LOW = 0x00000002,
2961MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL_FORCE_HIGH = 0x00000003,
2962} MPCC_SM_CONTROL_MPCC_SM_FORCE_NEXT_TOP_POL;
2963
2964/*
2965 * MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT enum
2966 */
2967
2968typedef enum MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT {
2969MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_FALSE = 0x00000000,
2970MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT_TRUE = 0x00000001,
2971} MPCC_SM_CONTROL_MPCC_SM_FRAME_ALT;
2972
2973/*
2974 * MPCC_SM_CONTROL_MPCC_SM_MODE enum
2975 */
2976
2977typedef enum MPCC_SM_CONTROL_MPCC_SM_MODE {
2978MPCC_SM_CONTROL_MPCC_SM_MODE_SINGLE_PLANE = 0x00000000,
2979MPCC_SM_CONTROL_MPCC_SM_MODE_ROW_SUBSAMPLING = 0x00000002,
2980MPCC_SM_CONTROL_MPCC_SM_MODE_COLUMN_SUBSAMPLING = 0x00000004,
2981MPCC_SM_CONTROL_MPCC_SM_MODE_CHECKERBOARD_SUBSAMPLING = 0x00000006,
2982} MPCC_SM_CONTROL_MPCC_SM_MODE;
2983
2984/*
2985 * MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN enum
2986 */
2987
2988typedef enum MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN {
2989MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
2990MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
2991} MPCC_TEST_DEBUG_INDEX_MPCC_TEST_DEBUG_WRITE_EN;
2992
2993/*******************************************************
2994 * MPCC_OGAM Enums
2995 *******************************************************/
2996
2997/*
2998 * MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM enum
2999 */
3000
3001typedef enum MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM {
3002MPCC_GAMUT_REMAP_COEF_FORMAT_S2_13 = 0x00000000,
3003MPCC_GAMUT_REMAP_COEF_FORMAT_S3_12 = 0x00000001,
3004} MPCC_GAMUT_REMAP_COEF_FORMAT_ENUM;
3005
3006/*
3007 * MPCC_GAMUT_REMAP_MODE_ENUM enum
3008 */
3009
3010typedef enum MPCC_GAMUT_REMAP_MODE_ENUM {
3011MPCC_GAMUT_REMAP_MODE_0 = 0x00000000,
3012MPCC_GAMUT_REMAP_MODE_1 = 0x00000001,
3013MPCC_GAMUT_REMAP_MODE_2 = 0x00000002,
3014MPCC_GAMUT_REMAP_MODE_RSV = 0x00000003,
3015} MPCC_GAMUT_REMAP_MODE_ENUM;
3016
3017/*
3018 * MPCC_OGAM_LUT_2_CONFIG_ENUM enum
3019 */
3020
3021typedef enum MPCC_OGAM_LUT_2_CONFIG_ENUM {
3022MPCC_OGAM_LUT_2CFG_NO_MEMORY = 0x00000000,
3023MPCC_OGAM_LUT_2CFG_MEMORY_A = 0x00000001,
3024MPCC_OGAM_LUT_2CFG_MEMORY_B = 0x00000002,
3025} MPCC_OGAM_LUT_2_CONFIG_ENUM;
3026
3027/*
3028 * MPCC_OGAM_LUT_CONFIG_MODE enum
3029 */
3030
3031typedef enum MPCC_OGAM_LUT_CONFIG_MODE {
3032MPCC_OGAM_DIFFERENT_RGB = 0x00000000,
3033MPCC_OGAM_ALL_USE_R = 0x00000001,
3034} MPCC_OGAM_LUT_CONFIG_MODE;
3035
3036/*
3037 * MPCC_OGAM_LUT_PWL_DISABLE_ENUM enum
3038 */
3039
3040typedef enum MPCC_OGAM_LUT_PWL_DISABLE_ENUM {
3041MPCC_OGAM_ENABLE_PWL = 0x00000000,
3042MPCC_OGAM_DISABLE_PWL = 0x00000001,
3043} MPCC_OGAM_LUT_PWL_DISABLE_ENUM;
3044
3045/*
3046 * MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL enum
3047 */
3048
3049typedef enum MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL {
3050MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMA = 0x00000000,
3051MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL_RAMB = 0x00000001,
3052} MPCC_OGAM_LUT_RAM_CONTROL_MPCC_OGAM_LUT_RAM_SEL;
3053
3054/*
3055 * MPCC_OGAM_LUT_RAM_SEL enum
3056 */
3057
3058typedef enum MPCC_OGAM_LUT_RAM_SEL {
3059MPCC_OGAM_RAMA_ACCESS = 0x00000000,
3060MPCC_OGAM_RAMB_ACCESS = 0x00000001,
3061} MPCC_OGAM_LUT_RAM_SEL;
3062
3063/*
3064 * MPCC_OGAM_LUT_READ_COLOR_SEL enum
3065 */
3066
3067typedef enum MPCC_OGAM_LUT_READ_COLOR_SEL {
3068MPCC_OGAM_BLUE_LUT = 0x00000000,
3069MPCC_OGAM_GREEN_LUT = 0x00000001,
3070MPCC_OGAM_RED_LUT = 0x00000002,
3071} MPCC_OGAM_LUT_READ_COLOR_SEL;
3072
3073/*
3074 * MPCC_OGAM_LUT_READ_DBG enum
3075 */
3076
3077typedef enum MPCC_OGAM_LUT_READ_DBG {
3078MPCC_OGAM_DISABLE_DEBUG = 0x00000000,
3079MPCC_OGAM_ENABLE_DEBUG = 0x00000001,
3080} MPCC_OGAM_LUT_READ_DBG;
3081
3082/*
3083 * MPCC_OGAM_LUT_SEL_ENUM enum
3084 */
3085
3086typedef enum MPCC_OGAM_LUT_SEL_ENUM {
3087MPCC_OGAM_RAMA = 0x00000000,
3088MPCC_OGAM_RAMB = 0x00000001,
3089} MPCC_OGAM_LUT_SEL_ENUM;
3090
3091/*
3092 * MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM enum
3093 */
3094
3095typedef enum MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM {
3096MPCC_OGAM_MODE_0 = 0x00000000,
3097MPCC_OGAM_MODE_RSV1 = 0x00000001,
3098MPCC_OGAM_MODE_2 = 0x00000002,
3099MPCC_OGAM_MODE_RSV = 0x00000003,
3100} MPCC_OGAM_MODE_MPCC_OGAM_MODE_ENUM;
3101
3102/*
3103 * MPCC_OGAM_NUM_SEG enum
3104 */
3105
3106typedef enum MPCC_OGAM_NUM_SEG {
3107MPCC_OGAM_SEGMENTS_1 = 0x00000000,
3108MPCC_OGAM_SEGMENTS_2 = 0x00000001,
3109MPCC_OGAM_SEGMENTS_4 = 0x00000002,
3110MPCC_OGAM_SEGMENTS_8 = 0x00000003,
3111MPCC_OGAM_SEGMENTS_16 = 0x00000004,
3112MPCC_OGAM_SEGMENTS_32 = 0x00000005,
3113MPCC_OGAM_SEGMENTS_64 = 0x00000006,
3114MPCC_OGAM_SEGMENTS_128 = 0x00000007,
3115} MPCC_OGAM_NUM_SEG;
3116
3117/*
3118 * MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN enum
3119 */
3120
3121typedef enum MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN {
3122MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_FALSE = 0x00000000,
3123MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN_TRUE = 0x00000001,
3124} MPCC_OGAM_TEST_DEBUG_INDEX_MPCC_OGAM_TEST_DEBUG_WRITE_EN;
3125
3126/*******************************************************
3127 * MPCC_MCM Enums
3128 *******************************************************/
3129
3130/*
3131 * MPCC_MCM_3DLUT_30BIT_ENUM enum
3132 */
3133
3134typedef enum MPCC_MCM_3DLUT_30BIT_ENUM {
3135MPCC_MCM_3DLUT_36BIT = 0x00000000,
3136MPCC_MCM_3DLUT_30BIT = 0x00000001,
3137} MPCC_MCM_3DLUT_30BIT_ENUM;
3138
3139/*
3140 * MPCC_MCM_3DLUT_RAM_SEL enum
3141 */
3142
3143typedef enum MPCC_MCM_3DLUT_RAM_SEL {
3144MPCC_MCM_RAM0_ACCESS = 0x00000000,
3145MPCC_MCM_RAM1_ACCESS = 0x00000001,
3146MPCC_MCM_RAM2_ACCESS = 0x00000002,
3147MPCC_MCM_RAM3_ACCESS = 0x00000003,
3148} MPCC_MCM_3DLUT_RAM_SEL;
3149
3150/*
3151 * MPCC_MCM_3DLUT_SIZE_ENUM enum
3152 */
3153
3154typedef enum MPCC_MCM_3DLUT_SIZE_ENUM {
3155MPCC_MCM_3DLUT_17CUBE = 0x00000000,
3156MPCC_MCM_3DLUT_9CUBE = 0x00000001,
3157} MPCC_MCM_3DLUT_SIZE_ENUM;
3158
3159/*
3160 * MPCC_MCM_GAMMA_LUT_MODE_ENUM enum
3161 */
3162
3163typedef enum MPCC_MCM_GAMMA_LUT_MODE_ENUM {
3164MPCC_MCM_GAMMA_LUT_BYPASS = 0x00000000,
3165MPCC_MCM_GAMMA_LUT_RESERVED_1 = 0x00000001,
3166MPCC_MCM_GAMMA_LUT_RAM_LUT = 0x00000002,
3167MPCC_MCM_GAMMA_LUT_RESERVED_3 = 0x00000003,
3168} MPCC_MCM_GAMMA_LUT_MODE_ENUM;
3169
3170/*
3171 * MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM enum
3172 */
3173
3174typedef enum MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM {
3175MPCC_MCM_GAMMA_LUT_ENABLE_PWL = 0x00000000,
3176MPCC_MCM_GAMMA_LUT_DISABLE_PWL = 0x00000001,
3177} MPCC_MCM_GAMMA_LUT_PWL_DISABLE_ENUM;
3178
3179/*
3180 * MPCC_MCM_GAMMA_LUT_SEL_ENUM enum
3181 */
3182
3183typedef enum MPCC_MCM_GAMMA_LUT_SEL_ENUM {
3184MPCC_MCM_GAMMA_LUT_RAMA = 0x00000000,
3185MPCC_MCM_GAMMA_LUT_RAMB = 0x00000001,
3186} MPCC_MCM_GAMMA_LUT_SEL_ENUM;
3187
3188/*
3189 * MPCC_MCM_LUT_2_MODE_ENUM enum
3190 */
3191
3192typedef enum MPCC_MCM_LUT_2_MODE_ENUM {
3193MPCC_MCM_LUT_2_MODE_BYPASS = 0x00000000,
3194MPCC_MCM_LUT_2_MODE_RAMA_LUT = 0x00000001,
3195MPCC_MCM_LUT_2_MODE_RAMB_LUT = 0x00000002,
3196} MPCC_MCM_LUT_2_MODE_ENUM;
3197
3198/*
3199 * MPCC_MCM_LUT_CONFIG_MODE enum
3200 */
3201
3202typedef enum MPCC_MCM_LUT_CONFIG_MODE {
3203MPCC_MCM_LUT_DIFFERENT_RGB = 0x00000000,
3204MPCC_MCM_LUT_ALL_USE_R = 0x00000001,
3205} MPCC_MCM_LUT_CONFIG_MODE;
3206
3207/*
3208 * MPCC_MCM_LUT_NUM_SEG enum
3209 */
3210
3211typedef enum MPCC_MCM_LUT_NUM_SEG {
3212MPCC_MCM_LUT_SEGMENTS_1 = 0x00000000,
3213MPCC_MCM_LUT_SEGMENTS_2 = 0x00000001,
3214MPCC_MCM_LUT_SEGMENTS_4 = 0x00000002,
3215MPCC_MCM_LUT_SEGMENTS_8 = 0x00000003,
3216MPCC_MCM_LUT_SEGMENTS_16 = 0x00000004,
3217MPCC_MCM_LUT_SEGMENTS_32 = 0x00000005,
3218MPCC_MCM_LUT_SEGMENTS_64 = 0x00000006,
3219MPCC_MCM_LUT_SEGMENTS_128 = 0x00000007,
3220} MPCC_MCM_LUT_NUM_SEG;
3221
3222/*
3223 * MPCC_MCM_LUT_RAM_SEL enum
3224 */
3225
3226typedef enum MPCC_MCM_LUT_RAM_SEL {
3227MPCC_MCM_LUT_RAMA_ACCESS = 0x00000000,
3228MPCC_MCM_LUT_RAMB_ACCESS = 0x00000001,
3229} MPCC_MCM_LUT_RAM_SEL;
3230
3231/*
3232 * MPCC_MCM_LUT_READ_COLOR_SEL enum
3233 */
3234
3235typedef enum MPCC_MCM_LUT_READ_COLOR_SEL {
3236MPCC_MCM_LUT_BLUE_LUT = 0x00000000,
3237MPCC_MCM_LUT_GREEN_LUT = 0x00000001,
3238MPCC_MCM_LUT_RED_LUT = 0x00000002,
3239} MPCC_MCM_LUT_READ_COLOR_SEL;
3240
3241/*
3242 * MPCC_MCM_LUT_READ_DBG enum
3243 */
3244
3245typedef enum MPCC_MCM_LUT_READ_DBG {
3246MPCC_MCM_LUT_DISABLE_DEBUG = 0x00000000,
3247MPCC_MCM_LUT_ENABLE_DEBUG = 0x00000001,
3248} MPCC_MCM_LUT_READ_DBG;
3249
3250/*
3251 * MPCC_MCM_MEM_PWR_FORCE_ENUM enum
3252 */
3253
3254typedef enum MPCC_MCM_MEM_PWR_FORCE_ENUM {
3255MPCC_MCM_MEM_PWR_FORCE_DIS = 0x00000000,
3256MPCC_MCM_MEM_PWR_FORCE_LS = 0x00000001,
3257MPCC_MCM_MEM_PWR_FORCE_DS = 0x00000002,
3258MPCC_MCM_MEM_PWR_FORCE_SD = 0x00000003,
3259} MPCC_MCM_MEM_PWR_FORCE_ENUM;
3260
3261/*
3262 * MPCC_MCM_MEM_PWR_STATE_ENUM enum
3263 */
3264
3265typedef enum MPCC_MCM_MEM_PWR_STATE_ENUM {
3266MPCC_MCM_MEM_PWR_STATE_ON = 0x00000000,
3267MPCC_MCM_MEM_PWR_STATE_LS = 0x00000001,
3268MPCC_MCM_MEM_PWR_STATE_DS = 0x00000002,
3269MPCC_MCM_MEM_PWR_STATE_SD = 0x00000003,
3270} MPCC_MCM_MEM_PWR_STATE_ENUM;
3271
3272/*******************************************************
3273 * ABM Enums
3274 *******************************************************/
3275
3276/*******************************************************
3277 * DPG Enums
3278 *******************************************************/
3279
3280/*
3281 * ENUM_DPG_BIT_DEPTH enum
3282 */
3283
3284typedef enum ENUM_DPG_BIT_DEPTH {
3285ENUM_DPG_BIT_DEPTH_6BPC = 0x00000000,
3286ENUM_DPG_BIT_DEPTH_8BPC = 0x00000001,
3287ENUM_DPG_BIT_DEPTH_10BPC = 0x00000002,
3288ENUM_DPG_BIT_DEPTH_12BPC = 0x00000003,
3289} ENUM_DPG_BIT_DEPTH;
3290
3291/*
3292 * ENUM_DPG_DYNAMIC_RANGE enum
3293 */
3294
3295typedef enum ENUM_DPG_DYNAMIC_RANGE {
3296ENUM_DPG_DYNAMIC_RANGE_VESA = 0x00000000,
3297ENUM_DPG_DYNAMIC_RANGE_CEA = 0x00000001,
3298} ENUM_DPG_DYNAMIC_RANGE;
3299
3300/*
3301 * ENUM_DPG_EN enum
3302 */
3303
3304typedef enum ENUM_DPG_EN {
3305ENUM_DPG_DISABLE = 0x00000000,
3306ENUM_DPG_ENABLE = 0x00000001,
3307} ENUM_DPG_EN;
3308
3309/*
3310 * ENUM_DPG_FIELD_POLARITY enum
3311 */
3312
3313typedef enum ENUM_DPG_FIELD_POLARITY {
3314ENUM_DPG_FIELD_POLARITY_TOP_EVEN_BOTTOM_ODD = 0x00000000,
3315ENUM_DPG_FIELD_POLARITY_TOP_ODD_BOTTOM_EVEN = 0x00000001,
3316} ENUM_DPG_FIELD_POLARITY;
3317
3318/*
3319 * ENUM_DPG_MODE enum
3320 */
3321
3322typedef enum ENUM_DPG_MODE {
3323ENUM_DPG_MODE_RGB_COLOUR_BLOCK = 0x00000000,
3324ENUM_DPG_MODE_YCBCR_601_COLOUR_BLOCK = 0x00000001,
3325ENUM_DPG_MODE_YCBCR_709_COLOUR_BLOCK = 0x00000002,
3326ENUM_DPG_MODE_VERTICAL_BAR = 0x00000003,
3327ENUM_DPG_MODE_HORIZONTAL_BAR = 0x00000004,
3328ENUM_DPG_MODE_RGB_SINGLE_RAMP = 0x00000005,
3329ENUM_DPG_MODE_RGB_DUAL_RAMP = 0x00000006,
3330ENUM_DPG_MODE_RGB_XR_BIAS = 0x00000007,
3331} ENUM_DPG_MODE;
3332
3333/*******************************************************
3334 * FMT Enums
3335 *******************************************************/
3336
3337/*
3338 * FMTMEM_PWR_DIS_CTRL enum
3339 */
3340
3341typedef enum FMTMEM_PWR_DIS_CTRL {
3342FMTMEM_ENABLE_MEM_PWR_CTRL = 0x00000000,
3343FMTMEM_DISABLE_MEM_PWR_CTRL = 0x00000001,
3344} FMTMEM_PWR_DIS_CTRL;
3345
3346/*
3347 * FMTMEM_PWR_FORCE_CTRL enum
3348 */
3349
3350typedef enum FMTMEM_PWR_FORCE_CTRL {
3351FMTMEM_NO_FORCE_REQUEST = 0x00000000,
3352FMTMEM_FORCE_LIGHT_SLEEP_REQUEST = 0x00000001,
3353FMTMEM_FORCE_DEEP_SLEEP_REQUEST = 0x00000002,
3354FMTMEM_FORCE_SHUT_DOWN_REQUEST = 0x00000003,
3355} FMTMEM_PWR_FORCE_CTRL;
3356
3357/*
3358 * FMT_BIT_DEPTH_CONTROL_25FRC_SEL enum
3359 */
3360
3361typedef enum FMT_BIT_DEPTH_CONTROL_25FRC_SEL {
3362FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Ei = 0x00000000,
3363FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Fi = 0x00000001,
3364FMT_BIT_DEPTH_CONTROL_25FRC_SEL_Gi = 0x00000002,
3365FMT_BIT_DEPTH_CONTROL_25FRC_SEL_RESERVED = 0x00000003,
3366} FMT_BIT_DEPTH_CONTROL_25FRC_SEL;
3367
3368/*
3369 * FMT_BIT_DEPTH_CONTROL_50FRC_SEL enum
3370 */
3371
3372typedef enum FMT_BIT_DEPTH_CONTROL_50FRC_SEL {
3373FMT_BIT_DEPTH_CONTROL_50FRC_SEL_A = 0x00000000,
3374FMT_BIT_DEPTH_CONTROL_50FRC_SEL_B = 0x00000001,
3375FMT_BIT_DEPTH_CONTROL_50FRC_SEL_C = 0x00000002,
3376FMT_BIT_DEPTH_CONTROL_50FRC_SEL_D = 0x00000003,
3377} FMT_BIT_DEPTH_CONTROL_50FRC_SEL;
3378
3379/*
3380 * FMT_BIT_DEPTH_CONTROL_75FRC_SEL enum
3381 */
3382
3383typedef enum FMT_BIT_DEPTH_CONTROL_75FRC_SEL {
3384FMT_BIT_DEPTH_CONTROL_75FRC_SEL_E = 0x00000000,
3385FMT_BIT_DEPTH_CONTROL_75FRC_SEL_F = 0x00000001,
3386FMT_BIT_DEPTH_CONTROL_75FRC_SEL_G = 0x00000002,
3387FMT_BIT_DEPTH_CONTROL_75FRC_SEL_RESERVED = 0x00000003,
3388} FMT_BIT_DEPTH_CONTROL_75FRC_SEL;
3389
3390/*
3391 * FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH enum
3392 */
3393
3394typedef enum FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH {
3395FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_18BPP = 0x00000000,
3396FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_24BPP = 0x00000001,
3397FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH_30BPP = 0x00000002,
3398} FMT_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH;
3399
3400/*
3401 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH enum
3402 */
3403
3404typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH {
3405FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_18BPP = 0x00000000,
3406FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_24BPP = 0x00000001,
3407FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH_30BPP = 0x00000002,
3408} FMT_BIT_DEPTH_CONTROL_TEMPORAL_DITHER_DEPTH;
3409
3410/*
3411 * FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL enum
3412 */
3413
3414typedef enum FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL {
3415FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL2 = 0x00000000,
3416FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL_GREY_LEVEL4 = 0x00000001,
3417} FMT_BIT_DEPTH_CONTROL_TEMPORAL_LEVEL;
3418
3419/*
3420 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH enum
3421 */
3422
3423typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH {
3424FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_18BPP = 0x00000000,
3425FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_24BPP = 0x00000001,
3426FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH_30BPP = 0x00000002,
3427} FMT_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH;
3428
3429/*
3430 * FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE enum
3431 */
3432
3433typedef enum FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE {
3434FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_TRUNCATION = 0x00000000,
3435FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE_ROUNDING = 0x00000001,
3436} FMT_BIT_DEPTH_CONTROL_TRUNCATE_MODE;
3437
3438/*
3439 * FMT_CLAMP_CNTL_COLOR_FORMAT enum
3440 */
3441
3442typedef enum FMT_CLAMP_CNTL_COLOR_FORMAT {
3443FMT_CLAMP_CNTL_COLOR_FORMAT_6BPC = 0x00000000,
3444FMT_CLAMP_CNTL_COLOR_FORMAT_8BPC = 0x00000001,
3445FMT_CLAMP_CNTL_COLOR_FORMAT_10BPC = 0x00000002,
3446FMT_CLAMP_CNTL_COLOR_FORMAT_12BPC = 0x00000003,
3447FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED1 = 0x00000004,
3448FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED2 = 0x00000005,
3449FMT_CLAMP_CNTL_COLOR_FORMAT_RESERVED3 = 0x00000006,
3450FMT_CLAMP_CNTL_COLOR_FORMAT_PROGRAMMABLE = 0x00000007,
3451} FMT_CLAMP_CNTL_COLOR_FORMAT;
3452
3453/*
3454 * FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS enum
3455 */
3456
3457typedef enum FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS {
3458FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_DISABLE = 0x00000000,
3459FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS_ENABLE = 0x00000001,
3460} FMT_CONTROL_CBCR_BIT_REDUCTION_BYPASS;
3461
3462/*
3463 * FMT_CONTROL_PIXEL_ENCODING enum
3464 */
3465
3466typedef enum FMT_CONTROL_PIXEL_ENCODING {
3467FMT_CONTROL_PIXEL_ENCODING_RGB444_OR_YCBCR444 = 0x00000000,
3468FMT_CONTROL_PIXEL_ENCODING_YCBCR422 = 0x00000001,
3469FMT_CONTROL_PIXEL_ENCODING_YCBCR420 = 0x00000002,
3470FMT_CONTROL_PIXEL_ENCODING_RESERVED = 0x00000003,
3471} FMT_CONTROL_PIXEL_ENCODING;
3472
3473/*
3474 * FMT_CONTROL_SUBSAMPLING_MODE enum
3475 */
3476
3477typedef enum FMT_CONTROL_SUBSAMPLING_MODE {
3478FMT_CONTROL_SUBSAMPLING_MODE_DROP = 0x00000000,
3479FMT_CONTROL_SUBSAMPLING_MODE_AVERAGE = 0x00000001,
3480FMT_CONTROL_SUBSAMPLING_MOME_3_TAP = 0x00000002,
3481FMT_CONTROL_SUBSAMPLING_MOME_RESERVED = 0x00000003,
3482} FMT_CONTROL_SUBSAMPLING_MODE;
3483
3484/*
3485 * FMT_CONTROL_SUBSAMPLING_ORDER enum
3486 */
3487
3488typedef enum FMT_CONTROL_SUBSAMPLING_ORDER {
3489FMT_CONTROL_SUBSAMPLING_ORDER_CB_BEFORE_CR = 0x00000000,
3490FMT_CONTROL_SUBSAMPLING_ORDER_CR_BEFORE_CB = 0x00000001,
3491} FMT_CONTROL_SUBSAMPLING_ORDER;
3492
3493/*
3494 * FMT_DEBUG_CNTL_COLOR_SELECT enum
3495 */
3496
3497typedef enum FMT_DEBUG_CNTL_COLOR_SELECT {
3498FMT_DEBUG_CNTL_COLOR_SELECT_BLUE = 0x00000000,
3499FMT_DEBUG_CNTL_COLOR_SELECT_GREEN = 0x00000001,
3500FMT_DEBUG_CNTL_COLOR_SELECT_RED1 = 0x00000002,
3501FMT_DEBUG_CNTL_COLOR_SELECT_RED2 = 0x00000003,
3502} FMT_DEBUG_CNTL_COLOR_SELECT;
3503
3504/*
3505 * FMT_DYNAMIC_EXP_MODE enum
3506 */
3507
3508typedef enum FMT_DYNAMIC_EXP_MODE {
3509FMT_DYNAMIC_EXP_MODE_10to12 = 0x00000000,
3510FMT_DYNAMIC_EXP_MODE_8to12 = 0x00000001,
3511} FMT_DYNAMIC_EXP_MODE;
3512
3513/*
3514 * FMT_FRAME_RANDOM_ENABLE_CONTROL enum
3515 */
3516
3517typedef enum FMT_FRAME_RANDOM_ENABLE_CONTROL {
3518FMT_FRAME_RANDOM_ENABLE_RESET_EACH_FRAME = 0x00000000,
3519FMT_FRAME_RANDOM_ENABLE_RESET_ONCE = 0x00000001,
3520} FMT_FRAME_RANDOM_ENABLE_CONTROL;
3521
3522/*
3523 * FMT_POWER_STATE_ENUM enum
3524 */
3525
3526typedef enum FMT_POWER_STATE_ENUM {
3527FMT_POWER_STATE_ENUM_ON = 0x00000000,
3528FMT_POWER_STATE_ENUM_LS = 0x00000001,
3529FMT_POWER_STATE_ENUM_DS = 0x00000002,
3530FMT_POWER_STATE_ENUM_SD = 0x00000003,
3531} FMT_POWER_STATE_ENUM;
3532
3533/*
3534 * FMT_RGB_RANDOM_ENABLE_CONTROL enum
3535 */
3536
3537typedef enum FMT_RGB_RANDOM_ENABLE_CONTROL {
3538FMT_RGB_RANDOM_ENABLE_CONTROL_DISABLE = 0x00000000,
3539FMT_RGB_RANDOM_ENABLE_CONTROL_ENABLE = 0x00000001,
3540} FMT_RGB_RANDOM_ENABLE_CONTROL;
3541
3542/*
3543 * FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL enum
3544 */
3545
3546typedef enum FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL {
3547FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_NO_SWAP = 0x00000000,
3548FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_1 = 0x00000001,
3549FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_2 = 0x00000002,
3550FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_RESERVED = 0x00000003,
3551} FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_CONTROL;
3552
3553/*
3554 * FMT_SPATIAL_DITHER_MODE enum
3555 */
3556
3557typedef enum FMT_SPATIAL_DITHER_MODE {
3558FMT_SPATIAL_DITHER_MODE_0 = 0x00000000,
3559FMT_SPATIAL_DITHER_MODE_1 = 0x00000001,
3560FMT_SPATIAL_DITHER_MODE_2 = 0x00000002,
3561FMT_SPATIAL_DITHER_MODE_3 = 0x00000003,
3562} FMT_SPATIAL_DITHER_MODE;
3563
3564/*
3565 * FMT_STEREOSYNC_OVERRIDE_CONTROL enum
3566 */
3567
3568typedef enum FMT_STEREOSYNC_OVERRIDE_CONTROL {
3569FMT_STEREOSYNC_OVERRIDE_CONTROL_0 = 0x00000000,
3570FMT_STEREOSYNC_OVERRIDE_CONTROL_1 = 0x00000001,
3571} FMT_STEREOSYNC_OVERRIDE_CONTROL;
3572
3573/*
3574 * FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 enum
3575 */
3576
3577typedef enum FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0 {
3578FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_BGR = 0x00000000,
3579FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0_RGB = 0x00000001,
3580} FMT_TEMPORAL_DITHER_PATTERN_CONTROL_RGB1_BGR0;
3581
3582/*******************************************************
3583 * OPPBUF Enums
3584 *******************************************************/
3585
3586/*
3587 * OPPBUF_DISPLAY_SEGMENTATION enum
3588 */
3589
3590typedef enum OPPBUF_DISPLAY_SEGMENTATION {
3591OPPBUF_DISPLAY_SEGMENTATION_1_SEGMENT = 0x00000000,
3592OPPBUF_DISPLAY_SEGMENTATION_2_SEGMENT = 0x00000001,
3593OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT = 0x00000002,
3594OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_LEFT = 0x00000003,
3595OPPBUF_DISPLAY_SEGMENTATION_4_SEGMENT_SPLIT_RIGHT = 0x00000004,
3596} OPPBUF_DISPLAY_SEGMENTATION;
3597
3598/*******************************************************
3599 * OPP_PIPE Enums
3600 *******************************************************/
3601
3602/*
3603 * OPP_PIPE_CLOCK_ENABLE_CONTROL enum
3604 */
3605
3606typedef enum OPP_PIPE_CLOCK_ENABLE_CONTROL {
3607OPP_PIPE_CLOCK_DISABLE = 0x00000000,
3608OPP_PIPE_CLOCK_ENABLE = 0x00000001,
3609} OPP_PIPE_CLOCK_ENABLE_CONTROL;
3610
3611/*
3612 * OPP_PIPE_DIGTIAL_BYPASS_CONTROL enum
3613 */
3614
3615typedef enum OPP_PIPE_DIGTIAL_BYPASS_CONTROL {
3616OPP_PIPE_DIGTIAL_BYPASS_DISABLE = 0x00000000,
3617OPP_PIPE_DIGTIAL_BYPASS_ENABLE = 0x00000001,
3618} OPP_PIPE_DIGTIAL_BYPASS_CONTROL;
3619
3620/*******************************************************
3621 * OPP_PIPE_CRC Enums
3622 *******************************************************/
3623
3624/*
3625 * OPP_PIPE_CRC_CONT_EN enum
3626 */
3627
3628typedef enum OPP_PIPE_CRC_CONT_EN {
3629OPP_PIPE_CRC_MODE_ONE_SHOT = 0x00000000,
3630OPP_PIPE_CRC_MODE_CONTINUOUS = 0x00000001,
3631} OPP_PIPE_CRC_CONT_EN;
3632
3633/*
3634 * OPP_PIPE_CRC_EN enum
3635 */
3636
3637typedef enum OPP_PIPE_CRC_EN {
3638OPP_PIPE_CRC_DISABLE = 0x00000000,
3639OPP_PIPE_CRC_ENABLE = 0x00000001,
3640} OPP_PIPE_CRC_EN;
3641
3642/*
3643 * OPP_PIPE_CRC_INTERLACE_EN enum
3644 */
3645
3646typedef enum OPP_PIPE_CRC_INTERLACE_EN {
3647OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_PROGRESSIVE = 0x00000000,
3648OPP_PIPE_CRC_INTERLACE_EN_INTERPRET_AS_INTERLACED = 0x00000001,
3649} OPP_PIPE_CRC_INTERLACE_EN;
3650
3651/*
3652 * OPP_PIPE_CRC_INTERLACE_MODE enum
3653 */
3654
3655typedef enum OPP_PIPE_CRC_INTERLACE_MODE {
3656OPP_PIPE_CRC_INTERLACE_MODE_TOP = 0x00000000,
3657OPP_PIPE_CRC_INTERLACE_MODE_BOTTOM = 0x00000001,
3658OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_BOTTOM_FIELD = 0x00000002,
3659OPP_PIPE_CRC_INTERLACE_MODE_BOTH_RESET_AFTER_EACH_FIELD = 0x00000003,
3660} OPP_PIPE_CRC_INTERLACE_MODE;
3661
3662/*
3663 * OPP_PIPE_CRC_ONE_SHOT_PENDING enum
3664 */
3665
3666typedef enum OPP_PIPE_CRC_ONE_SHOT_PENDING {
3667OPP_PIPE_CRC_ONE_SHOT_PENDING_NOT_PENDING = 0x00000000,
3668OPP_PIPE_CRC_ONE_SHOT_PENDING_PENDING = 0x00000001,
3669} OPP_PIPE_CRC_ONE_SHOT_PENDING;
3670
3671/*
3672 * OPP_PIPE_CRC_PIXEL_SELECT enum
3673 */
3674
3675typedef enum OPP_PIPE_CRC_PIXEL_SELECT {
3676OPP_PIPE_CRC_PIXEL_SELECT_ALL_PIXELS = 0x00000000,
3677OPP_PIPE_CRC_PIXEL_SELECT_RESERVED = 0x00000001,
3678OPP_PIPE_CRC_PIXEL_SELECT_EVEN_PIXELS = 0x00000002,
3679OPP_PIPE_CRC_PIXEL_SELECT_ODD_PIXELS = 0x00000003,
3680} OPP_PIPE_CRC_PIXEL_SELECT;
3681
3682/*
3683 * OPP_PIPE_CRC_SOURCE_SELECT enum
3684 */
3685
3686typedef enum OPP_PIPE_CRC_SOURCE_SELECT {
3687OPP_PIPE_CRC_SOURCE_SELECT_FMT = 0x00000000,
3688OPP_PIPE_CRC_SOURCE_SELECT_SFT = 0x00000001,
3689} OPP_PIPE_CRC_SOURCE_SELECT;
3690
3691/*
3692 * OPP_PIPE_CRC_STEREO_EN enum
3693 */
3694
3695typedef enum OPP_PIPE_CRC_STEREO_EN {
3696OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_NON_STEREO = 0x00000000,
3697OPP_PIPE_CRC_STEREO_EN_INTERPRET_AS_STEREO = 0x00000001,
3698} OPP_PIPE_CRC_STEREO_EN;
3699
3700/*
3701 * OPP_PIPE_CRC_STEREO_MODE enum
3702 */
3703
3704typedef enum OPP_PIPE_CRC_STEREO_MODE {
3705OPP_PIPE_CRC_STEREO_MODE_LEFT = 0x00000000,
3706OPP_PIPE_CRC_STEREO_MODE_RIGHT = 0x00000001,
3707OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_RIGHT_EYE = 0x00000002,
3708OPP_PIPE_CRC_STEREO_MODE_BOTH_RESET_AFTER_EACH_EYE = 0x00000003,
3709} OPP_PIPE_CRC_STEREO_MODE;
3710
3711/*******************************************************
3712 * OPP_TOP Enums
3713 *******************************************************/
3714
3715/*
3716 * OPP_ABM_DEBUG_BUS_SELECT_CONTROL enum
3717 */
3718
3719typedef enum OPP_ABM_DEBUG_BUS_SELECT_CONTROL {
3720DEBUG_BUS_SELECT_ABM0 = 0x00000000,
3721DEBUG_BUS_SELECT_ABM1 = 0x00000001,
3722DEBUG_BUS_SELECT_ABM2 = 0x00000002,
3723DEBUG_BUS_SELECT_ABM3 = 0x00000003,
3724DEBUG_BUS_SELECT_ABM_RESERVED0 = 0x00000004,
3725DEBUG_BUS_SELECT_ABM_RESERVED1 = 0x00000005,
3726} OPP_ABM_DEBUG_BUS_SELECT_CONTROL;
3727
3728/*
3729 * OPP_DPG_DEBUG_BUS_SELECT_CONTROL enum
3730 */
3731
3732typedef enum OPP_DPG_DEBUG_BUS_SELECT_CONTROL {
3733DEBUG_BUS_SELECT_DPG0 = 0x00000000,
3734DEBUG_BUS_SELECT_DPG1 = 0x00000001,
3735DEBUG_BUS_SELECT_DPG2 = 0x00000002,
3736DEBUG_BUS_SELECT_DPG3 = 0x00000003,
3737DEBUG_BUS_SELECT_DPG_RESERVED0 = 0x00000004,
3738DEBUG_BUS_SELECT_DPG_RESERVED1 = 0x00000005,
3739} OPP_DPG_DEBUG_BUS_SELECT_CONTROL;
3740
3741/*
3742 * OPP_FMT_DEBUG_BUS_SELECT_CONTROL enum
3743 */
3744
3745typedef enum OPP_FMT_DEBUG_BUS_SELECT_CONTROL {
3746DEBUG_BUS_SELECT_FMT0 = 0x00000000,
3747DEBUG_BUS_SELECT_FMT1 = 0x00000001,
3748DEBUG_BUS_SELECT_FMT2 = 0x00000002,
3749DEBUG_BUS_SELECT_FMT3 = 0x00000003,
3750DEBUG_BUS_SELECT_FMT_RESERVED0 = 0x00000004,
3751DEBUG_BUS_SELECT_FMT_RESERVED1 = 0x00000005,
3752} OPP_FMT_DEBUG_BUS_SELECT_CONTROL;
3753
3754/*
3755 * OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL enum
3756 */
3757
3758typedef enum OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL {
3759DEBUG_BUS_SELECT_OPPBUF0 = 0x00000000,
3760DEBUG_BUS_SELECT_OPPBUF1 = 0x00000001,
3761DEBUG_BUS_SELECT_OPPBUF2 = 0x00000002,
3762DEBUG_BUS_SELECT_OPPBUF3 = 0x00000003,
3763DEBUG_BUS_SELECT_OPPBUF_RESERVED0 = 0x00000004,
3764DEBUG_BUS_SELECT_OPPBUF_RESERVED1 = 0x00000005,
3765} OPP_OPPBUF_DEBUG_BUS_SELECT_CONTROL;
3766
3767/*
3768 * OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL enum
3769 */
3770
3771typedef enum OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL {
3772DEBUG_BUS_SELECT_OPP_PIPE0 = 0x00000000,
3773DEBUG_BUS_SELECT_OPP_PIPE1 = 0x00000001,
3774DEBUG_BUS_SELECT_OPP_PIPE2 = 0x00000002,
3775DEBUG_BUS_SELECT_OPP_PIPE3 = 0x00000003,
3776DEBUG_BUS_SELECT_OPP_PIPE_RESERVED0 = 0x00000004,
3777DEBUG_BUS_SELECT_OPP_PIPE_RESERVED1 = 0x00000005,
3778} OPP_OPP_PIPE_DEBUG_BUS_SELECT_CONTROL;
3779
3780/*
3781 * OPP_TEST_CLK_SEL_CONTROL enum
3782 */
3783
3784typedef enum OPP_TEST_CLK_SEL_CONTROL {
3785OPP_TEST_CLK_SEL_DISPCLK_P = 0x00000000,
3786OPP_TEST_CLK_SEL_DISPCLK_R = 0x00000001,
3787OPP_TEST_CLK_SEL_DISPCLK_ABM0 = 0x00000002,
3788OPP_TEST_CLK_SEL_DISPCLK_ABM1 = 0x00000003,
3789OPP_TEST_CLK_SEL_DISPCLK_ABM2 = 0x00000004,
3790OPP_TEST_CLK_SEL_DISPCLK_ABM3 = 0x00000005,
3791OPP_TEST_CLK_SEL_RESERVED0 = 0x00000006,
3792OPP_TEST_CLK_SEL_RESERVED1 = 0x00000007,
3793OPP_TEST_CLK_SEL_DISPCLK_OPP0 = 0x00000008,
3794OPP_TEST_CLK_SEL_DISPCLK_OPP1 = 0x00000009,
3795OPP_TEST_CLK_SEL_DISPCLK_OPP2 = 0x0000000a,
3796OPP_TEST_CLK_SEL_DISPCLK_OPP3 = 0x0000000b,
3797OPP_TEST_CLK_SEL_RESERVED2 = 0x0000000c,
3798OPP_TEST_CLK_SEL_RESERVED3 = 0x0000000d,
3799} OPP_TEST_CLK_SEL_CONTROL;
3800
3801/*
3802 * OPP_TOP_CLOCK_ENABLE_STATUS enum
3803 */
3804
3805typedef enum OPP_TOP_CLOCK_ENABLE_STATUS {
3806OPP_TOP_CLOCK_DISABLED_STATUS = 0x00000000,
3807OPP_TOP_CLOCK_ENABLED_STATUS = 0x00000001,
3808} OPP_TOP_CLOCK_ENABLE_STATUS;
3809
3810/*
3811 * OPP_TOP_CLOCK_GATING_CONTROL enum
3812 */
3813
3814typedef enum OPP_TOP_CLOCK_GATING_CONTROL {
3815OPP_TOP_CLOCK_GATING_ENABLED = 0x00000000,
3816OPP_TOP_CLOCK_GATING_DISABLED = 0x00000001,
3817} OPP_TOP_CLOCK_GATING_CONTROL;
3818
3819/*******************************************************
3820 * DSCRM Enums
3821 *******************************************************/
3822
3823/*
3824 * ENUM_DSCRM_EN enum
3825 */
3826
3827typedef enum ENUM_DSCRM_EN {
3828ENUM_DSCRM_DISABLE = 0x00000000,
3829ENUM_DSCRM_ENABLE = 0x00000001,
3830} ENUM_DSCRM_EN;
3831
3832/*******************************************************
3833 * OTG Enums
3834 *******************************************************/
3835
3836/*
3837 * MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK enum
3838 */
3839
3840typedef enum MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK {
3841MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_FALSE = 0x00000000,
3842MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK_TRUE = 0x00000001,
3843} MASTER_UPDATE_LOCK_MASTER_UPDATE_LOCK;
3844
3845/*
3846 * MASTER_UPDATE_LOCK_SEL enum
3847 */
3848
3849typedef enum MASTER_UPDATE_LOCK_SEL {
3850MASTER_UPDATE_LOCK_SEL_0 = 0x00000000,
3851MASTER_UPDATE_LOCK_SEL_1 = 0x00000001,
3852MASTER_UPDATE_LOCK_SEL_2 = 0x00000002,
3853MASTER_UPDATE_LOCK_SEL_3 = 0x00000003,
3854MASTER_UPDATE_LOCK_SEL_RESERVED4 = 0x00000004,
3855MASTER_UPDATE_LOCK_SEL_RESERVED5 = 0x00000005,
3856} MASTER_UPDATE_LOCK_SEL;
3857
3858/*
3859 * MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE enum
3860 */
3861
3862typedef enum MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE {
3863MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTH = 0x00000000,
3864MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_TOP = 0x00000001,
3865MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_BOTTOM = 0x00000002,
3866MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE_RESERVED = 0x00000003,
3867} MASTER_UPDATE_MODE_MASTER_UPDATE_INTERLACED_MODE;
3868
3869/*
3870 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN enum
3871 */
3872
3873typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN {
3874OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_FALSE = 0x00000000,
3875OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_TRUE = 0x00000001,
3876} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN;
3877
3878/*
3879 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB enum
3880 */
3881
3882typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB {
3883OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_FALSE = 0x00000000,
3884OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB_TRUE = 0x00000001,
3885} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_EN_DB;
3886
3887/*
3888 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR enum
3889 */
3890
3891typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR {
3892OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_FALSE = 0x00000000,
3893OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR_TRUE = 0x00000001,
3894} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_STEREO_SEL_OVR;
3895
3896/*
3897 * OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE enum
3898 */
3899
3900typedef enum OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE {
3901OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_BOTH = 0x00000000,
3902OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_INTERLACE = 0x00000001,
3903OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_BLOCK_PROGRASSIVE = 0x00000002,
3904OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE_RESERVED = 0x00000003,
3905} OTG_3D_STRUCTURE_CONTROL_OTG_3D_STRUCTURE_V_UPDATE_MODE;
3906
3907/*
3908 * OTG_CONTROL_OTG_DISABLE_POINT_CNTL enum
3909 */
3910
3911typedef enum OTG_CONTROL_OTG_DISABLE_POINT_CNTL {
3912OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE = 0x00000000,
3913OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_CURRENT = 0x00000001,
3914OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_VUPDATE = 0x00000002,
3915OTG_CONTROL_OTG_DISABLE_POINT_CNTL_DISABLE_FIRST = 0x00000003,
3916} OTG_CONTROL_OTG_DISABLE_POINT_CNTL;
3917
3918/*
3919 * OTG_CONTROL_OTG_FIELD_NUMBER_CNTL enum
3920 */
3921
3922typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_CNTL {
3923OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_NORMAL = 0x00000000,
3924OTG_CONTROL_OTG_FIELD_NUMBER_CNTL_DP = 0x00000001,
3925} OTG_CONTROL_OTG_FIELD_NUMBER_CNTL;
3926
3927/*
3928 * OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY enum
3929 */
3930
3931typedef enum OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY {
3932OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_FALSE = 0x00000000,
3933OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY_TRUE = 0x00000001,
3934} OTG_CONTROL_OTG_FIELD_NUMBER_POLARITY;
3935
3936/*
3937 * OTG_CONTROL_OTG_MASTER_EN enum
3938 */
3939
3940typedef enum OTG_CONTROL_OTG_MASTER_EN {
3941OTG_CONTROL_OTG_MASTER_EN_FALSE = 0x00000000,
3942OTG_CONTROL_OTG_MASTER_EN_TRUE = 0x00000001,
3943} OTG_CONTROL_OTG_MASTER_EN;
3944
3945/*
3946 * OTG_CONTROL_OTG_OUT_MUX enum
3947 */
3948
3949typedef enum OTG_CONTROL_OTG_OUT_MUX {
3950OTG_CONTROL_OTG_OUT_MUX_0 = 0x00000000,
3951OTG_CONTROL_OTG_OUT_MUX_1 = 0x00000001,
3952OTG_CONTROL_OTG_OUT_MUX_2 = 0x00000002,
3953} OTG_CONTROL_OTG_OUT_MUX;
3954
3955/*
3956 * OTG_CONTROL_OTG_START_POINT_CNTL enum
3957 */
3958
3959typedef enum OTG_CONTROL_OTG_START_POINT_CNTL {
3960OTG_CONTROL_OTG_START_POINT_CNTL_NORMAL = 0x00000000,
3961OTG_CONTROL_OTG_START_POINT_CNTL_DP = 0x00000001,
3962} OTG_CONTROL_OTG_START_POINT_CNTL;
3963
3964/*
3965 * OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN enum
3966 */
3967
3968typedef enum OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN {
3969OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_FALSE = 0x00000000,
3970OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN_TRUE = 0x00000001,
3971} OTG_COUNT_CONTROL_OTG_HORZ_COUNT_BY2_EN;
3972
3973/*
3974 * OTG_CRC_CNTL_OTG_CRC1_EN enum
3975 */
3976
3977typedef enum OTG_CRC_CNTL_OTG_CRC1_EN {
3978OTG_CRC_CNTL_OTG_CRC1_EN_FALSE = 0x00000000,
3979OTG_CRC_CNTL_OTG_CRC1_EN_TRUE = 0x00000001,
3980} OTG_CRC_CNTL_OTG_CRC1_EN;
3981
3982/*
3983 * OTG_CRC_CNTL_OTG_CRC_CONT_EN enum
3984 */
3985
3986typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_EN {
3987OTG_CRC_CNTL_OTG_CRC_CONT_EN_FALSE = 0x00000000,
3988OTG_CRC_CNTL_OTG_CRC_CONT_EN_TRUE = 0x00000001,
3989} OTG_CRC_CNTL_OTG_CRC_CONT_EN;
3990
3991/*
3992 * OTG_CRC_CNTL_OTG_CRC_CONT_MODE enum
3993 */
3994
3995typedef enum OTG_CRC_CNTL_OTG_CRC_CONT_MODE {
3996OTG_CRC_CNTL_OTG_CRC_CONT_MODE_RESET = 0x00000000,
3997OTG_CRC_CNTL_OTG_CRC_CONT_MODE_NORESET = 0x00000001,
3998} OTG_CRC_CNTL_OTG_CRC_CONT_MODE;
3999
4000/*
4001 * OTG_CRC_CNTL_OTG_CRC_EN enum
4002 */
4003
4004typedef enum OTG_CRC_CNTL_OTG_CRC_EN {
4005OTG_CRC_CNTL_OTG_CRC_EN_FALSE = 0x00000000,
4006OTG_CRC_CNTL_OTG_CRC_EN_TRUE = 0x00000001,
4007} OTG_CRC_CNTL_OTG_CRC_EN;
4008
4009/*
4010 * OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE enum
4011 */
4012
4013typedef enum OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE {
4014OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_TOP = 0x00000000,
4015OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTTOM = 0x00000001,
4016OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_BOTTOM = 0x00000002,
4017OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE_BOTH_FIELD = 0x00000003,
4018} OTG_CRC_CNTL_OTG_CRC_INTERLACE_MODE;
4019
4020/*
4021 * OTG_CRC_CNTL_OTG_CRC_STEREO_MODE enum
4022 */
4023
4024typedef enum OTG_CRC_CNTL_OTG_CRC_STEREO_MODE {
4025OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_LEFT = 0x00000000,
4026OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_RIGHT = 0x00000001,
4027OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_EYES = 0x00000002,
4028OTG_CRC_CNTL_OTG_CRC_STEREO_MODE_BOTH_FIELDS = 0x00000003,
4029} OTG_CRC_CNTL_OTG_CRC_STEREO_MODE;
4030
4031/*
4032 * OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS enum
4033 */
4034
4035typedef enum OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS {
4036OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_FALSE = 0x00000000,
4037OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS_TRUE = 0x00000001,
4038} OTG_CRC_CNTL_OTG_CRC_USE_NEW_AND_REPEATED_PIXELS;
4039
4040/*
4041 * OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT enum
4042 */
4043
4044typedef enum OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT {
4045OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UAB = 0x00000000,
4046OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_UA_B = 0x00000001,
4047OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_AB = 0x00000002,
4048OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_U_A_B = 0x00000003,
4049OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IAB = 0x00000004,
4050OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_IA_B = 0x00000005,
4051OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_AB = 0x00000006,
4052OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT_I_A_B = 0x00000007,
4053} OTG_CRC_CNTL_OTG_OTG_CRC0_SELECT;
4054
4055/*
4056 * OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT enum
4057 */
4058
4059typedef enum OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT {
4060OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UAB = 0x00000000,
4061OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_UA_B = 0x00000001,
4062OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_AB = 0x00000002,
4063OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_U_A_B = 0x00000003,
4064OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IAB = 0x00000004,
4065OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_IA_B = 0x00000005,
4066OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_AB = 0x00000006,
4067OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT_I_A_B = 0x00000007,
4068} OTG_CRC_CNTL_OTG_OTG_CRC1_SELECT;
4069
4070/*
4071 * OTG_DIG_UPDATE_VCOUNT_MODE enum
4072 */
4073
4074typedef enum OTG_DIG_UPDATE_VCOUNT_MODE {
4075OTG_DIG_UPDATE_VCOUNT_0 = 0x00000000,
4076OTG_DIG_UPDATE_VCOUNT_1 = 0x00000001,
4077} OTG_DIG_UPDATE_VCOUNT_MODE;
4078
4079/*
4080 * OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE enum
4081 */
4082
4083typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE {
4084OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_0 = 0x00000000,
4085OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_1 = 0x00000001,
4086OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_2 = 0x00000002,
4087OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE_3 = 0x00000003,
4088} OTG_DOUBLE_BUFFER_CONTROL_OTG_DRR_TIMING_DBUF_UPDATE_MODE;
4089
4090/*
4091 * OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY enum
4092 */
4093
4094typedef enum OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY {
4095OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_FALSE = 0x00000000,
4096OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY_TRUE = 0x00000001,
4097} OTG_DOUBLE_BUFFER_CONTROL_OTG_UPDATE_INSTANTLY;
4098
4099/*
4100 * OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME enum
4101 */
4102
4103typedef enum OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME {
4104OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_1FRAME = 0x00000000,
4105OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_2FRAME = 0x00000001,
4106OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_4FRAME = 0x00000002,
4107OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME_8FRAME = 0x00000003,
4108} OTG_DRR_CONTROL_OTG_DRR_AVERAGE_FRAME;
4109
4110/*
4111 * OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN enum
4112 */
4113
4114typedef enum OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN {
4115OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_FALSE = 0x00000000,
4116OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN_TRUE = 0x00000001,
4117} OTG_DTMTEST_CNTL_OTG_DTMTEST_OTG_EN;
4118
4119/*
4120 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY enum
4121 */
4122
4123typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY {
4124OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_FALSE = 0x00000000,
4125OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY_TRUE = 0x00000001,
4126} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_GRANULARITY;
4127
4128/*
4129 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY enum
4130 */
4131
4132typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY {
4133OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_FALSE = 0x00000000,
4134OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY_TRUE = 0x00000001,
4135} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_POLARITY;
4136
4137/*
4138 * OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT enum
4139 */
4140
4141typedef enum OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT {
4142OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC0 = 0x00000000,
4143OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_LOGIC1 = 0x00000001,
4144OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICA = 0x00000002,
4145OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICB = 0x00000003,
4146OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICC = 0x00000004,
4147OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICD = 0x00000005,
4148OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICE = 0x00000006,
4149OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENERICF = 0x00000007,
4150OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD1 = 0x00000008,
4151OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_HPD2 = 0x00000009,
4152OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1DATA = 0x0000000a,
4153OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC1CLK = 0x0000000b,
4154OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2DATA = 0x0000000c,
4155OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_DDC2CLK = 0x0000000d,
4156OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x0000000e,
4157OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_RESERVED = 0x0000000f,
4158OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_CLK = 0x00000010,
4159OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_GENLK_VSYNC = 0x00000011,
4160OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKA = 0x00000012,
4161OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT_SWAPLOCKB = 0x00000013,
4162} OTG_FLOW_CONTROL_OTG_FLOW_CONTROL_SOURCE_SELECT;
4163
4164/*
4165 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK enum
4166 */
4167
4168typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK {
4169OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_FALSE = 0x00000000,
4170OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK_TRUE = 0x00000001,
4171} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CHECK;
4172
4173/*
4174 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR enum
4175 */
4176
4177typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR {
4178OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_FALSE = 0x00000000,
4179OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR_TRUE = 0x00000001,
4180} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_CLEAR;
4181
4182/*
4183 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE enum
4184 */
4185
4186typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE {
4187OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_DISABLE = 0x00000000,
4188OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT = 0x00000001,
4189OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_HCOUNT_VCOUNT = 0x00000002,
4190OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE_RESERVED = 0x00000003,
4191} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_MODE;
4192
4193/*
4194 * OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL enum
4195 */
4196
4197typedef enum OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL {
4198OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_FALSE = 0x00000000,
4199OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL_TRUE = 0x00000001,
4200} OTG_FORCE_COUNT_NOW_CNTL_OTG_FORCE_COUNT_NOW_TRIG_SEL;
4201
4202/*
4203 * OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL enum
4204 */
4205
4206typedef enum OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL {
4207OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG0 = 0x00000000,
4208OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG1 = 0x00000001,
4209OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG2 = 0x00000002,
4210OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_OTG3 = 0x00000003,
4211OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED4 = 0x00000004,
4212OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL_RESERVED5 = 0x00000005,
4213} OTG_GLOBAL_CONTROL2_MANUAL_FLOW_CONTROL_SEL;
4214
4215/*
4216 * OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL enum
4217 */
4218
4219typedef enum OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL {
4220DIG_UPDATE_EYE_SEL_BOTH = 0x00000000,
4221DIG_UPDATE_EYE_SEL_LEFT = 0x00000001,
4222DIG_UPDATE_EYE_SEL_RIGHT = 0x00000002,
4223} OTG_GLOBAL_CONTROL3_DIG_UPDATE_EYE_SEL;
4224
4225/*
4226 * OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL enum
4227 */
4228
4229typedef enum OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL {
4230DIG_UPDATE_FIELD_SEL_BOTH = 0x00000000,
4231DIG_UPDATE_FIELD_SEL_TOP = 0x00000001,
4232DIG_UPDATE_FIELD_SEL_BOTTOM = 0x00000002,
4233DIG_UPDATE_FIELD_SEL_RESERVED = 0x00000003,
4234} OTG_GLOBAL_CONTROL3_DIG_UPDATE_FIELD_SEL;
4235
4236/*
4237 * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD enum
4238 */
4239
4240typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD {
4241MASTER_UPDATE_LOCK_DB_FIELD_BOTH = 0x00000000,
4242MASTER_UPDATE_LOCK_DB_FIELD_TOP = 0x00000001,
4243MASTER_UPDATE_LOCK_DB_FIELD_BOTTOM = 0x00000002,
4244MASTER_UPDATE_LOCK_DB_FIELD_RESERVED = 0x00000003,
4245} OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_FIELD;
4246
4247/*
4248 * OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL enum
4249 */
4250
4251typedef enum OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL {
4252MASTER_UPDATE_LOCK_DB_STEREO_SEL_BOTH = 0x00000000,
4253MASTER_UPDATE_LOCK_DB_STEREO_SEL_LEFT = 0x00000001,
4254MASTER_UPDATE_LOCK_DB_STEREO_SEL_RIGHT = 0x00000002,
4255MASTER_UPDATE_LOCK_DB_STEREO_SEL_RESERVED = 0x00000003,
4256} OTG_GLOBAL_CONTROL3_MASTER_UPDATE_LOCK_DB_STEREO_SEL;
4257
4258/*
4259 * OTG_GLOBAL_UPDATE_LOCK_EN enum
4260 */
4261
4262typedef enum OTG_GLOBAL_UPDATE_LOCK_EN {
4263OTG_GLOBAL_UPDATE_LOCK_DISABLE = 0x00000000,
4264OTG_GLOBAL_UPDATE_LOCK_ENABLE = 0x00000001,
4265} OTG_GLOBAL_UPDATE_LOCK_EN;
4266
4267/*
4268 * OTG_GSL_MASTER_MODE enum
4269 */
4270
4271typedef enum OTG_GSL_MASTER_MODE {
4272OTG_GSL_MASTER_MODE_0 = 0x00000000,
4273OTG_GSL_MASTER_MODE_1 = 0x00000001,
4274OTG_GSL_MASTER_MODE_2 = 0x00000002,
4275OTG_GSL_MASTER_MODE_3 = 0x00000003,
4276} OTG_GSL_MASTER_MODE;
4277
4278/*
4279 * OTG_HORZ_REPETITION_COUNT enum
4280 */
4281
4282typedef enum OTG_HORZ_REPETITION_COUNT {
4283OTG_HORZ_REPETITION_COUNT_0 = 0x00000000,
4284OTG_HORZ_REPETITION_COUNT_1 = 0x00000001,
4285OTG_HORZ_REPETITION_COUNT_2 = 0x00000002,
4286OTG_HORZ_REPETITION_COUNT_3 = 0x00000003,
4287OTG_HORZ_REPETITION_COUNT_4 = 0x00000004,
4288OTG_HORZ_REPETITION_COUNT_5 = 0x00000005,
4289OTG_HORZ_REPETITION_COUNT_6 = 0x00000006,
4290OTG_HORZ_REPETITION_COUNT_7 = 0x00000007,
4291OTG_HORZ_REPETITION_COUNT_8 = 0x00000008,
4292OTG_HORZ_REPETITION_COUNT_9 = 0x00000009,
4293OTG_HORZ_REPETITION_COUNT_10 = 0x0000000a,
4294OTG_HORZ_REPETITION_COUNT_11 = 0x0000000b,
4295OTG_HORZ_REPETITION_COUNT_12 = 0x0000000c,
4296OTG_HORZ_REPETITION_COUNT_13 = 0x0000000d,
4297OTG_HORZ_REPETITION_COUNT_14 = 0x0000000e,
4298OTG_HORZ_REPETITION_COUNT_15 = 0x0000000f,
4299} OTG_HORZ_REPETITION_COUNT;
4300
4301/*
4302 * OTG_H_SYNC_A_POL enum
4303 */
4304
4305typedef enum OTG_H_SYNC_A_POL {
4306OTG_H_SYNC_A_POL_HIGH = 0x00000000,
4307OTG_H_SYNC_A_POL_LOW = 0x00000001,
4308} OTG_H_SYNC_A_POL;
4309
4310/*
4311 * OTG_H_TIMING_DIV_MODE enum
4312 */
4313
4314typedef enum OTG_H_TIMING_DIV_MODE {
4315OTG_H_TIMING_DIV_MODE_NO_DIV = 0x00000000,
4316OTG_H_TIMING_DIV_MODE_DIV_BY2 = 0x00000001,
4317OTG_H_TIMING_DIV_MODE_RESERVED = 0x00000002,
4318OTG_H_TIMING_DIV_MODE_DIV_BY4 = 0x00000003,
4319} OTG_H_TIMING_DIV_MODE;
4320
4321/*
4322 * OTG_H_TIMING_DIV_MODE_MANUAL enum
4323 */
4324
4325typedef enum OTG_H_TIMING_DIV_MODE_MANUAL {
4326OTG_H_TIMING_DIV_MODE_AUTO = 0x00000000,
4327OTG_H_TIMING_DIV_MODE_NOAUTO = 0x00000001,
4328} OTG_H_TIMING_DIV_MODE_MANUAL;
4329
4330/*
4331 * OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE enum
4332 */
4333
4334typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE {
4335OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_FALSE = 0x00000000,
4336OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE_TRUE = 0x00000001,
4337} OTG_INTERLACE_CONTROL_OTG_INTERLACE_ENABLE;
4338
4339/*
4340 * OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD enum
4341 */
4342
4343typedef enum OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD {
4344OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT = 0x00000000,
4345OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_BOTTOM = 0x00000001,
4346OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_TOP = 0x00000002,
4347OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD_NOT2 = 0x00000003,
4348} OTG_INTERLACE_CONTROL_OTG_INTERLACE_FORCE_NEXT_FIELD;
4349
4350/*
4351 * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK enum
4352 */
4353
4354typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK {
4355OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_FALSE = 0x00000000,
4356OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK_TRUE = 0x00000001,
4357} OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_MSK;
4358
4359/*
4360 * OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE enum
4361 */
4362
4363typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE {
4364OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_FALSE = 0x00000000,
4365OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE_TRUE = 0x00000001,
4366} OTG_INTERRUPT_CONTROL_OTG_FORCE_COUNT_NOW_INT_TYPE;
4367
4368/*
4369 * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK enum
4370 */
4371
4372typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK {
4373OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_FALSE = 0x00000000,
4374OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK_TRUE = 0x00000001,
4375} OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_MSK;
4376
4377/*
4378 * OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE enum
4379 */
4380
4381typedef enum OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE {
4382OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_FALSE = 0x00000000,
4383OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE_TRUE = 0x00000001,
4384} OTG_INTERRUPT_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_INT_TYPE;
4385
4386/*
4387 * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK enum
4388 */
4389
4390typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK {
4391OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_FALSE = 0x00000000,
4392OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK_TRUE = 0x00000001,
4393} OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_MSK;
4394
4395/*
4396 * OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE enum
4397 */
4398
4399typedef enum OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE {
4400OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_FALSE = 0x00000000,
4401OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE_TRUE = 0x00000001,
4402} OTG_INTERRUPT_CONTROL_OTG_GSL_VSYNC_GAP_INT_TYPE;
4403
4404/*
4405 * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK enum
4406 */
4407
4408typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK {
4409OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_FALSE = 0x00000000,
4410OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK_TRUE = 0x00000001,
4411} OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_MSK;
4412
4413/*
4414 * OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE enum
4415 */
4416
4417typedef enum OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE {
4418OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_FALSE = 0x00000000,
4419OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE_TRUE = 0x00000001,
4420} OTG_INTERRUPT_CONTROL_OTG_SNAPSHOT_INT_TYPE;
4421
4422/*
4423 * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK enum
4424 */
4425
4426typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK {
4427OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_FALSE = 0x00000000,
4428OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK_TRUE = 0x00000001,
4429} OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_MSK;
4430
4431/*
4432 * OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE enum
4433 */
4434
4435typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE {
4436OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_FALSE = 0x00000000,
4437OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE_TRUE = 0x00000001,
4438} OTG_INTERRUPT_CONTROL_OTG_TRIGA_INT_TYPE;
4439
4440/*
4441 * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK enum
4442 */
4443
4444typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK {
4445OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_FALSE = 0x00000000,
4446OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK_TRUE = 0x00000001,
4447} OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_MSK;
4448
4449/*
4450 * OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE enum
4451 */
4452
4453typedef enum OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE {
4454OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_FALSE = 0x00000000,
4455OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE_TRUE = 0x00000001,
4456} OTG_INTERRUPT_CONTROL_OTG_TRIGB_INT_TYPE;
4457
4458/*
4459 * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK enum
4460 */
4461
4462typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK {
4463OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_FALSE = 0x00000000,
4464OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK_TRUE = 0x00000001,
4465} OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_MSK;
4466
4467/*
4468 * OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE enum
4469 */
4470
4471typedef enum OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE {
4472OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_FALSE = 0x00000000,
4473OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE_TRUE = 0x00000001,
4474} OTG_INTERRUPT_CONTROL_OTG_VSYNC_NOM_INT_TYPE;
4475
4476/*
4477 * OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE enum
4478 */
4479
4480typedef enum OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE {
4481OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_FALSE = 0x00000000,
4482OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_TRUE = 0x00000001,
4483} OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE;
4484
4485/*
4486 * OTG_MASTER_UPDATE_LOCK_DB_EN enum
4487 */
4488
4489typedef enum OTG_MASTER_UPDATE_LOCK_DB_EN {
4490OTG_MASTER_UPDATE_LOCK_DISABLE = 0x00000000,
4491OTG_MASTER_UPDATE_LOCK_ENABLE = 0x00000001,
4492} OTG_MASTER_UPDATE_LOCK_DB_EN;
4493
4494/*
4495 * OTG_MASTER_UPDATE_LOCK_GSL_EN enum
4496 */
4497
4498typedef enum OTG_MASTER_UPDATE_LOCK_GSL_EN {
4499OTG_MASTER_UPDATE_LOCK_GSL_EN_FALSE = 0x00000000,
4500OTG_MASTER_UPDATE_LOCK_GSL_EN_TRUE = 0x00000001,
4501} OTG_MASTER_UPDATE_LOCK_GSL_EN;
4502
4503/*
4504 * OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE enum
4505 */
4506
4507typedef enum OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE {
4508OTG_MASTER_UPDATE_LOCK_VCOUNT_0 = 0x00000000,
4509OTG_MASTER_UPDATE_LOCK_VCOUNT_1 = 0x00000001,
4510} OTG_MASTER_UPDATE_LOCK_VCOUNT_MODE;
4511
4512/*
4513 * OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL enum
4514 */
4515
4516typedef enum OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL {
4517OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_DISABLE = 0x00000000,
4518OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERA = 0x00000001,
4519OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_TRIGGERB = 0x00000002,
4520OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL_RESERVED = 0x00000003,
4521} OTG_SNAPSHOT_CONTROL_OTG_AUTO_SNAPSHOT_TRIG_SEL;
4522
4523/*
4524 * OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR enum
4525 */
4526
4527typedef enum OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR {
4528OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_FALSE = 0x00000000,
4529OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR_TRUE = 0x00000001,
4530} OTG_SNAPSHOT_STATUS_OTG_SNAPSHOT_CLEAR;
4531
4532/*
4533 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR enum
4534 */
4535
4536typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR {
4537OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_FALSE = 0x00000000,
4538OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR_TRUE = 0x00000001,
4539} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_CLEAR;
4540
4541/*
4542 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE enum
4543 */
4544
4545typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE {
4546OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_FALSE = 0x00000000,
4547OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE_TRUE = 0x00000001,
4548} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_ENABLE;
4549
4550/*
4551 * OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE enum
4552 */
4553
4554typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE {
4555OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_FALSE = 0x00000000,
4556OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE_TRUE = 0x00000001,
4557} OTG_STATIC_SCREEN_CONTROL_OTG_CPU_SS_INT_TYPE;
4558
4559/*
4560 * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE enum
4561 */
4562
4563typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE {
4564OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_FALSE = 0x00000000,
4565OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_TRUE = 0x00000001,
4566} OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE;
4567
4568/*
4569 * OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE enum
4570 */
4571
4572typedef enum OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE {
4573OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_OFF = 0x00000000,
4574OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE_ON = 0x00000001,
4575} OTG_STATIC_SCREEN_CONTROL_OTG_STATIC_SCREEN_OVERRIDE_VALUE;
4576
4577/*
4578 * OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL enum
4579 */
4580
4581typedef enum OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL {
4582OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_FALSE = 0x00000000,
4583OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL_TRUE = 0x00000001,
4584} OTG_STEREO_CONTROL_OTG_FIELD_NUM_SEL;
4585
4586/*
4587 * OTG_STEREO_CONTROL_OTG_STEREO_EN enum
4588 */
4589
4590typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EN {
4591OTG_STEREO_CONTROL_OTG_STEREO_EN_FALSE = 0x00000000,
4592OTG_STEREO_CONTROL_OTG_STEREO_EN_TRUE = 0x00000001,
4593} OTG_STEREO_CONTROL_OTG_STEREO_EN;
4594
4595/*
4596 * OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY enum
4597 */
4598
4599typedef enum OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY {
4600OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_FALSE = 0x00000000,
4601OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY_TRUE = 0x00000001,
4602} OTG_STEREO_CONTROL_OTG_STEREO_EYE_FLAG_POLARITY;
4603
4604/*
4605 * OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY enum
4606 */
4607
4608typedef enum OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY {
4609OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_FALSE = 0x00000000,
4610OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY_TRUE = 0x00000001,
4611} OTG_STEREO_CONTROL_OTG_STEREO_SYNC_OUTPUT_POLARITY;
4612
4613/*
4614 * OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE enum
4615 */
4616
4617typedef enum OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE {
4618OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_NO = 0x00000000,
4619OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RIGHT = 0x00000001,
4620OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_LEFT = 0x00000002,
4621OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE_RESERVED = 0x00000003,
4622} OTG_STEREO_FORCE_NEXT_EYE_OTG_STEREO_FORCE_NEXT_EYE;
4623
4624/*
4625 * OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR enum
4626 */
4627
4628typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR {
4629OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_FALSE = 0x00000000,
4630OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR_TRUE = 0x00000001,
4631} OTG_TRIGA_CNTL_OTG_TRIGA_CLEAR;
4632
4633/*
4634 * OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT enum
4635 */
4636
4637typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT {
4638OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC0 = 0x00000000,
4639OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_INTERLACE = 0x00000001,
4640OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICA = 0x00000002,
4641OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICB = 0x00000003,
4642OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_HSYNCA = 0x00000004,
4643OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_LOGIC1 = 0x00000005,
4644OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICC = 0x00000006,
4645OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT_GENERICD = 0x00000007,
4646} OTG_TRIGA_CNTL_OTG_TRIGA_POLARITY_SELECT;
4647
4648/*
4649 * OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN enum
4650 */
4651
4652typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN {
4653OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_FALSE = 0x00000000,
4654OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN_TRUE = 0x00000001,
4655} OTG_TRIGA_CNTL_OTG_TRIGA_RESYNC_BYPASS_EN;
4656
4657/*
4658 * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT enum
4659 */
4660
4661typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT {
4662OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG0 = 0x00000000,
4663OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG1 = 0x00000001,
4664OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG2 = 0x00000002,
4665OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_OTG3 = 0x00000003,
4666OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED4 = 0x00000004,
4667OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT_RESERVED5 = 0x00000005,
4668} OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_PIPE_SELECT;
4669
4670/*
4671 * OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT enum
4672 */
4673
4674typedef enum OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT {
4675OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC0 = 0x00000000,
4676OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICA_PIN = 0x00000001,
4677OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICB_PIN = 0x00000002,
4678OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICC_PIN = 0x00000003,
4679OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICD_PIN = 0x00000004,
4680OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICE_PIN = 0x00000005,
4681OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENERICF_PIN = 0x00000006,
4682OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007,
4683OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008,
4684OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009,
4685OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a,
4686OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD1 = 0x0000000b,
4687OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HPD2 = 0x0000000c,
4688OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d,
4689OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_RESERVED14 = 0x0000000e,
4690OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f,
4691OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010,
4692OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_UPDATE_PENDING = 0x00000011,
4693OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_SOF = 0x00000012,
4694OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_HSYNC = 0x00000013,
4695OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_VSYNC = 0x00000014,
4696OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015,
4697OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016,
4698OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_LOGIC1 = 0x00000017,
4699OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT_FLIP_PENDING = 0x00000018,
4700} OTG_TRIGA_CNTL_OTG_TRIGA_SOURCE_SELECT;
4701
4702/*
4703 * OTG_TRIGA_FALLING_EDGE_DETECT_CNTL enum
4704 */
4705
4706typedef enum OTG_TRIGA_FALLING_EDGE_DETECT_CNTL {
4707OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_0 = 0x00000000,
4708OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_1 = 0x00000001,
4709OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_2 = 0x00000002,
4710OTG_TRIGA_FALLING_EDGE_DETECT_CNTL_3 = 0x00000003,
4711} OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;
4712
4713/*
4714 * OTG_TRIGA_FREQUENCY_SELECT enum
4715 */
4716
4717typedef enum OTG_TRIGA_FREQUENCY_SELECT {
4718OTG_TRIGA_FREQUENCY_SELECT_0 = 0x00000000,
4719OTG_TRIGA_FREQUENCY_SELECT_1 = 0x00000001,
4720OTG_TRIGA_FREQUENCY_SELECT_2 = 0x00000002,
4721OTG_TRIGA_FREQUENCY_SELECT_3 = 0x00000003,
4722} OTG_TRIGA_FREQUENCY_SELECT;
4723
4724/*
4725 * OTG_TRIGA_RISING_EDGE_DETECT_CNTL enum
4726 */
4727
4728typedef enum OTG_TRIGA_RISING_EDGE_DETECT_CNTL {
4729OTG_TRIGA_RISING_EDGE_DETECT_CNTL_0 = 0x00000000,
4730OTG_TRIGA_RISING_EDGE_DETECT_CNTL_1 = 0x00000001,
4731OTG_TRIGA_RISING_EDGE_DETECT_CNTL_2 = 0x00000002,
4732OTG_TRIGA_RISING_EDGE_DETECT_CNTL_3 = 0x00000003,
4733} OTG_TRIGA_RISING_EDGE_DETECT_CNTL;
4734
4735/*
4736 * OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR enum
4737 */
4738
4739typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR {
4740OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_FALSE = 0x00000000,
4741OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR_TRUE = 0x00000001,
4742} OTG_TRIGB_CNTL_OTG_TRIGB_CLEAR;
4743
4744/*
4745 * OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT enum
4746 */
4747
4748typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT {
4749OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC0 = 0x00000000,
4750OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_INTERLACE = 0x00000001,
4751OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICA = 0x00000002,
4752OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICB = 0x00000003,
4753OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_HSYNCA = 0x00000004,
4754OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_LOGIC1 = 0x00000005,
4755OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICC = 0x00000006,
4756OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT_GENERICD = 0x00000007,
4757} OTG_TRIGB_CNTL_OTG_TRIGB_POLARITY_SELECT;
4758
4759/*
4760 * OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN enum
4761 */
4762
4763typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN {
4764OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_FALSE = 0x00000000,
4765OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN_TRUE = 0x00000001,
4766} OTG_TRIGB_CNTL_OTG_TRIGB_RESYNC_BYPASS_EN;
4767
4768/*
4769 * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT enum
4770 */
4771
4772typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT {
4773OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG0 = 0x00000000,
4774OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG1 = 0x00000001,
4775OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG2 = 0x00000002,
4776OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_OTG3 = 0x00000003,
4777OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED4 = 0x00000004,
4778OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT_RESERVED5 = 0x00000005,
4779} OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_PIPE_SELECT;
4780
4781/*
4782 * OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT enum
4783 */
4784
4785typedef enum OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT {
4786OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC0 = 0x00000000,
4787OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICA_PIN = 0x00000001,
4788OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICB_PIN = 0x00000002,
4789OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICC_PIN = 0x00000003,
4790OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICD_PIN = 0x00000004,
4791OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICE_PIN = 0x00000005,
4792OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENERICF_PIN = 0x00000006,
4793OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKA_PIN = 0x00000007,
4794OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_SWAPLOCKB_PIN = 0x00000008,
4795OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_CLK_PIN = 0x00000009,
4796OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GENLK_VSYNC_PIN = 0x0000000a,
4797OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD1 = 0x0000000b,
4798OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HPD2 = 0x0000000c,
4799OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_BLON_Y_PIN = 0x0000000d,
4800OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_RESERVED14 = 0x0000000e,
4801OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_LOCK = 0x0000000f,
4802OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_GSL_ALLOW_FLIP = 0x00000010,
4803OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_UPDATE_PENDING = 0x00000011,
4804OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_SOF = 0x00000012,
4805OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_HSYNC = 0x00000013,
4806OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_VSYNC = 0x00000014,
4807OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_OTG_TRIG_MANUAL_CONTROL = 0x00000015,
4808OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_MANUAL_FLOW_CONTROL = 0x00000016,
4809OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_LOGIC1 = 0x00000017,
4810OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT_FLIP_PENDING = 0x00000018,
4811} OTG_TRIGB_CNTL_OTG_TRIGB_SOURCE_SELECT;
4812
4813/*
4814 * OTG_TRIGB_FALLING_EDGE_DETECT_CNTL enum
4815 */
4816
4817typedef enum OTG_TRIGB_FALLING_EDGE_DETECT_CNTL {
4818OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_0 = 0x00000000,
4819OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_1 = 0x00000001,
4820OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_2 = 0x00000002,
4821OTG_TRIGB_FALLING_EDGE_DETECT_CNTL_3 = 0x00000003,
4822} OTG_TRIGB_FALLING_EDGE_DETECT_CNTL;
4823
4824/*
4825 * OTG_TRIGB_FREQUENCY_SELECT enum
4826 */
4827
4828typedef enum OTG_TRIGB_FREQUENCY_SELECT {
4829OTG_TRIGB_FREQUENCY_SELECT_0 = 0x00000000,
4830OTG_TRIGB_FREQUENCY_SELECT_1 = 0x00000001,
4831OTG_TRIGB_FREQUENCY_SELECT_2 = 0x00000002,
4832OTG_TRIGB_FREQUENCY_SELECT_3 = 0x00000003,
4833} OTG_TRIGB_FREQUENCY_SELECT;
4834
4835/*
4836 * OTG_TRIGB_RISING_EDGE_DETECT_CNTL enum
4837 */
4838
4839typedef enum OTG_TRIGB_RISING_EDGE_DETECT_CNTL {
4840OTG_TRIGB_RISING_EDGE_DETECT_CNTL_0 = 0x00000000,
4841OTG_TRIGB_RISING_EDGE_DETECT_CNTL_1 = 0x00000001,
4842OTG_TRIGB_RISING_EDGE_DETECT_CNTL_2 = 0x00000002,
4843OTG_TRIGB_RISING_EDGE_DETECT_CNTL_3 = 0x00000003,
4844} OTG_TRIGB_RISING_EDGE_DETECT_CNTL;
4845
4846/*
4847 * OTG_UPDATE_LOCK_OTG_UPDATE_LOCK enum
4848 */
4849
4850typedef enum OTG_UPDATE_LOCK_OTG_UPDATE_LOCK {
4851OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_FALSE = 0x00000000,
4852OTG_UPDATE_LOCK_OTG_UPDATE_LOCK_TRUE = 0x00000001,
4853} OTG_UPDATE_LOCK_OTG_UPDATE_LOCK;
4854
4855/*
4856 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR enum
4857 */
4858
4859typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR {
4860OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_FALSE = 0x00000000,
4861OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR_TRUE = 0x00000001,
4862} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_CLEAR;
4863
4864/*
4865 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE enum
4866 */
4867
4868typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE {
4869OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_FALSE = 0x00000000,
4870OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE_TRUE = 0x00000001,
4871} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_ENABLE;
4872
4873/*
4874 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE enum
4875 */
4876
4877typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE {
4878OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_FALSE = 0x00000000,
4879OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE_TRUE = 0x00000001,
4880} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_INT_TYPE;
4881
4882/*
4883 * OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY enum
4884 */
4885
4886typedef enum OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY {
4887OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_FALSE = 0x00000000,
4888OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY_TRUE = 0x00000001,
4889} OTG_VERTICAL_INTERRUPT0_CONTROL_OTG_VERTICAL_INTERRUPT0_OUTPUT_POLARITY;
4890
4891/*
4892 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR enum
4893 */
4894
4895typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR {
4896OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_CLEAR_FALSE = 0x00000000,
4897OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR_TRUE = 0x00000001,
4898} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_CLEAR;
4899
4900/*
4901 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE enum
4902 */
4903
4904typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE {
4905OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_FALSE = 0x00000000,
4906OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE_TRUE = 0x00000001,
4907} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_ENABLE;
4908
4909/*
4910 * OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE enum
4911 */
4912
4913typedef enum OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE {
4914OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_FALSE = 0x00000000,
4915OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE_TRUE = 0x00000001,
4916} OTG_VERTICAL_INTERRUPT1_CONTROL_OTG_VERTICAL_INTERRUPT1_INT_TYPE;
4917
4918/*
4919 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR enum
4920 */
4921
4922typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR {
4923OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_CLEAR_FALSE = 0x00000000,
4924OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR_TRUE = 0x00000001,
4925} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_CLEAR;
4926
4927/*
4928 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE enum
4929 */
4930
4931typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE {
4932OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_FALSE = 0x00000000,
4933OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE_TRUE = 0x00000001,
4934} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_ENABLE;
4935
4936/*
4937 * OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE enum
4938 */
4939
4940typedef enum OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE {
4941OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_FALSE = 0x00000000,
4942OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE_TRUE = 0x00000001,
4943} OTG_VERTICAL_INTERRUPT2_CONTROL_OTG_VERTICAL_INTERRUPT2_INT_TYPE;
4944
4945/*
4946 * OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE enum
4947 */
4948
4949typedef enum OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE {
4950OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_DISABLE = 0x00000000,
4951OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERA = 0x00000001,
4952OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_TRIGGERB = 0x00000002,
4953OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE_RESERVED = 0x00000003,
4954} OTG_VERT_SYNC_CONTROL_OTG_AUTO_FORCE_VSYNC_MODE;
4955
4956/*
4957 * OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR enum
4958 */
4959
4960typedef enum OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR {
4961OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_FALSE = 0x00000000,
4962OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR_TRUE = 0x00000001,
4963} OTG_VERT_SYNC_CONTROL_OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;
4964
4965/*
4966 * OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR enum
4967 */
4968
4969typedef enum OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR {
4970OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_FALSE = 0x00000000,
4971OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR_TRUE = 0x00000001,
4972} OTG_VSYNC_NOM_INT_STATUS_OTG_VSYNC_NOM_INT_CLEAR;
4973
4974/*
4975 * OTG_VUPDATE_BLOCK_DISABLE enum
4976 */
4977
4978typedef enum OTG_VUPDATE_BLOCK_DISABLE {
4979OTG_VUPDATE_BLOCK_DISABLE_OFF = 0x00000000,
4980OTG_VUPDATE_BLOCK_DISABLE_ON = 0x00000001,
4981} OTG_VUPDATE_BLOCK_DISABLE;
4982
4983/*
4984 * OTG_V_SYNC_A_POL enum
4985 */
4986
4987typedef enum OTG_V_SYNC_A_POL {
4988OTG_V_SYNC_A_POL_HIGH = 0x00000000,
4989OTG_V_SYNC_A_POL_LOW = 0x00000001,
4990} OTG_V_SYNC_A_POL;
4991
4992/*
4993 * OTG_V_SYNC_MODE enum
4994 */
4995
4996typedef enum OTG_V_SYNC_MODE {
4997OTG_V_SYNC_MODE_HSYNC = 0x00000000,
4998OTG_V_SYNC_MODE_HBLANK = 0x00000001,
4999} OTG_V_SYNC_MODE;
5000
5001/*
5002 * OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD enum
5003 */
5004
5005typedef enum OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD {
5006OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_0 = 0x00000000,
5007OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD_1 = 0x00000001,
5008} OTG_V_TOTAL_CONTROL_OTG_DRR_EVENT_ACTIVE_PERIOD;
5009
5010/*
5011 * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT enum
5012 */
5013
5014typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT {
5015OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_DISABLE = 0x00000000,
5016OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT_ENABLE = 0x00000001,
5017} OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_ON_EVENT;
5018
5019/*
5020 * OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC enum
5021 */
5022
5023typedef enum OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC {
5024OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_DISABLE = 0x00000000,
5025OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC_ENABLE = 0x00000001,
5026} OTG_V_TOTAL_CONTROL_OTG_FORCE_LOCK_TO_MASTER_VSYNC;
5027
5028/*
5029 * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL enum
5030 */
5031
5032typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL {
5033OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_FALSE = 0x00000000,
5034OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL_TRUE = 0x00000001,
5035} OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MAX_SEL;
5036
5037/*
5038 * OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL enum
5039 */
5040
5041typedef enum OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL {
5042OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_FALSE = 0x00000000,
5043OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL_TRUE = 0x00000001,
5044} OTG_V_TOTAL_CONTROL_OTG_V_TOTAL_MIN_SEL;
5045
5046/*
5047 * OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK enum
5048 */
5049
5050typedef enum OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK {
5051OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_FALSE = 0x00000000,
5052OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK_TRUE = 0x00000001,
5053} OTG_V_TOTAL_INT_STATUS_OTG_SET_V_TOTAL_MIN_EVENT_OCCURRED_ACK;
5054
5055/*******************************************************
5056 * OPTC_MISC Enums
5057 *******************************************************/
5058
5059/*
5060 * OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL enum
5061 */
5062
5063typedef enum OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL {
5064OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG0 = 0x00000000,
5065OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG1 = 0x00000001,
5066OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG2 = 0x00000002,
5067OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_OTG3 = 0x00000003,
5068OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED4 = 0x00000004,
5069OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL_RESERVED5 = 0x00000005,
5070} OPTC_GSL_SOURCE_SELECT_GSL_TIMING_SYNC_SEL;
5071
5072/*******************************************************
5073 * DMCUB Enums
5074 *******************************************************/
5075
5076/*
5077 * DC_DMCUB_INT_TYPE enum
5078 */
5079
5080typedef enum DC_DMCUB_INT_TYPE {
5081INT_LEVEL = 0x00000000,
5082INT_PULSE = 0x00000001,
5083} DC_DMCUB_INT_TYPE;
5084
5085/*
5086 * DC_DMCUB_TIMER_WINDOW enum
5087 */
5088
5089typedef enum DC_DMCUB_TIMER_WINDOW {
5090BITS_31_0 = 0x00000000,
5091BITS_32_1 = 0x00000001,
5092BITS_33_2 = 0x00000002,
5093BITS_34_3 = 0x00000003,
5094BITS_35_4 = 0x00000004,
5095BITS_36_5 = 0x00000005,
5096BITS_37_6 = 0x00000006,
5097BITS_38_7 = 0x00000007,
5098} DC_DMCUB_TIMER_WINDOW;
5099
5100/*******************************************************
5101 * RBBMIF Enums
5102 *******************************************************/
5103
5104/*
5105 * INVALID_REG_ACCESS_TYPE enum
5106 */
5107
5108typedef enum INVALID_REG_ACCESS_TYPE {
5109REG_UNALLOCATED_ADDR_WRITE = 0x00000000,
5110REG_UNALLOCATED_ADDR_READ = 0x00000001,
5111REG_VIRTUAL_WRITE = 0x00000002,
5112REG_VIRTUAL_READ = 0x00000003,
5113REG_SECURE_VIOLATE_WRITE = 0x00000004,
5114REG_SECURE_VIOLATE_READ = 0x00000005,
5115} INVALID_REG_ACCESS_TYPE;
5116
5117/*******************************************************
5118 * IHC Enums
5119 *******************************************************/
5120
5121/*
5122 * DMU_DC_GPU_TIMER_READ_SELECT enum
5123 */
5124
5125typedef enum DMU_DC_GPU_TIMER_READ_SELECT {
5126DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_0 = 0x00000000,
5127DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_1 = 0x00000001,
5128DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_2 = 0x00000002,
5129DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_3 = 0x00000003,
5130DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_4 = 0x00000004,
5131DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_5 = 0x00000005,
5132DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_6 = 0x00000006,
5133DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_7 = 0x00000007,
5134RESERVED_8 = 0x00000008,
5135RESERVED_9 = 0x00000009,
5136RESERVED_10 = 0x0000000a,
5137RESERVED_11 = 0x0000000b,
5138DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_STARTUP_12 = 0x0000000c,
5139DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_STARTUP_13 = 0x0000000d,
5140DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_STARTUP_14 = 0x0000000e,
5141DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_STARTUP_15 = 0x0000000f,
5142DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_STARTUP_16 = 0x00000010,
5143DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_STARTUP_17 = 0x00000011,
5144DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_STARTUP_18 = 0x00000012,
5145DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_STARTUP_19 = 0x00000013,
5146RESERVED_20 = 0x00000014,
5147RESERVED_21 = 0x00000015,
5148RESERVED_22 = 0x00000016,
5149RESERVED_23 = 0x00000017,
5150DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VSYNC_NOM_24 = 0x00000018,
5151DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VSYNC_NOM_25 = 0x00000019,
5152DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VSYNC_NOM_26 = 0x0000001a,
5153DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VSYNC_NOM_27 = 0x0000001b,
5154DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VSYNC_NOM_28 = 0x0000001c,
5155DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VSYNC_NOM_29 = 0x0000001d,
5156DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VSYNC_NOM_30 = 0x0000001e,
5157DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VSYNC_NOM_31 = 0x0000001f,
5158RESERVED_32 = 0x00000020,
5159RESERVED_33 = 0x00000021,
5160RESERVED_34 = 0x00000022,
5161RESERVED_35 = 0x00000023,
5162DMU_GPU_TIMER_READ_SELECT_LOWER_D1_VREADY_36 = 0x00000024,
5163DMU_GPU_TIMER_READ_SELECT_UPPER_D1_VREADY_37 = 0x00000025,
5164DMU_GPU_TIMER_READ_SELECT_LOWER_D2_VREADY_38 = 0x00000026,
5165DMU_GPU_TIMER_READ_SELECT_UPPER_D2_VREADY_39 = 0x00000027,
5166DMU_GPU_TIMER_READ_SELECT_LOWER_D3_VREADY_40 = 0x00000028,
5167DMU_GPU_TIMER_READ_SELECT_UPPER_D3_VREADY_41 = 0x00000029,
5168DMU_GPU_TIMER_READ_SELECT_LOWER_D4_VREADY_42 = 0x0000002a,
5169DMU_GPU_TIMER_READ_SELECT_UPPER_D4_VREADY_43 = 0x0000002b,
5170RESERVED_44 = 0x0000002c,
5171RESERVED_45 = 0x0000002d,
5172RESERVED_46 = 0x0000002e,
5173RESERVED_47 = 0x0000002f,
5174DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_48 = 0x00000030,
5175DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_49 = 0x00000031,
5176DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_50 = 0x00000032,
5177DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_51 = 0x00000033,
5178DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_52 = 0x00000034,
5179DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_53 = 0x00000035,
5180DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_54 = 0x00000036,
5181DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_55 = 0x00000037,
5182RESERVED_56 = 0x00000038,
5183RESERVED_57 = 0x00000039,
5184RESERVED_58 = 0x0000003a,
5185RESERVED_59 = 0x0000003b,
5186RESERVED_60 = 0x0000003c,
5187RESERVED_61 = 0x0000003d,
5188RESERVED_62 = 0x0000003e,
5189RESERVED_63 = 0x0000003f,
5190DMU_GPU_TIMER_READ_SELECT_LOWER_D1_V_UPDATE_NO_LOCK_64 = 0x00000040,
5191DMU_GPU_TIMER_READ_SELECT_UPPER_D1_V_UPDATE_NO_LOCK_65 = 0x00000041,
5192DMU_GPU_TIMER_READ_SELECT_LOWER_D2_V_UPDATE_NO_LOCK_66 = 0x00000042,
5193DMU_GPU_TIMER_READ_SELECT_UPPER_D2_V_UPDATE_NO_LOCK_67 = 0x00000043,
5194DMU_GPU_TIMER_READ_SELECT_LOWER_D3_V_UPDATE_NO_LOCK_68 = 0x00000044,
5195DMU_GPU_TIMER_READ_SELECT_UPPER_D3_V_UPDATE_NO_LOCK_69 = 0x00000045,
5196DMU_GPU_TIMER_READ_SELECT_LOWER_D4_V_UPDATE_NO_LOCK_70 = 0x00000046,
5197DMU_GPU_TIMER_READ_SELECT_UPPER_D4_V_UPDATE_NO_LOCK_71 = 0x00000047,
5198RESERVED_72 = 0x00000048,
5199RESERVED_73 = 0x00000049,
5200RESERVED_74 = 0x0000004a,
5201RESERVED_75 = 0x0000004b,
5202DMU_GPU_TIMER_READ_SELECT_LOWER_D1_FLIP_AWAY_76 = 0x0000004c,
5203DMU_GPU_TIMER_READ_SELECT_UPPER_D1_FLIP_AWAY_77 = 0x0000004d,
5204DMU_GPU_TIMER_READ_SELECT_LOWER_D2_FLIP_AWAY_78 = 0x0000004e,
5205DMU_GPU_TIMER_READ_SELECT_UPPER_D2_FLIP_AWAY_79 = 0x0000004f,
5206DMU_GPU_TIMER_READ_SELECT_LOWER_D3_FLIP_AWAY_80 = 0x00000050,
5207DMU_GPU_TIMER_READ_SELECT_UPPER_D3_FLIP_AWAY_81 = 0x00000051,
5208DMU_GPU_TIMER_READ_SELECT_LOWER_D4_FLIP_AWAY_82 = 0x00000052,
5209DMU_GPU_TIMER_READ_SELECT_UPPER_D4_FLIP_AWAY_83 = 0x00000053,
5210RESERVED_84 = 0x00000054,
5211RESERVED_85 = 0x00000055,
5212RESERVED_86 = 0x00000056,
5213RESERVED_87 = 0x00000057,
5214RESERVED_88 = 0x00000058,
5215RESERVED_89 = 0x00000059,
5216RESERVED_90 = 0x0000005a,
5217RESERVED_91 = 0x0000005b,
5218} DMU_DC_GPU_TIMER_READ_SELECT;
5219
5220/*
5221 * DMU_DC_GPU_TIMER_START_POSITION enum
5222 */
5223
5224typedef enum DMU_DC_GPU_TIMER_START_POSITION {
5225DMU_GPU_TIMER_START_0_END_27 = 0x00000000,
5226DMU_GPU_TIMER_START_1_END_28 = 0x00000001,
5227DMU_GPU_TIMER_START_2_END_29 = 0x00000002,
5228DMU_GPU_TIMER_START_3_END_30 = 0x00000003,
5229DMU_GPU_TIMER_START_4_END_31 = 0x00000004,
5230DMU_GPU_TIMER_START_6_END_33 = 0x00000005,
5231DMU_GPU_TIMER_START_8_END_35 = 0x00000006,
5232DMU_GPU_TIMER_START_10_END_37 = 0x00000007,
5233} DMU_DC_GPU_TIMER_START_POSITION;
5234
5235/*
5236 * IHC_INTERRUPT_DEST enum
5237 */
5238
5239typedef enum IHC_INTERRUPT_DEST {
5240INTERRUPT_SENT_TO_IH = 0x00000000,
5241INTERRUPT_SENT_TO_DMCUB = 0x00000001,
5242} IHC_INTERRUPT_DEST;
5243
5244/*
5245 * IHC_INTERRUPT_LINE_STATUS enum
5246 */
5247
5248typedef enum IHC_INTERRUPT_LINE_STATUS {
5249INTERRUPT_LINE_NOT_ASSERTED = 0x00000000,
5250INTERRUPT_LINE_ASSERTED = 0x00000001,
5251} IHC_INTERRUPT_LINE_STATUS;
5252
5253/*******************************************************
5254 * DMU_MISC Enums
5255 *******************************************************/
5256
5257/*
5258 * DC_SMU_INTERRUPT_ENABLE enum
5259 */
5260
5261typedef enum DC_SMU_INTERRUPT_ENABLE {
5262DISABLE_THE_INTERRUPT = 0x00000000,
5263ENABLE_THE_INTERRUPT = 0x00000001,
5264} DC_SMU_INTERRUPT_ENABLE;
5265
5266/*
5267 * DMU_CLOCK_ON enum
5268 */
5269
5270typedef enum DMU_CLOCK_ON {
5271DMU_CLOCK_STATUS_ON = 0x00000000,
5272DMU_CLOCK_STATUS_OFF = 0x00000001,
5273} DMU_CLOCK_ON;
5274
5275/*
5276 * SMU_INTR enum
5277 */
5278
5279typedef enum SMU_INTR {
5280SMU_MSG_INTR_NOOP = 0x00000000,
5281SET_SMU_MSG_INTR = 0x00000001,
5282} SMU_INTR;
5283
5284/*******************************************************
5285 * DCCG Enums
5286 *******************************************************/
5287
5288/*
5289 * ALLOW_SR_ON_TRANS_REQ enum
5290 */
5291
5292typedef enum ALLOW_SR_ON_TRANS_REQ {
5293ALLOW_SR_ON_TRANS_REQ_ENABLE = 0x00000000,
5294ALLOW_SR_ON_TRANS_REQ_DISABLE = 0x00000001,
5295} ALLOW_SR_ON_TRANS_REQ;
5296
5297/*
5298 * AMCLOCK_ENABLE enum
5299 */
5300
5301typedef enum AMCLOCK_ENABLE {
5302ENABLE_AMCLK0 = 0x00000000,
5303ENABLE_AMCLK1 = 0x00000001,
5304} AMCLOCK_ENABLE;
5305
5306/*
5307 * CLEAR_SMU_INTR enum
5308 */
5309
5310typedef enum CLEAR_SMU_INTR {
5311SMU_INTR_STATUS_NOOP = 0x00000000,
5312SMU_INTR_STATUS_CLEAR = 0x00000001,
5313} CLEAR_SMU_INTR;
5314
5315/*
5316 * CLOCK_BRANCH_SOFT_RESET enum
5317 */
5318
5319typedef enum CLOCK_BRANCH_SOFT_RESET {
5320CLOCK_BRANCH_SOFT_RESET_NOOP = 0x00000000,
5321CLOCK_BRANCH_SOFT_RESET_FORCE = 0x00000001,
5322} CLOCK_BRANCH_SOFT_RESET;
5323
5324/*
5325 * DCCG_AUDIO_DTO0_SOURCE_SEL enum
5326 */
5327
5328typedef enum DCCG_AUDIO_DTO0_SOURCE_SEL {
5329DCCG_AUDIO_DTO0_SOURCE_SEL_OTG0 = 0x00000000,
5330DCCG_AUDIO_DTO0_SOURCE_SEL_OTG1 = 0x00000001,
5331DCCG_AUDIO_DTO0_SOURCE_SEL_OTG2 = 0x00000002,
5332DCCG_AUDIO_DTO0_SOURCE_SEL_OTG3 = 0x00000003,
5333DCCG_AUDIO_DTO0_SOURCE_SEL_RESERVED = 0x00000004,
5334} DCCG_AUDIO_DTO0_SOURCE_SEL;
5335
5336/*
5337 * DCCG_AUDIO_DTO2_SOURCE_SEL enum
5338 */
5339
5340typedef enum DCCG_AUDIO_DTO2_SOURCE_SEL {
5341DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0 = 0x00000000,
5342DCCG_AUDIO_DTO2_SOURCE_SEL_AMCLK0_DIV2 = 0x00000001,
5343} DCCG_AUDIO_DTO2_SOURCE_SEL;
5344
5345/*
5346 * DCCG_AUDIO_DTO_SEL enum
5347 */
5348
5349typedef enum DCCG_AUDIO_DTO_SEL {
5350DCCG_AUDIO_DTO_SEL_AUDIO_DTO0 = 0x00000000,
5351DCCG_AUDIO_DTO_SEL_AUDIO_DTO1 = 0x00000001,
5352DCCG_AUDIO_DTO_SEL_NO_AUDIO_DTO = 0x00000002,
5353DCCG_AUDIO_DTO_SEL_AUDIO_DTO_DTBCLK = 0x00000003,
5354} DCCG_AUDIO_DTO_SEL;
5355
5356/*
5357 * DCCG_AUDIO_DTO_USE_512FBR_DTO enum
5358 */
5359
5360typedef enum DCCG_AUDIO_DTO_USE_512FBR_DTO {
5361DCCG_AUDIO_DTO_USE_128FBR_FOR_DP = 0x00000000,
5362DCCG_AUDIO_DTO_USE_512FBR_FOR_DP = 0x00000001,
5363} DCCG_AUDIO_DTO_USE_512FBR_DTO;
5364
5365/*
5366 * DCCG_DBG_BLOCK_SEL enum
5367 */
5368
5369typedef enum DCCG_DBG_BLOCK_SEL {
5370DCCG_DBG_BLOCK_SEL_DCCG = 0x00000000,
5371DCCG_DBG_BLOCK_SEL_PMON = 0x00000001,
5372DCCG_DBG_BLOCK_SEL_PMON2 = 0x00000002,
5373} DCCG_DBG_BLOCK_SEL;
5374
5375/*
5376 * DCCG_DBG_EN enum
5377 */
5378
5379typedef enum DCCG_DBG_EN {
5380DCCG_DBG_EN_DISABLE = 0x00000000,
5381DCCG_DBG_EN_ENABLE = 0x00000001,
5382} DCCG_DBG_EN;
5383
5384/*
5385 * DCCG_DEEP_COLOR_CNTL enum
5386 */
5387
5388typedef enum DCCG_DEEP_COLOR_CNTL {
5389DCCG_DEEP_COLOR_DTO_DISABLE = 0x00000000,
5390DCCG_DEEP_COLOR_DTO_5_4_RATIO = 0x00000001,
5391DCCG_DEEP_COLOR_DTO_3_2_RATIO = 0x00000002,
5392DCCG_DEEP_COLOR_DTO_2_1_RATIO = 0x00000003,
5393} DCCG_DEEP_COLOR_CNTL;
5394
5395/*
5396 * DCCG_FIFO_ERRDET_OVR_EN enum
5397 */
5398
5399typedef enum DCCG_FIFO_ERRDET_OVR_EN {
5400DCCG_FIFO_ERRDET_OVR_DISABLE = 0x00000000,
5401DCCG_FIFO_ERRDET_OVR_ENABLE = 0x00000001,
5402} DCCG_FIFO_ERRDET_OVR_EN;
5403
5404/*
5405 * DCCG_FIFO_ERRDET_RESET enum
5406 */
5407
5408typedef enum DCCG_FIFO_ERRDET_RESET {
5409DCCG_FIFO_ERRDET_RESET_NOOP = 0x00000000,
5410DCCG_FIFO_ERRDET_RESET_FORCE = 0x00000001,
5411} DCCG_FIFO_ERRDET_RESET;
5412
5413/*
5414 * DCCG_FIFO_ERRDET_STATE enum
5415 */
5416
5417typedef enum DCCG_FIFO_ERRDET_STATE {
5418DCCG_FIFO_ERRDET_STATE_CALIBRATION = 0x00000000,
5419DCCG_FIFO_ERRDET_STATE_DETECTION = 0x00000001,
5420} DCCG_FIFO_ERRDET_STATE;
5421
5422/*
5423 * DCCG_PERF_MODE_HSYNC enum
5424 */
5425
5426typedef enum DCCG_PERF_MODE_HSYNC {
5427DCCG_PERF_MODE_HSYNC_NOOP = 0x00000000,
5428DCCG_PERF_MODE_HSYNC_START = 0x00000001,
5429} DCCG_PERF_MODE_HSYNC;
5430
5431/*
5432 * DCCG_PERF_MODE_VSYNC enum
5433 */
5434
5435typedef enum DCCG_PERF_MODE_VSYNC {
5436DCCG_PERF_MODE_VSYNC_NOOP = 0x00000000,
5437DCCG_PERF_MODE_VSYNC_START = 0x00000001,
5438} DCCG_PERF_MODE_VSYNC;
5439
5440/*
5441 * DCCG_PERF_OTG_SELECT enum
5442 */
5443
5444typedef enum DCCG_PERF_OTG_SELECT {
5445DCCG_PERF_SEL_OTG0 = 0x00000000,
5446DCCG_PERF_SEL_OTG1 = 0x00000001,
5447DCCG_PERF_SEL_OTG2 = 0x00000002,
5448DCCG_PERF_SEL_OTG3 = 0x00000003,
5449DCCG_PERF_SEL_RESERVED = 0x00000004,
5450} DCCG_PERF_OTG_SELECT;
5451
5452/*
5453 * DCCG_PERF_RUN enum
5454 */
5455
5456typedef enum DCCG_PERF_RUN {
5457DCCG_PERF_RUN_NOOP = 0x00000000,
5458DCCG_PERF_RUN_START = 0x00000001,
5459} DCCG_PERF_RUN;
5460
5461/*
5462 * DC_MEM_GLOBAL_PWR_REQ_DIS enum
5463 */
5464
5465typedef enum DC_MEM_GLOBAL_PWR_REQ_DIS {
5466DC_MEM_GLOBAL_PWR_REQ_ENABLE = 0x00000000,
5467DC_MEM_GLOBAL_PWR_REQ_DISABLE = 0x00000001,
5468} DC_MEM_GLOBAL_PWR_REQ_DIS;
5469
5470/*
5471 * DIO_FIFO_ERROR enum
5472 */
5473
5474typedef enum DIO_FIFO_ERROR {
5475DIO_FIFO_ERROR_00 = 0x00000000,
5476DIO_FIFO_ERROR_01 = 0x00000001,
5477DIO_FIFO_ERROR_10 = 0x00000002,
5478DIO_FIFO_ERROR_11 = 0x00000003,
5479} DIO_FIFO_ERROR;
5480
5481/*
5482 * DISABLE_CLOCK_GATING enum
5483 */
5484
5485typedef enum DISABLE_CLOCK_GATING {
5486CLOCK_GATING_ENABLED = 0x00000000,
5487CLOCK_GATING_DISABLED = 0x00000001,
5488} DISABLE_CLOCK_GATING;
5489
5490/*
5491 * DISABLE_CLOCK_GATING_IN_DCO enum
5492 */
5493
5494typedef enum DISABLE_CLOCK_GATING_IN_DCO {
5495CLOCK_GATING_ENABLED_IN_DCO = 0x00000000,
5496CLOCK_GATING_DISABLED_IN_DCO = 0x00000001,
5497} DISABLE_CLOCK_GATING_IN_DCO;
5498
5499/*
5500 * DISPCLK_CHG_FWD_CORR_DISABLE enum
5501 */
5502
5503typedef enum DISPCLK_CHG_FWD_CORR_DISABLE {
5504DISPCLK_CHG_FWD_CORR_ENABLE_AT_BEGINNING = 0x00000000,
5505DISPCLK_CHG_FWD_CORR_DISABLE_AT_BEGINNING = 0x00000001,
5506} DISPCLK_CHG_FWD_CORR_DISABLE;
5507
5508/*
5509 * DISPCLK_FREQ_RAMP_DONE enum
5510 */
5511
5512typedef enum DISPCLK_FREQ_RAMP_DONE {
5513DISPCLK_FREQ_RAMP_IN_PROGRESS = 0x00000000,
5514DISPCLK_FREQ_RAMP_COMPLETED = 0x00000001,
5515} DISPCLK_FREQ_RAMP_DONE;
5516
5517/*
5518 * DPREFCLK_SRC_SEL enum
5519 */
5520
5521typedef enum DPREFCLK_SRC_SEL {
5522DPREFCLK_SRC_SEL_CK = 0x00000000,
5523DPREFCLK_SRC_SEL_P0PLL = 0x00000001,
5524DPREFCLK_SRC_SEL_P1PLL = 0x00000002,
5525DPREFCLK_SRC_SEL_P2PLL = 0x00000003,
5526} DPREFCLK_SRC_SEL;
5527
5528/*
5529 * DP_DTO_DS_DISABLE enum
5530 */
5531
5532typedef enum DP_DTO_DS_DISABLE {
5533DP_DTO_DESPREAD_DISABLE = 0x00000000,
5534DP_DTO_DESPREAD_ENABLE = 0x00000001,
5535} DP_DTO_DS_DISABLE;
5536
5537/*
5538 * DS_HW_CAL_ENABLE enum
5539 */
5540
5541typedef enum DS_HW_CAL_ENABLE {
5542DS_HW_CAL_DIS = 0x00000000,
5543DS_HW_CAL_EN = 0x00000001,
5544} DS_HW_CAL_ENABLE;
5545
5546/*
5547 * DS_JITTER_COUNT_SRC_SEL enum
5548 */
5549
5550typedef enum DS_JITTER_COUNT_SRC_SEL {
5551DS_JITTER_COUNT_SRC_SEL0 = 0x00000000,
5552DS_JITTER_COUNT_SRC_SEL1 = 0x00000001,
5553} DS_JITTER_COUNT_SRC_SEL;
5554
5555/*
5556 * DS_REF_SRC enum
5557 */
5558
5559typedef enum DS_REF_SRC {
5560DS_REF_IS_XTALIN = 0x00000000,
5561DS_REF_IS_EXT_GENLOCK = 0x00000001,
5562DS_REF_IS_PCIE = 0x00000002,
5563} DS_REF_SRC;
5564
5565/*
5566 * DVOACLKC_IN_PHASE enum
5567 */
5568
5569typedef enum DVOACLKC_IN_PHASE {
5570DVOACLKC_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
5571DVOACLKC_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
5572} DVOACLKC_IN_PHASE;
5573
5574/*
5575 * DVOACLKC_MVP_IN_PHASE enum
5576 */
5577
5578typedef enum DVOACLKC_MVP_IN_PHASE {
5579DVOACLKC_MVP_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
5580DVOACLKC_MVP_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
5581} DVOACLKC_MVP_IN_PHASE;
5582
5583/*
5584 * DVOACLKC_MVP_SKEW_PHASE_OVERRIDE enum
5585 */
5586
5587typedef enum DVOACLKC_MVP_SKEW_PHASE_OVERRIDE {
5588DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_DISABLE = 0x00000000,
5589DVOACLKC_MVP_SKEW_PHASE_OVERRIDE_ENABLE = 0x00000001,
5590} DVOACLKC_MVP_SKEW_PHASE_OVERRIDE;
5591
5592/*
5593 * DVOACLKD_IN_PHASE enum
5594 */
5595
5596typedef enum DVOACLKD_IN_PHASE {
5597DVOACLKD_IN_OPPOSITE_PHASE_WITH_PCLK_DVO = 0x00000000,
5598DVOACLKD_IN_PHASE_WITH_PCLK_DVO = 0x00000001,
5599} DVOACLKD_IN_PHASE;
5600
5601/*
5602 * DVOACLK_COARSE_SKEW_CNTL enum
5603 */
5604
5605typedef enum DVOACLK_COARSE_SKEW_CNTL {
5606DVOACLK_COARSE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000,
5607DVOACLK_COARSE_SKEW_CNTL_DELAY_1_STEP = 0x00000001,
5608DVOACLK_COARSE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002,
5609DVOACLK_COARSE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003,
5610DVOACLK_COARSE_SKEW_CNTL_DELAY_4_STEPS = 0x00000004,
5611DVOACLK_COARSE_SKEW_CNTL_DELAY_5_STEPS = 0x00000005,
5612DVOACLK_COARSE_SKEW_CNTL_DELAY_6_STEPS = 0x00000006,
5613DVOACLK_COARSE_SKEW_CNTL_DELAY_7_STEPS = 0x00000007,
5614DVOACLK_COARSE_SKEW_CNTL_DELAY_8_STEPS = 0x00000008,
5615DVOACLK_COARSE_SKEW_CNTL_DELAY_9_STEPS = 0x00000009,
5616DVOACLK_COARSE_SKEW_CNTL_DELAY_10_STEPS = 0x0000000a,
5617DVOACLK_COARSE_SKEW_CNTL_DELAY_11_STEPS = 0x0000000b,
5618DVOACLK_COARSE_SKEW_CNTL_DELAY_12_STEPS = 0x0000000c,
5619DVOACLK_COARSE_SKEW_CNTL_DELAY_13_STEPS = 0x0000000d,
5620DVOACLK_COARSE_SKEW_CNTL_DELAY_14_STEPS = 0x0000000e,
5621DVOACLK_COARSE_SKEW_CNTL_DELAY_15_STEPS = 0x0000000f,
5622DVOACLK_COARSE_SKEW_CNTL_EARLY_1_STEP = 0x00000010,
5623DVOACLK_COARSE_SKEW_CNTL_EARLY_2_STEPS = 0x00000011,
5624DVOACLK_COARSE_SKEW_CNTL_EARLY_3_STEPS = 0x00000012,
5625DVOACLK_COARSE_SKEW_CNTL_EARLY_4_STEPS = 0x00000013,
5626DVOACLK_COARSE_SKEW_CNTL_EARLY_5_STEPS = 0x00000014,
5627DVOACLK_COARSE_SKEW_CNTL_EARLY_6_STEPS = 0x00000015,
5628DVOACLK_COARSE_SKEW_CNTL_EARLY_7_STEPS = 0x00000016,
5629DVOACLK_COARSE_SKEW_CNTL_EARLY_8_STEPS = 0x00000017,
5630DVOACLK_COARSE_SKEW_CNTL_EARLY_9_STEPS = 0x00000018,
5631DVOACLK_COARSE_SKEW_CNTL_EARLY_10_STEPS = 0x00000019,
5632DVOACLK_COARSE_SKEW_CNTL_EARLY_11_STEPS = 0x0000001a,
5633DVOACLK_COARSE_SKEW_CNTL_EARLY_12_STEPS = 0x0000001b,
5634DVOACLK_COARSE_SKEW_CNTL_EARLY_13_STEPS = 0x0000001c,
5635DVOACLK_COARSE_SKEW_CNTL_EARLY_14_STEPS = 0x0000001d,
5636DVOACLK_COARSE_SKEW_CNTL_EARLY_15_STEPS = 0x0000001e,
5637} DVOACLK_COARSE_SKEW_CNTL;
5638
5639/*
5640 * DVOACLK_FINE_SKEW_CNTL enum
5641 */
5642
5643typedef enum DVOACLK_FINE_SKEW_CNTL {
5644DVOACLK_FINE_SKEW_CNTL_NO_ADJUSTMENT = 0x00000000,
5645DVOACLK_FINE_SKEW_CNTL_DELAY_1_STEP = 0x00000001,
5646DVOACLK_FINE_SKEW_CNTL_DELAY_2_STEPS = 0x00000002,
5647DVOACLK_FINE_SKEW_CNTL_DELAY_3_STEPS = 0x00000003,
5648DVOACLK_FINE_SKEW_CNTL_EARLY_1_STEP = 0x00000004,
5649DVOACLK_FINE_SKEW_CNTL_EARLY_2_STEPS = 0x00000005,
5650DVOACLK_FINE_SKEW_CNTL_EARLY_3_STEPS = 0x00000006,
5651DVOACLK_FINE_SKEW_CNTL_EARLY_4_STEPS = 0x00000007,
5652} DVOACLK_FINE_SKEW_CNTL;
5653
5654/*
5655 * DVO_ENABLE_RST enum
5656 */
5657
5658typedef enum DVO_ENABLE_RST {
5659DVO_ENABLE_RST_DISABLE = 0x00000000,
5660DVO_ENABLE_RST_ENABLE = 0x00000001,
5661} DVO_ENABLE_RST;
5662
5663/*
5664 * ENABLE enum
5665 */
5666
5667typedef enum ENABLE {
5668DISABLE_THE_FEATURE = 0x00000000,
5669ENABLE_THE_FEATURE = 0x00000001,
5670} ENABLE;
5671
5672/*
5673 * ENABLE_CLOCK enum
5674 */
5675
5676typedef enum ENABLE_CLOCK {
5677ENABLE_THE_REFCLK = 0x00000000,
5678ENABLE_THE_FUNC_CLOCK = 0x00000001,
5679} ENABLE_CLOCK;
5680
5681/*
5682 * FORCE_DISABLE_CLOCK enum
5683 */
5684
5685typedef enum FORCE_DISABLE_CLOCK {
5686NOT_FORCE_THE_CLOCK_DISABLED = 0x00000000,
5687FORCE_THE_CLOCK_DISABLED = 0x00000001,
5688} FORCE_DISABLE_CLOCK;
5689
5690/*
5691 * HDMICHARCLK_SRC_SEL enum
5692 */
5693
5694typedef enum HDMICHARCLK_SRC_SEL {
5695HDMICHARCLK_SRC_SEL_UNIPHYA = 0x00000000,
5696HDMICHARCLK_SRC_SEL_UNIPHYB = 0x00000001,
5697HDMICHARCLK_SRC_SEL_UNIPHYC = 0x00000002,
5698HDMICHARCLK_SRC_SEL_UNIPHYD = 0x00000003,
5699HDMICHARCLK_SRC_SEL_UNIPHYE = 0x00000004,
5700HDMICHARCLK_SRC_SEL_SRC_RESERVED = 0x00000005,
5701} HDMICHARCLK_SRC_SEL;
5702
5703/*
5704 * HDMISTREAMCLK_DTO_FORCE_DIS enum
5705 */
5706
5707typedef enum HDMISTREAMCLK_DTO_FORCE_DIS {
5708DTO_FORCE_NO_BYPASS = 0x00000000,
5709DTO_FORCE_BYPASS = 0x00000001,
5710} HDMISTREAMCLK_DTO_FORCE_DIS;
5711
5712/*
5713 * HDMISTREAMCLK_SRC_SEL enum
5714 */
5715
5716typedef enum HDMISTREAMCLK_SRC_SEL {
5717SEL_REFCLK0 = 0x00000000,
5718SEL_DTBCLK0 = 0x00000001,
5719SEL_DTBCLK1 = 0x00000002,
5720} HDMISTREAMCLK_SRC_SEL;
5721
5722/*
5723 * JITTER_REMOVE_DISABLE enum
5724 */
5725
5726typedef enum JITTER_REMOVE_DISABLE {
5727ENABLE_JITTER_REMOVAL = 0x00000000,
5728DISABLE_JITTER_REMOVAL = 0x00000001,
5729} JITTER_REMOVE_DISABLE;
5730
5731/*
5732 * MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
5733 */
5734
5735typedef enum MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL {
5736MICROSECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000,
5737MICROSECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 0x00000001,
5738} MICROSECOND_TIME_BASE_CLOCK_SOURCE_SEL;
5739
5740/*
5741 * MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL enum
5742 */
5743
5744typedef enum MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL {
5745MILLISECOND_TIME_BASE_CLOCK_IS_XTALIN = 0x00000000,
5746MILLISECOND_TIME_BASE_CLOCK_IS_DCCGREFCLK = 0x00000001,
5747} MILLISECOND_TIME_BASE_CLOCK_SOURCE_SEL;
5748
5749/*
5750 * OTG_ADD_PIXEL enum
5751 */
5752
5753typedef enum OTG_ADD_PIXEL {
5754OTG_ADD_PIXEL_NOOP = 0x00000000,
5755OTG_ADD_PIXEL_FORCE = 0x00000001,
5756} OTG_ADD_PIXEL;
5757
5758/*
5759 * OTG_DROP_PIXEL enum
5760 */
5761
5762typedef enum OTG_DROP_PIXEL {
5763OTG_DROP_PIXEL_NOOP = 0x00000000,
5764OTG_DROP_PIXEL_FORCE = 0x00000001,
5765} OTG_DROP_PIXEL;
5766
5767/*
5768 * PHYSYMCLK_FORCE_EN enum
5769 */
5770
5771typedef enum PHYSYMCLK_FORCE_EN {
5772PHYSYMCLK_FORCE_EN_DISABLE = 0x00000000,
5773PHYSYMCLK_FORCE_EN_ENABLE = 0x00000001,
5774} PHYSYMCLK_FORCE_EN;
5775
5776/*
5777 * PHYSYMCLK_FORCE_SRC_SEL enum
5778 */
5779
5780typedef enum PHYSYMCLK_FORCE_SRC_SEL {
5781PHYSYMCLK_FORCE_SRC_SYMCLK = 0x00000000,
5782PHYSYMCLK_FORCE_SRC_PHYD18CLK = 0x00000001,
5783PHYSYMCLK_FORCE_SRC_PHYD32CLK = 0x00000002,
5784} PHYSYMCLK_FORCE_SRC_SEL;
5785
5786/*
5787 * PIPE_PHYPLL_PIXEL_RATE_SOURCE enum
5788 */
5789
5790typedef enum PIPE_PHYPLL_PIXEL_RATE_SOURCE {
5791PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYA = 0x00000000,
5792PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYB = 0x00000001,
5793PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYC = 0x00000002,
5794PIPE_PHYPLL_PIXEL_RATE_SOURCE_UNIPHYD = 0x00000003,
5795PIPE_PHYPLL_PIXEL_RATE_SOURCE_RESERVED = 0x00000004,
5796} PIPE_PHYPLL_PIXEL_RATE_SOURCE;
5797
5798/*
5799 * PIPE_PIXEL_RATE_PLL_SOURCE enum
5800 */
5801
5802typedef enum PIPE_PIXEL_RATE_PLL_SOURCE {
5803PIPE_PIXEL_RATE_PLL_SOURCE_PHYPLL = 0x00000000,
5804PIPE_PIXEL_RATE_PLL_SOURCE_DISPPLL = 0x00000001,
5805} PIPE_PIXEL_RATE_PLL_SOURCE;
5806
5807/*
5808 * PIPE_PIXEL_RATE_SOURCE enum
5809 */
5810
5811typedef enum PIPE_PIXEL_RATE_SOURCE {
5812PIPE_PIXEL_RATE_SOURCE_P0PLL = 0x00000000,
5813PIPE_PIXEL_RATE_SOURCE_P1PLL = 0x00000001,
5814PIPE_PIXEL_RATE_SOURCE_P2PLL = 0x00000002,
5815} PIPE_PIXEL_RATE_SOURCE;
5816
5817/*
5818 * PLL_CFG_IF_SOFT_RESET enum
5819 */
5820
5821typedef enum PLL_CFG_IF_SOFT_RESET {
5822PLL_CFG_IF_SOFT_RESET_NOOP = 0x00000000,
5823PLL_CFG_IF_SOFT_RESET_FORCE = 0x00000001,
5824} PLL_CFG_IF_SOFT_RESET;
5825
5826/*
5827 * SYMCLK_FE_FORCE_EN enum
5828 */
5829
5830typedef enum SYMCLK_FE_FORCE_EN {
5831SYMCLK_FE_FORCE_EN_DISABLE = 0x00000000,
5832SYMCLK_FE_FORCE_EN_ENABLE = 0x00000001,
5833} SYMCLK_FE_FORCE_EN;
5834
5835/*
5836 * SYMCLK_FE_FORCE_SRC enum
5837 */
5838
5839typedef enum SYMCLK_FE_FORCE_SRC {
5840SYMCLK_FE_FORCE_SRC_UNIPHYA = 0x00000000,
5841SYMCLK_FE_FORCE_SRC_UNIPHYB = 0x00000001,
5842SYMCLK_FE_FORCE_SRC_UNIPHYC = 0x00000002,
5843SYMCLK_FE_FORCE_SRC_UNIPHYD = 0x00000003,
5844SYMCLK_FE_FORCE_SRC_RESERVED = 0x00000004,
5845} SYMCLK_FE_FORCE_SRC;
5846
5847/*
5848 * TEST_CLK_DIV_SEL enum
5849 */
5850
5851typedef enum TEST_CLK_DIV_SEL {
5852NO_DIV = 0x00000000,
5853DIV_2 = 0x00000001,
5854DIV_4 = 0x00000002,
5855DIV_8 = 0x00000003,
5856} TEST_CLK_DIV_SEL;
5857
5858/*
5859 * VSYNC_CNT_LATCH_MASK enum
5860 */
5861
5862typedef enum VSYNC_CNT_LATCH_MASK {
5863VSYNC_CNT_LATCH_MASK_0 = 0x00000000,
5864VSYNC_CNT_LATCH_MASK_1 = 0x00000001,
5865} VSYNC_CNT_LATCH_MASK;
5866
5867/*
5868 * VSYNC_CNT_RESET_SEL enum
5869 */
5870
5871typedef enum VSYNC_CNT_RESET_SEL {
5872VSYNC_CNT_RESET_SEL_0 = 0x00000000,
5873VSYNC_CNT_RESET_SEL_1 = 0x00000001,
5874} VSYNC_CNT_RESET_SEL;
5875
5876/*
5877 * XTAL_REF_CLOCK_SOURCE_SEL enum
5878 */
5879
5880typedef enum XTAL_REF_CLOCK_SOURCE_SEL {
5881XTAL_REF_CLOCK_SOURCE_SEL_XTALIN = 0x00000000,
5882XTAL_REF_CLOCK_SOURCE_SEL_DCCGREFCLK = 0x00000001,
5883} XTAL_REF_CLOCK_SOURCE_SEL;
5884
5885/*
5886 * XTAL_REF_SEL enum
5887 */
5888
5889typedef enum XTAL_REF_SEL {
5890XTAL_REF_SEL_1X = 0x00000000,
5891XTAL_REF_SEL_2X = 0x00000001,
5892} XTAL_REF_SEL;
5893
5894/*******************************************************
5895 * HPD Enums
5896 *******************************************************/
5897
5898/*
5899 * HPD_INT_CONTROL_ACK enum
5900 */
5901
5902typedef enum HPD_INT_CONTROL_ACK {
5903HPD_INT_CONTROL_ACK_0 = 0x00000000,
5904HPD_INT_CONTROL_ACK_1 = 0x00000001,
5905} HPD_INT_CONTROL_ACK;
5906
5907/*
5908 * HPD_INT_CONTROL_POLARITY enum
5909 */
5910
5911typedef enum HPD_INT_CONTROL_POLARITY {
5912HPD_INT_CONTROL_GEN_INT_ON_DISCON = 0x00000000,
5913HPD_INT_CONTROL_GEN_INT_ON_CON = 0x00000001,
5914} HPD_INT_CONTROL_POLARITY;
5915
5916/*
5917 * HPD_INT_CONTROL_RX_INT_ACK enum
5918 */
5919
5920typedef enum HPD_INT_CONTROL_RX_INT_ACK {
5921HPD_INT_CONTROL_RX_INT_ACK_0 = 0x00000000,
5922HPD_INT_CONTROL_RX_INT_ACK_1 = 0x00000001,
5923} HPD_INT_CONTROL_RX_INT_ACK;
5924
5925/*******************************************************
5926 * DP Enums
5927 *******************************************************/
5928
5929/*
5930 * DPHY_8B10B_CUR_DISP enum
5931 */
5932
5933typedef enum DPHY_8B10B_CUR_DISP {
5934DPHY_8B10B_CUR_DISP_ZERO = 0x00000000,
5935DPHY_8B10B_CUR_DISP_ONE = 0x00000001,
5936} DPHY_8B10B_CUR_DISP;
5937
5938/*
5939 * DPHY_8B10B_RESET enum
5940 */
5941
5942typedef enum DPHY_8B10B_RESET {
5943DPHY_8B10B_NOT_RESET = 0x00000000,
5944DPHY_8B10B_RESETET = 0x00000001,
5945} DPHY_8B10B_RESET;
5946
5947/*
5948 * DPHY_ALT_SCRAMBLER_RESET_EN enum
5949 */
5950
5951typedef enum DPHY_ALT_SCRAMBLER_RESET_EN {
5952DPHY_ALT_SCRAMBLER_REGULAR_RESET_VALUE = 0x00000000,
5953DPHY_ALT_SCRAMBLER_INTERNAL_RESET_SOLUTION = 0x00000001,
5954} DPHY_ALT_SCRAMBLER_RESET_EN;
5955
5956/*
5957 * DPHY_ALT_SCRAMBLER_RESET_SEL enum
5958 */
5959
5960typedef enum DPHY_ALT_SCRAMBLER_RESET_SEL {
5961DPHY_ALT_SCRAMBLER_RESET_SEL_EDP_RESET_VALUE = 0x00000000,
5962DPHY_ALT_SCRAMBLER_RESET_SEL_CUSTOM_RESET_VALUE = 0x00000001,
5963} DPHY_ALT_SCRAMBLER_RESET_SEL;
5964
5965/*
5966 * DPHY_ATEST_SEL_LANE0 enum
5967 */
5968
5969typedef enum DPHY_ATEST_SEL_LANE0 {
5970DPHY_ATEST_LANE0_PRBS_PATTERN = 0x00000000,
5971DPHY_ATEST_LANE0_REG_PATTERN = 0x00000001,
5972} DPHY_ATEST_SEL_LANE0;
5973
5974/*
5975 * DPHY_ATEST_SEL_LANE1 enum
5976 */
5977
5978typedef enum DPHY_ATEST_SEL_LANE1 {
5979DPHY_ATEST_LANE1_PRBS_PATTERN = 0x00000000,
5980DPHY_ATEST_LANE1_REG_PATTERN = 0x00000001,
5981} DPHY_ATEST_SEL_LANE1;
5982
5983/*
5984 * DPHY_ATEST_SEL_LANE2 enum
5985 */
5986
5987typedef enum DPHY_ATEST_SEL_LANE2 {
5988DPHY_ATEST_LANE2_PRBS_PATTERN = 0x00000000,
5989DPHY_ATEST_LANE2_REG_PATTERN = 0x00000001,
5990} DPHY_ATEST_SEL_LANE2;
5991
5992/*
5993 * DPHY_ATEST_SEL_LANE3 enum
5994 */
5995
5996typedef enum DPHY_ATEST_SEL_LANE3 {
5997DPHY_ATEST_LANE3_PRBS_PATTERN = 0x00000000,
5998DPHY_ATEST_LANE3_REG_PATTERN = 0x00000001,
5999} DPHY_ATEST_SEL_LANE3;
6000
6001/*
6002 * DPHY_BYPASS enum
6003 */
6004
6005typedef enum DPHY_BYPASS {
6006DPHY_8B10B_OUTPUT = 0x00000000,
6007DPHY_DBG_OUTPUT = 0x00000001,
6008} DPHY_BYPASS;
6009
6010/*
6011 * DPHY_CRC_CONT_EN enum
6012 */
6013
6014typedef enum