1/*
2 * Copyright (C) 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
20 */
21#ifndef _vega10_ip_offset_HEADER
22#define _vega10_ip_offset_HEADER
23
24#define MAX_INSTANCE 5
25#define MAX_SEGMENT 5
26
27struct IP_BASE_INSTANCE {
28 unsigned int segment[MAX_SEGMENT];
29};
30
31struct IP_BASE {
32 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
33};
34
35
36static const struct IP_BASE __maybe_unused NBIF_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
37 { { 0, 0, 0, 0, 0 } },
38 { { 0, 0, 0, 0, 0 } },
39 { { 0, 0, 0, 0, 0 } },
40 { { 0, 0, 0, 0, 0 } } } };
41static const struct IP_BASE __maybe_unused NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0 } },
42 { { 0, 0, 0, 0, 0 } },
43 { { 0, 0, 0, 0, 0 } },
44 { { 0, 0, 0, 0, 0 } },
45 { { 0, 0, 0, 0, 0 } } } };
46static const struct IP_BASE __maybe_unused DCE_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
47 { { 0, 0, 0, 0, 0 } },
48 { { 0, 0, 0, 0, 0 } },
49 { { 0, 0, 0, 0, 0 } },
50 { { 0, 0, 0, 0, 0 } } } };
51static const struct IP_BASE __maybe_unused DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } },
52 { { 0, 0, 0, 0, 0 } },
53 { { 0, 0, 0, 0, 0 } },
54 { { 0, 0, 0, 0, 0 } },
55 { { 0, 0, 0, 0, 0 } } } };
56static const struct IP_BASE __maybe_unused MP0_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
57 { { 0, 0, 0, 0, 0 } },
58 { { 0, 0, 0, 0, 0 } },
59 { { 0, 0, 0, 0, 0 } },
60 { { 0, 0, 0, 0, 0 } } } };
61static const struct IP_BASE __maybe_unused MP1_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
62 { { 0, 0, 0, 0, 0 } },
63 { { 0, 0, 0, 0, 0 } },
64 { { 0, 0, 0, 0, 0 } },
65 { { 0, 0, 0, 0, 0 } } } };
66static const struct IP_BASE __maybe_unused MP2_BASE = { { { { 0x00016000, 0, 0, 0, 0 } },
67 { { 0, 0, 0, 0, 0 } },
68 { { 0, 0, 0, 0, 0 } },
69 { { 0, 0, 0, 0, 0 } },
70 { { 0, 0, 0, 0, 0 } } } };
71static const struct IP_BASE __maybe_unused DF_BASE = { { { { 0x00007000, 0, 0, 0, 0 } },
72 { { 0, 0, 0, 0, 0 } },
73 { { 0, 0, 0, 0, 0 } },
74 { { 0, 0, 0, 0, 0 } },
75 { { 0, 0, 0, 0, 0 } } } };
76static const struct IP_BASE __maybe_unused UVD_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
77 { { 0, 0, 0, 0, 0 } },
78 { { 0, 0, 0, 0, 0 } },
79 { { 0, 0, 0, 0, 0 } },
80 { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment
81static const struct IP_BASE __maybe_unused VCN_BASE = { { { { 0x00007800, 0x00007E00, 0, 0, 0 } },
82 { { 0, 0, 0, 0, 0 } },
83 { { 0, 0, 0, 0, 0 } },
84 { { 0, 0, 0, 0, 0 } },
85 { { 0, 0, 0, 0, 0 } } } }; //note: GLN does not use the first segment
86static const struct IP_BASE __maybe_unused DBGU_BASE = { { { { 0x00000180, 0x000001A0, 0, 0, 0 } },
87 { { 0, 0, 0, 0, 0 } },
88 { { 0, 0, 0, 0, 0 } },
89 { { 0, 0, 0, 0, 0 } },
90 { { 0, 0, 0, 0, 0 } } } }; // not exist
91static const struct IP_BASE __maybe_unused DBGU_NBIO_BASE = { { { { 0x000001C0, 0, 0, 0, 0 } },
92 { { 0, 0, 0, 0, 0 } },
93 { { 0, 0, 0, 0, 0 } },
94 { { 0, 0, 0, 0, 0 } },
95 { { 0, 0, 0, 0, 0 } } } }; // not exist
96static const struct IP_BASE __maybe_unused DBGU_IO_BASE = { { { { 0x000001E0, 0, 0, 0, 0 } },
97 { { 0, 0, 0, 0, 0 } },
98 { { 0, 0, 0, 0, 0 } },
99 { { 0, 0, 0, 0, 0 } },
100 { { 0, 0, 0, 0, 0 } } } }; // not exist
101static const struct IP_BASE __maybe_unused DFX_DAP_BASE = { { { { 0x000005A0, 0, 0, 0, 0 } },
102 { { 0, 0, 0, 0, 0 } },
103 { { 0, 0, 0, 0, 0 } },
104 { { 0, 0, 0, 0, 0 } },
105 { { 0, 0, 0, 0, 0 } } } }; // not exist
106static const struct IP_BASE __maybe_unused DFX_BASE = { { { { 0x00000580, 0, 0, 0, 0 } },
107 { { 0, 0, 0, 0, 0 } },
108 { { 0, 0, 0, 0, 0 } },
109 { { 0, 0, 0, 0, 0 } },
110 { { 0, 0, 0, 0, 0 } } } }; // this file does not contain registers
111static const struct IP_BASE __maybe_unused ISP_BASE = { { { { 0x00018000, 0, 0, 0, 0 } },
112 { { 0, 0, 0, 0, 0 } },
113 { { 0, 0, 0, 0, 0 } },
114 { { 0, 0, 0, 0, 0 } },
115 { { 0, 0, 0, 0, 0 } } } }; // not exist
116static const struct IP_BASE __maybe_unused SYSTEMHUB_BASE = { { { { 0x00000EA0, 0, 0, 0, 0 } },
117 { { 0, 0, 0, 0, 0 } },
118 { { 0, 0, 0, 0, 0 } },
119 { { 0, 0, 0, 0, 0 } },
120 { { 0, 0, 0, 0, 0 } } } }; // not exist
121static const struct IP_BASE __maybe_unused L2IMU_BASE = { { { { 0x00007DC0, 0, 0, 0, 0 } },
122 { { 0, 0, 0, 0, 0 } },
123 { { 0, 0, 0, 0, 0 } },
124 { { 0, 0, 0, 0, 0 } },
125 { { 0, 0, 0, 0, 0 } } } };
126static const struct IP_BASE __maybe_unused IOHC_BASE = { { { { 0x00010000, 0, 0, 0, 0 } },
127 { { 0, 0, 0, 0, 0 } },
128 { { 0, 0, 0, 0, 0 } },
129 { { 0, 0, 0, 0, 0 } },
130 { { 0, 0, 0, 0, 0 } } } };
131static const struct IP_BASE __maybe_unused ATHUB_BASE = { { { { 0x00000C20, 0, 0, 0, 0 } },
132 { { 0, 0, 0, 0, 0 } },
133 { { 0, 0, 0, 0, 0 } },
134 { { 0, 0, 0, 0, 0 } },
135 { { 0, 0, 0, 0, 0 } } } };
136static const struct IP_BASE __maybe_unused VCE_BASE = { { { { 0x00007E00, 0x00048800, 0, 0, 0 } },
137 { { 0, 0, 0, 0, 0 } },
138 { { 0, 0, 0, 0, 0 } },
139 { { 0, 0, 0, 0, 0 } },
140 { { 0, 0, 0, 0, 0 } } } };
141static const struct IP_BASE __maybe_unused GC_BASE = { { { { 0x00002000, 0x0000A000, 0, 0, 0 } },
142 { { 0, 0, 0, 0, 0 } },
143 { { 0, 0, 0, 0, 0 } },
144 { { 0, 0, 0, 0, 0 } },
145 { { 0, 0, 0, 0, 0 } } } };
146static const struct IP_BASE __maybe_unused MMHUB_BASE = { { { { 0x0001A000, 0, 0, 0, 0 } },
147 { { 0, 0, 0, 0, 0 } },
148 { { 0, 0, 0, 0, 0 } },
149 { { 0, 0, 0, 0, 0 } },
150 { { 0, 0, 0, 0, 0 } } } };
151static const struct IP_BASE __maybe_unused RSMU_BASE = { { { { 0x00012000, 0, 0, 0, 0 } },
152 { { 0, 0, 0, 0, 0 } },
153 { { 0, 0, 0, 0, 0 } },
154 { { 0, 0, 0, 0, 0 } },
155 { { 0, 0, 0, 0, 0 } } } };
156static const struct IP_BASE __maybe_unused HDP_BASE = { { { { 0x00000F20, 0, 0, 0, 0 } },
157 { { 0, 0, 0, 0, 0 } },
158 { { 0, 0, 0, 0, 0 } },
159 { { 0, 0, 0, 0, 0 } },
160 { { 0, 0, 0, 0, 0 } } } };
161static const struct IP_BASE __maybe_unused OSSSYS_BASE = { { { { 0x000010A0, 0, 0, 0, 0 } },
162 { { 0, 0, 0, 0, 0 } },
163 { { 0, 0, 0, 0, 0 } },
164 { { 0, 0, 0, 0, 0 } },
165 { { 0, 0, 0, 0, 0 } } } };
166static const struct IP_BASE __maybe_unused SDMA0_BASE = { { { { 0x00001260, 0, 0, 0, 0 } },
167 { { 0, 0, 0, 0, 0 } },
168 { { 0, 0, 0, 0, 0 } },
169 { { 0, 0, 0, 0, 0 } },
170 { { 0, 0, 0, 0, 0 } } } };
171static const struct IP_BASE __maybe_unused SDMA1_BASE = { { { { 0x00001460, 0, 0, 0, 0 } },
172 { { 0, 0, 0, 0, 0 } },
173 { { 0, 0, 0, 0, 0 } },
174 { { 0, 0, 0, 0, 0 } },
175 { { 0, 0, 0, 0, 0 } } } };
176static const struct IP_BASE __maybe_unused XDMA_BASE = { { { { 0x00003400, 0, 0, 0, 0 } },
177 { { 0, 0, 0, 0, 0 } },
178 { { 0, 0, 0, 0, 0 } },
179 { { 0, 0, 0, 0, 0 } },
180 { { 0, 0, 0, 0, 0 } } } };
181static const struct IP_BASE __maybe_unused UMC_BASE = { { { { 0x00014000, 0, 0, 0, 0 } },
182 { { 0, 0, 0, 0, 0 } },
183 { { 0, 0, 0, 0, 0 } },
184 { { 0, 0, 0, 0, 0 } },
185 { { 0, 0, 0, 0, 0 } } } };
186static const struct IP_BASE __maybe_unused THM_BASE = { { { { 0x00016600, 0, 0, 0, 0 } },
187 { { 0, 0, 0, 0, 0 } },
188 { { 0, 0, 0, 0, 0 } },
189 { { 0, 0, 0, 0, 0 } },
190 { { 0, 0, 0, 0, 0 } } } };
191static const struct IP_BASE __maybe_unused SMUIO_BASE = { { { { 0x00016800, 0, 0, 0, 0 } },
192 { { 0, 0, 0, 0, 0 } },
193 { { 0, 0, 0, 0, 0 } },
194 { { 0, 0, 0, 0, 0 } },
195 { { 0, 0, 0, 0, 0 } } } };
196static const struct IP_BASE __maybe_unused PWR_BASE = { { { { 0x00016A00, 0, 0, 0, 0 } },
197 { { 0, 0, 0, 0, 0 } },
198 { { 0, 0, 0, 0, 0 } },
199 { { 0, 0, 0, 0, 0 } },
200 { { 0, 0, 0, 0, 0 } } } };
201static const struct IP_BASE __maybe_unused CLK_BASE = { { { { 0x00016C00, 0, 0, 0, 0 } },
202 { { 0x00016E00, 0, 0, 0, 0 } },
203 { { 0x00017000, 0, 0, 0, 0 } },
204 { { 0x00017200, 0, 0, 0, 0 } },
205 { { 0x00017E00, 0, 0, 0, 0 } } } };
206static const struct IP_BASE __maybe_unused FUSE_BASE = { { { { 0x00017400, 0, 0, 0, 0 } },
207 { { 0, 0, 0, 0, 0 } },
208 { { 0, 0, 0, 0, 0 } },
209 { { 0, 0, 0, 0, 0 } },
210 { { 0, 0, 0, 0, 0 } } } };
211
212
213#define NBIF_BASE__INST0_SEG0 0x00000000
214#define NBIF_BASE__INST0_SEG1 0x00000014
215#define NBIF_BASE__INST0_SEG2 0x00000D20
216#define NBIF_BASE__INST0_SEG3 0x00010400
217#define NBIF_BASE__INST0_SEG4 0
218
219#define NBIF_BASE__INST1_SEG0 0
220#define NBIF_BASE__INST1_SEG1 0
221#define NBIF_BASE__INST1_SEG2 0
222#define NBIF_BASE__INST1_SEG3 0
223#define NBIF_BASE__INST1_SEG4 0
224
225#define NBIF_BASE__INST2_SEG0 0
226#define NBIF_BASE__INST2_SEG1 0
227#define NBIF_BASE__INST2_SEG2 0
228#define NBIF_BASE__INST2_SEG3 0
229#define NBIF_BASE__INST2_SEG4 0
230
231#define NBIF_BASE__INST3_SEG0 0
232#define NBIF_BASE__INST3_SEG1 0
233#define NBIF_BASE__INST3_SEG2 0
234#define NBIF_BASE__INST3_SEG3 0
235#define NBIF_BASE__INST3_SEG4 0
236
237#define NBIF_BASE__INST4_SEG0 0
238#define NBIF_BASE__INST4_SEG1 0
239#define NBIF_BASE__INST4_SEG2 0
240#define NBIF_BASE__INST4_SEG3 0
241#define NBIF_BASE__INST4_SEG4 0
242
243#define NBIO_BASE__INST0_SEG0 0x00000000
244#define NBIO_BASE__INST0_SEG1 0x00000014
245#define NBIO_BASE__INST0_SEG2 0x00000D20
246#define NBIO_BASE__INST0_SEG3 0x00010400
247#define NBIO_BASE__INST0_SEG4 0
248
249#define NBIO_BASE__INST1_SEG0 0
250#define NBIO_BASE__INST1_SEG1 0
251#define NBIO_BASE__INST1_SEG2 0
252#define NBIO_BASE__INST1_SEG3 0
253#define NBIO_BASE__INST1_SEG4 0
254
255#define NBIO_BASE__INST2_SEG0 0
256#define NBIO_BASE__INST2_SEG1 0
257#define NBIO_BASE__INST2_SEG2 0
258#define NBIO_BASE__INST2_SEG3 0
259#define NBIO_BASE__INST2_SEG4 0
260
261#define NBIO_BASE__INST3_SEG0 0
262#define NBIO_BASE__INST3_SEG1 0
263#define NBIO_BASE__INST3_SEG2 0
264#define NBIO_BASE__INST3_SEG3 0
265#define NBIO_BASE__INST3_SEG4 0
266
267#define NBIO_BASE__INST4_SEG0 0
268#define NBIO_BASE__INST4_SEG1 0
269#define NBIO_BASE__INST4_SEG2 0
270#define NBIO_BASE__INST4_SEG3 0
271#define NBIO_BASE__INST4_SEG4 0
272
273#define DCE_BASE__INST0_SEG0 0x00000012
274#define DCE_BASE__INST0_SEG1 0x000000C0
275#define DCE_BASE__INST0_SEG2 0x000034C0
276#define DCE_BASE__INST0_SEG3 0
277#define DCE_BASE__INST0_SEG4 0
278
279#define DCE_BASE__INST1_SEG0 0
280#define DCE_BASE__INST1_SEG1 0
281#define DCE_BASE__INST1_SEG2 0
282#define DCE_BASE__INST1_SEG3 0
283#define DCE_BASE__INST1_SEG4 0
284
285#define DCE_BASE__INST2_SEG0 0
286#define DCE_BASE__INST2_SEG1 0
287#define DCE_BASE__INST2_SEG2 0
288#define DCE_BASE__INST2_SEG3 0
289#define DCE_BASE__INST2_SEG4 0
290
291#define DCE_BASE__INST3_SEG0 0
292#define DCE_BASE__INST3_SEG1 0
293#define DCE_BASE__INST3_SEG2 0
294#define DCE_BASE__INST3_SEG3 0
295#define DCE_BASE__INST3_SEG4 0
296
297#define DCE_BASE__INST4_SEG0 0
298#define DCE_BASE__INST4_SEG1 0
299#define DCE_BASE__INST4_SEG2 0
300#define DCE_BASE__INST4_SEG3 0
301#define DCE_BASE__INST4_SEG4 0
302
303#define DCN_BASE__INST0_SEG0 0x00000012
304#define DCN_BASE__INST0_SEG1 0x000000C0
305#define DCN_BASE__INST0_SEG2 0x000034C0
306#define DCN_BASE__INST0_SEG3 0
307#define DCN_BASE__INST0_SEG4 0
308
309#define DCN_BASE__INST1_SEG0 0
310#define DCN_BASE__INST1_SEG1 0
311#define DCN_BASE__INST1_SEG2 0
312#define DCN_BASE__INST1_SEG3 0
313#define DCN_BASE__INST1_SEG4 0
314
315#define DCN_BASE__INST2_SEG0 0
316#define DCN_BASE__INST2_SEG1 0
317#define DCN_BASE__INST2_SEG2 0
318#define DCN_BASE__INST2_SEG3 0
319#define DCN_BASE__INST2_SEG4 0
320
321#define DCN_BASE__INST3_SEG0 0
322#define DCN_BASE__INST3_SEG1 0
323#define DCN_BASE__INST3_SEG2 0
324#define DCN_BASE__INST3_SEG3 0
325#define DCN_BASE__INST3_SEG4 0
326
327#define DCN_BASE__INST4_SEG0 0
328#define DCN_BASE__INST4_SEG1 0
329#define DCN_BASE__INST4_SEG2 0
330#define DCN_BASE__INST4_SEG3 0
331#define DCN_BASE__INST4_SEG4 0
332
333#define MP0_BASE__INST0_SEG0 0x00016000
334#define MP0_BASE__INST0_SEG1 0
335#define MP0_BASE__INST0_SEG2 0
336#define MP0_BASE__INST0_SEG3 0
337#define MP0_BASE__INST0_SEG4 0
338
339#define MP0_BASE__INST1_SEG0 0
340#define MP0_BASE__INST1_SEG1 0
341#define MP0_BASE__INST1_SEG2 0
342#define MP0_BASE__INST1_SEG3 0
343#define MP0_BASE__INST1_SEG4 0
344
345#define MP0_BASE__INST2_SEG0 0
346#define MP0_BASE__INST2_SEG1 0
347#define MP0_BASE__INST2_SEG2 0
348#define MP0_BASE__INST2_SEG3 0
349#define MP0_BASE__INST2_SEG4 0
350
351#define MP0_BASE__INST3_SEG0 0
352#define MP0_BASE__INST3_SEG1 0
353#define MP0_BASE__INST3_SEG2 0
354#define MP0_BASE__INST3_SEG3 0
355#define MP0_BASE__INST3_SEG4 0
356
357#define MP0_BASE__INST4_SEG0 0
358#define MP0_BASE__INST4_SEG1 0
359#define MP0_BASE__INST4_SEG2 0
360#define MP0_BASE__INST4_SEG3 0
361#define MP0_BASE__INST4_SEG4 0
362
363#define MP1_BASE__INST0_SEG0 0x00016200
364#define MP1_BASE__INST0_SEG1 0
365#define MP1_BASE__INST0_SEG2 0
366#define MP1_BASE__INST0_SEG3 0
367#define MP1_BASE__INST0_SEG4 0
368
369#define MP1_BASE__INST1_SEG0 0
370#define MP1_BASE__INST1_SEG1 0
371#define MP1_BASE__INST1_SEG2 0
372#define MP1_BASE__INST1_SEG3 0
373#define MP1_BASE__INST1_SEG4 0
374
375#define MP1_BASE__INST2_SEG0 0
376#define MP1_BASE__INST2_SEG1 0
377#define MP1_BASE__INST2_SEG2 0
378#define MP1_BASE__INST2_SEG3 0
379#define MP1_BASE__INST2_SEG4 0
380
381#define MP1_BASE__INST3_SEG0 0
382#define MP1_BASE__INST3_SEG1 0
383#define MP1_BASE__INST3_SEG2 0
384#define MP1_BASE__INST3_SEG3 0
385#define MP1_BASE__INST3_SEG4 0
386
387#define MP1_BASE__INST4_SEG0 0
388#define MP1_BASE__INST4_SEG1 0
389#define MP1_BASE__INST4_SEG2 0
390#define MP1_BASE__INST4_SEG3 0
391#define MP1_BASE__INST4_SEG4 0
392
393#define MP2_BASE__INST0_SEG0 0x00016400
394#define MP2_BASE__INST0_SEG1 0
395#define MP2_BASE__INST0_SEG2 0
396#define MP2_BASE__INST0_SEG3 0
397#define MP2_BASE__INST0_SEG4 0
398
399#define MP2_BASE__INST1_SEG0 0
400#define MP2_BASE__INST1_SEG1 0
401#define MP2_BASE__INST1_SEG2 0
402#define MP2_BASE__INST1_SEG3 0
403#define MP2_BASE__INST1_SEG4 0
404
405#define MP2_BASE__INST2_SEG0 0
406#define MP2_BASE__INST2_SEG1 0
407#define MP2_BASE__INST2_SEG2 0
408#define MP2_BASE__INST2_SEG3 0
409#define MP2_BASE__INST2_SEG4 0
410
411#define MP2_BASE__INST3_SEG0 0
412#define MP2_BASE__INST3_SEG1 0
413#define MP2_BASE__INST3_SEG2 0
414#define MP2_BASE__INST3_SEG3 0
415#define MP2_BASE__INST3_SEG4 0
416
417#define MP2_BASE__INST4_SEG0 0
418#define MP2_BASE__INST4_SEG1 0
419#define MP2_BASE__INST4_SEG2 0
420#define MP2_BASE__INST4_SEG3 0
421#define MP2_BASE__INST4_SEG4 0
422
423#define DF_BASE__INST0_SEG0 0x00007000
424#define DF_BASE__INST0_SEG1 0
425#define DF_BASE__INST0_SEG2 0
426#define DF_BASE__INST0_SEG3 0
427#define DF_BASE__INST0_SEG4 0
428
429#define DF_BASE__INST1_SEG0 0
430#define DF_BASE__INST1_SEG1 0
431#define DF_BASE__INST1_SEG2 0
432#define DF_BASE__INST1_SEG3 0
433#define DF_BASE__INST1_SEG4 0
434
435#define DF_BASE__INST2_SEG0 0
436#define DF_BASE__INST2_SEG1 0
437#define DF_BASE__INST2_SEG2 0
438#define DF_BASE__INST2_SEG3 0
439#define DF_BASE__INST2_SEG4 0
440
441#define DF_BASE__INST3_SEG0 0
442#define DF_BASE__INST3_SEG1 0
443#define DF_BASE__INST3_SEG2 0
444#define DF_BASE__INST3_SEG3 0
445#define DF_BASE__INST3_SEG4 0
446
447#define DF_BASE__INST4_SEG0 0
448#define DF_BASE__INST4_SEG1 0
449#define DF_BASE__INST4_SEG2 0
450#define DF_BASE__INST4_SEG3 0
451#define DF_BASE__INST4_SEG4 0
452
453#define UVD_BASE__INST0_SEG0 0x00007800
454#define UVD_BASE__INST0_SEG1 0x00007E00
455#define UVD_BASE__INST0_SEG2 0
456#define UVD_BASE__INST0_SEG3 0
457#define UVD_BASE__INST0_SEG4 0
458
459#define UVD_BASE__INST1_SEG0 0
460#define UVD_BASE__INST1_SEG1 0
461#define UVD_BASE__INST1_SEG2 0
462#define UVD_BASE__INST1_SEG3 0
463#define UVD_BASE__INST1_SEG4 0
464
465#define UVD_BASE__INST2_SEG0 0
466#define UVD_BASE__INST2_SEG1 0
467#define UVD_BASE__INST2_SEG2 0
468#define UVD_BASE__INST2_SEG3 0
469#define UVD_BASE__INST2_SEG4 0
470
471#define UVD_BASE__INST3_SEG0 0
472#define UVD_BASE__INST3_SEG1 0
473#define UVD_BASE__INST3_SEG2 0
474#define UVD_BASE__INST3_SEG3 0
475#define UVD_BASE__INST3_SEG4 0
476
477#define UVD_BASE__INST4_SEG0 0
478#define UVD_BASE__INST4_SEG1 0
479#define UVD_BASE__INST4_SEG2 0
480#define UVD_BASE__INST4_SEG3 0
481#define UVD_BASE__INST4_SEG4 0
482
483#define VCN_BASE__INST0_SEG0 0x00007800
484#define VCN_BASE__INST0_SEG1 0x00007E00
485#define VCN_BASE__INST0_SEG2 0
486#define VCN_BASE__INST0_SEG3 0
487#define VCN_BASE__INST0_SEG4 0
488
489#define VCN_BASE__INST1_SEG0 0
490#define VCN_BASE__INST1_SEG1 0
491#define VCN_BASE__INST1_SEG2 0
492#define VCN_BASE__INST1_SEG3 0
493#define VCN_BASE__INST1_SEG4 0
494
495#define VCN_BASE__INST2_SEG0 0
496#define VCN_BASE__INST2_SEG1 0
497#define VCN_BASE__INST2_SEG2 0
498#define VCN_BASE__INST2_SEG3 0
499#define VCN_BASE__INST2_SEG4 0
500
501#define VCN_BASE__INST3_SEG0 0
502#define VCN_BASE__INST3_SEG1 0
503#define VCN_BASE__INST3_SEG2 0
504#define VCN_BASE__INST3_SEG3 0
505#define VCN_BASE__INST3_SEG4 0
506
507#define VCN_BASE__INST4_SEG0 0
508#define VCN_BASE__INST4_SEG1 0
509#define VCN_BASE__INST4_SEG2 0
510#define VCN_BASE__INST4_SEG3 0
511#define VCN_BASE__INST4_SEG4 0
512
513#define DBGU_BASE__INST0_SEG0 0x00000180
514#define DBGU_BASE__INST0_SEG1 0x000001A0
515#define DBGU_BASE__INST0_SEG2 0
516#define DBGU_BASE__INST0_SEG3 0
517#define DBGU_BASE__INST0_SEG4 0
518
519#define DBGU_BASE__INST1_SEG0 0
520#define DBGU_BASE__INST1_SEG1 0
521#define DBGU_BASE__INST1_SEG2 0
522#define DBGU_BASE__INST1_SEG3 0
523#define DBGU_BASE__INST1_SEG4 0
524
525#define DBGU_BASE__INST2_SEG0 0
526#define DBGU_BASE__INST2_SEG1 0
527#define DBGU_BASE__INST2_SEG2 0
528#define DBGU_BASE__INST2_SEG3 0
529#define DBGU_BASE__INST2_SEG4 0
530
531#define DBGU_BASE__INST3_SEG0 0
532#define DBGU_BASE__INST3_SEG1 0
533#define DBGU_BASE__INST3_SEG2 0
534#define DBGU_BASE__INST3_SEG3 0
535#define DBGU_BASE__INST3_SEG4 0
536
537#define DBGU_BASE__INST4_SEG0 0
538#define DBGU_BASE__INST4_SEG1 0
539#define DBGU_BASE__INST4_SEG2 0
540#define DBGU_BASE__INST4_SEG3 0
541#define DBGU_BASE__INST4_SEG4 0
542
543#define DBGU_NBIO_BASE__INST0_SEG0 0x000001C0
544#define DBGU_NBIO_BASE__INST0_SEG1 0
545#define DBGU_NBIO_BASE__INST0_SEG2 0
546#define DBGU_NBIO_BASE__INST0_SEG3 0
547#define DBGU_NBIO_BASE__INST0_SEG4 0
548
549#define DBGU_NBIO_BASE__INST1_SEG0 0
550#define DBGU_NBIO_BASE__INST1_SEG1 0
551#define DBGU_NBIO_BASE__INST1_SEG2 0
552#define DBGU_NBIO_BASE__INST1_SEG3 0
553#define DBGU_NBIO_BASE__INST1_SEG4 0
554
555#define DBGU_NBIO_BASE__INST2_SEG0 0
556#define DBGU_NBIO_BASE__INST2_SEG1 0
557#define DBGU_NBIO_BASE__INST2_SEG2 0
558#define DBGU_NBIO_BASE__INST2_SEG3 0
559#define DBGU_NBIO_BASE__INST2_SEG4 0
560
561#define DBGU_NBIO_BASE__INST3_SEG0 0
562#define DBGU_NBIO_BASE__INST3_SEG1 0
563#define DBGU_NBIO_BASE__INST3_SEG2 0
564#define DBGU_NBIO_BASE__INST3_SEG3 0
565#define DBGU_NBIO_BASE__INST3_SEG4 0
566
567#define DBGU_NBIO_BASE__INST4_SEG0 0
568#define DBGU_NBIO_BASE__INST4_SEG1 0
569#define DBGU_NBIO_BASE__INST4_SEG2 0
570#define DBGU_NBIO_BASE__INST4_SEG3 0
571#define DBGU_NBIO_BASE__INST4_SEG4 0
572
573#define DBGU_IO_BASE__INST0_SEG0 0x000001E0
574#define DBGU_IO_BASE__INST0_SEG1 0
575#define DBGU_IO_BASE__INST0_SEG2 0
576#define DBGU_IO_BASE__INST0_SEG3 0
577#define DBGU_IO_BASE__INST0_SEG4 0
578
579#define DBGU_IO_BASE__INST1_SEG0 0
580#define DBGU_IO_BASE__INST1_SEG1 0
581#define DBGU_IO_BASE__INST1_SEG2 0
582#define DBGU_IO_BASE__INST1_SEG3 0
583#define DBGU_IO_BASE__INST1_SEG4 0
584
585#define DBGU_IO_BASE__INST2_SEG0 0
586#define DBGU_IO_BASE__INST2_SEG1 0
587#define DBGU_IO_BASE__INST2_SEG2 0
588#define DBGU_IO_BASE__INST2_SEG3 0
589#define DBGU_IO_BASE__INST2_SEG4 0
590
591#define DBGU_IO_BASE__INST3_SEG0 0
592#define DBGU_IO_BASE__INST3_SEG1 0
593#define DBGU_IO_BASE__INST3_SEG2 0
594#define DBGU_IO_BASE__INST3_SEG3 0
595#define DBGU_IO_BASE__INST3_SEG4 0
596
597#define DBGU_IO_BASE__INST4_SEG0 0
598#define DBGU_IO_BASE__INST4_SEG1 0
599#define DBGU_IO_BASE__INST4_SEG2 0
600#define DBGU_IO_BASE__INST4_SEG3 0
601#define DBGU_IO_BASE__INST4_SEG4 0
602
603#define DFX_DAP_BASE__INST0_SEG0 0x000005A0
604#define DFX_DAP_BASE__INST0_SEG1 0
605#define DFX_DAP_BASE__INST0_SEG2 0
606#define DFX_DAP_BASE__INST0_SEG3 0
607#define DFX_DAP_BASE__INST0_SEG4 0
608
609#define DFX_DAP_BASE__INST1_SEG0 0
610#define DFX_DAP_BASE__INST1_SEG1 0
611#define DFX_DAP_BASE__INST1_SEG2 0
612#define DFX_DAP_BASE__INST1_SEG3 0
613#define DFX_DAP_BASE__INST1_SEG4 0
614
615#define DFX_DAP_BASE__INST2_SEG0 0
616#define DFX_DAP_BASE__INST2_SEG1 0
617#define DFX_DAP_BASE__INST2_SEG2 0
618#define DFX_DAP_BASE__INST2_SEG3 0
619#define DFX_DAP_BASE__INST2_SEG4 0
620
621#define DFX_DAP_BASE__INST3_SEG0 0
622#define DFX_DAP_BASE__INST3_SEG1 0
623#define DFX_DAP_BASE__INST3_SEG2 0
624#define DFX_DAP_BASE__INST3_SEG3 0
625#define DFX_DAP_BASE__INST3_SEG4 0
626
627#define DFX_DAP_BASE__INST4_SEG0 0
628#define DFX_DAP_BASE__INST4_SEG1 0
629#define DFX_DAP_BASE__INST4_SEG2 0
630#define DFX_DAP_BASE__INST4_SEG3 0
631#define DFX_DAP_BASE__INST4_SEG4 0
632
633#define DFX_BASE__INST0_SEG0 0x00000580
634#define DFX_BASE__INST0_SEG1 0
635#define DFX_BASE__INST0_SEG2 0
636#define DFX_BASE__INST0_SEG3 0
637#define DFX_BASE__INST0_SEG4 0
638
639#define DFX_BASE__INST1_SEG0 0
640#define DFX_BASE__INST1_SEG1 0
641#define DFX_BASE__INST1_SEG2 0
642#define DFX_BASE__INST1_SEG3 0
643#define DFX_BASE__INST1_SEG4 0
644
645#define DFX_BASE__INST2_SEG0 0
646#define DFX_BASE__INST2_SEG1 0
647#define DFX_BASE__INST2_SEG2 0
648#define DFX_BASE__INST2_SEG3 0
649#define DFX_BASE__INST2_SEG4 0
650
651#define DFX_BASE__INST3_SEG0 0
652#define DFX_BASE__INST3_SEG1 0
653#define DFX_BASE__INST3_SEG2 0
654#define DFX_BASE__INST3_SEG3 0
655#define DFX_BASE__INST3_SEG4 0
656
657#define DFX_BASE__INST4_SEG0 0
658#define DFX_BASE__INST4_SEG1 0
659#define DFX_BASE__INST4_SEG2 0
660#define DFX_BASE__INST4_SEG3 0
661#define DFX_BASE__INST4_SEG4 0
662
663#define ISP_BASE__INST0_SEG0 0x00018000
664#define ISP_BASE__INST0_SEG1 0
665#define ISP_BASE__INST0_SEG2 0
666#define ISP_BASE__INST0_SEG3 0
667#define ISP_BASE__INST0_SEG4 0
668
669#define ISP_BASE__INST1_SEG0 0
670#define ISP_BASE__INST1_SEG1 0
671#define ISP_BASE__INST1_SEG2 0
672#define ISP_BASE__INST1_SEG3 0
673#define ISP_BASE__INST1_SEG4 0
674
675#define ISP_BASE__INST2_SEG0 0
676#define ISP_BASE__INST2_SEG1 0
677#define ISP_BASE__INST2_SEG2 0
678#define ISP_BASE__INST2_SEG3 0
679#define ISP_BASE__INST2_SEG4 0
680
681#define ISP_BASE__INST3_SEG0 0
682#define ISP_BASE__INST3_SEG1 0
683#define ISP_BASE__INST3_SEG2 0
684#define ISP_BASE__INST3_SEG3 0
685#define ISP_BASE__INST3_SEG4 0
686
687#define ISP_BASE__INST4_SEG0 0
688#define ISP_BASE__INST4_SEG1 0
689#define ISP_BASE__INST4_SEG2 0
690#define ISP_BASE__INST4_SEG3 0
691#define ISP_BASE__INST4_SEG4 0
692
693#define SYSTEMHUB_BASE__INST0_SEG0 0x00000EA0
694#define SYSTEMHUB_BASE__INST0_SEG1 0
695#define SYSTEMHUB_BASE__INST0_SEG2 0
696#define SYSTEMHUB_BASE__INST0_SEG3 0
697#define SYSTEMHUB_BASE__INST0_SEG4 0
698
699#define SYSTEMHUB_BASE__INST1_SEG0 0
700#define SYSTEMHUB_BASE__INST1_SEG1 0
701#define SYSTEMHUB_BASE__INST1_SEG2 0
702#define SYSTEMHUB_BASE__INST1_SEG3 0
703#define SYSTEMHUB_BASE__INST1_SEG4 0
704
705#define SYSTEMHUB_BASE__INST2_SEG0 0
706#define SYSTEMHUB_BASE__INST2_SEG1 0
707#define SYSTEMHUB_BASE__INST2_SEG2 0
708#define SYSTEMHUB_BASE__INST2_SEG3 0
709#define SYSTEMHUB_BASE__INST2_SEG4 0
710
711#define SYSTEMHUB_BASE__INST3_SEG0 0
712#define SYSTEMHUB_BASE__INST3_SEG1 0
713#define SYSTEMHUB_BASE__INST3_SEG2 0
714#define SYSTEMHUB_BASE__INST3_SEG3 0
715#define SYSTEMHUB_BASE__INST3_SEG4 0
716
717#define SYSTEMHUB_BASE__INST4_SEG0 0
718#define SYSTEMHUB_BASE__INST4_SEG1 0
719#define SYSTEMHUB_BASE__INST4_SEG2 0
720#define SYSTEMHUB_BASE__INST4_SEG3 0
721#define SYSTEMHUB_BASE__INST4_SEG4 0
722
723#define L2IMU_BASE__INST0_SEG0 0x00007DC0
724#define L2IMU_BASE__INST0_SEG1 0
725#define L2IMU_BASE__INST0_SEG2 0
726#define L2IMU_BASE__INST0_SEG3 0
727#define L2IMU_BASE__INST0_SEG4 0
728
729#define L2IMU_BASE__INST1_SEG0 0
730#define L2IMU_BASE__INST1_SEG1 0
731#define L2IMU_BASE__INST1_SEG2 0
732#define L2IMU_BASE__INST1_SEG3 0
733#define L2IMU_BASE__INST1_SEG4 0
734
735#define L2IMU_BASE__INST2_SEG0 0
736#define L2IMU_BASE__INST2_SEG1 0
737#define L2IMU_BASE__INST2_SEG2 0
738#define L2IMU_BASE__INST2_SEG3 0
739#define L2IMU_BASE__INST2_SEG4 0
740
741#define L2IMU_BASE__INST3_SEG0 0
742#define L2IMU_BASE__INST3_SEG1 0
743#define L2IMU_BASE__INST3_SEG2 0
744#define L2IMU_BASE__INST3_SEG3 0
745#define L2IMU_BASE__INST3_SEG4 0
746
747#define L2IMU_BASE__INST4_SEG0 0
748#define L2IMU_BASE__INST4_SEG1 0
749#define L2IMU_BASE__INST4_SEG2 0
750#define L2IMU_BASE__INST4_SEG3 0
751#define L2IMU_BASE__INST4_SEG4 0
752
753#define IOHC_BASE__INST0_SEG0 0x00010000
754#define IOHC_BASE__INST0_SEG1 0
755#define IOHC_BASE__INST0_SEG2 0
756#define IOHC_BASE__INST0_SEG3 0
757#define IOHC_BASE__INST0_SEG4 0
758
759#define IOHC_BASE__INST1_SEG0 0
760#define IOHC_BASE__INST1_SEG1 0
761#define IOHC_BASE__INST1_SEG2 0
762#define IOHC_BASE__INST1_SEG3 0
763#define IOHC_BASE__INST1_SEG4 0
764
765#define IOHC_BASE__INST2_SEG0 0
766#define IOHC_BASE__INST2_SEG1 0
767#define IOHC_BASE__INST2_SEG2 0
768#define IOHC_BASE__INST2_SEG3 0
769#define IOHC_BASE__INST2_SEG4 0
770
771#define IOHC_BASE__INST3_SEG0 0
772#define IOHC_BASE__INST3_SEG1 0
773#define IOHC_BASE__INST3_SEG2 0
774#define IOHC_BASE__INST3_SEG3 0
775#define IOHC_BASE__INST3_SEG4 0
776
777#define IOHC_BASE__INST4_SEG0 0
778#define IOHC_BASE__INST4_SEG1 0
779#define IOHC_BASE__INST4_SEG2 0
780#define IOHC_BASE__INST4_SEG3 0
781#define IOHC_BASE__INST4_SEG4 0
782
783#define ATHUB_BASE__INST0_SEG0 0x00000C20
784#define ATHUB_BASE__INST0_SEG1 0
785#define ATHUB_BASE__INST0_SEG2 0
786#define ATHUB_BASE__INST0_SEG3 0
787#define ATHUB_BASE__INST0_SEG4 0
788
789#define ATHUB_BASE__INST1_SEG0 0
790#define ATHUB_BASE__INST1_SEG1 0
791#define ATHUB_BASE__INST1_SEG2 0
792#define ATHUB_BASE__INST1_SEG3 0
793#define ATHUB_BASE__INST1_SEG4 0
794
795#define ATHUB_BASE__INST2_SEG0 0
796#define ATHUB_BASE__INST2_SEG1 0
797#define ATHUB_BASE__INST2_SEG2 0
798#define ATHUB_BASE__INST2_SEG3 0
799#define ATHUB_BASE__INST2_SEG4 0
800
801#define ATHUB_BASE__INST3_SEG0 0
802#define ATHUB_BASE__INST3_SEG1 0
803#define ATHUB_BASE__INST3_SEG2 0
804#define ATHUB_BASE__INST3_SEG3 0
805#define ATHUB_BASE__INST3_SEG4 0
806
807#define ATHUB_BASE__INST4_SEG0 0
808#define ATHUB_BASE__INST4_SEG1 0
809#define ATHUB_BASE__INST4_SEG2 0
810#define ATHUB_BASE__INST4_SEG3 0
811#define ATHUB_BASE__INST4_SEG4 0
812
813#define VCE_BASE__INST0_SEG0 0x00007E00
814#define VCE_BASE__INST0_SEG1 0x00048800
815#define VCE_BASE__INST0_SEG2 0
816#define VCE_BASE__INST0_SEG3 0
817#define VCE_BASE__INST0_SEG4 0
818
819#define VCE_BASE__INST1_SEG0 0
820#define VCE_BASE__INST1_SEG1 0
821#define VCE_BASE__INST1_SEG2 0
822#define VCE_BASE__INST1_SEG3 0
823#define VCE_BASE__INST1_SEG4 0
824
825#define VCE_BASE__INST2_SEG0 0
826#define VCE_BASE__INST2_SEG1 0
827#define VCE_BASE__INST2_SEG2 0
828#define VCE_BASE__INST2_SEG3 0
829#define VCE_BASE__INST2_SEG4 0
830
831#define VCE_BASE__INST3_SEG0 0
832#define VCE_BASE__INST3_SEG1 0
833#define VCE_BASE__INST3_SEG2 0
834#define VCE_BASE__INST3_SEG3 0
835#define VCE_BASE__INST3_SEG4 0
836
837#define VCE_BASE__INST4_SEG0 0
838#define VCE_BASE__INST4_SEG1 0
839#define VCE_BASE__INST4_SEG2 0
840#define VCE_BASE__INST4_SEG3 0
841#define VCE_BASE__INST4_SEG4 0
842
843#define GC_BASE__INST0_SEG0 0x00002000
844#define GC_BASE__INST0_SEG1 0x0000A000
845#define GC_BASE__INST0_SEG2 0
846#define GC_BASE__INST0_SEG3 0
847#define GC_BASE__INST0_SEG4 0
848
849#define GC_BASE__INST1_SEG0 0
850#define GC_BASE__INST1_SEG1 0
851#define GC_BASE__INST1_SEG2 0
852#define GC_BASE__INST1_SEG3 0
853#define GC_BASE__INST1_SEG4 0
854
855#define GC_BASE__INST2_SEG0 0
856#define GC_BASE__INST2_SEG1 0
857#define GC_BASE__INST2_SEG2 0
858#define GC_BASE__INST2_SEG3 0
859#define GC_BASE__INST2_SEG4 0
860
861#define GC_BASE__INST3_SEG0 0
862#define GC_BASE__INST3_SEG1 0
863#define GC_BASE__INST3_SEG2 0
864#define GC_BASE__INST3_SEG3 0
865#define GC_BASE__INST3_SEG4 0
866
867#define GC_BASE__INST4_SEG0 0
868#define GC_BASE__INST4_SEG1 0
869#define GC_BASE__INST4_SEG2 0
870#define GC_BASE__INST4_SEG3 0
871#define GC_BASE__INST4_SEG4 0
872
873#define MMHUB_BASE__INST0_SEG0 0x0001A000
874#define MMHUB_BASE__INST0_SEG1 0
875#define MMHUB_BASE__INST0_SEG2 0
876#define MMHUB_BASE__INST0_SEG3 0
877#define MMHUB_BASE__INST0_SEG4 0
878
879#define MMHUB_BASE__INST1_SEG0 0
880#define MMHUB_BASE__INST1_SEG1 0
881#define MMHUB_BASE__INST1_SEG2 0
882#define MMHUB_BASE__INST1_SEG3 0
883#define MMHUB_BASE__INST1_SEG4 0
884
885#define MMHUB_BASE__INST2_SEG0 0
886#define MMHUB_BASE__INST2_SEG1 0
887#define MMHUB_BASE__INST2_SEG2 0
888#define MMHUB_BASE__INST2_SEG3 0
889#define MMHUB_BASE__INST2_SEG4 0
890
891#define MMHUB_BASE__INST3_SEG0 0
892#define MMHUB_BASE__INST3_SEG1 0
893#define MMHUB_BASE__INST3_SEG2 0
894#define MMHUB_BASE__INST3_SEG3 0
895#define MMHUB_BASE__INST3_SEG4 0
896
897#define MMHUB_BASE__INST4_SEG0 0
898#define MMHUB_BASE__INST4_SEG1 0
899#define MMHUB_BASE__INST4_SEG2 0
900#define MMHUB_BASE__INST4_SEG3 0
901#define MMHUB_BASE__INST4_SEG4 0
902
903#define RSMU_BASE__INST0_SEG0 0x00012000
904#define RSMU_BASE__INST0_SEG1 0
905#define RSMU_BASE__INST0_SEG2 0
906#define RSMU_BASE__INST0_SEG3 0
907#define RSMU_BASE__INST0_SEG4 0
908
909#define RSMU_BASE__INST1_SEG0 0
910#define RSMU_BASE__INST1_SEG1 0
911#define RSMU_BASE__INST1_SEG2 0
912#define RSMU_BASE__INST1_SEG3 0
913#define RSMU_BASE__INST1_SEG4 0
914
915#define RSMU_BASE__INST2_SEG0 0
916#define RSMU_BASE__INST2_SEG1 0
917#define RSMU_BASE__INST2_SEG2 0
918#define RSMU_BASE__INST2_SEG3 0
919#define RSMU_BASE__INST2_SEG4 0
920
921#define RSMU_BASE__INST3_SEG0 0
922#define RSMU_BASE__INST3_SEG1 0
923#define RSMU_BASE__INST3_SEG2 0
924#define RSMU_BASE__INST3_SEG3 0
925#define RSMU_BASE__INST3_SEG4 0
926
927#define RSMU_BASE__INST4_SEG0 0
928#define RSMU_BASE__INST4_SEG1 0
929#define RSMU_BASE__INST4_SEG2 0
930#define RSMU_BASE__INST4_SEG3 0
931#define RSMU_BASE__INST4_SEG4 0
932
933#define HDP_BASE__INST0_SEG0 0x00000F20
934#define HDP_BASE__INST0_SEG1 0
935#define HDP_BASE__INST0_SEG2 0
936#define HDP_BASE__INST0_SEG3 0
937#define HDP_BASE__INST0_SEG4 0
938
939#define HDP_BASE__INST1_SEG0 0
940#define HDP_BASE__INST1_SEG1 0
941#define HDP_BASE__INST1_SEG2 0
942#define HDP_BASE__INST1_SEG3 0
943#define HDP_BASE__INST1_SEG4 0
944
945#define HDP_BASE__INST2_SEG0 0
946#define HDP_BASE__INST2_SEG1 0
947#define HDP_BASE__INST2_SEG2 0
948#define HDP_BASE__INST2_SEG3 0
949#define HDP_BASE__INST2_SEG4 0
950
951#define HDP_BASE__INST3_SEG0 0
952#define HDP_BASE__INST3_SEG1 0
953#define HDP_BASE__INST3_SEG2 0
954#define HDP_BASE__INST3_SEG3 0
955#define HDP_BASE__INST3_SEG4 0
956
957#define HDP_BASE__INST4_SEG0 0
958#define HDP_BASE__INST4_SEG1 0
959#define HDP_BASE__INST4_SEG2 0
960#define HDP_BASE__INST4_SEG3 0
961#define HDP_BASE__INST4_SEG4 0
962
963#define OSSSYS_BASE__INST0_SEG0 0x000010A0
964#define OSSSYS_BASE__INST0_SEG1 0
965#define OSSSYS_BASE__INST0_SEG2 0
966#define OSSSYS_BASE__INST0_SEG3 0
967#define OSSSYS_BASE__INST0_SEG4 0
968
969#define OSSSYS_BASE__INST1_SEG0 0
970#define OSSSYS_BASE__INST1_SEG1 0
971#define OSSSYS_BASE__INST1_SEG2 0
972#define OSSSYS_BASE__INST1_SEG3 0
973#define OSSSYS_BASE__INST1_SEG4 0
974
975#define OSSSYS_BASE__INST2_SEG0 0
976#define OSSSYS_BASE__INST2_SEG1 0
977#define OSSSYS_BASE__INST2_SEG2 0
978#define OSSSYS_BASE__INST2_SEG3 0
979#define OSSSYS_BASE__INST2_SEG4 0
980
981#define OSSSYS_BASE__INST3_SEG0 0
982#define OSSSYS_BASE__INST3_SEG1 0
983#define OSSSYS_BASE__INST3_SEG2 0
984#define OSSSYS_BASE__INST3_SEG3 0
985#define OSSSYS_BASE__INST3_SEG4 0
986
987#define OSSSYS_BASE__INST4_SEG0 0
988#define OSSSYS_BASE__INST4_SEG1 0
989#define OSSSYS_BASE__INST4_SEG2 0
990#define OSSSYS_BASE__INST4_SEG3 0
991#define OSSSYS_BASE__INST4_SEG4 0
992
993#define SDMA0_BASE__INST0_SEG0 0x00001260
994#define SDMA0_BASE__INST0_SEG1 0
995#define SDMA0_BASE__INST0_SEG2 0
996#define SDMA0_BASE__INST0_SEG3 0
997#define SDMA0_BASE__INST0_SEG4 0
998
999#define SDMA0_BASE__INST1_SEG0 0
1000#define SDMA0_BASE__INST1_SEG1 0
1001#define SDMA0_BASE__INST1_SEG2 0
1002#define SDMA0_BASE__INST1_SEG3 0
1003#define SDMA0_BASE__INST1_SEG4 0
1004
1005#define SDMA0_BASE__INST2_SEG0 0
1006#define SDMA0_BASE__INST2_SEG1 0
1007#define SDMA0_BASE__INST2_SEG2 0
1008#define SDMA0_BASE__INST2_SEG3 0
1009#define SDMA0_BASE__INST2_SEG4 0
1010
1011#define SDMA0_BASE__INST3_SEG0 0
1012#define SDMA0_BASE__INST3_SEG1 0
1013#define SDMA0_BASE__INST3_SEG2 0
1014#define SDMA0_BASE__INST3_SEG3 0
1015#define SDMA0_BASE__INST3_SEG4 0
1016
1017#define SDMA0_BASE__INST4_SEG0 0
1018#define SDMA0_BASE__INST4_SEG1 0
1019#define SDMA0_BASE__INST4_SEG2 0
1020#define SDMA0_BASE__INST4_SEG3 0
1021#define SDMA0_BASE__INST4_SEG4 0
1022
1023#define SDMA1_BASE__INST0_SEG0 0x00001460
1024#define SDMA1_BASE__INST0_SEG1 0
1025#define SDMA1_BASE__INST0_SEG2 0
1026#define SDMA1_BASE__INST0_SEG3 0
1027#define SDMA1_BASE__INST0_SEG4 0
1028
1029#define SDMA1_BASE__INST1_SEG0 0
1030#define SDMA1_BASE__INST1_SEG1 0
1031#define SDMA1_BASE__INST1_SEG2 0
1032#define SDMA1_BASE__INST1_SEG3 0
1033#define SDMA1_BASE__INST1_SEG4 0
1034
1035#define SDMA1_BASE__INST2_SEG0 0
1036#define SDMA1_BASE__INST2_SEG1 0
1037#define SDMA1_BASE__INST2_SEG2 0
1038#define SDMA1_BASE__INST2_SEG3 0
1039#define SDMA1_BASE__INST2_SEG4 0
1040
1041#define SDMA1_BASE__INST3_SEG0 0
1042#define SDMA1_BASE__INST3_SEG1 0
1043#define SDMA1_BASE__INST3_SEG2 0
1044#define SDMA1_BASE__INST3_SEG3 0
1045#define SDMA1_BASE__INST3_SEG4 0
1046
1047#define SDMA1_BASE__INST4_SEG0 0
1048#define SDMA1_BASE__INST4_SEG1 0
1049#define SDMA1_BASE__INST4_SEG2 0
1050#define SDMA1_BASE__INST4_SEG3 0
1051#define SDMA1_BASE__INST4_SEG4 0
1052
1053#define XDMA_BASE__INST0_SEG0 0x00003400
1054#define XDMA_BASE__INST0_SEG1 0
1055#define XDMA_BASE__INST0_SEG2 0
1056#define XDMA_BASE__INST0_SEG3 0
1057#define XDMA_BASE__INST0_SEG4 0
1058
1059#define XDMA_BASE__INST1_SEG0 0
1060#define XDMA_BASE__INST1_SEG1 0
1061#define XDMA_BASE__INST1_SEG2 0
1062#define XDMA_BASE__INST1_SEG3 0
1063#define XDMA_BASE__INST1_SEG4 0
1064
1065#define XDMA_BASE__INST2_SEG0 0
1066#define XDMA_BASE__INST2_SEG1 0
1067#define XDMA_BASE__INST2_SEG2 0
1068#define XDMA_BASE__INST2_SEG3 0
1069#define XDMA_BASE__INST2_SEG4 0
1070
1071#define XDMA_BASE__INST3_SEG0 0
1072#define XDMA_BASE__INST3_SEG1 0
1073#define XDMA_BASE__INST3_SEG2 0
1074#define XDMA_BASE__INST3_SEG3 0
1075#define XDMA_BASE__INST3_SEG4 0
1076
1077#define XDMA_BASE__INST4_SEG0 0
1078#define XDMA_BASE__INST4_SEG1 0
1079#define XDMA_BASE__INST4_SEG2 0
1080#define XDMA_BASE__INST4_SEG3 0
1081#define XDMA_BASE__INST4_SEG4 0
1082
1083#define UMC_BASE__INST0_SEG0 0x00014000
1084#define UMC_BASE__INST0_SEG1 0
1085#define UMC_BASE__INST0_SEG2 0
1086#define UMC_BASE__INST0_SEG3 0
1087#define UMC_BASE__INST0_SEG4 0
1088
1089#define UMC_BASE__INST1_SEG0 0
1090#define UMC_BASE__INST1_SEG1 0
1091#define UMC_BASE__INST1_SEG2 0
1092#define UMC_BASE__INST1_SEG3 0
1093#define UMC_BASE__INST1_SEG4 0
1094
1095#define UMC_BASE__INST2_SEG0 0
1096#define UMC_BASE__INST2_SEG1 0
1097#define UMC_BASE__INST2_SEG2 0
1098#define UMC_BASE__INST2_SEG3 0
1099#define UMC_BASE__INST2_SEG4 0
1100
1101#define UMC_BASE__INST3_SEG0 0
1102#define UMC_BASE__INST3_SEG1 0
1103#define UMC_BASE__INST3_SEG2 0
1104#define UMC_BASE__INST3_SEG3 0
1105#define UMC_BASE__INST3_SEG4 0
1106
1107#define UMC_BASE__INST4_SEG0 0
1108#define UMC_BASE__INST4_SEG1 0
1109#define UMC_BASE__INST4_SEG2 0
1110#define UMC_BASE__INST4_SEG3 0
1111#define UMC_BASE__INST4_SEG4 0
1112
1113#define THM_BASE__INST0_SEG0 0x00016600
1114#define THM_BASE__INST0_SEG1 0
1115#define THM_BASE__INST0_SEG2 0
1116#define THM_BASE__INST0_SEG3 0
1117#define THM_BASE__INST0_SEG4 0
1118
1119#define THM_BASE__INST1_SEG0 0
1120#define THM_BASE__INST1_SEG1 0
1121#define THM_BASE__INST1_SEG2 0
1122#define THM_BASE__INST1_SEG3 0
1123#define THM_BASE__INST1_SEG4 0
1124
1125#define THM_BASE__INST2_SEG0 0
1126#define THM_BASE__INST2_SEG1 0
1127#define THM_BASE__INST2_SEG2 0
1128#define THM_BASE__INST2_SEG3 0
1129#define THM_BASE__INST2_SEG4 0
1130
1131#define THM_BASE__INST3_SEG0 0
1132#define THM_BASE__INST3_SEG1 0
1133#define THM_BASE__INST3_SEG2 0
1134#define THM_BASE__INST3_SEG3 0
1135#define THM_BASE__INST3_SEG4 0
1136
1137#define THM_BASE__INST4_SEG0 0
1138#define THM_BASE__INST4_SEG1 0
1139#define THM_BASE__INST4_SEG2 0
1140#define THM_BASE__INST4_SEG3 0
1141#define THM_BASE__INST4_SEG4 0
1142
1143#define SMUIO_BASE__INST0_SEG0 0x00016800
1144#define SMUIO_BASE__INST0_SEG1 0
1145#define SMUIO_BASE__INST0_SEG2 0
1146#define SMUIO_BASE__INST0_SEG3 0
1147#define SMUIO_BASE__INST0_SEG4 0
1148
1149#define SMUIO_BASE__INST1_SEG0 0
1150#define SMUIO_BASE__INST1_SEG1 0
1151#define SMUIO_BASE__INST1_SEG2 0
1152#define SMUIO_BASE__INST1_SEG3 0
1153#define SMUIO_BASE__INST1_SEG4 0
1154
1155#define SMUIO_BASE__INST2_SEG0 0
1156#define SMUIO_BASE__INST2_SEG1 0
1157#define SMUIO_BASE__INST2_SEG2 0
1158#define SMUIO_BASE__INST2_SEG3 0
1159#define SMUIO_BASE__INST2_SEG4 0
1160
1161#define SMUIO_BASE__INST3_SEG0 0
1162#define SMUIO_BASE__INST3_SEG1 0
1163#define SMUIO_BASE__INST3_SEG2 0
1164#define SMUIO_BASE__INST3_SEG3 0
1165#define SMUIO_BASE__INST3_SEG4 0
1166
1167#define SMUIO_BASE__INST4_SEG0 0
1168#define SMUIO_BASE__INST4_SEG1 0
1169#define SMUIO_BASE__INST4_SEG2 0
1170#define SMUIO_BASE__INST4_SEG3 0
1171#define SMUIO_BASE__INST4_SEG4 0
1172
1173#define PWR_BASE__INST0_SEG0 0x00016A00
1174#define PWR_BASE__INST0_SEG1 0
1175#define PWR_BASE__INST0_SEG2 0
1176#define PWR_BASE__INST0_SEG3 0
1177#define PWR_BASE__INST0_SEG4 0
1178
1179#define PWR_BASE__INST1_SEG0 0
1180#define PWR_BASE__INST1_SEG1 0
1181#define PWR_BASE__INST1_SEG2 0
1182#define PWR_BASE__INST1_SEG3 0
1183#define PWR_BASE__INST1_SEG4 0
1184
1185#define PWR_BASE__INST2_SEG0 0
1186#define PWR_BASE__INST2_SEG1 0
1187#define PWR_BASE__INST2_SEG2 0
1188#define PWR_BASE__INST2_SEG3 0
1189#define PWR_BASE__INST2_SEG4 0
1190
1191#define PWR_BASE__INST3_SEG0 0
1192#define PWR_BASE__INST3_SEG1 0
1193#define PWR_BASE__INST3_SEG2 0
1194#define PWR_BASE__INST3_SEG3 0
1195#define PWR_BASE__INST3_SEG4 0
1196
1197#define PWR_BASE__INST4_SEG0 0
1198#define PWR_BASE__INST4_SEG1 0
1199#define PWR_BASE__INST4_SEG2 0
1200#define PWR_BASE__INST4_SEG3 0
1201#define PWR_BASE__INST4_SEG4 0
1202
1203#define CLK_BASE__INST0_SEG0 0x00016C00
1204#define CLK_BASE__INST0_SEG1 0
1205#define CLK_BASE__INST0_SEG2 0
1206#define CLK_BASE__INST0_SEG3 0
1207#define CLK_BASE__INST0_SEG4 0
1208
1209#define CLK_BASE__INST1_SEG0 0x00016E00
1210#define CLK_BASE__INST1_SEG1 0
1211#define CLK_BASE__INST1_SEG2 0
1212#define CLK_BASE__INST1_SEG3 0
1213#define CLK_BASE__INST1_SEG4 0
1214
1215#define CLK_BASE__INST2_SEG0 0x00017000
1216#define CLK_BASE__INST2_SEG1 0
1217#define CLK_BASE__INST2_SEG2 0
1218#define CLK_BASE__INST2_SEG3 0
1219#define CLK_BASE__INST2_SEG4 0
1220
1221#define CLK_BASE__INST3_SEG0 0x00017200
1222#define CLK_BASE__INST3_SEG1 0
1223#define CLK_BASE__INST3_SEG2 0
1224#define CLK_BASE__INST3_SEG3 0
1225#define CLK_BASE__INST3_SEG4 0
1226
1227#define CLK_BASE__INST4_SEG0 0x00017E00
1228#define CLK_BASE__INST4_SEG1 0
1229#define CLK_BASE__INST4_SEG2 0
1230#define CLK_BASE__INST4_SEG3 0
1231#define CLK_BASE__INST4_SEG4 0
1232
1233#define FUSE_BASE__INST0_SEG0 0x00017400
1234#define FUSE_BASE__INST0_SEG1 0
1235#define FUSE_BASE__INST0_SEG2 0
1236#define FUSE_BASE__INST0_SEG3 0
1237#define FUSE_BASE__INST0_SEG4 0
1238
1239#define FUSE_BASE__INST1_SEG0 0
1240#define FUSE_BASE__INST1_SEG1 0
1241#define FUSE_BASE__INST1_SEG2 0
1242#define FUSE_BASE__INST1_SEG3 0
1243#define FUSE_BASE__INST1_SEG4 0
1244
1245#define FUSE_BASE__INST2_SEG0 0
1246#define FUSE_BASE__INST2_SEG1 0
1247#define FUSE_BASE__INST2_SEG2 0
1248#define FUSE_BASE__INST2_SEG3 0
1249#define FUSE_BASE__INST2_SEG4 0
1250
1251#define FUSE_BASE__INST3_SEG0 0
1252#define FUSE_BASE__INST3_SEG1 0
1253#define FUSE_BASE__INST3_SEG2 0
1254#define FUSE_BASE__INST3_SEG3 0
1255#define FUSE_BASE__INST3_SEG4 0
1256
1257#define FUSE_BASE__INST4_SEG0 0
1258#define FUSE_BASE__INST4_SEG1 0
1259#define FUSE_BASE__INST4_SEG2 0
1260#define FUSE_BASE__INST4_SEG3 0
1261#define FUSE_BASE__INST4_SEG4 0
1262#endif
1263
1264

source code of linux/drivers/gpu/drm/amd/include/vega10_ip_offset.h