| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | |
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| 3 | #ifndef __AST_REG_H__ |
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| 4 | #define __AST_REG_H__ |
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| 5 | |
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| 6 | #include <linux/bits.h> |
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| 7 | |
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| 8 | /* |
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| 9 | * Modesetting |
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| 10 | */ |
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| 11 | |
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| 12 | #define AST_IO_MM_OFFSET (0x380) |
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| 13 | #define AST_IO_MM_LENGTH (128) |
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| 14 | |
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| 15 | #define AST_IO_VGAARI_W (0x40) |
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| 16 | |
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| 17 | #define AST_IO_VGAMR_W (0x42) |
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| 18 | #define AST_IO_VGAMR_R (0x4c) |
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| 19 | #define AST_IO_VGAMR_IOSEL BIT(0) |
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| 20 | |
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| 21 | #define AST_IO_VGAER (0x43) |
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| 22 | #define AST_IO_VGAER_VGA_ENABLE BIT(0) |
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| 23 | |
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| 24 | #define AST_IO_VGASRI (0x44) |
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| 25 | #define AST_IO_VGASR1_SD BIT(5) |
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| 26 | #define AST_IO_VGADRR (0x47) |
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| 27 | #define AST_IO_VGADWR (0x48) |
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| 28 | #define AST_IO_VGAPDR (0x49) |
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| 29 | #define AST_IO_VGAGRI (0x4E) |
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| 30 | |
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| 31 | #define AST_IO_VGACRI (0x54) |
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| 32 | #define AST_IO_VGACR80_PASSWORD (0xa8) |
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| 33 | #define AST_IO_VGACR99_VGAMEM_RSRV_MASK GENMASK(1, 0) |
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| 34 | #define AST_IO_VGACRA1_VGAIO_DISABLED BIT(1) |
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| 35 | #define AST_IO_VGACRA1_MMIO_ENABLED BIT(2) |
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| 36 | #define AST_IO_VGACRA3_DVO_ENABLED BIT(7) |
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| 37 | #define AST_IO_VGACRAA_VGAMEM_SIZE_MASK GENMASK(1, 0) |
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| 38 | #define AST_IO_VGACRB6_HSYNC_OFF BIT(0) |
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| 39 | #define AST_IO_VGACRB6_VSYNC_OFF BIT(1) |
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| 40 | #define AST_IO_VGACRCB_HWC_16BPP BIT(0) /* set: ARGB4444, cleared: 2bpp palette */ |
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| 41 | #define AST_IO_VGACRCB_HWC_ENABLED BIT(1) |
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| 42 | |
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| 43 | /* mirrors SCU100[7:0] */ |
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| 44 | #define AST_IO_VGACRD0_VRAM_INIT_STATUS_MASK GENMASK(7, 6) |
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| 45 | #define AST_IO_VGACRD0_VRAM_INIT_BY_BMC BIT(7) |
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| 46 | #define AST_IO_VGACRD0_VRAM_INIT_READY BIT(6) |
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| 47 | #define AST_IO_VGACRD0_IKVM_WIDESCREEN BIT(0) |
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| 48 | |
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| 49 | #define AST_IO_VGACRD1_MCU_FW_EXECUTING BIT(5) |
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| 50 | /* Display Transmitter Type */ |
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| 51 | #define AST_IO_VGACRD1_TX_TYPE_MASK GENMASK(3, 1) |
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| 52 | #define AST_IO_VGACRD1_NO_TX 0x00 |
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| 53 | #define AST_IO_VGACRD1_TX_ITE66121_VBIOS 0x02 |
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| 54 | #define AST_IO_VGACRD1_TX_SIL164_VBIOS 0x04 |
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| 55 | #define AST_IO_VGACRD1_TX_CH7003_VBIOS 0x06 |
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| 56 | #define AST_IO_VGACRD1_TX_DP501_VBIOS 0x08 |
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| 57 | #define AST_IO_VGACRD1_TX_ANX9807_VBIOS 0x0a |
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| 58 | #define AST_IO_VGACRD1_TX_FW_EMBEDDED_FW 0x0c /* special case of DP501 */ |
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| 59 | #define AST_IO_VGACRD1_TX_ASTDP 0x0e |
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| 60 | #define AST_IO_VGACRD1_SUPPORTS_WUXGA BIT(0) |
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| 61 | |
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| 62 | /* |
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| 63 | * AST DisplayPort |
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| 64 | */ |
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| 65 | #define AST_IO_VGACRD7_EDID_VALID_FLAG BIT(0) |
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| 66 | #define AST_IO_VGACRDC_LINK_SUCCESS BIT(0) |
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| 67 | #define AST_IO_VGACRDF_HPD BIT(0) |
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| 68 | #define AST_IO_VGACRDF_DP_VIDEO_ENABLE BIT(4) /* mirrors AST_IO_VGACRE3_DP_VIDEO_ENABLE */ |
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| 69 | #define AST_IO_VGACRE0_24BPP BIT(5) /* 18 bpp, if unset */ |
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| 70 | #define AST_IO_VGACRE3_DP_VIDEO_ENABLE BIT(0) |
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| 71 | #define AST_IO_VGACRE3_DP_PHY_SLEEP BIT(4) |
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| 72 | #define AST_IO_VGACRE5_EDID_READ_DONE BIT(0) |
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| 73 | |
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| 74 | #define AST_IO_VGAIR1_R (0x5A) |
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| 75 | #define AST_IO_VGAIR1_VREFRESH BIT(3) |
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| 76 | |
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| 77 | #endif |
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| 78 | |
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