1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
2 | /* |
3 | * Copyright(c) 2016, Analogix Semiconductor. All rights reserved. |
4 | */ |
5 | |
6 | #ifndef __ANX78xx_H |
7 | #define __ANX78xx_H |
8 | |
9 | #include "analogix-i2c-dptx.h" |
10 | #include "analogix-i2c-txcommon.h" |
11 | |
12 | /***************************************************************/ |
13 | /* Register definitions for RX_PO */ |
14 | /***************************************************************/ |
15 | |
16 | /* |
17 | * System Control and Status |
18 | */ |
19 | |
20 | /* Software Reset Register 1 */ |
21 | #define SP_SOFTWARE_RESET1_REG 0x11 |
22 | #define SP_VIDEO_RST BIT(4) |
23 | #define SP_HDCP_MAN_RST BIT(2) |
24 | #define SP_TMDS_RST BIT(1) |
25 | #define SP_SW_MAN_RST BIT(0) |
26 | |
27 | /* System Status Register */ |
28 | #define SP_SYSTEM_STATUS_REG 0x14 |
29 | #define SP_TMDS_CLOCK_DET BIT(1) |
30 | #define SP_TMDS_DE_DET BIT(0) |
31 | |
32 | /* HDMI Status Register */ |
33 | #define SP_HDMI_STATUS_REG 0x15 |
34 | #define SP_HDMI_AUD_LAYOUT BIT(3) |
35 | #define SP_HDMI_DET BIT(0) |
36 | # define SP_DVI_MODE 0 |
37 | # define SP_HDMI_MODE 1 |
38 | |
39 | /* HDMI Mute Control Register */ |
40 | #define SP_HDMI_MUTE_CTRL_REG 0x16 |
41 | #define SP_AUD_MUTE BIT(1) |
42 | #define SP_VID_MUTE BIT(0) |
43 | |
44 | /* System Power Down Register 1 */ |
45 | #define SP_SYSTEM_POWER_DOWN1_REG 0x18 |
46 | #define SP_PWDN_CTRL BIT(0) |
47 | |
48 | /* |
49 | * Audio and Video Auto Control |
50 | */ |
51 | |
52 | /* Auto Audio and Video Control register */ |
53 | #define SP_AUDVID_CTRL_REG 0x20 |
54 | #define SP_AVC_OE BIT(7) |
55 | #define SP_AAC_OE BIT(6) |
56 | #define SP_AVC_EN BIT(1) |
57 | #define SP_AAC_EN BIT(0) |
58 | |
59 | /* Audio Exception Enable Registers */ |
60 | #define SP_AUD_EXCEPTION_ENABLE_BASE (0x24 - 1) |
61 | /* Bits for Audio Exception Enable Register 3 */ |
62 | #define SP_AEC_EN21 BIT(5) |
63 | |
64 | /* |
65 | * Interrupt |
66 | */ |
67 | |
68 | /* Interrupt Status Register 1 */ |
69 | #define SP_INT_STATUS1_REG 0x31 |
70 | /* Bits for Interrupt Status Register 1 */ |
71 | #define SP_HDMI_DVI BIT(7) |
72 | #define SP_CKDT_CHG BIT(6) |
73 | #define SP_SCDT_CHG BIT(5) |
74 | #define SP_PCLK_CHG BIT(4) |
75 | #define SP_PLL_UNLOCK BIT(3) |
76 | #define SP_CABLE_PLUG_CHG BIT(2) |
77 | #define SP_SET_MUTE BIT(1) |
78 | #define SP_SW_INTR BIT(0) |
79 | /* Bits for Interrupt Status Register 2 */ |
80 | #define SP_HDCP_ERR BIT(5) |
81 | #define SP_AUDIO_SAMPLE_CHG BIT(0) /* undocumented */ |
82 | /* Bits for Interrupt Status Register 3 */ |
83 | #define SP_AUD_MODE_CHG BIT(0) |
84 | /* Bits for Interrupt Status Register 5 */ |
85 | #define SP_AUDIO_RCV BIT(0) |
86 | /* Bits for Interrupt Status Register 6 */ |
87 | #define SP_INT_STATUS6_REG 0x36 |
88 | #define SP_CTS_RCV BIT(7) |
89 | #define SP_NEW_AUD_PKT BIT(4) |
90 | #define SP_NEW_AVI_PKT BIT(1) |
91 | #define SP_NEW_CP_PKT BIT(0) |
92 | /* Bits for Interrupt Status Register 7 */ |
93 | #define SP_NO_VSI BIT(7) |
94 | #define SP_NEW_VS BIT(4) |
95 | |
96 | /* Interrupt Mask 1 Status Registers */ |
97 | #define SP_INT_MASK1_REG 0x41 |
98 | |
99 | /* HDMI US TIMER Control Register */ |
100 | #define SP_HDMI_US_TIMER_CTRL_REG 0x49 |
101 | #define SP_MS_TIMER_MARGIN_10_8_MASK 0x07 |
102 | |
103 | /* |
104 | * TMDS Control |
105 | */ |
106 | |
107 | /* TMDS Control Registers */ |
108 | #define SP_TMDS_CTRL_BASE (0x50 - 1) |
109 | /* Bits for TMDS Control Register 7 */ |
110 | #define SP_PD_RT BIT(0) |
111 | |
112 | /* |
113 | * Video Control |
114 | */ |
115 | |
116 | /* Video Status Register */ |
117 | #define SP_VIDEO_STATUS_REG 0x70 |
118 | #define SP_COLOR_DEPTH_MASK 0xf0 |
119 | #define SP_COLOR_DEPTH_SHIFT 4 |
120 | # define SP_COLOR_DEPTH_MODE_LEGACY 0x00 |
121 | # define SP_COLOR_DEPTH_MODE_24BIT 0x04 |
122 | # define SP_COLOR_DEPTH_MODE_30BIT 0x05 |
123 | # define SP_COLOR_DEPTH_MODE_36BIT 0x06 |
124 | # define SP_COLOR_DEPTH_MODE_48BIT 0x07 |
125 | |
126 | /* Video Data Range Control Register */ |
127 | #define SP_VID_DATA_RANGE_CTRL_REG 0x83 |
128 | #define SP_R2Y_INPUT_LIMIT BIT(1) |
129 | |
130 | /* Pixel Clock High Resolution Counter Registers */ |
131 | #define SP_PCLK_HIGHRES_CNT_BASE (0x8c - 1) |
132 | |
133 | /* |
134 | * Audio Control |
135 | */ |
136 | |
137 | /* Number of Audio Channels Status Registers */ |
138 | #define SP_AUD_CH_STATUS_REG_NUM 6 |
139 | |
140 | /* Audio IN S/PDIF Channel Status Registers */ |
141 | #define SP_AUD_SPDIF_CH_STATUS_BASE 0xc7 |
142 | |
143 | /* Audio IN S/PDIF Channel Status Register 4 */ |
144 | #define SP_FS_FREQ_MASK 0x0f |
145 | # define SP_FS_FREQ_44100HZ 0x00 |
146 | # define SP_FS_FREQ_48000HZ 0x02 |
147 | # define SP_FS_FREQ_32000HZ 0x03 |
148 | # define SP_FS_FREQ_88200HZ 0x08 |
149 | # define SP_FS_FREQ_96000HZ 0x0a |
150 | # define SP_FS_FREQ_176400HZ 0x0c |
151 | # define SP_FS_FREQ_192000HZ 0x0e |
152 | |
153 | /* |
154 | * Micellaneous Control Block |
155 | */ |
156 | |
157 | /* CHIP Control Register */ |
158 | #define SP_CHIP_CTRL_REG 0xe3 |
159 | #define SP_MAN_HDMI5V_DET BIT(3) |
160 | #define SP_PLLLOCK_CKDT_EN BIT(2) |
161 | #define SP_ANALOG_CKDT_EN BIT(1) |
162 | #define SP_DIGITAL_CKDT_EN BIT(0) |
163 | |
164 | /* Packet Receiving Status Register */ |
165 | #define SP_PACKET_RECEIVING_STATUS_REG 0xf3 |
166 | #define SP_AVI_RCVD BIT(5) |
167 | #define SP_VSI_RCVD BIT(1) |
168 | |
169 | /***************************************************************/ |
170 | /* Register definitions for RX_P1 */ |
171 | /***************************************************************/ |
172 | |
173 | /* HDCP BCAPS Shadow Register */ |
174 | #define SP_HDCP_BCAPS_SHADOW_REG 0x2a |
175 | #define SP_BCAPS_REPEATER BIT(5) |
176 | |
177 | /* HDCP Status Register */ |
178 | #define SP_RX_HDCP_STATUS_REG 0x3f |
179 | #define SP_AUTH_EN BIT(4) |
180 | |
181 | /* |
182 | * InfoFrame and Control Packet Registers |
183 | */ |
184 | |
185 | /* AVI InfoFrame packet checksum */ |
186 | #define SP_AVI_INFOFRAME_CHECKSUM 0xa3 |
187 | |
188 | /* AVI InfoFrame Registers */ |
189 | #define SP_AVI_INFOFRAME_DATA_BASE 0xa4 |
190 | |
191 | #define SP_AVI_COLOR_F_MASK 0x60 |
192 | #define SP_AVI_COLOR_F_SHIFT 5 |
193 | |
194 | /* Audio InfoFrame Registers */ |
195 | #define SP_AUD_INFOFRAME_DATA_BASE 0xc4 |
196 | #define SP_AUD_INFOFRAME_LAYOUT_MASK 0x0f |
197 | |
198 | /* MPEG/HDMI Vendor Specific InfoFrame Packet type code */ |
199 | #define SP_MPEG_VS_INFOFRAME_TYPE_REG 0xe0 |
200 | |
201 | /* MPEG/HDMI Vendor Specific InfoFrame Packet length */ |
202 | #define SP_MPEG_VS_INFOFRAME_LEN_REG 0xe2 |
203 | |
204 | /* MPEG/HDMI Vendor Specific InfoFrame Packet version number */ |
205 | #define SP_MPEG_VS_INFOFRAME_VER_REG 0xe1 |
206 | |
207 | /* MPEG/HDMI Vendor Specific InfoFrame Packet content */ |
208 | #define SP_MPEG_VS_INFOFRAME_DATA_BASE 0xe4 |
209 | |
210 | /* General Control Packet Register */ |
211 | #define SP_GENERAL_CTRL_PACKET_REG 0x9f |
212 | #define SP_CLEAR_AVMUTE BIT(4) |
213 | #define SP_SET_AVMUTE BIT(0) |
214 | |
215 | /***************************************************************/ |
216 | /* Register definitions for TX_P1 */ |
217 | /***************************************************************/ |
218 | |
219 | /* DP TX Link Training Control Register */ |
220 | #define SP_DP_TX_LT_CTRL0_REG 0x30 |
221 | |
222 | /* PD 1.2 Lint Training 80bit Pattern Register */ |
223 | #define SP_DP_LT_80BIT_PATTERN0_REG 0x80 |
224 | #define SP_DP_LT_80BIT_PATTERN_REG_NUM 10 |
225 | |
226 | /* Audio Interface Control Register 0 */ |
227 | #define SP_AUD_INTERFACE_CTRL0_REG 0x5f |
228 | #define SP_AUD_INTERFACE_DISABLE 0x80 |
229 | |
230 | /* Audio Interface Control Register 2 */ |
231 | #define SP_AUD_INTERFACE_CTRL2_REG 0x60 |
232 | #define SP_M_AUD_ADJUST_ST 0x04 |
233 | |
234 | /* Audio Interface Control Register 3 */ |
235 | #define SP_AUD_INTERFACE_CTRL3_REG 0x62 |
236 | |
237 | /* Audio Interface Control Register 4 */ |
238 | #define SP_AUD_INTERFACE_CTRL4_REG 0x67 |
239 | |
240 | /* Audio Interface Control Register 5 */ |
241 | #define SP_AUD_INTERFACE_CTRL5_REG 0x68 |
242 | |
243 | /* Audio Interface Control Register 6 */ |
244 | #define SP_AUD_INTERFACE_CTRL6_REG 0x69 |
245 | |
246 | /* Firmware Version Register */ |
247 | #define SP_FW_VER_REG 0xb7 |
248 | |
249 | #endif |
250 | |