1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Header file for Analogix DP (Display Port) core interface driver. |
4 | * |
5 | * Copyright (C) 2012 Samsung Electronics Co., Ltd. |
6 | * Author: Jingoo Han <jg1.han@samsung.com> |
7 | */ |
8 | |
9 | #ifndef _ANALOGIX_DP_CORE_H |
10 | #define _ANALOGIX_DP_CORE_H |
11 | |
12 | #include <drm/display/drm_dp_helper.h> |
13 | #include <drm/drm_crtc.h> |
14 | |
15 | #define DP_TIMEOUT_LOOP_COUNT 100 |
16 | #define MAX_CR_LOOP 5 |
17 | #define MAX_EQ_LOOP 5 |
18 | #define MAX_PLL_LOCK_LOOP 5 |
19 | |
20 | /* Training takes 22ms if AUX channel comm fails. Use this as retry interval */ |
21 | #define DP_TIMEOUT_TRAINING_US 22000 |
22 | #define DP_TIMEOUT_PSR_LOOP_MS 300 |
23 | |
24 | /* DP_MAX_LANE_COUNT */ |
25 | #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1) |
26 | #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f) |
27 | |
28 | /* DP_LANE_COUNT_SET */ |
29 | #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f) |
30 | |
31 | /* DP_TRAINING_LANE0_SET */ |
32 | #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3) |
33 | #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3) |
34 | #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0) |
35 | #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3) |
36 | |
37 | struct gpio_desc; |
38 | |
39 | enum link_lane_count_type { |
40 | LANE_COUNT1 = 1, |
41 | LANE_COUNT2 = 2, |
42 | LANE_COUNT4 = 4 |
43 | }; |
44 | |
45 | enum link_training_state { |
46 | START, |
47 | CLOCK_RECOVERY, |
48 | EQUALIZER_TRAINING, |
49 | FINISHED, |
50 | FAILED |
51 | }; |
52 | |
53 | enum voltage_swing_level { |
54 | VOLTAGE_LEVEL_0, |
55 | VOLTAGE_LEVEL_1, |
56 | VOLTAGE_LEVEL_2, |
57 | VOLTAGE_LEVEL_3, |
58 | }; |
59 | |
60 | enum pre_emphasis_level { |
61 | PRE_EMPHASIS_LEVEL_0, |
62 | PRE_EMPHASIS_LEVEL_1, |
63 | PRE_EMPHASIS_LEVEL_2, |
64 | PRE_EMPHASIS_LEVEL_3, |
65 | }; |
66 | |
67 | enum pattern_set { |
68 | PRBS7, |
69 | D10_2, |
70 | TRAINING_PTN1, |
71 | TRAINING_PTN2, |
72 | DP_NONE |
73 | }; |
74 | |
75 | enum color_space { |
76 | COLOR_RGB, |
77 | COLOR_YCBCR422, |
78 | COLOR_YCBCR444 |
79 | }; |
80 | |
81 | enum color_depth { |
82 | COLOR_6, |
83 | COLOR_8, |
84 | COLOR_10, |
85 | COLOR_12 |
86 | }; |
87 | |
88 | enum color_coefficient { |
89 | COLOR_YCBCR601, |
90 | COLOR_YCBCR709 |
91 | }; |
92 | |
93 | enum dynamic_range { |
94 | VESA, |
95 | CEA |
96 | }; |
97 | |
98 | enum pll_status { |
99 | PLL_UNLOCKED, |
100 | PLL_LOCKED |
101 | }; |
102 | |
103 | enum clock_recovery_m_value_type { |
104 | CALCULATED_M, |
105 | REGISTER_M |
106 | }; |
107 | |
108 | enum video_timing_recognition_type { |
109 | VIDEO_TIMING_FROM_CAPTURE, |
110 | VIDEO_TIMING_FROM_REGISTER |
111 | }; |
112 | |
113 | enum analog_power_block { |
114 | AUX_BLOCK, |
115 | CH0_BLOCK, |
116 | CH1_BLOCK, |
117 | CH2_BLOCK, |
118 | CH3_BLOCK, |
119 | ANALOG_TOTAL, |
120 | POWER_ALL |
121 | }; |
122 | |
123 | enum dp_irq_type { |
124 | DP_IRQ_TYPE_HP_CABLE_IN = BIT(0), |
125 | DP_IRQ_TYPE_HP_CABLE_OUT = BIT(1), |
126 | DP_IRQ_TYPE_HP_CHANGE = BIT(2), |
127 | DP_IRQ_TYPE_UNKNOWN = BIT(3), |
128 | }; |
129 | |
130 | struct video_info { |
131 | char *name; |
132 | |
133 | bool h_sync_polarity; |
134 | bool v_sync_polarity; |
135 | bool interlaced; |
136 | |
137 | enum color_space color_space; |
138 | enum dynamic_range dynamic_range; |
139 | enum color_coefficient ycbcr_coeff; |
140 | enum color_depth color_depth; |
141 | |
142 | int max_link_rate; |
143 | enum link_lane_count_type max_lane_count; |
144 | }; |
145 | |
146 | struct link_train { |
147 | int eq_loop; |
148 | int cr_loop[4]; |
149 | |
150 | u8 link_rate; |
151 | u8 lane_count; |
152 | u8 training_lane[4]; |
153 | |
154 | enum link_training_state lt_state; |
155 | }; |
156 | |
157 | struct analogix_dp_device { |
158 | struct drm_encoder *encoder; |
159 | struct device *dev; |
160 | struct drm_device *drm_dev; |
161 | struct drm_connector connector; |
162 | struct drm_bridge *bridge; |
163 | struct drm_dp_aux aux; |
164 | struct clk *clock; |
165 | unsigned int irq; |
166 | void __iomem *reg_base; |
167 | |
168 | struct video_info video_info; |
169 | struct link_train link_train; |
170 | struct phy *phy; |
171 | int dpms_mode; |
172 | struct gpio_desc *hpd_gpiod; |
173 | bool force_hpd; |
174 | bool fast_train_enable; |
175 | bool psr_supported; |
176 | |
177 | struct mutex panel_lock; |
178 | bool panel_is_modeset; |
179 | |
180 | struct analogix_dp_plat_data *plat_data; |
181 | }; |
182 | |
183 | /* analogix_dp_reg.c */ |
184 | void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable); |
185 | void analogix_dp_stop_video(struct analogix_dp_device *dp); |
186 | void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable); |
187 | void analogix_dp_init_analog_param(struct analogix_dp_device *dp); |
188 | void analogix_dp_init_interrupt(struct analogix_dp_device *dp); |
189 | void analogix_dp_reset(struct analogix_dp_device *dp); |
190 | void analogix_dp_swreset(struct analogix_dp_device *dp); |
191 | void analogix_dp_config_interrupt(struct analogix_dp_device *dp); |
192 | void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp); |
193 | void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp); |
194 | enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp); |
195 | void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable); |
196 | void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, |
197 | enum analog_power_block block, |
198 | bool enable); |
199 | int analogix_dp_init_analog_func(struct analogix_dp_device *dp); |
200 | void analogix_dp_init_hpd(struct analogix_dp_device *dp); |
201 | void analogix_dp_force_hpd(struct analogix_dp_device *dp); |
202 | enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp); |
203 | void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp); |
204 | void analogix_dp_reset_aux(struct analogix_dp_device *dp); |
205 | void analogix_dp_init_aux(struct analogix_dp_device *dp); |
206 | int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp); |
207 | void analogix_dp_enable_sw_function(struct analogix_dp_device *dp); |
208 | void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype); |
209 | void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype); |
210 | void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count); |
211 | void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count); |
212 | void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, |
213 | bool enable); |
214 | void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, |
215 | enum pattern_set pattern); |
216 | void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, |
217 | u32 level); |
218 | void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, |
219 | u32 level); |
220 | void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, |
221 | u32 level); |
222 | void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, |
223 | u32 level); |
224 | void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp, |
225 | u32 training_lane); |
226 | void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp, |
227 | u32 training_lane); |
228 | void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp, |
229 | u32 training_lane); |
230 | void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp, |
231 | u32 training_lane); |
232 | u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp); |
233 | u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp); |
234 | u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp); |
235 | u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp); |
236 | void analogix_dp_reset_macro(struct analogix_dp_device *dp); |
237 | void analogix_dp_init_video(struct analogix_dp_device *dp); |
238 | |
239 | void analogix_dp_set_video_color_format(struct analogix_dp_device *dp); |
240 | int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp); |
241 | void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, |
242 | enum clock_recovery_m_value_type type, |
243 | u32 m_value, |
244 | u32 n_value); |
245 | void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type); |
246 | void analogix_dp_enable_video_master(struct analogix_dp_device *dp, |
247 | bool enable); |
248 | void analogix_dp_start_video(struct analogix_dp_device *dp); |
249 | int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp); |
250 | void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp); |
251 | void analogix_dp_enable_scrambling(struct analogix_dp_device *dp); |
252 | void analogix_dp_disable_scrambling(struct analogix_dp_device *dp); |
253 | void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp); |
254 | int analogix_dp_send_psr_spd(struct analogix_dp_device *dp, |
255 | struct dp_sdp *vsc, bool blocking); |
256 | ssize_t analogix_dp_transfer(struct analogix_dp_device *dp, |
257 | struct drm_dp_aux_msg *msg); |
258 | |
259 | #endif /* _ANALOGIX_DP_CORE_H */ |
260 | |