1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* |
3 | * Copyright (C) 2018 Samsung Electronics Co., Ltd |
4 | * |
5 | * Authors: |
6 | * Andrzej Hajda <a.hajda@samsung.com> |
7 | * Maciej Purski <m.purski@samsung.com> |
8 | */ |
9 | |
10 | #include <linux/delay.h> |
11 | #include <linux/gpio/consumer.h> |
12 | #include <linux/mod_devicetable.h> |
13 | #include <linux/module.h> |
14 | #include <linux/of_graph.h> |
15 | #include <linux/regulator/consumer.h> |
16 | |
17 | #include <video/mipi_display.h> |
18 | |
19 | #include <drm/drm_atomic_helper.h> |
20 | #include <drm/drm_mipi_dsi.h> |
21 | #include <drm/drm_of.h> |
22 | #include <drm/drm_print.h> |
23 | |
24 | #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end)) |
25 | #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end)) |
26 | |
27 | /* PPI layer registers */ |
28 | #define PPI_STARTPPI 0x0104 /* START control bit */ |
29 | #define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */ |
30 | #define PPI_LANEENABLE 0x0134 /* Enables each lane */ |
31 | #define PPI_TX_RX_TA 0x013C /* BTA timing parameters */ |
32 | #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */ |
33 | #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */ |
34 | #define PPI_D2S_CLRSIPOCOUNT 0x016C /* Assertion timer for Lane 2 */ |
35 | #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */ |
36 | #define PPI_START_FUNCTION 1 |
37 | |
38 | /* DSI layer registers */ |
39 | #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */ |
40 | #define DSI_LANEENABLE 0x0210 /* Enables each lane */ |
41 | #define DSI_RX_START 1 |
42 | |
43 | /* Video path registers */ |
44 | #define VP_CTRL 0x0450 /* Video Path Control */ |
45 | #define VP_CTRL_MSF BIT(0) /* Magic square in RGB666 */ |
46 | #define VP_CTRL_VTGEN BIT(4) /* Use chip clock for timing */ |
47 | #define VP_CTRL_EVTMODE BIT(5) /* Event mode */ |
48 | #define VP_CTRL_RGB888 BIT(8) /* RGB888 mode */ |
49 | #define VP_CTRL_VSDELAY(v) FLD_VAL(v, 31, 20) /* VSYNC delay */ |
50 | #define VP_CTRL_HSPOL BIT(17) /* Polarity of HSYNC signal */ |
51 | #define VP_CTRL_DEPOL BIT(18) /* Polarity of DE signal */ |
52 | #define VP_CTRL_VSPOL BIT(19) /* Polarity of VSYNC signal */ |
53 | #define VP_HTIM1 0x0454 /* Horizontal Timing Control 1 */ |
54 | #define VP_HTIM1_HBP(v) FLD_VAL(v, 24, 16) |
55 | #define VP_HTIM1_HSYNC(v) FLD_VAL(v, 8, 0) |
56 | #define VP_HTIM2 0x0458 /* Horizontal Timing Control 2 */ |
57 | #define VP_HTIM2_HFP(v) FLD_VAL(v, 24, 16) |
58 | #define VP_HTIM2_HACT(v) FLD_VAL(v, 10, 0) |
59 | #define VP_VTIM1 0x045C /* Vertical Timing Control 1 */ |
60 | #define VP_VTIM1_VBP(v) FLD_VAL(v, 23, 16) |
61 | #define VP_VTIM1_VSYNC(v) FLD_VAL(v, 7, 0) |
62 | #define VP_VTIM2 0x0460 /* Vertical Timing Control 2 */ |
63 | #define VP_VTIM2_VFP(v) FLD_VAL(v, 23, 16) |
64 | #define VP_VTIM2_VACT(v) FLD_VAL(v, 10, 0) |
65 | #define VP_VFUEN 0x0464 /* Video Frame Timing Update Enable */ |
66 | |
67 | /* LVDS registers */ |
68 | #define LV_MX0003 0x0480 /* Mux input bit 0 to 3 */ |
69 | #define LV_MX0407 0x0484 /* Mux input bit 4 to 7 */ |
70 | #define LV_MX0811 0x0488 /* Mux input bit 8 to 11 */ |
71 | #define LV_MX1215 0x048C /* Mux input bit 12 to 15 */ |
72 | #define LV_MX1619 0x0490 /* Mux input bit 16 to 19 */ |
73 | #define LV_MX2023 0x0494 /* Mux input bit 20 to 23 */ |
74 | #define LV_MX2427 0x0498 /* Mux input bit 24 to 27 */ |
75 | #define LV_MX(b0, b1, b2, b3) (FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \ |
76 | FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24)) |
77 | |
78 | /* Input bit numbers used in mux registers */ |
79 | enum { |
80 | LVI_R0, |
81 | LVI_R1, |
82 | LVI_R2, |
83 | LVI_R3, |
84 | LVI_R4, |
85 | LVI_R5, |
86 | LVI_R6, |
87 | LVI_R7, |
88 | LVI_G0, |
89 | LVI_G1, |
90 | LVI_G2, |
91 | LVI_G3, |
92 | LVI_G4, |
93 | LVI_G5, |
94 | LVI_G6, |
95 | LVI_G7, |
96 | LVI_B0, |
97 | LVI_B1, |
98 | LVI_B2, |
99 | LVI_B3, |
100 | LVI_B4, |
101 | LVI_B5, |
102 | LVI_B6, |
103 | LVI_B7, |
104 | LVI_HS, |
105 | LVI_VS, |
106 | LVI_DE, |
107 | LVI_L0 |
108 | }; |
109 | |
110 | #define LV_CFG 0x049C /* LVDS Configuration */ |
111 | #define LV_PHY0 0x04A0 /* LVDS PHY 0 */ |
112 | #define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */ |
113 | #define LV_PHY0_IS(v) FLD_VAL(v, 15, 14) |
114 | #define LV_PHY0_ND(v) FLD_VAL(v, 4, 0) /* Frequency range select */ |
115 | #define LV_PHY0_PRBS_ON(v) FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */ |
116 | |
117 | /* System registers */ |
118 | #define SYS_RST 0x0504 /* System Reset */ |
119 | #define SYS_ID 0x0580 /* System ID */ |
120 | |
121 | #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */ |
122 | #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */ |
123 | #define SYS_RST_LCD BIT(2) /* Reset LCD controller */ |
124 | #define SYS_RST_BM BIT(3) /* Reset Bus Management controller */ |
125 | #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */ |
126 | #define SYS_RST_REG BIT(5) /* Reset Register module */ |
127 | |
128 | #define LPX_PERIOD 2 |
129 | #define TTA_SURE 3 |
130 | #define TTA_GET 0x20000 |
131 | |
132 | /* Lane enable PPI and DSI register bits */ |
133 | #define LANEENABLE_CLEN BIT(0) |
134 | #define LANEENABLE_L0EN BIT(1) |
135 | #define LANEENABLE_L1EN BIT(2) |
136 | #define LANEENABLE_L2EN BIT(3) |
137 | #define LANEENABLE_L3EN BIT(4) |
138 | |
139 | /* LVCFG fields */ |
140 | #define LV_CFG_LVEN BIT(0) |
141 | #define LV_CFG_LVDLINK BIT(1) |
142 | #define LV_CFG_CLKPOL1 BIT(2) |
143 | #define LV_CFG_CLKPOL2 BIT(3) |
144 | |
145 | static const char * const tc358764_supplies[] = { |
146 | "vddc" , "vddio" , "vddlvds" |
147 | }; |
148 | |
149 | struct tc358764 { |
150 | struct device *dev; |
151 | struct drm_bridge bridge; |
152 | struct drm_bridge *next_bridge; |
153 | struct regulator_bulk_data supplies[ARRAY_SIZE(tc358764_supplies)]; |
154 | struct gpio_desc *gpio_reset; |
155 | int error; |
156 | }; |
157 | |
158 | static int tc358764_clear_error(struct tc358764 *ctx) |
159 | { |
160 | int ret = ctx->error; |
161 | |
162 | ctx->error = 0; |
163 | return ret; |
164 | } |
165 | |
166 | static void tc358764_read(struct tc358764 *ctx, u16 addr, u32 *val) |
167 | { |
168 | struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); |
169 | ssize_t ret; |
170 | |
171 | if (ctx->error) |
172 | return; |
173 | |
174 | cpu_to_le16s(&addr); |
175 | ret = mipi_dsi_generic_read(dsi, params: &addr, num_params: sizeof(addr), data: val, size: sizeof(*val)); |
176 | if (ret >= 0) |
177 | le32_to_cpus(val); |
178 | |
179 | dev_dbg(ctx->dev, "read: addr=0x%04x data=0x%08x\n" , addr, *val); |
180 | } |
181 | |
182 | static void tc358764_write(struct tc358764 *ctx, u16 addr, u32 val) |
183 | { |
184 | struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev); |
185 | ssize_t ret; |
186 | u8 data[6]; |
187 | |
188 | if (ctx->error) |
189 | return; |
190 | |
191 | data[0] = addr; |
192 | data[1] = addr >> 8; |
193 | data[2] = val; |
194 | data[3] = val >> 8; |
195 | data[4] = val >> 16; |
196 | data[5] = val >> 24; |
197 | |
198 | ret = mipi_dsi_generic_write(dsi, payload: data, size: sizeof(data)); |
199 | if (ret < 0) |
200 | ctx->error = ret; |
201 | } |
202 | |
203 | static inline struct tc358764 *bridge_to_tc358764(struct drm_bridge *bridge) |
204 | { |
205 | return container_of(bridge, struct tc358764, bridge); |
206 | } |
207 | |
208 | static int tc358764_init(struct tc358764 *ctx) |
209 | { |
210 | u32 v = 0; |
211 | |
212 | tc358764_read(ctx, SYS_ID, val: &v); |
213 | if (ctx->error) |
214 | return tc358764_clear_error(ctx); |
215 | dev_info(ctx->dev, "ID: %#x\n" , v); |
216 | |
217 | /* configure PPI counters */ |
218 | tc358764_write(ctx, PPI_TX_RX_TA, TTA_GET | TTA_SURE); |
219 | tc358764_write(ctx, PPI_LPTXTIMECNT, LPX_PERIOD); |
220 | tc358764_write(ctx, PPI_D0S_CLRSIPOCOUNT, val: 5); |
221 | tc358764_write(ctx, PPI_D1S_CLRSIPOCOUNT, val: 5); |
222 | tc358764_write(ctx, PPI_D2S_CLRSIPOCOUNT, val: 5); |
223 | tc358764_write(ctx, PPI_D3S_CLRSIPOCOUNT, val: 5); |
224 | |
225 | /* enable four data lanes and clock lane */ |
226 | tc358764_write(ctx, PPI_LANEENABLE, LANEENABLE_L3EN | LANEENABLE_L2EN | |
227 | LANEENABLE_L1EN | LANEENABLE_L0EN | LANEENABLE_CLEN); |
228 | tc358764_write(ctx, DSI_LANEENABLE, LANEENABLE_L3EN | LANEENABLE_L2EN | |
229 | LANEENABLE_L1EN | LANEENABLE_L0EN | LANEENABLE_CLEN); |
230 | |
231 | /* start */ |
232 | tc358764_write(ctx, PPI_STARTPPI, PPI_START_FUNCTION); |
233 | tc358764_write(ctx, DSI_STARTDSI, DSI_RX_START); |
234 | |
235 | /* configure video path */ |
236 | tc358764_write(ctx, VP_CTRL, VP_CTRL_VSDELAY(15) | VP_CTRL_RGB888 | |
237 | VP_CTRL_EVTMODE | VP_CTRL_HSPOL | VP_CTRL_VSPOL); |
238 | |
239 | /* reset PHY */ |
240 | tc358764_write(ctx, LV_PHY0, LV_PHY0_RST(1) | |
241 | LV_PHY0_PRBS_ON(4) | LV_PHY0_IS(2) | LV_PHY0_ND(6)); |
242 | tc358764_write(ctx, LV_PHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_IS(2) | |
243 | LV_PHY0_ND(6)); |
244 | |
245 | /* reset bridge */ |
246 | tc358764_write(ctx, SYS_RST, SYS_RST_LCD); |
247 | |
248 | /* set bit order */ |
249 | tc358764_write(ctx, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3)); |
250 | tc358764_write(ctx, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0)); |
251 | tc358764_write(ctx, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7)); |
252 | tc358764_write(ctx, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0)); |
253 | tc358764_write(ctx, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2)); |
254 | tc358764_write(ctx, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0)); |
255 | tc358764_write(ctx, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6)); |
256 | tc358764_write(ctx, LV_CFG, LV_CFG_CLKPOL2 | LV_CFG_CLKPOL1 | |
257 | LV_CFG_LVEN); |
258 | |
259 | return tc358764_clear_error(ctx); |
260 | } |
261 | |
262 | static void tc358764_reset(struct tc358764 *ctx) |
263 | { |
264 | gpiod_set_value(desc: ctx->gpio_reset, value: 1); |
265 | usleep_range(min: 1000, max: 2000); |
266 | gpiod_set_value(desc: ctx->gpio_reset, value: 0); |
267 | usleep_range(min: 1000, max: 2000); |
268 | } |
269 | |
270 | static void tc358764_post_disable(struct drm_bridge *bridge) |
271 | { |
272 | struct tc358764 *ctx = bridge_to_tc358764(bridge); |
273 | int ret; |
274 | |
275 | tc358764_reset(ctx); |
276 | usleep_range(min: 10000, max: 15000); |
277 | ret = regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), consumers: ctx->supplies); |
278 | if (ret < 0) |
279 | dev_err(ctx->dev, "error disabling regulators (%d)\n" , ret); |
280 | } |
281 | |
282 | static void tc358764_pre_enable(struct drm_bridge *bridge) |
283 | { |
284 | struct tc358764 *ctx = bridge_to_tc358764(bridge); |
285 | int ret; |
286 | |
287 | ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), consumers: ctx->supplies); |
288 | if (ret < 0) |
289 | dev_err(ctx->dev, "error enabling regulators (%d)\n" , ret); |
290 | usleep_range(min: 10000, max: 15000); |
291 | tc358764_reset(ctx); |
292 | ret = tc358764_init(ctx); |
293 | if (ret < 0) |
294 | dev_err(ctx->dev, "error initializing bridge (%d)\n" , ret); |
295 | } |
296 | |
297 | static int tc358764_attach(struct drm_bridge *bridge, |
298 | enum drm_bridge_attach_flags flags) |
299 | { |
300 | struct tc358764 *ctx = bridge_to_tc358764(bridge); |
301 | |
302 | return drm_bridge_attach(encoder: bridge->encoder, bridge: ctx->next_bridge, previous: bridge, flags); |
303 | } |
304 | |
305 | static const struct drm_bridge_funcs tc358764_bridge_funcs = { |
306 | .post_disable = tc358764_post_disable, |
307 | .pre_enable = tc358764_pre_enable, |
308 | .attach = tc358764_attach, |
309 | }; |
310 | |
311 | static int tc358764_parse_dt(struct tc358764 *ctx) |
312 | { |
313 | struct device *dev = ctx->dev; |
314 | |
315 | ctx->gpio_reset = devm_gpiod_get(dev, con_id: "reset" , flags: GPIOD_OUT_LOW); |
316 | if (IS_ERR(ptr: ctx->gpio_reset)) { |
317 | dev_err(dev, "no reset GPIO pin provided\n" ); |
318 | return PTR_ERR(ptr: ctx->gpio_reset); |
319 | } |
320 | |
321 | ctx->next_bridge = devm_drm_of_get_bridge(dev, node: dev->of_node, port: 1, endpoint: 0); |
322 | if (IS_ERR(ptr: ctx->next_bridge)) |
323 | return PTR_ERR(ptr: ctx->next_bridge); |
324 | |
325 | return 0; |
326 | } |
327 | |
328 | static int tc358764_configure_regulators(struct tc358764 *ctx) |
329 | { |
330 | int i, ret; |
331 | |
332 | for (i = 0; i < ARRAY_SIZE(ctx->supplies); ++i) |
333 | ctx->supplies[i].supply = tc358764_supplies[i]; |
334 | |
335 | ret = devm_regulator_bulk_get(dev: ctx->dev, ARRAY_SIZE(ctx->supplies), |
336 | consumers: ctx->supplies); |
337 | if (ret < 0) |
338 | dev_err(ctx->dev, "failed to get regulators: %d\n" , ret); |
339 | |
340 | return ret; |
341 | } |
342 | |
343 | static int tc358764_probe(struct mipi_dsi_device *dsi) |
344 | { |
345 | struct device *dev = &dsi->dev; |
346 | struct tc358764 *ctx; |
347 | int ret; |
348 | |
349 | ctx = devm_kzalloc(dev, size: sizeof(struct tc358764), GFP_KERNEL); |
350 | if (!ctx) |
351 | return -ENOMEM; |
352 | |
353 | mipi_dsi_set_drvdata(dsi, data: ctx); |
354 | |
355 | ctx->dev = dev; |
356 | |
357 | dsi->lanes = 4; |
358 | dsi->format = MIPI_DSI_FMT_RGB888; |
359 | dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
360 | | MIPI_DSI_MODE_VIDEO_AUTO_VERT | MIPI_DSI_MODE_LPM; |
361 | |
362 | ret = tc358764_parse_dt(ctx); |
363 | if (ret < 0) |
364 | return ret; |
365 | |
366 | ret = tc358764_configure_regulators(ctx); |
367 | if (ret < 0) |
368 | return ret; |
369 | |
370 | ctx->bridge.funcs = &tc358764_bridge_funcs; |
371 | ctx->bridge.of_node = dev->of_node; |
372 | ctx->bridge.pre_enable_prev_first = true; |
373 | |
374 | drm_bridge_add(bridge: &ctx->bridge); |
375 | |
376 | ret = mipi_dsi_attach(dsi); |
377 | if (ret < 0) { |
378 | drm_bridge_remove(bridge: &ctx->bridge); |
379 | dev_err(dev, "failed to attach dsi\n" ); |
380 | } |
381 | |
382 | return ret; |
383 | } |
384 | |
385 | static void tc358764_remove(struct mipi_dsi_device *dsi) |
386 | { |
387 | struct tc358764 *ctx = mipi_dsi_get_drvdata(dsi); |
388 | |
389 | mipi_dsi_detach(dsi); |
390 | drm_bridge_remove(bridge: &ctx->bridge); |
391 | } |
392 | |
393 | static const struct of_device_id tc358764_of_match[] = { |
394 | { .compatible = "toshiba,tc358764" }, |
395 | { } |
396 | }; |
397 | MODULE_DEVICE_TABLE(of, tc358764_of_match); |
398 | |
399 | static struct mipi_dsi_driver tc358764_driver = { |
400 | .probe = tc358764_probe, |
401 | .remove = tc358764_remove, |
402 | .driver = { |
403 | .name = "tc358764" , |
404 | .owner = THIS_MODULE, |
405 | .of_match_table = tc358764_of_match, |
406 | }, |
407 | }; |
408 | module_mipi_dsi_driver(tc358764_driver); |
409 | |
410 | MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>" ); |
411 | MODULE_AUTHOR("Maciej Purski <m.purski@samsung.com>" ); |
412 | MODULE_DESCRIPTION("MIPI-DSI based Driver for TC358764 DSI/LVDS Bridge" ); |
413 | MODULE_LICENSE("GPL v2" ); |
414 | |