1// SPDX-License-Identifier: GPL-2.0
2/*
3 * TC358775 DSI to LVDS bridge driver
4 *
5 * Copyright (C) 2020 SMART Wireless Computing
6 * Author: Vinay Simha BN <simhavcs@gmail.com>
7 *
8 */
9/* #define DEBUG */
10#include <linux/bitfield.h>
11#include <linux/clk.h>
12#include <linux/device.h>
13#include <linux/gpio/consumer.h>
14#include <linux/i2c.h>
15#include <linux/kernel.h>
16#include <linux/media-bus-format.h>
17#include <linux/module.h>
18#include <linux/regulator/consumer.h>
19#include <linux/slab.h>
20
21#include <asm/unaligned.h>
22
23#include <drm/display/drm_dp_helper.h>
24#include <drm/drm_atomic_helper.h>
25#include <drm/drm_bridge.h>
26#include <drm/drm_mipi_dsi.h>
27#include <drm/drm_of.h>
28#include <drm/drm_panel.h>
29#include <drm/drm_probe_helper.h>
30
31#define FLD_VAL(val, start, end) FIELD_PREP(GENMASK(start, end), val)
32
33/* Registers */
34
35/* DSI D-PHY Layer Registers */
36#define D0W_DPHYCONTTX 0x0004 /* Data Lane 0 DPHY Tx Control */
37#define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
38#define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
39#define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
40#define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
41#define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
42#define COM_DPHYCONTRX 0x0038 /* DPHY Rx Common Control */
43#define CLW_CNTRL 0x0040 /* Clock Lane Control */
44#define D0W_CNTRL 0x0044 /* Data Lane 0 Control */
45#define D1W_CNTRL 0x0048 /* Data Lane 1 Control */
46#define D2W_CNTRL 0x004C /* Data Lane 2 Control */
47#define D3W_CNTRL 0x0050 /* Data Lane 3 Control */
48#define DFTMODE_CNTRL 0x0054 /* DFT Mode Control */
49
50/* DSI PPI Layer Registers */
51#define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */
52#define PPI_START_FUNCTION 1
53
54#define PPI_BUSYPPI 0x0108
55#define PPI_LINEINITCNT 0x0110 /* Line Initialization Wait Counter */
56#define PPI_LPTXTIMECNT 0x0114
57#define PPI_LANEENABLE 0x0134 /* Enables each lane at the PPI layer. */
58#define PPI_TX_RX_TA 0x013C /* DSI Bus Turn Around timing parameters */
59
60/* Analog timer function enable */
61#define PPI_CLS_ATMR 0x0140 /* Delay for Clock Lane in LPRX */
62#define PPI_D0S_ATMR 0x0144 /* Delay for Data Lane 0 in LPRX */
63#define PPI_D1S_ATMR 0x0148 /* Delay for Data Lane 1 in LPRX */
64#define PPI_D2S_ATMR 0x014C /* Delay for Data Lane 2 in LPRX */
65#define PPI_D3S_ATMR 0x0150 /* Delay for Data Lane 3 in LPRX */
66
67#define PPI_D0S_CLRSIPOCOUNT 0x0164 /* For lane 0 */
68#define PPI_D1S_CLRSIPOCOUNT 0x0168 /* For lane 1 */
69#define PPI_D2S_CLRSIPOCOUNT 0x016C /* For lane 2 */
70#define PPI_D3S_CLRSIPOCOUNT 0x0170 /* For lane 3 */
71
72#define CLS_PRE 0x0180 /* Digital Counter inside of PHY IO */
73#define D0S_PRE 0x0184 /* Digital Counter inside of PHY IO */
74#define D1S_PRE 0x0188 /* Digital Counter inside of PHY IO */
75#define D2S_PRE 0x018C /* Digital Counter inside of PHY IO */
76#define D3S_PRE 0x0190 /* Digital Counter inside of PHY IO */
77#define CLS_PREP 0x01A0 /* Digital Counter inside of PHY IO */
78#define D0S_PREP 0x01A4 /* Digital Counter inside of PHY IO */
79#define D1S_PREP 0x01A8 /* Digital Counter inside of PHY IO */
80#define D2S_PREP 0x01AC /* Digital Counter inside of PHY IO */
81#define D3S_PREP 0x01B0 /* Digital Counter inside of PHY IO */
82#define CLS_ZERO 0x01C0 /* Digital Counter inside of PHY IO */
83#define D0S_ZERO 0x01C4 /* Digital Counter inside of PHY IO */
84#define D1S_ZERO 0x01C8 /* Digital Counter inside of PHY IO */
85#define D2S_ZERO 0x01CC /* Digital Counter inside of PHY IO */
86#define D3S_ZERO 0x01D0 /* Digital Counter inside of PHY IO */
87
88#define PPI_CLRFLG 0x01E0 /* PRE Counters has reached set values */
89#define PPI_CLRSIPO 0x01E4 /* Clear SIPO values, Slave mode use only. */
90#define HSTIMEOUT 0x01F0 /* HS Rx Time Out Counter */
91#define HSTIMEOUTENABLE 0x01F4 /* Enable HS Rx Time Out Counter */
92#define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX function */
93#define DSI_RX_START 1
94
95#define DSI_BUSYDSI 0x0208
96#define DSI_LANEENABLE 0x0210 /* Enables each lane at the Protocol layer. */
97#define DSI_LANESTATUS0 0x0214 /* Displays lane is in HS RX mode. */
98#define DSI_LANESTATUS1 0x0218 /* Displays lane is in ULPS or STOP state */
99
100#define DSI_INTSTATUS 0x0220 /* Interrupt Status */
101#define DSI_INTMASK 0x0224 /* Interrupt Mask */
102#define DSI_INTCLR 0x0228 /* Interrupt Clear */
103#define DSI_LPTXTO 0x0230 /* Low Power Tx Time Out Counter */
104
105#define DSIERRCNT 0x0300 /* DSI Error Count */
106#define APLCTRL 0x0400 /* Application Layer Control */
107#define RDPKTLN 0x0404 /* Command Read Packet Length */
108
109#define VPCTRL 0x0450 /* Video Path Control */
110#define HTIM1 0x0454 /* Horizontal Timing Control 1 */
111#define HTIM2 0x0458 /* Horizontal Timing Control 2 */
112#define VTIM1 0x045C /* Vertical Timing Control 1 */
113#define VTIM2 0x0460 /* Vertical Timing Control 2 */
114#define VFUEN 0x0464 /* Video Frame Timing Update Enable */
115#define VFUEN_EN BIT(0) /* Upload Enable */
116
117/* Mux Input Select for LVDS LINK Input */
118#define LV_MX0003 0x0480 /* Bit 0 to 3 */
119#define LV_MX0407 0x0484 /* Bit 4 to 7 */
120#define LV_MX0811 0x0488 /* Bit 8 to 11 */
121#define LV_MX1215 0x048C /* Bit 12 to 15 */
122#define LV_MX1619 0x0490 /* Bit 16 to 19 */
123#define LV_MX2023 0x0494 /* Bit 20 to 23 */
124#define LV_MX2427 0x0498 /* Bit 24 to 27 */
125#define LV_MX(b0, b1, b2, b3) (FLD_VAL(b0, 4, 0) | FLD_VAL(b1, 12, 8) | \
126 FLD_VAL(b2, 20, 16) | FLD_VAL(b3, 28, 24))
127
128/* Input bit numbers used in mux registers */
129enum {
130 LVI_R0,
131 LVI_R1,
132 LVI_R2,
133 LVI_R3,
134 LVI_R4,
135 LVI_R5,
136 LVI_R6,
137 LVI_R7,
138 LVI_G0,
139 LVI_G1,
140 LVI_G2,
141 LVI_G3,
142 LVI_G4,
143 LVI_G5,
144 LVI_G6,
145 LVI_G7,
146 LVI_B0,
147 LVI_B1,
148 LVI_B2,
149 LVI_B3,
150 LVI_B4,
151 LVI_B5,
152 LVI_B6,
153 LVI_B7,
154 LVI_HS,
155 LVI_VS,
156 LVI_DE,
157 LVI_L0
158};
159
160#define LVCFG 0x049C /* LVDS Configuration */
161#define LVPHY0 0x04A0 /* LVDS PHY 0 */
162#define LV_PHY0_RST(v) FLD_VAL(v, 22, 22) /* PHY reset */
163#define LV_PHY0_IS(v) FLD_VAL(v, 15, 14)
164#define LV_PHY0_ND(v) FLD_VAL(v, 4, 0) /* Frequency range select */
165#define LV_PHY0_PRBS_ON(v) FLD_VAL(v, 20, 16) /* Clock/Data Flag pins */
166
167#define LVPHY1 0x04A4 /* LVDS PHY 1 */
168#define SYSSTAT 0x0500 /* System Status */
169#define SYSRST 0x0504 /* System Reset */
170
171#define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
172#define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
173#define SYS_RST_LCD BIT(2) /* Reset LCD controller */
174#define SYS_RST_BM BIT(3) /* Reset Bus Management controller */
175#define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */
176#define SYS_RST_REG BIT(5) /* Reset Register module */
177
178/* GPIO Registers */
179#define GPIOC 0x0520 /* GPIO Control */
180#define GPIOO 0x0524 /* GPIO Output */
181#define GPIOI 0x0528 /* GPIO Input */
182
183/* I2C Registers */
184#define I2CTIMCTRL 0x0540 /* I2C IF Timing and Enable Control */
185#define I2CMADDR 0x0544 /* I2C Master Addressing */
186#define WDATAQ 0x0548 /* Write Data Queue */
187#define RDATAQ 0x054C /* Read Data Queue */
188
189/* Chip ID and Revision ID Register */
190#define IDREG 0x0580
191
192#define LPX_PERIOD 4
193#define TTA_GET 0x40000
194#define TTA_SURE 6
195#define SINGLE_LINK 1
196#define DUAL_LINK 2
197
198#define TC358775XBG_ID 0x00007500
199
200/* Debug Registers */
201#define DEBUG00 0x05A0 /* Debug */
202#define DEBUG01 0x05A4 /* LVDS Data */
203
204#define DSI_CLEN_BIT BIT(0)
205#define DIVIDE_BY_3 3 /* PCLK=DCLK/3 */
206#define DIVIDE_BY_6 6 /* PCLK=DCLK/6 */
207#define LVCFG_LVEN_BIT BIT(0)
208
209#define L0EN BIT(1)
210
211#define TC358775_VPCTRL_VSDELAY__MASK 0x3FF00000
212#define TC358775_VPCTRL_VSDELAY__SHIFT 20
213static inline u32 TC358775_VPCTRL_VSDELAY(uint32_t val)
214{
215 return ((val) << TC358775_VPCTRL_VSDELAY__SHIFT) &
216 TC358775_VPCTRL_VSDELAY__MASK;
217}
218
219#define TC358775_VPCTRL_OPXLFMT__MASK 0x00000100
220#define TC358775_VPCTRL_OPXLFMT__SHIFT 8
221static inline u32 TC358775_VPCTRL_OPXLFMT(uint32_t val)
222{
223 return ((val) << TC358775_VPCTRL_OPXLFMT__SHIFT) &
224 TC358775_VPCTRL_OPXLFMT__MASK;
225}
226
227#define TC358775_VPCTRL_MSF__MASK 0x00000001
228#define TC358775_VPCTRL_MSF__SHIFT 0
229static inline u32 TC358775_VPCTRL_MSF(uint32_t val)
230{
231 return ((val) << TC358775_VPCTRL_MSF__SHIFT) &
232 TC358775_VPCTRL_MSF__MASK;
233}
234
235#define TC358775_LVCFG_PCLKDIV__MASK 0x000000f0
236#define TC358775_LVCFG_PCLKDIV__SHIFT 4
237static inline u32 TC358775_LVCFG_PCLKDIV(uint32_t val)
238{
239 return ((val) << TC358775_LVCFG_PCLKDIV__SHIFT) &
240 TC358775_LVCFG_PCLKDIV__MASK;
241}
242
243#define TC358775_LVCFG_LVDLINK__MASK 0x00000002
244#define TC358775_LVCFG_LVDLINK__SHIFT 1
245static inline u32 TC358775_LVCFG_LVDLINK(uint32_t val)
246{
247 return ((val) << TC358775_LVCFG_LVDLINK__SHIFT) &
248 TC358775_LVCFG_LVDLINK__MASK;
249}
250
251enum tc358775_ports {
252 TC358775_DSI_IN,
253 TC358775_LVDS_OUT0,
254 TC358775_LVDS_OUT1,
255};
256
257struct tc_data {
258 struct i2c_client *i2c;
259 struct device *dev;
260
261 struct drm_bridge bridge;
262 struct drm_bridge *panel_bridge;
263
264 struct device_node *host_node;
265 struct mipi_dsi_device *dsi;
266 u8 num_dsi_lanes;
267
268 struct regulator *vdd;
269 struct regulator *vddio;
270 struct gpio_desc *reset_gpio;
271 struct gpio_desc *stby_gpio;
272 u8 lvds_link; /* single-link or dual-link */
273 u8 bpc;
274};
275
276static inline struct tc_data *bridge_to_tc(struct drm_bridge *b)
277{
278 return container_of(b, struct tc_data, bridge);
279}
280
281static void tc_bridge_pre_enable(struct drm_bridge *bridge)
282{
283 struct tc_data *tc = bridge_to_tc(b: bridge);
284 struct device *dev = &tc->dsi->dev;
285 int ret;
286
287 ret = regulator_enable(regulator: tc->vddio);
288 if (ret < 0)
289 dev_err(dev, "regulator vddio enable failed, %d\n", ret);
290 usleep_range(min: 10000, max: 11000);
291
292 ret = regulator_enable(regulator: tc->vdd);
293 if (ret < 0)
294 dev_err(dev, "regulator vdd enable failed, %d\n", ret);
295 usleep_range(min: 10000, max: 11000);
296
297 gpiod_set_value(desc: tc->stby_gpio, value: 0);
298 usleep_range(min: 10000, max: 11000);
299
300 gpiod_set_value(desc: tc->reset_gpio, value: 0);
301 usleep_range(min: 10, max: 20);
302}
303
304static void tc_bridge_post_disable(struct drm_bridge *bridge)
305{
306 struct tc_data *tc = bridge_to_tc(b: bridge);
307 struct device *dev = &tc->dsi->dev;
308 int ret;
309
310 gpiod_set_value(desc: tc->reset_gpio, value: 1);
311 usleep_range(min: 10, max: 20);
312
313 gpiod_set_value(desc: tc->stby_gpio, value: 1);
314 usleep_range(min: 10000, max: 11000);
315
316 ret = regulator_disable(regulator: tc->vdd);
317 if (ret < 0)
318 dev_err(dev, "regulator vdd disable failed, %d\n", ret);
319 usleep_range(min: 10000, max: 11000);
320
321 ret = regulator_disable(regulator: tc->vddio);
322 if (ret < 0)
323 dev_err(dev, "regulator vddio disable failed, %d\n", ret);
324 usleep_range(min: 10000, max: 11000);
325}
326
327static void d2l_read(struct i2c_client *i2c, u16 addr, u32 *val)
328{
329 int ret;
330 u8 buf_addr[2];
331
332 put_unaligned_be16(val: addr, p: buf_addr);
333 ret = i2c_master_send(client: i2c, buf: buf_addr, count: sizeof(buf_addr));
334 if (ret < 0)
335 goto fail;
336
337 ret = i2c_master_recv(client: i2c, buf: (u8 *)val, count: sizeof(*val));
338 if (ret < 0)
339 goto fail;
340
341 pr_debug("d2l: I2C : addr:%04x value:%08x\n", addr, *val);
342 return;
343
344fail:
345 dev_err(&i2c->dev, "Error %d reading from subaddress 0x%x\n",
346 ret, addr);
347}
348
349static void d2l_write(struct i2c_client *i2c, u16 addr, u32 val)
350{
351 u8 data[6];
352 int ret;
353
354 put_unaligned_be16(val: addr, p: data);
355 put_unaligned_le32(val, p: data + 2);
356
357 ret = i2c_master_send(client: i2c, buf: data, ARRAY_SIZE(data));
358 if (ret < 0)
359 dev_err(&i2c->dev, "Error %d writing to subaddress 0x%x\n",
360 ret, addr);
361}
362
363/* helper function to access bus_formats */
364static struct drm_connector *get_connector(struct drm_encoder *encoder)
365{
366 struct drm_device *dev = encoder->dev;
367 struct drm_connector *connector;
368
369 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
370 if (connector->encoder == encoder)
371 return connector;
372
373 return NULL;
374}
375
376static void tc_bridge_enable(struct drm_bridge *bridge)
377{
378 struct tc_data *tc = bridge_to_tc(b: bridge);
379 u32 hback_porch, hsync_len, hfront_porch, hactive, htime1, htime2;
380 u32 vback_porch, vsync_len, vfront_porch, vactive, vtime1, vtime2;
381 u32 val = 0;
382 u16 dsiclk, clkdiv, byteclk, t1, t2, t3, vsdelay;
383 struct drm_display_mode *mode;
384 struct drm_connector *connector = get_connector(encoder: bridge->encoder);
385
386 mode = &bridge->encoder->crtc->state->adjusted_mode;
387
388 hback_porch = mode->htotal - mode->hsync_end;
389 hsync_len = mode->hsync_end - mode->hsync_start;
390 vback_porch = mode->vtotal - mode->vsync_end;
391 vsync_len = mode->vsync_end - mode->vsync_start;
392
393 htime1 = (hback_porch << 16) + hsync_len;
394 vtime1 = (vback_porch << 16) + vsync_len;
395
396 hfront_porch = mode->hsync_start - mode->hdisplay;
397 hactive = mode->hdisplay;
398 vfront_porch = mode->vsync_start - mode->vdisplay;
399 vactive = mode->vdisplay;
400
401 htime2 = (hfront_porch << 16) + hactive;
402 vtime2 = (vfront_porch << 16) + vactive;
403
404 d2l_read(i2c: tc->i2c, IDREG, val: &val);
405
406 dev_info(tc->dev, "DSI2LVDS Chip ID.%02x Revision ID. %02x **\n",
407 (val >> 8) & 0xFF, val & 0xFF);
408
409 d2l_write(i2c: tc->i2c, SYSRST, SYS_RST_REG | SYS_RST_DSIRX | SYS_RST_BM |
410 SYS_RST_LCD | SYS_RST_I2CM);
411 usleep_range(min: 30000, max: 40000);
412
413 d2l_write(i2c: tc->i2c, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
414 d2l_write(i2c: tc->i2c, PPI_LPTXTIMECNT, LPX_PERIOD);
415 d2l_write(i2c: tc->i2c, PPI_D0S_CLRSIPOCOUNT, val: 3);
416 d2l_write(i2c: tc->i2c, PPI_D1S_CLRSIPOCOUNT, val: 3);
417 d2l_write(i2c: tc->i2c, PPI_D2S_CLRSIPOCOUNT, val: 3);
418 d2l_write(i2c: tc->i2c, PPI_D3S_CLRSIPOCOUNT, val: 3);
419
420 val = ((L0EN << tc->num_dsi_lanes) - L0EN) | DSI_CLEN_BIT;
421 d2l_write(i2c: tc->i2c, PPI_LANEENABLE, val);
422 d2l_write(i2c: tc->i2c, DSI_LANEENABLE, val);
423
424 d2l_write(i2c: tc->i2c, PPI_STARTPPI, PPI_START_FUNCTION);
425 d2l_write(i2c: tc->i2c, DSI_STARTDSI, DSI_RX_START);
426
427 if (tc->bpc == 8)
428 val = TC358775_VPCTRL_OPXLFMT(val: 1);
429 else /* bpc = 6; */
430 val = TC358775_VPCTRL_MSF(val: 1);
431
432 dsiclk = mode->crtc_clock * 3 * tc->bpc / tc->num_dsi_lanes / 1000;
433 clkdiv = dsiclk / (tc->lvds_link == DUAL_LINK ? DIVIDE_BY_6 : DIVIDE_BY_3);
434 byteclk = dsiclk / 4;
435 t1 = hactive * (tc->bpc * 3 / 8) / tc->num_dsi_lanes;
436 t2 = ((100000 / clkdiv)) * (hactive + hback_porch + hsync_len + hfront_porch) / 1000;
437 t3 = ((t2 * byteclk) / 100) - (hactive * (tc->bpc * 3 / 8) /
438 tc->num_dsi_lanes);
439
440 vsdelay = (clkdiv * (t1 + t3) / byteclk) - hback_porch - hsync_len - hactive;
441
442 val |= TC358775_VPCTRL_VSDELAY(val: vsdelay);
443 d2l_write(i2c: tc->i2c, VPCTRL, val);
444
445 d2l_write(i2c: tc->i2c, HTIM1, val: htime1);
446 d2l_write(i2c: tc->i2c, VTIM1, val: vtime1);
447 d2l_write(i2c: tc->i2c, HTIM2, val: htime2);
448 d2l_write(i2c: tc->i2c, VTIM2, val: vtime2);
449
450 d2l_write(i2c: tc->i2c, VFUEN, VFUEN_EN);
451 d2l_write(i2c: tc->i2c, SYSRST, SYS_RST_LCD);
452 d2l_write(i2c: tc->i2c, LVPHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_ND(6));
453
454 dev_dbg(tc->dev, "bus_formats %04x bpc %d\n",
455 connector->display_info.bus_formats[0],
456 tc->bpc);
457 /*
458 * Default hardware register settings of tc358775 configured
459 * with MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA jeida-24 format
460 */
461 if (connector->display_info.bus_formats[0] ==
462 MEDIA_BUS_FMT_RGB888_1X7X4_SPWG) {
463 /* VESA-24 */
464 d2l_write(i2c: tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));
465 d2l_write(i2c: tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0));
466 d2l_write(i2c: tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7));
467 d2l_write(i2c: tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));
468 d2l_write(i2c: tc->i2c, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2));
469 d2l_write(i2c: tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));
470 d2l_write(i2c: tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6));
471 } else { /* MEDIA_BUS_FMT_RGB666_1X7X3_SPWG - JEIDA-18 */
472 d2l_write(i2c: tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));
473 d2l_write(i2c: tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_L0, LVI_R5, LVI_G0));
474 d2l_write(i2c: tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_L0, LVI_L0));
475 d2l_write(i2c: tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));
476 d2l_write(i2c: tc->i2c, LV_MX1619, LV_MX(LVI_L0, LVI_L0, LVI_B1, LVI_B2));
477 d2l_write(i2c: tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));
478 d2l_write(i2c: tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_L0));
479 }
480
481 d2l_write(i2c: tc->i2c, VFUEN, VFUEN_EN);
482
483 val = LVCFG_LVEN_BIT;
484 if (tc->lvds_link == DUAL_LINK) {
485 val |= TC358775_LVCFG_LVDLINK(val: 1);
486 val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_6);
487 } else {
488 val |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_3);
489 }
490 d2l_write(i2c: tc->i2c, LVCFG, val);
491}
492
493static enum drm_mode_status
494tc_mode_valid(struct drm_bridge *bridge,
495 const struct drm_display_info *info,
496 const struct drm_display_mode *mode)
497{
498 struct tc_data *tc = bridge_to_tc(b: bridge);
499
500 /*
501 * Maximum pixel clock speed 135MHz for single-link
502 * 270MHz for dual-link
503 */
504 if ((mode->clock > 135000 && tc->lvds_link == SINGLE_LINK) ||
505 (mode->clock > 270000 && tc->lvds_link == DUAL_LINK))
506 return MODE_CLOCK_HIGH;
507
508 switch (info->bus_formats[0]) {
509 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
510 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
511 /* RGB888 */
512 tc->bpc = 8;
513 break;
514 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
515 /* RGB666 */
516 tc->bpc = 6;
517 break;
518 default:
519 dev_warn(tc->dev,
520 "unsupported LVDS bus format 0x%04x\n",
521 info->bus_formats[0]);
522 return MODE_NOMODE;
523 }
524
525 return MODE_OK;
526}
527
528static int tc358775_parse_dt(struct device_node *np, struct tc_data *tc)
529{
530 struct device_node *endpoint;
531 struct device_node *parent;
532 struct device_node *remote;
533 int dsi_lanes = -1;
534
535 /*
536 * To get the data-lanes of dsi, we need to access the dsi0_out of port1
537 * of dsi0 endpoint from bridge port0 of d2l_in
538 */
539 endpoint = of_graph_get_endpoint_by_regs(parent: tc->dev->of_node,
540 port_reg: TC358775_DSI_IN, reg: -1);
541 if (endpoint) {
542 /* dsi0_out node */
543 parent = of_graph_get_remote_port_parent(node: endpoint);
544 of_node_put(node: endpoint);
545 if (parent) {
546 /* dsi0 port 1 */
547 dsi_lanes = drm_of_get_data_lanes_count_ep(port: parent, port_reg: 1, reg: -1, min: 1, max: 4);
548 of_node_put(node: parent);
549 }
550 }
551
552 if (dsi_lanes < 0)
553 return dsi_lanes;
554
555 tc->num_dsi_lanes = dsi_lanes;
556
557 tc->host_node = of_graph_get_remote_node(node: np, port: 0, endpoint: 0);
558 if (!tc->host_node)
559 return -ENODEV;
560
561 of_node_put(node: tc->host_node);
562
563 tc->lvds_link = SINGLE_LINK;
564 endpoint = of_graph_get_endpoint_by_regs(parent: tc->dev->of_node,
565 port_reg: TC358775_LVDS_OUT1, reg: -1);
566 if (endpoint) {
567 remote = of_graph_get_remote_port_parent(node: endpoint);
568 of_node_put(node: endpoint);
569
570 if (remote) {
571 if (of_device_is_available(device: remote))
572 tc->lvds_link = DUAL_LINK;
573 of_node_put(node: remote);
574 }
575 }
576
577 dev_dbg(tc->dev, "no.of dsi lanes: %d\n", tc->num_dsi_lanes);
578 dev_dbg(tc->dev, "operating in %d-link mode\n", tc->lvds_link);
579
580 return 0;
581}
582
583static int tc_bridge_attach(struct drm_bridge *bridge,
584 enum drm_bridge_attach_flags flags)
585{
586 struct tc_data *tc = bridge_to_tc(b: bridge);
587
588 /* Attach the panel-bridge to the dsi bridge */
589 return drm_bridge_attach(encoder: bridge->encoder, bridge: tc->panel_bridge,
590 previous: &tc->bridge, flags);
591}
592
593static const struct drm_bridge_funcs tc_bridge_funcs = {
594 .attach = tc_bridge_attach,
595 .pre_enable = tc_bridge_pre_enable,
596 .enable = tc_bridge_enable,
597 .mode_valid = tc_mode_valid,
598 .post_disable = tc_bridge_post_disable,
599};
600
601static int tc_attach_host(struct tc_data *tc)
602{
603 struct device *dev = &tc->i2c->dev;
604 struct mipi_dsi_host *host;
605 struct mipi_dsi_device *dsi;
606 int ret;
607 const struct mipi_dsi_device_info info = { .type = "tc358775",
608 .channel = 0,
609 .node = NULL,
610 };
611
612 host = of_find_mipi_dsi_host_by_node(node: tc->host_node);
613 if (!host) {
614 dev_err(dev, "failed to find dsi host\n");
615 return -EPROBE_DEFER;
616 }
617
618 dsi = devm_mipi_dsi_device_register_full(dev, host, info: &info);
619 if (IS_ERR(ptr: dsi)) {
620 dev_err(dev, "failed to create dsi device\n");
621 return PTR_ERR(ptr: dsi);
622 }
623
624 tc->dsi = dsi;
625
626 dsi->lanes = tc->num_dsi_lanes;
627 dsi->format = MIPI_DSI_FMT_RGB888;
628 dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
629
630 ret = devm_mipi_dsi_attach(dev, dsi);
631 if (ret < 0) {
632 dev_err(dev, "failed to attach dsi to host\n");
633 return ret;
634 }
635
636 return 0;
637}
638
639static int tc_probe(struct i2c_client *client)
640{
641 struct device *dev = &client->dev;
642 struct tc_data *tc;
643 int ret;
644
645 tc = devm_kzalloc(dev, size: sizeof(*tc), GFP_KERNEL);
646 if (!tc)
647 return -ENOMEM;
648
649 tc->dev = dev;
650 tc->i2c = client;
651
652 tc->panel_bridge = devm_drm_of_get_bridge(dev, node: dev->of_node,
653 port: TC358775_LVDS_OUT0, endpoint: 0);
654 if (IS_ERR(ptr: tc->panel_bridge))
655 return PTR_ERR(ptr: tc->panel_bridge);
656
657 ret = tc358775_parse_dt(np: dev->of_node, tc);
658 if (ret)
659 return ret;
660
661 tc->vddio = devm_regulator_get(dev, id: "vddio-supply");
662 if (IS_ERR(ptr: tc->vddio)) {
663 ret = PTR_ERR(ptr: tc->vddio);
664 dev_err(dev, "vddio-supply not found\n");
665 return ret;
666 }
667
668 tc->vdd = devm_regulator_get(dev, id: "vdd-supply");
669 if (IS_ERR(ptr: tc->vdd)) {
670 ret = PTR_ERR(ptr: tc->vdd);
671 dev_err(dev, "vdd-supply not found\n");
672 return ret;
673 }
674
675 tc->stby_gpio = devm_gpiod_get(dev, con_id: "stby", flags: GPIOD_OUT_HIGH);
676 if (IS_ERR(ptr: tc->stby_gpio)) {
677 ret = PTR_ERR(ptr: tc->stby_gpio);
678 dev_err(dev, "cannot get stby-gpio %d\n", ret);
679 return ret;
680 }
681
682 tc->reset_gpio = devm_gpiod_get(dev, con_id: "reset", flags: GPIOD_OUT_HIGH);
683 if (IS_ERR(ptr: tc->reset_gpio)) {
684 ret = PTR_ERR(ptr: tc->reset_gpio);
685 dev_err(dev, "cannot get reset-gpios %d\n", ret);
686 return ret;
687 }
688
689 tc->bridge.funcs = &tc_bridge_funcs;
690 tc->bridge.of_node = dev->of_node;
691 drm_bridge_add(bridge: &tc->bridge);
692
693 i2c_set_clientdata(client, data: tc);
694
695 ret = tc_attach_host(tc);
696 if (ret)
697 goto err_bridge_remove;
698
699 return 0;
700
701err_bridge_remove:
702 drm_bridge_remove(bridge: &tc->bridge);
703 return ret;
704}
705
706static void tc_remove(struct i2c_client *client)
707{
708 struct tc_data *tc = i2c_get_clientdata(client);
709
710 drm_bridge_remove(bridge: &tc->bridge);
711}
712
713static const struct i2c_device_id tc358775_i2c_ids[] = {
714 { "tc358775", 0 },
715 { }
716};
717MODULE_DEVICE_TABLE(i2c, tc358775_i2c_ids);
718
719static const struct of_device_id tc358775_of_ids[] = {
720 { .compatible = "toshiba,tc358775", },
721 { }
722};
723MODULE_DEVICE_TABLE(of, tc358775_of_ids);
724
725static struct i2c_driver tc358775_driver = {
726 .driver = {
727 .name = "tc358775",
728 .of_match_table = tc358775_of_ids,
729 },
730 .id_table = tc358775_i2c_ids,
731 .probe = tc_probe,
732 .remove = tc_remove,
733};
734module_i2c_driver(tc358775_driver);
735
736MODULE_AUTHOR("Vinay Simha BN <simhavcs@gmail.com>");
737MODULE_DESCRIPTION("TC358775 DSI/LVDS bridge driver");
738MODULE_LICENSE("GPL v2");
739

source code of linux/drivers/gpu/drm/bridge/tc358775.c