1	/*
2	* Copyright © 2009 Keith Packard
3	*
4	* Permission to use, copy, modify, distribute, and sell this software and its
5	* documentation for any purpose is hereby granted without fee, provided that
6	* the above copyright notice appear in all copies and that both that copyright
7	* notice and this permission notice appear in supporting documentation, and
8	* that the name of the copyright holders not be used in advertising or
9	* publicity pertaining to distribution of the software without specific,
10	* written prior permission. The copyright holders make no representations
11	* about the suitability of this software for any purpose. It is provided "as
12	* is" without express or implied warranty.
13	*
14	* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15	* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16	* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17	* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18	* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19	* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20	* OF THIS SOFTWARE.
21	*/
22
23	#include <linux/backlight.h>
24	#include <linux/delay.h>
25	#include <linux/dynamic_debug.h>
26	#include <linux/errno.h>
27	#include <linux/i2c.h>
28	#include <linux/init.h>
29	#include <linux/iopoll.h>
30	#include <linux/kernel.h>
31	#include <linux/module.h>
32	#include <linux/sched.h>
33	#include <linux/seq_file.h>
34	#include <linux/string_helpers.h>
35
36	#include <drm/display/drm_dp_helper.h>
37	#include <drm/display/drm_dp_mst_helper.h>
38	#include <drm/drm_edid.h>
39	#include <drm/drm_fixed.h>
40	#include <drm/drm_print.h>
41	#include <drm/drm_vblank.h>
42	#include <drm/drm_panel.h>
43
44	#include "drm_dp_helper_internal.h"
45
46	DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
47	"DRM_UT_CORE",
48	"DRM_UT_DRIVER",
49	"DRM_UT_KMS",
50	"DRM_UT_PRIME",
51	"DRM_UT_ATOMIC",
52	"DRM_UT_VBL",
53	"DRM_UT_STATE",
54	"DRM_UT_LEASE",
55	"DRM_UT_DP",
56	"DRM_UT_DRMRES");
57
58	struct dp_aux_backlight {
59	struct backlight_device *base;
60	struct drm_dp_aux *aux;
61	struct drm_edp_backlight_info info;
62	bool enabled;
63	};
64
65	/**
66	* DOC: dp helpers
67	*
68	* These functions contain some common logic and helpers at various abstraction
69	* levels to deal with Display Port sink devices and related things like DP aux
70	* channel transfers, EDID reading over DP aux channels, decoding certain DPCD
71	* blocks, ...
72	*/
73
74	/* Helpers for DP link training */
75	static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
76	{
77	return link_status[r - DP_LANE0_1_STATUS];
78	}
79
80	static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
81	int lane)
82	{
83	int i = DP_LANE0_1_STATUS + (lane >> 1);
84	int s = (lane & 1) * 4;
85	u8 l = dp_link_status(link_status, r: i);
86
87	return (l >> s) & 0xf;
88	}
89
90	bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
91	int lane_count)
92	{
93	u8 lane_align;
94	u8 lane_status;
95	int lane;
96
97	lane_align = dp_link_status(link_status,
98	DP_LANE_ALIGN_STATUS_UPDATED);
99	if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
100	return false;
101	for (lane = 0; lane < lane_count; lane++) {
102	lane_status = dp_get_lane_status(link_status, lane);
103	if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
104	return false;
105	}
106	return true;
107	}
108	EXPORT_SYMBOL(drm_dp_channel_eq_ok);
109
110	bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
111	int lane_count)
112	{
113	int lane;
114	u8 lane_status;
115
116	for (lane = 0; lane < lane_count; lane++) {
117	lane_status = dp_get_lane_status(link_status, lane);
118	if ((lane_status & DP_LANE_CR_DONE) == 0)
119	return false;
120	}
121	return true;
122	}
123	EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
124
125	u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
126	int lane)
127	{
128	int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
129	int s = ((lane & 1) ?
130	DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
131	DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
132	u8 l = dp_link_status(link_status, r: i);
133
134	return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
135	}
136	EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
137
138	u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
139	int lane)
140	{
141	int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
142	int s = ((lane & 1) ?
143	DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
144	DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
145	u8 l = dp_link_status(link_status, r: i);
146
147	return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
148	}
149	EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
150
151	/* DP 2.0 128b/132b */
152	u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
153	int lane)
154	{
155	int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
156	int s = ((lane & 1) ?
157	DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT :
158	DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT);
159	u8 l = dp_link_status(link_status, r: i);
160
161	return (l >> s) & 0xf;
162	}
163	EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset);
164
165	/* DP 2.0 errata for 128b/132b */
166	bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
167	int lane_count)
168	{
169	u8 lane_align, lane_status;
170	int lane;
171
172	lane_align = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
173	if (!(lane_align & DP_INTERLANE_ALIGN_DONE))
174	return false;
175
176	for (lane = 0; lane < lane_count; lane++) {
177	lane_status = dp_get_lane_status(link_status, lane);
178	if (!(lane_status & DP_LANE_CHANNEL_EQ_DONE))
179	return false;
180	}
181	return true;
182	}
183	EXPORT_SYMBOL(drm_dp_128b132b_lane_channel_eq_done);
184
185	/* DP 2.0 errata for 128b/132b */
186	bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
187	int lane_count)
188	{
189	u8 lane_status;
190	int lane;
191
192	for (lane = 0; lane < lane_count; lane++) {
193	lane_status = dp_get_lane_status(link_status, lane);
194	if (!(lane_status & DP_LANE_SYMBOL_LOCKED))
195	return false;
196	}
197	return true;
198	}
199	EXPORT_SYMBOL(drm_dp_128b132b_lane_symbol_locked);
200
201	/* DP 2.0 errata for 128b/132b */
202	bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])
203	{
204	u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
205
206	return status & DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE;
207	}
208	EXPORT_SYMBOL(drm_dp_128b132b_eq_interlane_align_done);
209
210	/* DP 2.0 errata for 128b/132b */
211	bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])
212	{
213	u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
214
215	return status & DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE;
216	}
217	EXPORT_SYMBOL(drm_dp_128b132b_cds_interlane_align_done);
218
219	/* DP 2.0 errata for 128b/132b */
220	bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE])
221	{
222	u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
223
224	return status & DP_128B132B_LT_FAILED;
225	}
226	EXPORT_SYMBOL(drm_dp_128b132b_link_training_failed);
227
228	static int __8b10b_clock_recovery_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
229	{
230	if (rd_interval > 4)
231	drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n",
232	aux->name, rd_interval);
233
234	if (rd_interval == 0)
235	return 100;
236
237	return rd_interval * 4 * USEC_PER_MSEC;
238	}
239
240	static int __8b10b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
241	{
242	if (rd_interval > 4)
243	drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n",
244	aux->name, rd_interval);
245
246	if (rd_interval == 0)
247	return 400;
248
249	return rd_interval * 4 * USEC_PER_MSEC;
250	}
251
252	static int __128b132b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
253	{
254	switch (rd_interval) {
255	default:
256	drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n",
257	aux->name, rd_interval);
258	fallthrough;
259	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US:
260	return 400;
261	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS:
262	return 4000;
263	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS:
264	return 8000;
265	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS:
266	return 12000;
267	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS:
268	return 16000;
269	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS:
270	return 32000;
271	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS:
272	return 64000;
273	}
274	}
275
276	/*
277	* The link training delays are different for:
278	*
279	* - Clock recovery vs. channel equalization
280	* - DPRX vs. LTTPR
281	* - 128b/132b vs. 8b/10b
282	* - DPCD rev 1.3 vs. later
283	*
284	* Get the correct delay in us, reading DPCD if necessary.
285	*/
286	static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
287	enum drm_dp_phy dp_phy, bool uhbr, bool cr)
288	{
289	int (*parse)(const struct drm_dp_aux *aux, u8 rd_interval);
290	unsigned int offset;
291	u8 rd_interval, mask;
292
293	if (dp_phy == DP_PHY_DPRX) {
294	if (uhbr) {
295	if (cr)
296	return 100;
297
298	offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL;
299	mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
300	parse = __128b132b_channel_eq_delay_us;
301	} else {
302	if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
303	return 100;
304
305	offset = DP_TRAINING_AUX_RD_INTERVAL;
306	mask = DP_TRAINING_AUX_RD_MASK;
307	if (cr)
308	parse = __8b10b_clock_recovery_delay_us;
309	else
310	parse = __8b10b_channel_eq_delay_us;
311	}
312	} else {
313	if (uhbr) {
314	offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy);
315	mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
316	parse = __128b132b_channel_eq_delay_us;
317	} else {
318	if (cr)
319	return 100;
320
321	offset = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy);
322	mask = DP_TRAINING_AUX_RD_MASK;
323	parse = __8b10b_channel_eq_delay_us;
324	}
325	}
326
327	if (offset < DP_RECEIVER_CAP_SIZE) {
328	rd_interval = dpcd[offset];
329	} else {
330	if (drm_dp_dpcd_read_byte(aux, offset, valuep: &rd_interval) < 0) {
331	drm_dbg_kms(aux->drm_dev, "%s: failed rd interval read\n",
332	aux->name);
333	/* arbitrary default delay */
334	return 400;
335	}
336	}
337
338	return parse(aux, rd_interval & mask);
339	}
340
341	int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
342	enum drm_dp_phy dp_phy, bool uhbr)
343	{
344	return __read_delay(aux, dpcd, dp_phy, uhbr, cr: true);
345	}
346	EXPORT_SYMBOL(drm_dp_read_clock_recovery_delay);
347
348	int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
349	enum drm_dp_phy dp_phy, bool uhbr)
350	{
351	return __read_delay(aux, dpcd, dp_phy, uhbr, cr: false);
352	}
353	EXPORT_SYMBOL(drm_dp_read_channel_eq_delay);
354
355	/* Per DP 2.0 Errata */
356	int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux)
357	{
358	int unit;
359	u8 val;
360
361	if (drm_dp_dpcd_read_byte(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, valuep: &val) < 0) {
362	drm_err(aux->drm_dev, "%s: failed rd interval read\n",
363	aux->name);
364	/* default to max */
365	val = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
366	}
367
368	unit = (val & DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT) ? 1 : 2;
369	val &= DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
370
371	return (val + 1) * unit * 1000;
372	}
373	EXPORT_SYMBOL(drm_dp_128b132b_read_aux_rd_interval);
374
375	void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
376	const u8 dpcd[DP_RECEIVER_CAP_SIZE])
377	{
378	u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
379	DP_TRAINING_AUX_RD_MASK;
380	int delay_us;
381
382	if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
383	delay_us = 100;
384	else
385	delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval);
386
387	usleep_range(min: delay_us, max: delay_us * 2);
388	}
389	EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
390
391	static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
392	u8 rd_interval)
393	{
394	int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval);
395
396	usleep_range(min: delay_us, max: delay_us * 2);
397	}
398
399	void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
400	const u8 dpcd[DP_RECEIVER_CAP_SIZE])
401	{
402	__drm_dp_link_train_channel_eq_delay(aux,
403	rd_interval: dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
404	DP_TRAINING_AUX_RD_MASK);
405	}
406	EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
407
408	/**
409	* drm_dp_phy_name() - Get the name of the given DP PHY
410	* @dp_phy: The DP PHY identifier
411	*
412	* Given the @dp_phy, get a user friendly name of the DP PHY, either "DPRX" or
413	* "LTTPR <N>", or "<INVALID DP PHY>" on errors. The returned string is always
414	* non-NULL and valid.
415	*
416	* Returns: Name of the DP PHY.
417	*/
418	const char *drm_dp_phy_name(enum drm_dp_phy dp_phy)
419	{
420	static const char * const phy_names[] = {
421	[DP_PHY_DPRX] = "DPRX",
422	[DP_PHY_LTTPR1] = "LTTPR 1",
423	[DP_PHY_LTTPR2] = "LTTPR 2",
424	[DP_PHY_LTTPR3] = "LTTPR 3",
425	[DP_PHY_LTTPR4] = "LTTPR 4",
426	[DP_PHY_LTTPR5] = "LTTPR 5",
427	[DP_PHY_LTTPR6] = "LTTPR 6",
428	[DP_PHY_LTTPR7] = "LTTPR 7",
429	[DP_PHY_LTTPR8] = "LTTPR 8",
430	};
431
432	if (dp_phy < 0 || dp_phy >= ARRAY_SIZE(phy_names) ||
433	WARN_ON(!phy_names[dp_phy]))
434	return "<INVALID DP PHY>";
435
436	return phy_names[dp_phy];
437	}
438	EXPORT_SYMBOL(drm_dp_phy_name);
439
440	void drm_dp_lttpr_link_train_clock_recovery_delay(void)
441	{
442	usleep_range(min: 100, max: 200);
443	}
444	EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay);
445
446	static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r)
447	{
448	return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1];
449	}
450
451	void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
452	const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE])
453	{
454	u8 interval = dp_lttpr_phy_cap(phy_cap,
455	DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) &
456	DP_TRAINING_AUX_RD_MASK;
457
458	__drm_dp_link_train_channel_eq_delay(aux, rd_interval: interval);
459	}
460	EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
461
462	/**
463	* drm_dp_lttpr_wake_timeout_setup() - Grant extended time for sink to wake up
464	* @aux: The DP AUX channel to use
465	* @transparent_mode: This is true if lttpr is in transparent mode
466	*
467	* This function checks if the sink needs any extended wake time, if it does
468	* it grants this request. Post this setup the source device can keep trying
469	* the Aux transaction till the granted wake timeout.
470	* If this function is not called all Aux transactions are expected to take
471	* a default of 1ms before they throw an error.
472	*/
473	void drm_dp_lttpr_wake_timeout_setup(struct drm_dp_aux *aux, bool transparent_mode)
474	{
475	u8 val = 1;
476	int ret;
477
478	if (transparent_mode) {
479	static const u8 timeout_mapping[] = {
480	[DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_1_MS] = 1,
481	[DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_20_MS] = 20,
482	[DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_40_MS] = 40,
483	[DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_60_MS] = 60,
484	[DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_80_MS] = 80,
485	[DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_100_MS] = 100,
486	};
487
488	ret = drm_dp_dpcd_readb(aux, DP_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_REQUEST, valuep: &val);
489	if (ret != 1) {
490	drm_dbg_kms(aux->drm_dev,
491	"Failed to read Extended sleep wake timeout request\n");
492	return;
493	}
494
495	val = (val < sizeof(timeout_mapping) && timeout_mapping[val]) ?
496	timeout_mapping[val] : 1;
497
498	if (val > 1)
499	drm_dp_dpcd_writeb(aux,
500	DP_EXTENDED_DPRX_SLEEP_WAKE_TIMEOUT_GRANT,
501	DP_DPRX_SLEEP_WAKE_TIMEOUT_PERIOD_GRANTED);
502	} else {
503	ret = drm_dp_dpcd_readb(aux, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT, valuep: &val);
504	if (ret != 1) {
505	drm_dbg_kms(aux->drm_dev,
506	"Failed to read Extended sleep wake timeout request\n");
507	return;
508	}
509
510	val = (val & DP_EXTENDED_WAKE_TIMEOUT_REQUEST_MASK) ?
511	(val & DP_EXTENDED_WAKE_TIMEOUT_REQUEST_MASK) * 10 : 1;
512
513	if (val > 1)
514	drm_dp_dpcd_writeb(aux, DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT,
515	DP_EXTENDED_WAKE_TIMEOUT_GRANT);
516	}
517	}
518	EXPORT_SYMBOL(drm_dp_lttpr_wake_timeout_setup);
519
520	u8 drm_dp_link_rate_to_bw_code(int link_rate)
521	{
522	switch (link_rate) {
523	case 1000000:
524	return DP_LINK_BW_10;
525	case 1350000:
526	return DP_LINK_BW_13_5;
527	case 2000000:
528	return DP_LINK_BW_20;
529	default:
530	/* Spec says link_bw = link_rate / 0.27Gbps */
531	return link_rate / 27000;
532	}
533	}
534	EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
535
536	int drm_dp_bw_code_to_link_rate(u8 link_bw)
537	{
538	switch (link_bw) {
539	case DP_LINK_BW_10:
540	return 1000000;
541	case DP_LINK_BW_13_5:
542	return 1350000;
543	case DP_LINK_BW_20:
544	return 2000000;
545	default:
546	/* Spec says link_rate = link_bw * 0.27Gbps */
547	return link_bw * 27000;
548	}
549	}
550	EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
551
552	#define AUX_RETRY_INTERVAL 500 /* us */
553
554	static inline void
555	drm_dp_dump_access(const struct drm_dp_aux *aux,
556	u8 request, uint offset, void *buffer, int ret)
557	{
558	const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-";
559
560	if (ret > 0)
561	drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
562	aux->name, offset, arrow, ret, min(ret, 20), buffer);
563	else
564	drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n",
565	aux->name, offset, arrow, ret);
566	}
567
568	/**
569	* DOC: dp helpers
570	*
571	* The DisplayPort AUX channel is an abstraction to allow generic, driver-
572	* independent access to AUX functionality. Drivers can take advantage of
573	* this by filling in the fields of the drm_dp_aux structure.
574	*
575	* Transactions are described using a hardware-independent drm_dp_aux_msg
576	* structure, which is passed into a driver's .transfer() implementation.
577	* Both native and I2C-over-AUX transactions are supported.
578	*/
579
580	static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
581	unsigned int offset, void *buffer, size_t size)
582	{
583	struct drm_dp_aux_msg msg;
584	unsigned int retry, native_reply;
585	int err = 0, ret = 0;
586
587	memset(&msg, 0, sizeof(msg));
588	msg.address = offset;
589	msg.request = request;
590	msg.buffer = buffer;
591	msg.size = size;
592
593	mutex_lock(&aux->hw_mutex);
594
595	/*
596	* If the device attached to the aux bus is powered down then there's
597	* no reason to attempt a transfer. Error out immediately.
598	*/
599	if (aux->powered_down) {
600	ret = -EBUSY;
601	goto unlock;
602	}
603
604	/*
605	* The specification doesn't give any recommendation on how often to
606	* retry native transactions. We used to retry 7 times like for
607	* aux i2c transactions but real world devices this wasn't
608	* sufficient, bump to 32 which makes Dell 4k monitors happier.
609	*/
610	for (retry = 0; retry < 32; retry++) {
611	if (ret != 0 && ret != -ETIMEDOUT) {
612	usleep_range(AUX_RETRY_INTERVAL,
613	AUX_RETRY_INTERVAL + 100);
614	}
615
616	ret = aux->transfer(aux, &msg);
617	if (ret >= 0) {
618	native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
619	if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
620	if (ret == size)
621	goto unlock;
622
623	ret = -EPROTO;
624	} else
625	ret = -EIO;
626	}
627
628	/*
629	* We want the error we return to be the error we received on
630	* the first transaction, since we may get a different error the
631	* next time we retry
632	*/
633	if (!err)
634	err = ret;
635	}
636
637	drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First error: %d\n",
638	aux->name, err);
639	ret = err;
640
641	unlock:
642	mutex_unlock(lock: &aux->hw_mutex);
643	return ret;
644	}
645
646	/**
647	* drm_dp_dpcd_probe() - probe a given DPCD address with a 1-byte read access
648	* @aux: DisplayPort AUX channel (SST)
649	* @offset: address of the register to probe
650	*
651	* Probe the provided DPCD address by reading 1 byte from it. The function can
652	* be used to trigger some side-effect the read access has, like waking up the
653	* sink, without the need for the read-out value.
654	*
655	* Returns 0 if the read access suceeded, or a negative error code on failure.
656	*/
657	int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset)
658	{
659	u8 buffer;
660	int ret;
661
662	ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, buffer: &buffer, size: 1);
663	WARN_ON(ret == 0);
664
665	drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer: &buffer, ret);
666
667	return ret < 0 ? ret : 0;
668	}
669	EXPORT_SYMBOL(drm_dp_dpcd_probe);
670
671	/**
672	* drm_dp_dpcd_set_powered() - Set whether the DP device is powered
673	* @aux: DisplayPort AUX channel; for convenience it's OK to pass NULL here
674	* and the function will be a no-op.
675	* @powered: true if powered; false if not
676	*
677	* If the endpoint device on the DP AUX bus is known to be powered down
678	* then this function can be called to make future transfers fail immediately
679	* instead of needing to time out.
680	*
681	* If this function is never called then a device defaults to being powered.
682	*/
683	void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered)
684	{
685	if (!aux)
686	return;
687
688	mutex_lock(&aux->hw_mutex);
689	aux->powered_down = !powered;
690	mutex_unlock(lock: &aux->hw_mutex);
691	}
692	EXPORT_SYMBOL(drm_dp_dpcd_set_powered);
693
694	/**
695	* drm_dp_dpcd_read() - read a series of bytes from the DPCD
696	* @aux: DisplayPort AUX channel (SST or MST)
697	* @offset: address of the (first) register to read
698	* @buffer: buffer to store the register values
699	* @size: number of bytes in @buffer
700	*
701	* Returns the number of bytes transferred on success, or a negative error
702	* code on failure. -EIO is returned if the request was NAKed by the sink or
703	* if the retry count was exceeded. If not all bytes were transferred, this
704	* function returns -EPROTO. Errors from the underlying AUX channel transfer
705	* function, with the exception of -EBUSY (which causes the transaction to
706	* be retried), are propagated to the caller.
707	*
708	* In most of the cases you want to use drm_dp_dpcd_read_data() instead.
709	*/
710	ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
711	void *buffer, size_t size)
712	{
713	int ret;
714
715	/*
716	* HP ZR24w corrupts the first DPCD access after entering power save
717	* mode. Eg. on a read, the entire buffer will be filled with the same
718	* byte. Do a throw away read to avoid corrupting anything we care
719	* about. Afterwards things will work correctly until the monitor
720	* gets woken up and subsequently re-enters power save mode.
721	*
722	* The user pressing any button on the monitor is enough to wake it
723	* up, so there is no particularly good place to do the workaround.
724	* We just have to do it before any DPCD access and hope that the
725	* monitor doesn't power down exactly after the throw away read.
726	*/
727	if (!aux->is_remote) {
728	ret = drm_dp_dpcd_probe(aux, DP_DPCD_REV);
729	if (ret < 0)
730	return ret;
731	}
732
733	if (aux->is_remote)
734	ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size);
735	else
736	ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset,
737	buffer, size);
738
739	drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret);
740	return ret;
741	}
742	EXPORT_SYMBOL(drm_dp_dpcd_read);
743
744	/**
745	* drm_dp_dpcd_write() - write a series of bytes to the DPCD
746	* @aux: DisplayPort AUX channel (SST or MST)
747	* @offset: address of the (first) register to write
748	* @buffer: buffer containing the values to write
749	* @size: number of bytes in @buffer
750	*
751	* Returns the number of bytes transferred on success, or a negative error
752	* code on failure. -EIO is returned if the request was NAKed by the sink or
753	* if the retry count was exceeded. If not all bytes were transferred, this
754	* function returns -EPROTO. Errors from the underlying AUX channel transfer
755	* function, with the exception of -EBUSY (which causes the transaction to
756	* be retried), are propagated to the caller.
757	*
758	* In most of the cases you want to use drm_dp_dpcd_write_data() instead.
759	*/
760	ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
761	void *buffer, size_t size)
762	{
763	int ret;
764
765	if (aux->is_remote)
766	ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size);
767	else
768	ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset,
769	buffer, size);
770
771	drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
772	return ret;
773	}
774	EXPORT_SYMBOL(drm_dp_dpcd_write);
775
776	/**
777	* drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
778	* @aux: DisplayPort AUX channel
779	* @status: buffer to store the link status in (must be at least 6 bytes)
780	*
781	* Returns a negative error code on failure or 0 on success.
782	*/
783	int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
784	u8 status[DP_LINK_STATUS_SIZE])
785	{
786	return drm_dp_dpcd_read_data(aux, DP_LANE0_1_STATUS, buffer: status,
787	DP_LINK_STATUS_SIZE);
788	}
789	EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
790
791	/**
792	* drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY
793	* @aux: DisplayPort AUX channel
794	* @dp_phy: the DP PHY to get the link status for
795	* @link_status: buffer to return the status in
796	*
797	* Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The
798	* layout of the returned @link_status matches the DPCD register layout of the
799	* DPRX PHY link status.
800	*
801	* Returns 0 if the information was read successfully or a negative error code
802	* on failure.
803	*/
804	int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
805	enum drm_dp_phy dp_phy,
806	u8 link_status[DP_LINK_STATUS_SIZE])
807	{
808	int ret;
809
810	if (dp_phy == DP_PHY_DPRX)
811	return drm_dp_dpcd_read_data(aux,
812	DP_LANE0_1_STATUS,
813	buffer: link_status,
814	DP_LINK_STATUS_SIZE);
815
816	ret = drm_dp_dpcd_read_data(aux,
817	DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy),
818	buffer: link_status,
819	DP_LINK_STATUS_SIZE - 1);
820
821	if (ret < 0)
822	return ret;
823
824	/* Convert the LTTPR to the sink PHY link status layout */
825	memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1],
826	&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS],
827	DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1);
828	link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0;
829
830	return 0;
831	}
832	EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status);
833
834	/**
835	* drm_dp_link_power_up() - power up a DisplayPort link
836	* @aux: DisplayPort AUX channel
837	* @revision: DPCD revision supported on the link
838	*
839	* Returns 0 on success or a negative error code on failure.
840	*/
841	int drm_dp_link_power_up(struct drm_dp_aux *aux, unsigned char revision)
842	{
843	u8 value;
844	int err;
845
846	/* DP_SET_POWER register is only available on DPCD v1.1 and later */
847	if (revision < DP_DPCD_REV_11)
848	return 0;
849
850	err = drm_dp_dpcd_readb(aux, DP_SET_POWER, valuep: &value);
851	if (err < 0)
852	return err;
853
854	value &= ~DP_SET_POWER_MASK;
855	value |= DP_SET_POWER_D0;
856
857	err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
858	if (err < 0)
859	return err;
860
861	/*
862	* According to the DP 1.1 specification, a "Sink Device must exit the
863	* power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
864	* Control Field" (register 0x600).
865	*/
866	usleep_range(min: 1000, max: 2000);
867
868	return 0;
869	}
870	EXPORT_SYMBOL(drm_dp_link_power_up);
871
872	/**
873	* drm_dp_link_power_down() - power down a DisplayPort link
874	* @aux: DisplayPort AUX channel
875	* @revision: DPCD revision supported on the link
876	*
877	* Returns 0 on success or a negative error code on failure.
878	*/
879	int drm_dp_link_power_down(struct drm_dp_aux *aux, unsigned char revision)
880	{
881	u8 value;
882	int err;
883
884	/* DP_SET_POWER register is only available on DPCD v1.1 and later */
885	if (revision < DP_DPCD_REV_11)
886	return 0;
887
888	err = drm_dp_dpcd_readb(aux, DP_SET_POWER, valuep: &value);
889	if (err < 0)
890	return err;
891
892	value &= ~DP_SET_POWER_MASK;
893	value |= DP_SET_POWER_D3;
894
895	err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
896	if (err < 0)
897	return err;
898
899	return 0;
900	}
901	EXPORT_SYMBOL(drm_dp_link_power_down);
902
903	static int read_payload_update_status(struct drm_dp_aux *aux)
904	{
905	int ret;
906	u8 status;
907
908	ret = drm_dp_dpcd_read_byte(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, valuep: &status);
909	if (ret < 0)
910	return ret;
911
912	return status;
913	}
914
915	/**
916	* drm_dp_dpcd_write_payload() - Write Virtual Channel information to payload table
917	* @aux: DisplayPort AUX channel
918	* @vcpid: Virtual Channel Payload ID
919	* @start_time_slot: Starting time slot
920	* @time_slot_count: Time slot count
921	*
922	* Write the Virtual Channel payload allocation table, checking the payload
923	* update status and retrying as necessary.
924	*
925	* Returns:
926	* 0 on success, negative error otherwise
927	*/
928	int drm_dp_dpcd_write_payload(struct drm_dp_aux *aux,
929	int vcpid, u8 start_time_slot, u8 time_slot_count)
930	{
931	u8 payload_alloc[3], status;
932	int ret;
933	int retries = 0;
934
935	drm_dp_dpcd_write_byte(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS,
936	DP_PAYLOAD_TABLE_UPDATED);
937
938	payload_alloc[0] = vcpid;
939	payload_alloc[1] = start_time_slot;
940	payload_alloc[2] = time_slot_count;
941
942	ret = drm_dp_dpcd_write_data(aux, DP_PAYLOAD_ALLOCATE_SET, buffer: payload_alloc, size: 3);
943	if (ret < 0) {
944	drm_dbg_kms(aux->drm_dev, "failed to write payload allocation %d\n", ret);
945	goto fail;
946	}
947
948	retry:
949	ret = drm_dp_dpcd_read_byte(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, valuep: &status);
950	if (ret < 0) {
951	drm_dbg_kms(aux->drm_dev, "failed to read payload table status %d\n", ret);
952	goto fail;
953	}
954
955	if (!(status & DP_PAYLOAD_TABLE_UPDATED)) {
956	retries++;
957	if (retries < 20) {
958	usleep_range(min: 10000, max: 20000);
959	goto retry;
960	}
961	drm_dbg_kms(aux->drm_dev, "status not set after read payload table status %d\n",
962	status);
963	ret = -EINVAL;
964	goto fail;
965	}
966	ret = 0;
967	fail:
968	return ret;
969	}
970	EXPORT_SYMBOL(drm_dp_dpcd_write_payload);
971
972	/**
973	* drm_dp_dpcd_clear_payload() - Clear the entire VC Payload ID table
974	* @aux: DisplayPort AUX channel
975	*
976	* Clear the entire VC Payload ID table.
977	*
978	* Returns: 0 on success, negative error code on errors.
979	*/
980	int drm_dp_dpcd_clear_payload(struct drm_dp_aux *aux)
981	{
982	return drm_dp_dpcd_write_payload(aux, 0, 0, 0x3f);
983	}
984	EXPORT_SYMBOL(drm_dp_dpcd_clear_payload);
985
986	/**
987	* drm_dp_dpcd_poll_act_handled() - Poll for ACT handled status
988	* @aux: DisplayPort AUX channel
989	* @timeout_ms: Timeout in ms
990	*
991	* Try waiting for the sink to finish updating its payload table by polling for
992	* the ACT handled bit of DP_PAYLOAD_TABLE_UPDATE_STATUS for up to @timeout_ms
993	* milliseconds, defaulting to 3000 ms if 0.
994	*
995	* Returns:
996	* 0 if the ACT was handled in time, negative error code on failure.
997	*/
998	int drm_dp_dpcd_poll_act_handled(struct drm_dp_aux *aux, int timeout_ms)
999	{
1000	int ret, status;
1001
1002	/* default to 3 seconds, this is arbitrary */
1003	timeout_ms = timeout_ms ?: 3000;
1004
1005	ret = readx_poll_timeout(read_payload_update_status, aux, status,
1006	status & DP_PAYLOAD_ACT_HANDLED || status < 0,
1007	200, timeout_ms * USEC_PER_MSEC);
1008	if (ret < 0 && status >= 0) {
1009	drm_err(aux->drm_dev, "Failed to get ACT after %d ms, last status: %02x\n",
1010	timeout_ms, status);
1011	return -EINVAL;
1012	} else if (status < 0) {
1013	/*
1014	* Failure here isn't unexpected - the hub may have
1015	* just been unplugged
1016	*/
1017	drm_dbg_kms(aux->drm_dev, "Failed to read payload table status: %d\n", status);
1018	return status;
1019	}
1020
1021	return 0;
1022	}
1023	EXPORT_SYMBOL(drm_dp_dpcd_poll_act_handled);
1024
1025	static bool is_edid_digital_input_dp(const struct drm_edid *drm_edid)
1026	{
1027	/* FIXME: get rid of drm_edid_raw() */
1028	const struct edid *edid = drm_edid_raw(drm_edid);
1029
1030	return edid && edid->revision >= 4 &&
1031	edid->input & DRM_EDID_INPUT_DIGITAL &&
1032	(edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP;
1033	}
1034
1035	/**
1036	* drm_dp_downstream_is_type() - is the downstream facing port of certain type?
1037	* @dpcd: DisplayPort configuration data
1038	* @port_cap: port capabilities
1039	* @type: port type to be checked. Can be:
1040	* %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI,
1041	* %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID,
1042	* %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS.
1043	*
1044	* Caveat: Only works with DPCD 1.1+ port caps.
1045	*
1046	* Returns: whether the downstream facing port matches the type.
1047	*/
1048	bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1049	const u8 port_cap[4], u8 type)
1050	{
1051	return drm_dp_is_branch(dpcd) &&
1052	dpcd[DP_DPCD_REV] >= 0x11 &&
1053	(port_cap[0] & DP_DS_PORT_TYPE_MASK) == type;
1054	}
1055	EXPORT_SYMBOL(drm_dp_downstream_is_type);
1056
1057	/**
1058	* drm_dp_downstream_is_tmds() - is the downstream facing port TMDS?
1059	* @dpcd: DisplayPort configuration data
1060	* @port_cap: port capabilities
1061	* @drm_edid: EDID
1062	*
1063	* Returns: whether the downstream facing port is TMDS (HDMI/DVI).
1064	*/
1065	bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1066	const u8 port_cap[4],
1067	const struct drm_edid *drm_edid)
1068	{
1069	if (dpcd[DP_DPCD_REV] < 0x11) {
1070	switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1071	case DP_DWN_STRM_PORT_TYPE_TMDS:
1072	return true;
1073	default:
1074	return false;
1075	}
1076	}
1077
1078	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1079	case DP_DS_PORT_TYPE_DP_DUALMODE:
1080	if (is_edid_digital_input_dp(drm_edid))
1081	return false;
1082	fallthrough;
1083	case DP_DS_PORT_TYPE_DVI:
1084	case DP_DS_PORT_TYPE_HDMI:
1085	return true;
1086	default:
1087	return false;
1088	}
1089	}
1090	EXPORT_SYMBOL(drm_dp_downstream_is_tmds);
1091
1092	/**
1093	* drm_dp_send_real_edid_checksum() - send back real edid checksum value
1094	* @aux: DisplayPort AUX channel
1095	* @real_edid_checksum: real edid checksum for the last block
1096	*
1097	* Returns:
1098	* True on success
1099	*/
1100	bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
1101	u8 real_edid_checksum)
1102	{
1103	u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
1104
1105	if (drm_dp_dpcd_read_byte(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
1106	valuep: &auto_test_req) < 0) {
1107	drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",
1108	aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
1109	return false;
1110	}
1111	auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
1112
1113	if (drm_dp_dpcd_read_byte(aux, DP_TEST_REQUEST, valuep: &link_edid_read) < 0) {
1114	drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",
1115	aux->name, DP_TEST_REQUEST);
1116	return false;
1117	}
1118	link_edid_read &= DP_TEST_LINK_EDID_READ;
1119
1120	if (!auto_test_req || !link_edid_read) {
1121	drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support TEST_EDID_READ\n",
1122	aux->name);
1123	return false;
1124	}
1125
1126	if (drm_dp_dpcd_write_byte(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
1127	value: auto_test_req) < 0) {
1128	drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
1129	aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
1130	return false;
1131	}
1132
1133	/* send back checksum for the last edid extension block data */
1134	if (drm_dp_dpcd_write_byte(aux, DP_TEST_EDID_CHECKSUM,
1135	value: real_edid_checksum) < 0) {
1136	drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
1137	aux->name, DP_TEST_EDID_CHECKSUM);
1138	return false;
1139	}
1140
1141	test_resp |= DP_TEST_EDID_CHECKSUM_WRITE;
1142	if (drm_dp_dpcd_write_byte(aux, DP_TEST_RESPONSE, value: test_resp) < 0) {
1143	drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
1144	aux->name, DP_TEST_RESPONSE);
1145	return false;
1146	}
1147
1148	return true;
1149	}
1150	EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);
1151
1152	static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
1153	{
1154	u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK;
1155
1156	if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4)
1157	port_count = 4;
1158
1159	return port_count;
1160	}
1161
1162	static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,
1163	u8 dpcd[DP_RECEIVER_CAP_SIZE])
1164	{
1165	u8 dpcd_ext[DP_RECEIVER_CAP_SIZE];
1166	int ret;
1167
1168	/*
1169	* Prior to DP1.3 the bit represented by
1170	* DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
1171	* If it is set DP_DPCD_REV at 0000h could be at a value less than
1172	* the true capability of the panel. The only way to check is to
1173	* then compare 0000h and 2200h.
1174	*/
1175	if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
1176	DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
1177	return 0;
1178
1179	ret = drm_dp_dpcd_read_data(aux, DP_DP13_DPCD_REV, buffer: &dpcd_ext,
1180	size: sizeof(dpcd_ext));
1181	if (ret < 0)
1182	return ret;
1183
1184	if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
1185	drm_dbg_kms(aux->drm_dev,
1186	"%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n",
1187	aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]);
1188	return 0;
1189	}
1190
1191	if (!memcmp(p: dpcd, q: dpcd_ext, size: sizeof(dpcd_ext)))
1192	return 0;
1193
1194	drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
1195
1196	memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext));
1197
1198	return 0;
1199	}
1200
1201	/**
1202	* drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if
1203	* available
1204	* @aux: DisplayPort AUX channel
1205	* @dpcd: Buffer to store the resulting DPCD in
1206	*
1207	* Attempts to read the base DPCD caps for @aux. Additionally, this function
1208	* checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if
1209	* present.
1210	*
1211	* Returns: %0 if the DPCD was read successfully, negative error code
1212	* otherwise.
1213	*/
1214	int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
1215	u8 dpcd[DP_RECEIVER_CAP_SIZE])
1216	{
1217	int ret;
1218
1219	ret = drm_dp_dpcd_read_data(aux, DP_DPCD_REV, buffer: dpcd, DP_RECEIVER_CAP_SIZE);
1220	if (ret < 0)
1221	return ret;
1222	if (dpcd[DP_DPCD_REV] == 0)
1223	return -EIO;
1224
1225	ret = drm_dp_read_extended_dpcd_caps(aux, dpcd);
1226	if (ret < 0)
1227	return ret;
1228
1229	drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
1230
1231	return ret;
1232	}
1233	EXPORT_SYMBOL(drm_dp_read_dpcd_caps);
1234
1235	/**
1236	* drm_dp_read_downstream_info() - read DPCD downstream port info if available
1237	* @aux: DisplayPort AUX channel
1238	* @dpcd: A cached copy of the port's DPCD
1239	* @downstream_ports: buffer to store the downstream port info in
1240	*
1241	* See also:
1242	* drm_dp_downstream_max_clock()
1243	* drm_dp_downstream_max_bpc()
1244	*
1245	* Returns: 0 if either the downstream port info was read successfully or
1246	* there was no downstream info to read, or a negative error code otherwise.
1247	*/
1248	int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
1249	const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1250	u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS])
1251	{
1252	int ret;
1253	u8 len;
1254
1255	memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS);
1256
1257	/* No downstream info to read */
1258	if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10)
1259	return 0;
1260
1261	/* Some branches advertise having 0 downstream ports, despite also advertising they have a
1262	* downstream port present. The DP spec isn't clear on if this is allowed or not, but since
1263	* some branches do it we need to handle it regardless.
1264	*/
1265	len = drm_dp_downstream_port_count(dpcd);
1266	if (!len)
1267	return 0;
1268
1269	if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE)
1270	len *= 4;
1271
1272	ret = drm_dp_dpcd_read_data(aux, DP_DOWNSTREAM_PORT_0, buffer: downstream_ports, size: len);
1273	if (ret < 0)
1274	return ret;
1275
1276	drm_dbg_kms(aux->drm_dev, "%s: DPCD DFP: %*ph\n", aux->name, len, downstream_ports);
1277
1278	return 0;
1279	}
1280	EXPORT_SYMBOL(drm_dp_read_downstream_info);
1281
1282	/**
1283	* drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock
1284	* @dpcd: DisplayPort configuration data
1285	* @port_cap: port capabilities
1286	*
1287	* Returns: Downstream facing port max dot clock in kHz on success,
1288	* or 0 if max clock not defined
1289	*/
1290	int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1291	const u8 port_cap[4])
1292	{
1293	if (!drm_dp_is_branch(dpcd))
1294	return 0;
1295
1296	if (dpcd[DP_DPCD_REV] < 0x11)
1297	return 0;
1298
1299	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1300	case DP_DS_PORT_TYPE_VGA:
1301	if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1302	return 0;
1303	return port_cap[1] * 8000;
1304	default:
1305	return 0;
1306	}
1307	}
1308	EXPORT_SYMBOL(drm_dp_downstream_max_dotclock);
1309
1310	/**
1311	* drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock
1312	* @dpcd: DisplayPort configuration data
1313	* @port_cap: port capabilities
1314	* @drm_edid: EDID
1315	*
1316	* Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success,
1317	* or 0 if max TMDS clock not defined
1318	*/
1319	int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1320	const u8 port_cap[4],
1321	const struct drm_edid *drm_edid)
1322	{
1323	if (!drm_dp_is_branch(dpcd))
1324	return 0;
1325
1326	if (dpcd[DP_DPCD_REV] < 0x11) {
1327	switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1328	case DP_DWN_STRM_PORT_TYPE_TMDS:
1329	return 165000;
1330	default:
1331	return 0;
1332	}
1333	}
1334
1335	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1336	case DP_DS_PORT_TYPE_DP_DUALMODE:
1337	if (is_edid_digital_input_dp(drm_edid))
1338	return 0;
1339	/*
1340	* It's left up to the driver to check the
1341	* DP dual mode adapter's max TMDS clock.
1342	*
1343	* Unfortunately it looks like branch devices
1344	* may not fordward that the DP dual mode i2c
1345	* access so we just usually get i2c nak :(
1346	*/
1347	fallthrough;
1348	case DP_DS_PORT_TYPE_HDMI:
1349	/*
1350	* We should perhaps assume 165 MHz when detailed cap
1351	* info is not available. But looks like many typical
1352	* branch devices fall into that category and so we'd
1353	* probably end up with users complaining that they can't
1354	* get high resolution modes with their favorite dongle.
1355	*
1356	* So let's limit to 300 MHz instead since DPCD 1.4
1357	* HDMI 2.0 DFPs are required to have the detailed cap
1358	* info. So it's more likely we're dealing with a HDMI 1.4
1359	* compatible* device here.
1360	*/
1361	if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1362	return 300000;
1363	return port_cap[1] * 2500;
1364	case DP_DS_PORT_TYPE_DVI:
1365	if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1366	return 165000;
1367	/* FIXME what to do about DVI dual link? */
1368	return port_cap[1] * 2500;
1369	default:
1370	return 0;
1371	}
1372	}
1373	EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock);
1374
1375	/**
1376	* drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock
1377	* @dpcd: DisplayPort configuration data
1378	* @port_cap: port capabilities
1379	* @drm_edid: EDID
1380	*
1381	* Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success,
1382	* or 0 if max TMDS clock not defined
1383	*/
1384	int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1385	const u8 port_cap[4],
1386	const struct drm_edid *drm_edid)
1387	{
1388	if (!drm_dp_is_branch(dpcd))
1389	return 0;
1390
1391	if (dpcd[DP_DPCD_REV] < 0x11) {
1392	switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1393	case DP_DWN_STRM_PORT_TYPE_TMDS:
1394	return 25000;
1395	default:
1396	return 0;
1397	}
1398	}
1399
1400	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1401	case DP_DS_PORT_TYPE_DP_DUALMODE:
1402	if (is_edid_digital_input_dp(drm_edid))
1403	return 0;
1404	fallthrough;
1405	case DP_DS_PORT_TYPE_DVI:
1406	case DP_DS_PORT_TYPE_HDMI:
1407	/*
1408	* Unclear whether the protocol converter could
1409	* utilize pixel replication. Assume it won't.
1410	*/
1411	return 25000;
1412	default:
1413	return 0;
1414	}
1415	}
1416	EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock);
1417
1418	/**
1419	* drm_dp_downstream_max_bpc() - extract downstream facing port max
1420	* bits per component
1421	* @dpcd: DisplayPort configuration data
1422	* @port_cap: downstream facing port capabilities
1423	* @drm_edid: EDID
1424	*
1425	* Returns: Max bpc on success or 0 if max bpc not defined
1426	*/
1427	int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1428	const u8 port_cap[4],
1429	const struct drm_edid *drm_edid)
1430	{
1431	if (!drm_dp_is_branch(dpcd))
1432	return 0;
1433
1434	if (dpcd[DP_DPCD_REV] < 0x11) {
1435	switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1436	case DP_DWN_STRM_PORT_TYPE_DP:
1437	return 0;
1438	default:
1439	return 8;
1440	}
1441	}
1442
1443	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1444	case DP_DS_PORT_TYPE_DP:
1445	return 0;
1446	case DP_DS_PORT_TYPE_DP_DUALMODE:
1447	if (is_edid_digital_input_dp(drm_edid))
1448	return 0;
1449	fallthrough;
1450	case DP_DS_PORT_TYPE_HDMI:
1451	case DP_DS_PORT_TYPE_DVI:
1452	case DP_DS_PORT_TYPE_VGA:
1453	if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1454	return 8;
1455
1456	switch (port_cap[2] & DP_DS_MAX_BPC_MASK) {
1457	case DP_DS_8BPC:
1458	return 8;
1459	case DP_DS_10BPC:
1460	return 10;
1461	case DP_DS_12BPC:
1462	return 12;
1463	case DP_DS_16BPC:
1464	return 16;
1465	default:
1466	return 8;
1467	}
1468	break;
1469	default:
1470	return 8;
1471	}
1472	}
1473	EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
1474
1475	/**
1476	* drm_dp_downstream_420_passthrough() - determine downstream facing port
1477	* YCbCr 4:2:0 pass-through capability
1478	* @dpcd: DisplayPort configuration data
1479	* @port_cap: downstream facing port capabilities
1480	*
1481	* Returns: whether the downstream facing port can pass through YCbCr 4:2:0
1482	*/
1483	bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1484	const u8 port_cap[4])
1485	{
1486	if (!drm_dp_is_branch(dpcd))
1487	return false;
1488
1489	if (dpcd[DP_DPCD_REV] < 0x13)
1490	return false;
1491
1492	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1493	case DP_DS_PORT_TYPE_DP:
1494	return true;
1495	case DP_DS_PORT_TYPE_HDMI:
1496	if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1497	return false;
1498
1499	return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;
1500	default:
1501	return false;
1502	}
1503	}
1504	EXPORT_SYMBOL(drm_dp_downstream_420_passthrough);
1505
1506	/**
1507	* drm_dp_downstream_444_to_420_conversion() - determine downstream facing port
1508	* YCbCr 4:4:4->4:2:0 conversion capability
1509	* @dpcd: DisplayPort configuration data
1510	* @port_cap: downstream facing port capabilities
1511	*
1512	* Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0
1513	*/
1514	bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1515	const u8 port_cap[4])
1516	{
1517	if (!drm_dp_is_branch(dpcd))
1518	return false;
1519
1520	if (dpcd[DP_DPCD_REV] < 0x13)
1521	return false;
1522
1523	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1524	case DP_DS_PORT_TYPE_HDMI:
1525	if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1526	return false;
1527
1528	return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;
1529	default:
1530	return false;
1531	}
1532	}
1533	EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);
1534
1535	/**
1536	* drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream facing port
1537	* RGB->YCbCr conversion capability
1538	* @dpcd: DisplayPort configuration data
1539	* @port_cap: downstream facing port capabilities
1540	* @color_spc: Colorspace for which conversion cap is sought
1541	*
1542	* Returns: whether the downstream facing port can convert RGB->YCbCr for a given
1543	* colorspace.
1544	*/
1545	bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1546	const u8 port_cap[4],
1547	u8 color_spc)
1548	{
1549	if (!drm_dp_is_branch(dpcd))
1550	return false;
1551
1552	if (dpcd[DP_DPCD_REV] < 0x13)
1553	return false;
1554
1555	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1556	case DP_DS_PORT_TYPE_HDMI:
1557	if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1558	return false;
1559
1560	return port_cap[3] & color_spc;
1561	default:
1562	return false;
1563	}
1564	}
1565	EXPORT_SYMBOL(drm_dp_downstream_rgb_to_ycbcr_conversion);
1566
1567	/**
1568	* drm_dp_downstream_mode() - return a mode for downstream facing port
1569	* @dev: DRM device
1570	* @dpcd: DisplayPort configuration data
1571	* @port_cap: port capabilities
1572	*
1573	* Provides a suitable mode for downstream facing ports without EDID.
1574	*
1575	* Returns: A new drm_display_mode on success or NULL on failure
1576	*/
1577	struct drm_display_mode *
1578	drm_dp_downstream_mode(struct drm_device *dev,
1579	const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1580	const u8 port_cap[4])
1581
1582	{
1583	u8 vic;
1584
1585	if (!drm_dp_is_branch(dpcd))
1586	return NULL;
1587
1588	if (dpcd[DP_DPCD_REV] < 0x11)
1589	return NULL;
1590
1591	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1592	case DP_DS_PORT_TYPE_NON_EDID:
1593	switch (port_cap[0] & DP_DS_NON_EDID_MASK) {
1594	case DP_DS_NON_EDID_720x480i_60:
1595	vic = 6;
1596	break;
1597	case DP_DS_NON_EDID_720x480i_50:
1598	vic = 21;
1599	break;
1600	case DP_DS_NON_EDID_1920x1080i_60:
1601	vic = 5;
1602	break;
1603	case DP_DS_NON_EDID_1920x1080i_50:
1604	vic = 20;
1605	break;
1606	case DP_DS_NON_EDID_1280x720_60:
1607	vic = 4;
1608	break;
1609	case DP_DS_NON_EDID_1280x720_50:
1610	vic = 19;
1611	break;
1612	default:
1613	return NULL;
1614	}
1615	return drm_display_mode_from_cea_vic(dev, video_code: vic);
1616	default:
1617	return NULL;
1618	}
1619	}
1620	EXPORT_SYMBOL(drm_dp_downstream_mode);
1621
1622	/**
1623	* drm_dp_downstream_id() - identify branch device
1624	* @aux: DisplayPort AUX channel
1625	* @id: DisplayPort branch device id
1626	*
1627	* Returns branch device id on success or NULL on failure
1628	*/
1629	int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
1630	{
1631	return drm_dp_dpcd_read_data(aux, DP_BRANCH_ID, buffer: id, size: 6);
1632	}
1633	EXPORT_SYMBOL(drm_dp_downstream_id);
1634
1635	/**
1636	* drm_dp_downstream_debug() - debug DP branch devices
1637	* @m: pointer for debugfs file
1638	* @dpcd: DisplayPort configuration data
1639	* @port_cap: port capabilities
1640	* @drm_edid: EDID
1641	* @aux: DisplayPort AUX channel
1642	*
1643	*/
1644	void drm_dp_downstream_debug(struct seq_file *m,
1645	const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1646	const u8 port_cap[4],
1647	const struct drm_edid *drm_edid,
1648	struct drm_dp_aux *aux)
1649	{
1650	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1651	DP_DETAILED_CAP_INFO_AVAILABLE;
1652	int clk;
1653	int bpc;
1654	char id[7];
1655	int len;
1656	uint8_t rev[2];
1657	int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1658	bool branch_device = drm_dp_is_branch(dpcd);
1659
1660	seq_printf(m, fmt: "\tDP branch device present: %s\n",
1661	str_yes_no(v: branch_device));
1662
1663	if (!branch_device)
1664	return;
1665
1666	switch (type) {
1667	case DP_DS_PORT_TYPE_DP:
1668	seq_puts(m, s: "\t\tType: DisplayPort\n");
1669	break;
1670	case DP_DS_PORT_TYPE_VGA:
1671	seq_puts(m, s: "\t\tType: VGA\n");
1672	break;
1673	case DP_DS_PORT_TYPE_DVI:
1674	seq_puts(m, s: "\t\tType: DVI\n");
1675	break;
1676	case DP_DS_PORT_TYPE_HDMI:
1677	seq_puts(m, s: "\t\tType: HDMI\n");
1678	break;
1679	case DP_DS_PORT_TYPE_NON_EDID:
1680	seq_puts(m, s: "\t\tType: others without EDID support\n");
1681	break;
1682	case DP_DS_PORT_TYPE_DP_DUALMODE:
1683	seq_puts(m, s: "\t\tType: DP++\n");
1684	break;
1685	case DP_DS_PORT_TYPE_WIRELESS:
1686	seq_puts(m, s: "\t\tType: Wireless\n");
1687	break;
1688	default:
1689	seq_puts(m, s: "\t\tType: N/A\n");
1690	}
1691
1692	memset(id, 0, sizeof(id));
1693	drm_dp_downstream_id(aux, id);
1694	seq_printf(m, fmt: "\t\tID: %s\n", id);
1695
1696	len = drm_dp_dpcd_read_data(aux, DP_BRANCH_HW_REV, buffer: &rev[0], size: 1);
1697	if (!len)
1698	seq_printf(m, fmt: "\t\tHW: %d.%d\n",
1699	(rev[0] & 0xf0) >> 4, rev[0] & 0xf);
1700
1701	len = drm_dp_dpcd_read_data(aux, DP_BRANCH_SW_REV, buffer: rev, size: 2);
1702	if (!len)
1703	seq_printf(m, fmt: "\t\tSW: %d.%d\n", rev[0], rev[1]);
1704
1705	if (detailed_cap_info) {
1706	clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);
1707	if (clk > 0)
1708	seq_printf(m, fmt: "\t\tMax dot clock: %d kHz\n", clk);
1709
1710	clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, drm_edid);
1711	if (clk > 0)
1712	seq_printf(m, fmt: "\t\tMax TMDS clock: %d kHz\n", clk);
1713
1714	clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, drm_edid);
1715	if (clk > 0)
1716	seq_printf(m, fmt: "\t\tMin TMDS clock: %d kHz\n", clk);
1717
1718	bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, drm_edid);
1719
1720	if (bpc > 0)
1721	seq_printf(m, fmt: "\t\tMax bpc: %d\n", bpc);
1722	}
1723	}
1724	EXPORT_SYMBOL(drm_dp_downstream_debug);
1725
1726	/**
1727	* drm_dp_subconnector_type() - get DP branch device type
1728	* @dpcd: DisplayPort configuration data
1729	* @port_cap: port capabilities
1730	*/
1731	enum drm_mode_subconnector
1732	drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1733	const u8 port_cap[4])
1734	{
1735	int type;
1736	if (!drm_dp_is_branch(dpcd))
1737	return DRM_MODE_SUBCONNECTOR_Native;
1738	/* DP 1.0 approach */
1739	if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) {
1740	type = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1741	DP_DWN_STRM_PORT_TYPE_MASK;
1742
1743	switch (type) {
1744	case DP_DWN_STRM_PORT_TYPE_TMDS:
1745	/* Can be HDMI or DVI-D, DVI-D is a safer option */
1746	return DRM_MODE_SUBCONNECTOR_DVID;
1747	case DP_DWN_STRM_PORT_TYPE_ANALOG:
1748	/* Can be VGA or DVI-A, VGA is more popular */
1749	return DRM_MODE_SUBCONNECTOR_VGA;
1750	case DP_DWN_STRM_PORT_TYPE_DP:
1751	return DRM_MODE_SUBCONNECTOR_DisplayPort;
1752	case DP_DWN_STRM_PORT_TYPE_OTHER:
1753	default:
1754	return DRM_MODE_SUBCONNECTOR_Unknown;
1755	}
1756	}
1757	type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1758
1759	switch (type) {
1760	case DP_DS_PORT_TYPE_DP:
1761	case DP_DS_PORT_TYPE_DP_DUALMODE:
1762	return DRM_MODE_SUBCONNECTOR_DisplayPort;
1763	case DP_DS_PORT_TYPE_VGA:
1764	return DRM_MODE_SUBCONNECTOR_VGA;
1765	case DP_DS_PORT_TYPE_DVI:
1766	return DRM_MODE_SUBCONNECTOR_DVID;
1767	case DP_DS_PORT_TYPE_HDMI:
1768	return DRM_MODE_SUBCONNECTOR_HDMIA;
1769	case DP_DS_PORT_TYPE_WIRELESS:
1770	return DRM_MODE_SUBCONNECTOR_Wireless;
1771	case DP_DS_PORT_TYPE_NON_EDID:
1772	default:
1773	return DRM_MODE_SUBCONNECTOR_Unknown;
1774	}
1775	}
1776	EXPORT_SYMBOL(drm_dp_subconnector_type);
1777
1778	/**
1779	* drm_dp_set_subconnector_property - set subconnector for DP connector
1780	* @connector: connector to set property on
1781	* @status: connector status
1782	* @dpcd: DisplayPort configuration data
1783	* @port_cap: port capabilities
1784	*
1785	* Called by a driver on every detect event.
1786	*/
1787	void drm_dp_set_subconnector_property(struct drm_connector *connector,
1788	enum drm_connector_status status,
1789	const u8 *dpcd,
1790	const u8 port_cap[4])
1791	{
1792	enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
1793
1794	if (status == connector_status_connected)
1795	subconnector = drm_dp_subconnector_type(dpcd, port_cap);
1796	drm_object_property_set_value(obj: &connector->base,
1797	property: connector->dev->mode_config.dp_subconnector_property,
1798	val: subconnector);
1799	}
1800	EXPORT_SYMBOL(drm_dp_set_subconnector_property);
1801
1802	/**
1803	* drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink
1804	* count
1805	* @connector: The DRM connector to check
1806	* @dpcd: A cached copy of the connector's DPCD RX capabilities
1807	* @desc: A cached copy of the connector's DP descriptor
1808	*
1809	* See also: drm_dp_read_sink_count()
1810	*
1811	* Returns: %True if the (e)DP connector has a valid sink count that should
1812	* be probed, %false otherwise.
1813	*/
1814	bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
1815	const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1816	const struct drm_dp_desc *desc)
1817	{
1818	/* Some eDP panels don't set a valid value for the sink count */
1819	return connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
1820	dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 &&
1821	dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
1822	!drm_dp_has_quirk(desc, quirk: DP_DPCD_QUIRK_NO_SINK_COUNT);
1823	}
1824	EXPORT_SYMBOL(drm_dp_read_sink_count_cap);
1825
1826	/**
1827	* drm_dp_read_sink_count() - Retrieve the sink count for a given sink
1828	* @aux: The DP AUX channel to use
1829	*
1830	* See also: drm_dp_read_sink_count_cap()
1831	*
1832	* Returns: The current sink count reported by @aux, or a negative error code
1833	* otherwise.
1834	*/
1835	int drm_dp_read_sink_count(struct drm_dp_aux *aux)
1836	{
1837	u8 count;
1838	int ret;
1839
1840	ret = drm_dp_dpcd_read_byte(aux, DP_SINK_COUNT, valuep: &count);
1841	if (ret < 0)
1842	return ret;
1843
1844	return DP_GET_SINK_COUNT(count);
1845	}
1846	EXPORT_SYMBOL(drm_dp_read_sink_count);
1847
1848	/*
1849	* I2C-over-AUX implementation
1850	*/
1851
1852	static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
1853	{
1854	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1855	I2C_FUNC_SMBUS_READ_BLOCK_DATA |
1856	I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1857	I2C_FUNC_10BIT_ADDR;
1858	}
1859
1860	static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
1861	{
1862	/*
1863	* In case of i2c defer or short i2c ack reply to a write,
1864	* we need to switch to WRITE_STATUS_UPDATE to drain the
1865	* rest of the message
1866	*/
1867	if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
1868	msg->request &= DP_AUX_I2C_MOT;
1869	msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
1870	}
1871	}
1872
1873	#define AUX_PRECHARGE_LEN 10 /* 10 to 16 */
1874	#define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */
1875	#define AUX_STOP_LEN 4
1876	#define AUX_CMD_LEN 4
1877	#define AUX_ADDRESS_LEN 20
1878	#define AUX_REPLY_PAD_LEN 4
1879	#define AUX_LENGTH_LEN 8
1880
1881	/*
1882	* Calculate the duration of the AUX request/reply in usec. Gives the
1883	* "best" case estimate, ie. successful while as short as possible.
1884	*/
1885	static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
1886	{
1887	int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1888	AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
1889
1890	if ((msg->request & DP_AUX_I2C_READ) == 0)
1891	len += msg->size * 8;
1892
1893	return len;
1894	}
1895
1896	static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
1897	{
1898	int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1899	AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
1900
1901	/*
1902	* For read we expect what was asked. For writes there will
1903	* be 0 or 1 data bytes. Assume 0 for the "best" case.
1904	*/
1905	if (msg->request & DP_AUX_I2C_READ)
1906	len += msg->size * 8;
1907
1908	return len;
1909	}
1910
1911	#define I2C_START_LEN 1
1912	#define I2C_STOP_LEN 1
1913	#define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */
1914	#define I2C_DATA_LEN 9 /* DATA + ACK/NACK */
1915
1916	/*
1917	* Calculate the length of the i2c transfer in usec, assuming
1918	* the i2c bus speed is as specified. Gives the "worst"
1919	* case estimate, ie. successful while as long as possible.
1920	* Doesn't account the "MOT" bit, and instead assumes each
1921	* message includes a START, ADDRESS and STOP. Neither does it
1922	* account for additional random variables such as clock stretching.
1923	*/
1924	static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
1925	int i2c_speed_khz)
1926	{
1927	/* AUX bitrate is 1MHz, i2c bitrate as specified */
1928	return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
1929	msg->size * I2C_DATA_LEN +
1930	I2C_STOP_LEN) * 1000, i2c_speed_khz);
1931	}
1932
1933	/*
1934	* Determine how many retries should be attempted to successfully transfer
1935	* the specified message, based on the estimated durations of the
1936	* i2c and AUX transfers.
1937	*/
1938	static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
1939	int i2c_speed_khz)
1940	{
1941	int aux_time_us = drm_dp_aux_req_duration(msg) +
1942	drm_dp_aux_reply_duration(msg);
1943	int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
1944
1945	return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
1946	}
1947
1948	/*
1949	* FIXME currently assumes 10 kHz as some real world devices seem
1950	* to require it. We should query/set the speed via DPCD if supported.
1951	*/
1952	static int dp_aux_i2c_speed_khz __read_mostly = 10;
1953	module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
1954	MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
1955	"Assumed speed of the i2c bus in kHz, (1-400, default 10)");
1956
1957	/*
1958	* Transfer a single I2C-over-AUX message and handle various error conditions,
1959	* retrying the transaction as appropriate. It is assumed that the
1960	* &drm_dp_aux.transfer function does not modify anything in the msg other than the
1961	* reply field.
1962	*
1963	* Returns bytes transferred on success, or a negative error code on failure.
1964	*/
1965	static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1966	{
1967	unsigned int retry, defer_i2c;
1968	int ret;
1969	/*
1970	* DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
1971	* is required to retry at least seven times upon receiving AUX_DEFER
1972	* before giving up the AUX transaction.
1973	*
1974	* We also try to account for the i2c bus speed.
1975	*/
1976	int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
1977
1978	for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
1979	ret = aux->transfer(aux, msg);
1980	if (ret < 0) {
1981	if (ret == -EBUSY)
1982	continue;
1983
1984	/*
1985	* While timeouts can be errors, they're usually normal
1986	* behavior (for instance, when a driver tries to
1987	* communicate with a non-existent DisplayPort device).
1988	* Avoid spamming the kernel log with timeout errors.
1989	*/
1990	if (ret == -ETIMEDOUT)
1991	drm_dbg_kms_ratelimited(aux->drm_dev, "%s: transaction timed out\n",
1992	aux->name);
1993	else
1994	drm_dbg_kms(aux->drm_dev, "%s: transaction failed: %d\n",
1995	aux->name, ret);
1996	return ret;
1997	}
1998
1999
2000	switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
2001	case DP_AUX_NATIVE_REPLY_ACK:
2002	/*
2003	* For I2C-over-AUX transactions this isn't enough, we
2004	* need to check for the I2C ACK reply.
2005	*/
2006	break;
2007
2008	case DP_AUX_NATIVE_REPLY_NACK:
2009	drm_dbg_kms(aux->drm_dev, "%s: native nack (result=%d, size=%zu)\n",
2010	aux->name, ret, msg->size);
2011	return -EREMOTEIO;
2012
2013	case DP_AUX_NATIVE_REPLY_DEFER:
2014	drm_dbg_kms(aux->drm_dev, "%s: native defer\n", aux->name);
2015	/*
2016	* We could check for I2C bit rate capabilities and if
2017	* available adjust this interval. We could also be
2018	* more careful with DP-to-legacy adapters where a
2019	* long legacy cable may force very low I2C bit rates.
2020	*
2021	* For now just defer for long enough to hopefully be
2022	* safe for all use-cases.
2023	*/
2024	usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
2025	continue;
2026
2027	default:
2028	drm_err(aux->drm_dev, "%s: invalid native reply %#04x\n",
2029	aux->name, msg->reply);
2030	return -EREMOTEIO;
2031	}
2032
2033	switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
2034	case DP_AUX_I2C_REPLY_ACK:
2035	/*
2036	* Both native ACK and I2C ACK replies received. We
2037	* can assume the transfer was successful.
2038	*/
2039	if (ret != msg->size)
2040	drm_dp_i2c_msg_write_status_update(msg);
2041	return ret;
2042
2043	case DP_AUX_I2C_REPLY_NACK:
2044	drm_dbg_kms(aux->drm_dev, "%s: I2C nack (result=%d, size=%zu)\n",
2045	aux->name, ret, msg->size);
2046	aux->i2c_nack_count++;
2047	return -EREMOTEIO;
2048
2049	case DP_AUX_I2C_REPLY_DEFER:
2050	drm_dbg_kms(aux->drm_dev, "%s: I2C defer\n", aux->name);
2051	/* DP Compliance Test 4.2.2.5 Requirement:
2052	* Must have at least 7 retries for I2C defers on the
2053	* transaction to pass this test
2054	*/
2055	aux->i2c_defer_count++;
2056	if (defer_i2c < 7)
2057	defer_i2c++;
2058	usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
2059	drm_dp_i2c_msg_write_status_update(msg);
2060
2061	continue;
2062
2063	default:
2064	drm_err(aux->drm_dev, "%s: invalid I2C reply %#04x\n",
2065	aux->name, msg->reply);
2066	return -EREMOTEIO;
2067	}
2068	}
2069
2070	drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up\n", aux->name);
2071	return -EREMOTEIO;
2072	}
2073
2074	static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
2075	const struct i2c_msg *i2c_msg)
2076	{
2077	msg->request = (i2c_msg->flags & I2C_M_RD) ?
2078	DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
2079	if (!(i2c_msg->flags & I2C_M_STOP))
2080	msg->request |= DP_AUX_I2C_MOT;
2081	}
2082
2083	/*
2084	* Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
2085	*
2086	* Returns an error code on failure, or a recommended transfer size on success.
2087	*/
2088	static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
2089	{
2090	int err, ret = orig_msg->size;
2091	struct drm_dp_aux_msg msg = *orig_msg;
2092
2093	while (msg.size > 0) {
2094	err = drm_dp_i2c_do_msg(aux, msg: &msg);
2095	if (err <= 0)
2096	return err == 0 ? -EPROTO : err;
2097
2098	if (err < msg.size && err < ret) {
2099	drm_dbg_kms(aux->drm_dev,
2100	"%s: Partial I2C reply: requested %zu bytes got %d bytes\n",
2101	aux->name, msg.size, err);
2102	ret = err;
2103	}
2104
2105	msg.size -= err;
2106	msg.buffer += err;
2107	}
2108
2109	return ret;
2110	}
2111
2112	/*
2113	* Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
2114	* packets to be as large as possible. If not, the I2C transactions never
2115	* succeed. Hence the default is maximum.
2116	*/
2117	static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
2118	module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
2119	MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
2120	"Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
2121
2122	static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
2123	int num)
2124	{
2125	struct drm_dp_aux *aux = adapter->algo_data;
2126	unsigned int i, j;
2127	unsigned transfer_size;
2128	struct drm_dp_aux_msg msg;
2129	int err = 0;
2130
2131	if (aux->powered_down)
2132	return -EBUSY;
2133
2134	dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
2135
2136	memset(&msg, 0, sizeof(msg));
2137
2138	for (i = 0; i < num; i++) {
2139	msg.address = msgs[i].addr;
2140
2141	if (!aux->no_zero_sized) {
2142	drm_dp_i2c_msg_set_request(msg: &msg, i2c_msg: &msgs[i]);
2143	/* Send a bare address packet to start the transaction.
2144	* Zero sized messages specify an address only (bare
2145	* address) transaction.
2146	*/
2147	msg.buffer = NULL;
2148	msg.size = 0;
2149	err = drm_dp_i2c_do_msg(aux, msg: &msg);
2150	}
2151
2152	/*
2153	* Reset msg.request in case in case it got
2154	* changed into a WRITE_STATUS_UPDATE.
2155	*/
2156	drm_dp_i2c_msg_set_request(msg: &msg, i2c_msg: &msgs[i]);
2157
2158	if (err < 0)
2159	break;
2160	/* We want each transaction to be as large as possible, but
2161	* we'll go to smaller sizes if the hardware gives us a
2162	* short reply.
2163	*/
2164	transfer_size = dp_aux_i2c_transfer_size;
2165	for (j = 0; j < msgs[i].len; j += msg.size) {
2166	msg.buffer = msgs[i].buf + j;
2167	msg.size = min(transfer_size, msgs[i].len - j);
2168
2169	if (j + msg.size == msgs[i].len && aux->no_zero_sized)
2170	msg.request &= ~DP_AUX_I2C_MOT;
2171	err = drm_dp_i2c_drain_msg(aux, orig_msg: &msg);
2172
2173	/*
2174	* Reset msg.request in case in case it got
2175	* changed into a WRITE_STATUS_UPDATE.
2176	*/
2177	drm_dp_i2c_msg_set_request(msg: &msg, i2c_msg: &msgs[i]);
2178
2179	if (err < 0)
2180	break;
2181	transfer_size = err;
2182	}
2183	if (err < 0)
2184	break;
2185	}
2186	if (err >= 0)
2187	err = num;
2188
2189	if (!aux->no_zero_sized) {
2190	/* Send a bare address packet to close out the transaction.
2191	* Zero sized messages specify an address only (bare
2192	* address) transaction.
2193	*/
2194	msg.request &= ~DP_AUX_I2C_MOT;
2195	msg.buffer = NULL;
2196	msg.size = 0;
2197	(void)drm_dp_i2c_do_msg(aux, msg: &msg);
2198	}
2199	return err;
2200	}
2201
2202	static const struct i2c_algorithm drm_dp_i2c_algo = {
2203	.functionality = drm_dp_i2c_functionality,
2204	.master_xfer = drm_dp_i2c_xfer,
2205	};
2206
2207	static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
2208	{
2209	return container_of(i2c, struct drm_dp_aux, ddc);
2210	}
2211
2212	static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
2213	{
2214	mutex_lock(&i2c_to_aux(i2c)->hw_mutex);
2215	}
2216
2217	static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
2218	{
2219	return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex);
2220	}
2221
2222	static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
2223	{
2224	mutex_unlock(lock: &i2c_to_aux(i2c)->hw_mutex);
2225	}
2226
2227	static const struct i2c_lock_operations drm_dp_i2c_lock_ops = {
2228	.lock_bus = lock_bus,
2229	.trylock_bus = trylock_bus,
2230	.unlock_bus = unlock_bus,
2231	};
2232
2233	static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)
2234	{
2235	u8 buf, count;
2236	int ret;
2237
2238	ret = drm_dp_dpcd_read_byte(aux, DP_TEST_SINK, valuep: &buf);
2239	if (ret < 0)
2240	return ret;
2241
2242	WARN_ON(!(buf & DP_TEST_SINK_START));
2243
2244	ret = drm_dp_dpcd_read_byte(aux, DP_TEST_SINK_MISC, valuep: &buf);
2245	if (ret < 0)
2246	return ret;
2247
2248	count = buf & DP_TEST_COUNT_MASK;
2249	if (count == aux->crc_count)
2250	return -EAGAIN; /* No CRC yet */
2251
2252	aux->crc_count = count;
2253
2254	/*
2255	* At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes
2256	* per component (RGB or CrYCb).
2257	*/
2258	return drm_dp_dpcd_read_data(aux, DP_TEST_CRC_R_CR, buffer: crc, size: 6);
2259	}
2260
2261	static void drm_dp_aux_crc_work(struct work_struct *work)
2262	{
2263	struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux,
2264	crc_work);
2265	struct drm_crtc *crtc;
2266	u8 crc_bytes[6];
2267	uint32_t crcs[3];
2268	int ret;
2269
2270	if (WARN_ON(!aux->crtc))
2271	return;
2272
2273	crtc = aux->crtc;
2274	while (crtc->crc.opened) {
2275	drm_crtc_wait_one_vblank(crtc);
2276	if (!crtc->crc.opened)
2277	break;
2278
2279	ret = drm_dp_aux_get_crc(aux, crc: crc_bytes);
2280	if (ret == -EAGAIN) {
2281	usleep_range(min: 1000, max: 2000);
2282	ret = drm_dp_aux_get_crc(aux, crc: crc_bytes);
2283	}
2284
2285	if (ret == -EAGAIN) {
2286	drm_dbg_kms(aux->drm_dev, "%s: Get CRC failed after retrying: %d\n",
2287	aux->name, ret);
2288	continue;
2289	} else if (ret) {
2290	drm_dbg_kms(aux->drm_dev, "%s: Failed to get a CRC: %d\n", aux->name, ret);
2291	continue;
2292	}
2293
2294	crcs[0] = crc_bytes[0] | crc_bytes[1] << 8;
2295	crcs[1] = crc_bytes[2] | crc_bytes[3] << 8;
2296	crcs[2] = crc_bytes[4] | crc_bytes[5] << 8;
2297	drm_crtc_add_crc_entry(crtc, has_frame: false, frame: 0, crcs);
2298	}
2299	}
2300
2301	/**
2302	* drm_dp_remote_aux_init() - minimally initialise a remote aux channel
2303	* @aux: DisplayPort AUX channel
2304	*
2305	* Used for remote aux channel in general. Merely initialize the crc work
2306	* struct.
2307	*/
2308	void drm_dp_remote_aux_init(struct drm_dp_aux *aux)
2309	{
2310	INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
2311	}
2312	EXPORT_SYMBOL(drm_dp_remote_aux_init);
2313
2314	/**
2315	* drm_dp_aux_init() - minimally initialise an aux channel
2316	* @aux: DisplayPort AUX channel
2317	*
2318	* If you need to use the drm_dp_aux's i2c adapter prior to registering it with
2319	* the outside world, call drm_dp_aux_init() first. For drivers which are
2320	* grandparents to their AUX adapters (e.g. the AUX adapter is parented by a
2321	* &drm_connector), you must still call drm_dp_aux_register() once the connector
2322	* has been registered to allow userspace access to the auxiliary DP channel.
2323	* Likewise, for such drivers you should also assign &drm_dp_aux.drm_dev as
2324	* early as possible so that the &drm_device that corresponds to the AUX adapter
2325	* may be mentioned in debugging output from the DRM DP helpers.
2326	*
2327	* For devices which use a separate platform device for their AUX adapters, this
2328	* may be called as early as required by the driver.
2329	*
2330	*/
2331	void drm_dp_aux_init(struct drm_dp_aux *aux)
2332	{
2333	mutex_init(&aux->hw_mutex);
2334	mutex_init(&aux->cec.lock);
2335	INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
2336
2337	aux->ddc.algo = &drm_dp_i2c_algo;
2338	aux->ddc.algo_data = aux;
2339	aux->ddc.retries = 3;
2340
2341	aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;
2342	}
2343	EXPORT_SYMBOL(drm_dp_aux_init);
2344
2345	/**
2346	* drm_dp_aux_register() - initialise and register aux channel
2347	* @aux: DisplayPort AUX channel
2348	*
2349	* Automatically calls drm_dp_aux_init() if this hasn't been done yet. This
2350	* should only be called once the parent of @aux, &drm_dp_aux.dev, is
2351	* initialized. For devices which are grandparents of their AUX channels,
2352	* &drm_dp_aux.dev will typically be the &drm_connector &device which
2353	* corresponds to @aux. For these devices, it's advised to call
2354	* drm_dp_aux_register() in &drm_connector_funcs.late_register, and likewise to
2355	* call drm_dp_aux_unregister() in &drm_connector_funcs.early_unregister.
2356	* Functions which don't follow this will likely Oops when
2357	* %CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is enabled.
2358	*
2359	* For devices where the AUX channel is a device that exists independently of
2360	* the &drm_device that uses it, such as SoCs and bridge devices, it is
2361	* recommended to call drm_dp_aux_register() after a &drm_device has been
2362	* assigned to &drm_dp_aux.drm_dev, and likewise to call
2363	* drm_dp_aux_unregister() once the &drm_device should no longer be associated
2364	* with the AUX channel (e.g. on bridge detach).
2365	*
2366	* Drivers which need to use the aux channel before either of the two points
2367	* mentioned above need to call drm_dp_aux_init() in order to use the AUX
2368	* channel before registration.
2369	*
2370	* Returns 0 on success or a negative error code on failure.
2371	*/
2372	int drm_dp_aux_register(struct drm_dp_aux *aux)
2373	{
2374	int ret;
2375
2376	WARN_ON_ONCE(!aux->drm_dev);
2377
2378	if (!aux->ddc.algo)
2379	drm_dp_aux_init(aux);
2380
2381	aux->ddc.owner = THIS_MODULE;
2382	aux->ddc.dev.parent = aux->dev;
2383
2384	strscpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
2385	sizeof(aux->ddc.name));
2386
2387	ret = drm_dp_aux_register_devnode(aux);
2388	if (ret)
2389	return ret;
2390
2391	ret = i2c_add_adapter(adap: &aux->ddc);
2392	if (ret) {
2393	drm_dp_aux_unregister_devnode(aux);
2394	return ret;
2395	}
2396
2397	return 0;
2398	}
2399	EXPORT_SYMBOL(drm_dp_aux_register);
2400
2401	/**
2402	* drm_dp_aux_unregister() - unregister an AUX adapter
2403	* @aux: DisplayPort AUX channel
2404	*/
2405	void drm_dp_aux_unregister(struct drm_dp_aux *aux)
2406	{
2407	drm_dp_aux_unregister_devnode(aux);
2408	i2c_del_adapter(adap: &aux->ddc);
2409	}
2410	EXPORT_SYMBOL(drm_dp_aux_unregister);
2411
2412	#define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
2413
2414	/**
2415	* drm_dp_psr_setup_time() - PSR setup in time usec
2416	* @psr_cap: PSR capabilities from DPCD
2417	*
2418	* Returns:
2419	* PSR setup time for the panel in microseconds, negative
2420	* error code on failure.
2421	*/
2422	int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
2423	{
2424	static const u16 psr_setup_time_us[] = {
2425	PSR_SETUP_TIME(330),
2426	PSR_SETUP_TIME(275),
2427	PSR_SETUP_TIME(220),
2428	PSR_SETUP_TIME(165),
2429	PSR_SETUP_TIME(110),
2430	PSR_SETUP_TIME(55),
2431	PSR_SETUP_TIME(0),
2432	};
2433	int i;
2434
2435	i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
2436	if (i >= ARRAY_SIZE(psr_setup_time_us))
2437	return -EINVAL;
2438
2439	return psr_setup_time_us[i];
2440	}
2441	EXPORT_SYMBOL(drm_dp_psr_setup_time);
2442
2443	#undef PSR_SETUP_TIME
2444
2445	/**
2446	* drm_dp_start_crc() - start capture of frame CRCs
2447	* @aux: DisplayPort AUX channel
2448	* @crtc: CRTC displaying the frames whose CRCs are to be captured
2449	*
2450	* Returns 0 on success or a negative error code on failure.
2451	*/
2452	int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
2453	{
2454	u8 buf;
2455	int ret;
2456
2457	ret = drm_dp_dpcd_read_byte(aux, DP_TEST_SINK, valuep: &buf);
2458	if (ret < 0)
2459	return ret;
2460
2461	ret = drm_dp_dpcd_write_byte(aux, DP_TEST_SINK, value: buf | DP_TEST_SINK_START);
2462	if (ret < 0)
2463	return ret;
2464
2465	aux->crc_count = 0;
2466	aux->crtc = crtc;
2467	schedule_work(work: &aux->crc_work);
2468
2469	return 0;
2470	}
2471	EXPORT_SYMBOL(drm_dp_start_crc);
2472
2473	/**
2474	* drm_dp_stop_crc() - stop capture of frame CRCs
2475	* @aux: DisplayPort AUX channel
2476	*
2477	* Returns 0 on success or a negative error code on failure.
2478	*/
2479	int drm_dp_stop_crc(struct drm_dp_aux *aux)
2480	{
2481	u8 buf;
2482	int ret;
2483
2484	ret = drm_dp_dpcd_read_byte(aux, DP_TEST_SINK, valuep: &buf);
2485	if (ret < 0)
2486	return ret;
2487
2488	ret = drm_dp_dpcd_write_byte(aux, DP_TEST_SINK, value: buf & ~DP_TEST_SINK_START);
2489	if (ret < 0)
2490	return ret;
2491
2492	flush_work(work: &aux->crc_work);
2493	aux->crtc = NULL;
2494
2495	return 0;
2496	}
2497	EXPORT_SYMBOL(drm_dp_stop_crc);
2498
2499	struct dpcd_quirk {
2500	u8 oui[3];
2501	u8 device_id[6];
2502	bool is_branch;
2503	u32 quirks;
2504	};
2505
2506	#define OUI(first, second, third) { (first), (second), (third) }
2507	#define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
2508	{ (first), (second), (third), (fourth), (fifth), (sixth) }
2509
2510	#define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0)
2511
2512	static const struct dpcd_quirk dpcd_quirk_list[] = {
2513	/* Analogix 7737 needs reduced M and N at HBR2 link rates */
2514	{ OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
2515	/* LG LP140WF6-SPM1 eDP panel */
2516	{ OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
2517	/* Apple panels need some additional handling to support PSR */
2518	{ OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
2519	/* CH7511 seems to leave SINK_COUNT zeroed */
2520	{ OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
2521	/* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
2522	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
2523	/* Synaptics DP1.4 MST hubs require DSC for some modes on which it applies HBLANK expansion. */
2524	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
2525	/* MediaTek panels (at least in U3224KBA) require DSC for modes with a short HBLANK on UHBR links. */
2526	{ OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
2527	/* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
2528	{ OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
2529	};
2530
2531	#undef OUI
2532
2533	/*
2534	* Get a bit mask of DPCD quirks for the sink/branch device identified by
2535	* ident. The quirk data is shared but it's up to the drivers to act on the
2536	* data.
2537	*
2538	* For now, only the OUI (first three bytes) is used, but this may be extended
2539	* to device identification string and hardware/firmware revisions later.
2540	*/
2541	static u32
2542	drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
2543	{
2544	const struct dpcd_quirk *quirk;
2545	u32 quirks = 0;
2546	int i;
2547	u8 any_device[] = DEVICE_ID_ANY;
2548
2549	for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
2550	quirk = &dpcd_quirk_list[i];
2551
2552	if (quirk->is_branch != is_branch)
2553	continue;
2554
2555	if (memcmp(p: quirk->oui, q: ident->oui, size: sizeof(ident->oui)) != 0)
2556	continue;
2557
2558	if (memcmp(p: quirk->device_id, q: any_device, size: sizeof(any_device)) != 0 &&
2559	memcmp(p: quirk->device_id, q: ident->device_id, size: sizeof(ident->device_id)) != 0)
2560	continue;
2561
2562	quirks |= quirk->quirks;
2563	}
2564
2565	return quirks;
2566	}
2567
2568	#undef DEVICE_ID_ANY
2569	#undef DEVICE_ID
2570
2571	static int drm_dp_read_ident(struct drm_dp_aux *aux, unsigned int offset,
2572	struct drm_dp_dpcd_ident *ident)
2573	{
2574	return drm_dp_dpcd_read_data(aux, offset, buffer: ident, size: sizeof(*ident));
2575	}
2576
2577	static void drm_dp_dump_desc(struct drm_dp_aux *aux,
2578	const char *device_name, const struct drm_dp_desc *desc)
2579	{
2580	const struct drm_dp_dpcd_ident *ident = &desc->ident;
2581
2582	drm_dbg_kms(aux->drm_dev,
2583	"%s: %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
2584	aux->name, device_name,
2585	(int)sizeof(ident->oui), ident->oui,
2586	(int)strnlen(ident->device_id, sizeof(ident->device_id)), ident->device_id,
2587	ident->hw_rev >> 4, ident->hw_rev & 0xf,
2588	ident->sw_major_rev, ident->sw_minor_rev,
2589	desc->quirks);
2590	}
2591
2592	/**
2593	* drm_dp_read_desc - read sink/branch descriptor from DPCD
2594	* @aux: DisplayPort AUX channel
2595	* @desc: Device descriptor to fill from DPCD
2596	* @is_branch: true for branch devices, false for sink devices
2597	*
2598	* Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
2599	* identification.
2600	*
2601	* Returns 0 on success or a negative error code on failure.
2602	*/
2603	int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
2604	bool is_branch)
2605	{
2606	struct drm_dp_dpcd_ident *ident = &desc->ident;
2607	unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
2608	int ret;
2609
2610	ret = drm_dp_read_ident(aux, offset, ident);
2611	if (ret < 0)
2612	return ret;
2613
2614	desc->quirks = drm_dp_get_quirks(ident, is_branch);
2615
2616	drm_dp_dump_desc(aux, device_name: is_branch ? "DP branch" : "DP sink", desc);
2617
2618	return 0;
2619	}
2620	EXPORT_SYMBOL(drm_dp_read_desc);
2621
2622	/**
2623	* drm_dp_dump_lttpr_desc - read and dump the DPCD descriptor for an LTTPR PHY
2624	* @aux: DisplayPort AUX channel
2625	* @dp_phy: LTTPR PHY instance
2626	*
2627	* Read the DPCD LTTPR PHY descriptor for @dp_phy and print a debug message
2628	* with its details to dmesg.
2629	*
2630	* Returns 0 on success or a negative error code on failure.
2631	*/
2632	int drm_dp_dump_lttpr_desc(struct drm_dp_aux *aux, enum drm_dp_phy dp_phy)
2633	{
2634	struct drm_dp_desc desc = {};
2635	int ret;
2636
2637	if (drm_WARN_ON(aux->drm_dev, dp_phy < DP_PHY_LTTPR1 || dp_phy > DP_MAX_LTTPR_COUNT))
2638	return -EINVAL;
2639
2640	ret = drm_dp_read_ident(aux, DP_OUI_PHY_REPEATER(dp_phy), ident: &desc.ident);
2641	if (ret < 0)
2642	return ret;
2643
2644	drm_dp_dump_desc(aux, device_name: drm_dp_phy_name(dp_phy), desc: &desc);
2645
2646	return 0;
2647	}
2648	EXPORT_SYMBOL(drm_dp_dump_lttpr_desc);
2649
2650	/**
2651	* drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
2652	* @dsc_dpcd: DSC capabilities from DPCD
2653	*
2654	* Returns the bpp precision supported by the DP sink.
2655	*/
2656	u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
2657	{
2658	u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];
2659
2660	switch (bpp_increment_dpcd & DP_DSC_BITS_PER_PIXEL_MASK) {
2661	case DP_DSC_BITS_PER_PIXEL_1_16:
2662	return 16;
2663	case DP_DSC_BITS_PER_PIXEL_1_8:
2664	return 8;
2665	case DP_DSC_BITS_PER_PIXEL_1_4:
2666	return 4;
2667	case DP_DSC_BITS_PER_PIXEL_1_2:
2668	return 2;
2669	case DP_DSC_BITS_PER_PIXEL_1_1:
2670	return 1;
2671	}
2672
2673	return 0;
2674	}
2675	EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
2676
2677	/**
2678	* drm_dp_dsc_sink_max_slice_count() - Get the max slice count
2679	* supported by the DSC sink.
2680	* @dsc_dpcd: DSC capabilities from DPCD
2681	* @is_edp: true if its eDP, false for DP
2682	*
2683	* Read the slice capabilities DPCD register from DSC sink to get
2684	* the maximum slice count supported. This is used to populate
2685	* the DSC parameters in the &struct drm_dsc_config by the driver.
2686	* Driver creates an infoframe using these parameters to populate
2687	* &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2688	* infoframe using the helper function drm_dsc_pps_infoframe_pack()
2689	*
2690	* Returns:
2691	* Maximum slice count supported by DSC sink or 0 its invalid
2692	*/
2693	u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2694	bool is_edp)
2695	{
2696	u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
2697
2698	if (is_edp) {
2699	/* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */
2700	if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2701	return 4;
2702	if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2703	return 2;
2704	if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2705	return 1;
2706	} else {
2707	/* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
2708	u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
2709
2710	if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
2711	return 24;
2712	if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
2713	return 20;
2714	if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
2715	return 16;
2716	if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
2717	return 12;
2718	if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
2719	return 10;
2720	if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
2721	return 8;
2722	if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
2723	return 6;
2724	if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2725	return 4;
2726	if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2727	return 2;
2728	if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2729	return 1;
2730	}
2731
2732	return 0;
2733	}
2734	EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
2735
2736	/**
2737	* drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
2738	* @dsc_dpcd: DSC capabilities from DPCD
2739	*
2740	* Read the DSC DPCD register to parse the line buffer depth in bits which is
2741	* number of bits of precision within the decoder line buffer supported by
2742	* the DSC sink. This is used to populate the DSC parameters in the
2743	* &struct drm_dsc_config by the driver.
2744	* Driver creates an infoframe using these parameters to populate
2745	* &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2746	* infoframe using the helper function drm_dsc_pps_infoframe_pack()
2747	*
2748	* Returns:
2749	* Line buffer depth supported by DSC panel or 0 its invalid
2750	*/
2751	u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
2752	{
2753	u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT];
2754
2755	switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
2756	case DP_DSC_LINE_BUF_BIT_DEPTH_9:
2757	return 9;
2758	case DP_DSC_LINE_BUF_BIT_DEPTH_10:
2759	return 10;
2760	case DP_DSC_LINE_BUF_BIT_DEPTH_11:
2761	return 11;
2762	case DP_DSC_LINE_BUF_BIT_DEPTH_12:
2763	return 12;
2764	case DP_DSC_LINE_BUF_BIT_DEPTH_13:
2765	return 13;
2766	case DP_DSC_LINE_BUF_BIT_DEPTH_14:
2767	return 14;
2768	case DP_DSC_LINE_BUF_BIT_DEPTH_15:
2769	return 15;
2770	case DP_DSC_LINE_BUF_BIT_DEPTH_16:
2771	return 16;
2772	case DP_DSC_LINE_BUF_BIT_DEPTH_8:
2773	return 8;
2774	}
2775
2776	return 0;
2777	}
2778	EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
2779
2780	/**
2781	* drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
2782	* values supported by the DSC sink.
2783	* @dsc_dpcd: DSC capabilities from DPCD
2784	* @dsc_bpc: An array to be filled by this helper with supported
2785	* input bpcs.
2786	*
2787	* Read the DSC DPCD from the sink device to parse the supported bits per
2788	* component values. This is used to populate the DSC parameters
2789	* in the &struct drm_dsc_config by the driver.
2790	* Driver creates an infoframe using these parameters to populate
2791	* &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2792	* infoframe using the helper function drm_dsc_pps_infoframe_pack()
2793	*
2794	* Returns:
2795	* Number of input BPC values parsed from the DPCD
2796	*/
2797	int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2798	u8 dsc_bpc[3])
2799	{
2800	int num_bpc = 0;
2801	u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
2802
2803	if (!drm_dp_sink_supports_dsc(dsc_dpcd))
2804	return 0;
2805
2806	if (color_depth & DP_DSC_12_BPC)
2807	dsc_bpc[num_bpc++] = 12;
2808	if (color_depth & DP_DSC_10_BPC)
2809	dsc_bpc[num_bpc++] = 10;
2810
2811	/* A DP DSC Sink device shall support 8 bpc. */
2812	dsc_bpc[num_bpc++] = 8;
2813
2814	return num_bpc;
2815	}
2816	EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
2817
2818	static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux,
2819	const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
2820	u8 *buf, int buf_size)
2821	{
2822	/*
2823	* At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns
2824	* corrupted values when reading from the 0xF0000- range with a block
2825	* size bigger than 1.
2826	*/
2827	int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;
2828	int offset;
2829	int ret;
2830
2831	for (offset = 0; offset < buf_size; offset += block_size) {
2832	ret = drm_dp_dpcd_read_data(aux,
2833	offset: address + offset,
2834	buffer: &buf[offset], size: block_size);
2835	if (ret < 0)
2836	return ret;
2837	}
2838
2839	return 0;
2840	}
2841
2842	/**
2843	* drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
2844	* @aux: DisplayPort AUX channel
2845	* @dpcd: DisplayPort configuration data
2846	* @caps: buffer to return the capability info in
2847	*
2848	* Read capabilities common to all LTTPRs.
2849	*
2850	* Returns 0 on success or a negative error code on failure.
2851	*/
2852	int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
2853	const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2854	u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2855	{
2856	return drm_dp_read_lttpr_regs(aux, dpcd,
2857	DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
2858	buf: caps, DP_LTTPR_COMMON_CAP_SIZE);
2859	}
2860	EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
2861
2862	/**
2863	* drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
2864	* @aux: DisplayPort AUX channel
2865	* @dpcd: DisplayPort configuration data
2866	* @dp_phy: LTTPR PHY to read the capabilities for
2867	* @caps: buffer to return the capability info in
2868	*
2869	* Read the capabilities for the given LTTPR PHY.
2870	*
2871	* Returns 0 on success or a negative error code on failure.
2872	*/
2873	int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
2874	const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2875	enum drm_dp_phy dp_phy,
2876	u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2877	{
2878	return drm_dp_read_lttpr_regs(aux, dpcd,
2879	DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
2880	buf: caps, DP_LTTPR_PHY_CAP_SIZE);
2881	}
2882	EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
2883
2884	static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r)
2885	{
2886	return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
2887	}
2888
2889	/**
2890	* drm_dp_lttpr_count - get the number of detected LTTPRs
2891	* @caps: LTTPR common capabilities
2892	*
2893	* Get the number of detected LTTPRs from the LTTPR common capabilities info.
2894	*
2895	* Returns:
2896	* -ERANGE if more than supported number (8) of LTTPRs are detected
2897	* -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value
2898	* otherwise the number of detected LTTPRs
2899	*/
2900	int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2901	{
2902	u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT);
2903
2904	switch (hweight8(count)) {
2905	case 0:
2906	return 0;
2907	case 1:
2908	return 8 - ilog2(count);
2909	case 8:
2910	return -ERANGE;
2911	default:
2912	return -EINVAL;
2913	}
2914	}
2915	EXPORT_SYMBOL(drm_dp_lttpr_count);
2916
2917	/**
2918	* drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs
2919	* @caps: LTTPR common capabilities
2920	*
2921	* Returns the maximum link rate supported by all detected LTTPRs.
2922	*/
2923	int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2924	{
2925	u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER);
2926
2927	return drm_dp_bw_code_to_link_rate(rate);
2928	}
2929	EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate);
2930
2931	/**
2932	* drm_dp_lttpr_set_transparent_mode() - set the LTTPR in transparent mode
2933	* @aux: DisplayPort AUX channel
2934	* @enable: Enable or disable transparent mode
2935	*
2936	* Returns: 0 on success or a negative error code on failure.
2937	*/
2938	int drm_dp_lttpr_set_transparent_mode(struct drm_dp_aux *aux, bool enable)
2939	{
2940	u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT :
2941	DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
2942	int ret = drm_dp_dpcd_writeb(aux, DP_PHY_REPEATER_MODE, value: val);
2943
2944	if (ret < 0)
2945	return ret;
2946
2947	return (ret == 1) ? 0 : -EIO;
2948	}
2949	EXPORT_SYMBOL(drm_dp_lttpr_set_transparent_mode);
2950
2951	/**
2952	* drm_dp_lttpr_init() - init LTTPR transparency mode according to DP standard
2953	* @aux: DisplayPort AUX channel
2954	* @lttpr_count: Number of LTTPRs. Between 0 and 8, according to DP standard.
2955	* Negative error code for any non-valid number.
2956	* See drm_dp_lttpr_count().
2957	*
2958	* Returns: 0 on success or a negative error code on failure.
2959	*/
2960	int drm_dp_lttpr_init(struct drm_dp_aux *aux, int lttpr_count)
2961	{
2962	int ret;
2963
2964	if (!lttpr_count)
2965	return 0;
2966
2967	/*
2968	* See DP Standard v2.0 3.6.6.1 about the explicit disabling of
2969	* non-transparent mode and the disable->enable non-transparent mode
2970	* sequence.
2971	*/
2972	ret = drm_dp_lttpr_set_transparent_mode(aux, true);
2973	if (ret)
2974	return ret;
2975
2976	if (lttpr_count < 0)
2977	return -ENODEV;
2978
2979	if (drm_dp_lttpr_set_transparent_mode(aux, false)) {
2980	/*
2981	* Roll-back to transparent mode if setting non-transparent
2982	* mode has failed
2983	*/
2984	drm_dp_lttpr_set_transparent_mode(aux, true);
2985	return -EINVAL;
2986	}
2987
2988	return 0;
2989	}
2990	EXPORT_SYMBOL(drm_dp_lttpr_init);
2991
2992	/**
2993	* drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs
2994	* @caps: LTTPR common capabilities
2995	*
2996	* Returns the maximum lane count supported by all detected LTTPRs.
2997	*/
2998	int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2999	{
3000	u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER);
3001
3002	return max_lanes & DP_MAX_LANE_COUNT_MASK;
3003	}
3004	EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count);
3005
3006	/**
3007	* drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support
3008	* @caps: LTTPR PHY capabilities
3009	*
3010	* Returns true if the @caps for an LTTPR TX PHY indicate support for
3011	* voltage swing level 3.
3012	*/
3013	bool
3014	drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
3015	{
3016	u8 txcap = dp_lttpr_phy_cap(phy_cap: caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
3017
3018	return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED;
3019	}
3020	EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported);
3021
3022	/**
3023	* drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support
3024	* @caps: LTTPR PHY capabilities
3025	*
3026	* Returns true if the @caps for an LTTPR TX PHY indicate support for
3027	* pre-emphasis level 3.
3028	*/
3029	bool
3030	drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
3031	{
3032	u8 txcap = dp_lttpr_phy_cap(phy_cap: caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
3033
3034	return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED;
3035	}
3036	EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported);
3037
3038	/**
3039	* drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
3040	* @aux: DisplayPort AUX channel
3041	* @data: DP phy compliance test parameters.
3042	*
3043	* Returns 0 on success or a negative error code on failure.
3044	*/
3045	int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
3046	struct drm_dp_phy_test_params *data)
3047	{
3048	int err;
3049	u8 rate, lanes;
3050
3051	err = drm_dp_dpcd_read_byte(aux, DP_TEST_LINK_RATE, valuep: &rate);
3052	if (err < 0)
3053	return err;
3054	data->link_rate = drm_dp_bw_code_to_link_rate(rate);
3055
3056	err = drm_dp_dpcd_read_byte(aux, DP_TEST_LANE_COUNT, valuep: &lanes);
3057	if (err < 0)
3058	return err;
3059	data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
3060
3061	if (lanes & DP_ENHANCED_FRAME_CAP)
3062	data->enhanced_frame_cap = true;
3063
3064	err = drm_dp_dpcd_read_byte(aux, DP_PHY_TEST_PATTERN, valuep: &data->phy_pattern);
3065	if (err < 0)
3066	return err;
3067
3068	switch (data->phy_pattern) {
3069	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
3070	err = drm_dp_dpcd_read_data(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
3071	buffer: &data->custom80, size: sizeof(data->custom80));
3072	if (err < 0)
3073	return err;
3074
3075	break;
3076	case DP_PHY_TEST_PATTERN_CP2520:
3077	err = drm_dp_dpcd_read_data(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
3078	buffer: &data->hbr2_reset,
3079	size: sizeof(data->hbr2_reset));
3080	if (err < 0)
3081	return err;
3082	}
3083
3084	return 0;
3085	}
3086	EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
3087
3088	/**
3089	* drm_dp_set_phy_test_pattern() - set the pattern to the sink.
3090	* @aux: DisplayPort AUX channel
3091	* @data: DP phy compliance test parameters.
3092	* @dp_rev: DP revision to use for compliance testing
3093	*
3094	* Returns 0 on success or a negative error code on failure.
3095	*/
3096	int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
3097	struct drm_dp_phy_test_params *data, u8 dp_rev)
3098	{
3099	int err, i;
3100	u8 test_pattern;
3101
3102	test_pattern = data->phy_pattern;
3103	if (dp_rev < 0x12) {
3104	test_pattern = (test_pattern << 2) &
3105	DP_LINK_QUAL_PATTERN_11_MASK;
3106	err = drm_dp_dpcd_write_byte(aux, DP_TRAINING_PATTERN_SET,
3107	value: test_pattern);
3108	if (err < 0)
3109	return err;
3110	} else {
3111	for (i = 0; i < data->num_lanes; i++) {
3112	err = drm_dp_dpcd_write_byte(aux,
3113	DP_LINK_QUAL_LANE0_SET + i,
3114	value: test_pattern);
3115	if (err < 0)
3116	return err;
3117	}
3118	}
3119
3120	return 0;
3121	}
3122	EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
3123
3124	static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat)
3125	{
3126	if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
3127	return "Invalid";
3128
3129	switch (pixelformat) {
3130	case DP_PIXELFORMAT_RGB:
3131	return "RGB";
3132	case DP_PIXELFORMAT_YUV444:
3133	return "YUV444";
3134	case DP_PIXELFORMAT_YUV422:
3135	return "YUV422";
3136	case DP_PIXELFORMAT_YUV420:
3137	return "YUV420";
3138	case DP_PIXELFORMAT_Y_ONLY:
3139	return "Y_ONLY";
3140	case DP_PIXELFORMAT_RAW:
3141	return "RAW";
3142	default:
3143	return "Reserved";
3144	}
3145	}
3146
3147	static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat,
3148	enum dp_colorimetry colorimetry)
3149	{
3150	if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
3151	return "Invalid";
3152
3153	switch (colorimetry) {
3154	case DP_COLORIMETRY_DEFAULT:
3155	switch (pixelformat) {
3156	case DP_PIXELFORMAT_RGB:
3157	return "sRGB";
3158	case DP_PIXELFORMAT_YUV444:
3159	case DP_PIXELFORMAT_YUV422:
3160	case DP_PIXELFORMAT_YUV420:
3161	return "BT.601";
3162	case DP_PIXELFORMAT_Y_ONLY:
3163	return "DICOM PS3.14";
3164	case DP_PIXELFORMAT_RAW:
3165	return "Custom Color Profile";
3166	default:
3167	return "Reserved";
3168	}
3169	case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
3170	switch (pixelformat) {
3171	case DP_PIXELFORMAT_RGB:
3172	return "Wide Fixed";
3173	case DP_PIXELFORMAT_YUV444:
3174	case DP_PIXELFORMAT_YUV422:
3175	case DP_PIXELFORMAT_YUV420:
3176	return "BT.709";
3177	default:
3178	return "Reserved";
3179	}
3180	case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
3181	switch (pixelformat) {
3182	case DP_PIXELFORMAT_RGB:
3183	return "Wide Float";
3184	case DP_PIXELFORMAT_YUV444:
3185	case DP_PIXELFORMAT_YUV422:
3186	case DP_PIXELFORMAT_YUV420:
3187	return "xvYCC 601";
3188	default:
3189	return "Reserved";
3190	}
3191	case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
3192	switch (pixelformat) {
3193	case DP_PIXELFORMAT_RGB:
3194	return "OpRGB";
3195	case DP_PIXELFORMAT_YUV444:
3196	case DP_PIXELFORMAT_YUV422:
3197	case DP_PIXELFORMAT_YUV420:
3198	return "xvYCC 709";
3199	default:
3200	return "Reserved";
3201	}
3202	case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
3203	switch (pixelformat) {
3204	case DP_PIXELFORMAT_RGB:
3205	return "DCI-P3";
3206	case DP_PIXELFORMAT_YUV444:
3207	case DP_PIXELFORMAT_YUV422:
3208	case DP_PIXELFORMAT_YUV420:
3209	return "sYCC 601";
3210	default:
3211	return "Reserved";
3212	}
3213	case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
3214	switch (pixelformat) {
3215	case DP_PIXELFORMAT_RGB:
3216	return "Custom Profile";
3217	case DP_PIXELFORMAT_YUV444:
3218	case DP_PIXELFORMAT_YUV422:
3219	case DP_PIXELFORMAT_YUV420:
3220	return "OpYCC 601";
3221	default:
3222	return "Reserved";
3223	}
3224	case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
3225	switch (pixelformat) {
3226	case DP_PIXELFORMAT_RGB:
3227	return "BT.2020 RGB";
3228	case DP_PIXELFORMAT_YUV444:
3229	case DP_PIXELFORMAT_YUV422:
3230	case DP_PIXELFORMAT_YUV420:
3231	return "BT.2020 CYCC";
3232	default:
3233	return "Reserved";
3234	}
3235	case DP_COLORIMETRY_BT2020_YCC:
3236	switch (pixelformat) {
3237	case DP_PIXELFORMAT_YUV444:
3238	case DP_PIXELFORMAT_YUV422:
3239	case DP_PIXELFORMAT_YUV420:
3240	return "BT.2020 YCC";
3241	default:
3242	return "Reserved";
3243	}
3244	default:
3245	return "Invalid";
3246	}
3247	}
3248
3249	static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
3250	{
3251	switch (dynamic_range) {
3252	case DP_DYNAMIC_RANGE_VESA:
3253	return "VESA range";
3254	case DP_DYNAMIC_RANGE_CTA:
3255	return "CTA range";
3256	default:
3257	return "Invalid";
3258	}
3259	}
3260
3261	static const char *dp_content_type_get_name(enum dp_content_type content_type)
3262	{
3263	switch (content_type) {
3264	case DP_CONTENT_TYPE_NOT_DEFINED:
3265	return "Not defined";
3266	case DP_CONTENT_TYPE_GRAPHICS:
3267	return "Graphics";
3268	case DP_CONTENT_TYPE_PHOTO:
3269	return "Photo";
3270	case DP_CONTENT_TYPE_VIDEO:
3271	return "Video";
3272	case DP_CONTENT_TYPE_GAME:
3273	return "Game";
3274	default:
3275	return "Reserved";
3276	}
3277	}
3278
3279	void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc)
3280	{
3281	drm_printf(p, f: "DP SDP: VSC, revision %u, length %u\n",
3282	vsc->revision, vsc->length);
3283	drm_printf(p, f: " pixelformat: %s\n",
3284	dp_pixelformat_get_name(pixelformat: vsc->pixelformat));
3285	drm_printf(p, f: " colorimetry: %s\n",
3286	dp_colorimetry_get_name(pixelformat: vsc->pixelformat, colorimetry: vsc->colorimetry));
3287	drm_printf(p, f: " bpc: %u\n", vsc->bpc);
3288	drm_printf(p, f: " dynamic range: %s\n",
3289	dp_dynamic_range_get_name(dynamic_range: vsc->dynamic_range));
3290	drm_printf(p, f: " content type: %s\n",
3291	dp_content_type_get_name(content_type: vsc->content_type));
3292	}
3293	EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
3294
3295	void drm_dp_as_sdp_log(struct drm_printer *p, const struct drm_dp_as_sdp *as_sdp)
3296	{
3297	drm_printf(p, f: "DP SDP: AS_SDP, revision %u, length %u\n",
3298	as_sdp->revision, as_sdp->length);
3299	drm_printf(p, f: " vtotal: %d\n", as_sdp->vtotal);
3300	drm_printf(p, f: " target_rr: %d\n", as_sdp->target_rr);
3301	drm_printf(p, f: " duration_incr_ms: %d\n", as_sdp->duration_incr_ms);
3302	drm_printf(p, f: " duration_decr_ms: %d\n", as_sdp->duration_decr_ms);
3303	drm_printf(p, f: " operation_mode: %d\n", as_sdp->mode);
3304	}
3305	EXPORT_SYMBOL(drm_dp_as_sdp_log);
3306
3307	/**
3308	* drm_dp_as_sdp_supported() - check if adaptive sync sdp is supported
3309	* @aux: DisplayPort AUX channel
3310	* @dpcd: DisplayPort configuration data
3311	*
3312	* Returns true if adaptive sync sdp is supported, else returns false
3313	*/
3314	bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
3315	{
3316	u8 rx_feature;
3317
3318	if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13)
3319	return false;
3320
3321	if (drm_dp_dpcd_read_byte(aux, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1,
3322	valuep: &rx_feature) < 0) {
3323	drm_dbg_dp(aux->drm_dev,
3324	"Failed to read DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1\n");
3325	return false;
3326	}
3327
3328	return (rx_feature & DP_ADAPTIVE_SYNC_SDP_SUPPORTED);
3329	}
3330	EXPORT_SYMBOL(drm_dp_as_sdp_supported);
3331
3332	/**
3333	* drm_dp_vsc_sdp_supported() - check if vsc sdp is supported
3334	* @aux: DisplayPort AUX channel
3335	* @dpcd: DisplayPort configuration data
3336	*
3337	* Returns true if vsc sdp is supported, else returns false
3338	*/
3339	bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE])
3340	{
3341	u8 rx_feature;
3342
3343	if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13)
3344	return false;
3345
3346	if (drm_dp_dpcd_read_byte(aux, DP_DPRX_FEATURE_ENUMERATION_LIST, valuep: &rx_feature) < 0) {
3347	drm_dbg_dp(aux->drm_dev, "failed to read DP_DPRX_FEATURE_ENUMERATION_LIST\n");
3348	return false;
3349	}
3350
3351	return (rx_feature & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED);
3352	}
3353	EXPORT_SYMBOL(drm_dp_vsc_sdp_supported);
3354
3355	/**
3356	* drm_dp_vsc_sdp_pack() - pack a given vsc sdp into generic dp_sdp
3357	* @vsc: vsc sdp initialized according to its purpose as defined in
3358	* table 2-118 - table 2-120 in DP 1.4a specification
3359	* @sdp: valid handle to the generic dp_sdp which will be packed
3360	*
3361	* Returns length of sdp on success and error code on failure
3362	*/
3363	ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
3364	struct dp_sdp *sdp)
3365	{
3366	size_t length = sizeof(struct dp_sdp);
3367
3368	memset(sdp, 0, sizeof(struct dp_sdp));
3369
3370	/*
3371	* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
3372	* VSC SDP Header Bytes
3373	*/
3374	sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
3375	sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
3376	sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
3377	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
3378
3379	if (vsc->revision == 0x6) {
3380	sdp->db[0] = 1;
3381	sdp->db[3] = 1;
3382	}
3383
3384	/*
3385	* Revision 0x5 and revision 0x7 supports Pixel Encoding/Colorimetry
3386	* Format as per DP 1.4a spec and DP 2.0 respectively.
3387	*/
3388	if (!(vsc->revision == 0x5 || vsc->revision == 0x7))
3389	goto out;
3390
3391	/* VSC SDP Payload for DB16 through DB18 */
3392	/* Pixel Encoding and Colorimetry Formats */
3393	sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
3394	sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
3395
3396	switch (vsc->bpc) {
3397	case 6:
3398	/* 6bpc: 0x0 */
3399	break;
3400	case 8:
3401	sdp->db[17] = 0x1; /* DB17[3:0] */
3402	break;
3403	case 10:
3404	sdp->db[17] = 0x2;
3405	break;
3406	case 12:
3407	sdp->db[17] = 0x3;
3408	break;
3409	case 16:
3410	sdp->db[17] = 0x4;
3411	break;
3412	default:
3413	WARN(1, "Missing case %d\n", vsc->bpc);
3414	return -EINVAL;
3415	}
3416
3417	/* Dynamic Range and Component Bit Depth */
3418	if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
3419	sdp->db[17] |= 0x80; /* DB17[7] */
3420
3421	/* Content Type */
3422	sdp->db[18] = vsc->content_type & 0x7;
3423
3424	out:
3425	return length;
3426	}
3427	EXPORT_SYMBOL(drm_dp_vsc_sdp_pack);
3428
3429	/**
3430	* drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON
3431	* @dpcd: DisplayPort configuration data
3432	* @port_cap: port capabilities
3433	*
3434	* Returns maximum frl bandwidth supported by PCON in GBPS,
3435	* returns 0 if not supported.
3436	*/
3437	int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
3438	const u8 port_cap[4])
3439	{
3440	int bw;
3441	u8 buf;
3442
3443	buf = port_cap[2];
3444	bw = buf & DP_PCON_MAX_FRL_BW;
3445
3446	switch (bw) {
3447	case DP_PCON_MAX_9GBPS:
3448	return 9;
3449	case DP_PCON_MAX_18GBPS:
3450	return 18;
3451	case DP_PCON_MAX_24GBPS:
3452	return 24;
3453	case DP_PCON_MAX_32GBPS:
3454	return 32;
3455	case DP_PCON_MAX_40GBPS:
3456	return 40;
3457	case DP_PCON_MAX_48GBPS:
3458	return 48;
3459	case DP_PCON_MAX_0GBPS:
3460	default:
3461	return 0;
3462	}
3463
3464	return 0;
3465	}
3466	EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw);
3467
3468	/**
3469	* drm_dp_pcon_frl_prepare() - Prepare PCON for FRL.
3470	* @aux: DisplayPort AUX channel
3471	* @enable_frl_ready_hpd: Configure DP_PCON_ENABLE_HPD_READY.
3472	*
3473	* Returns 0 if success, else returns negative error code.
3474	*/
3475	int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd)
3476	{
3477	u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE |
3478	DP_PCON_ENABLE_LINK_FRL_MODE;
3479
3480	if (enable_frl_ready_hpd)
3481	buf |= DP_PCON_ENABLE_HPD_READY;
3482
3483	return drm_dp_dpcd_write_byte(aux, DP_PCON_HDMI_LINK_CONFIG_1, value: buf);
3484	}
3485	EXPORT_SYMBOL(drm_dp_pcon_frl_prepare);
3486
3487	/**
3488	* drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL
3489	* @aux: DisplayPort AUX channel
3490	*
3491	* Returns true if success, else returns false.
3492	*/
3493	bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux)
3494	{
3495	int ret;
3496	u8 buf;
3497
3498	ret = drm_dp_dpcd_read_byte(aux, DP_PCON_HDMI_TX_LINK_STATUS, valuep: &buf);
3499	if (ret < 0)
3500	return false;
3501
3502	if (buf & DP_PCON_FRL_READY)
3503	return true;
3504
3505	return false;
3506	}
3507	EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
3508
3509	/**
3510	* drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
3511	* @aux: DisplayPort AUX channel
3512	* @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
3513	* @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
3514	* In Concurrent Mode, the FRL link bring up can be done along with
3515	* DP Link training. In Sequential mode, the FRL link bring up is done prior to
3516	* the DP Link training.
3517	*
3518	* Returns 0 if success, else returns negative error code.
3519	*/
3520
3521	int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
3522	u8 frl_mode)
3523	{
3524	int ret;
3525	u8 buf;
3526
3527	ret = drm_dp_dpcd_read_byte(aux, DP_PCON_HDMI_LINK_CONFIG_1, valuep: &buf);
3528	if (ret < 0)
3529	return ret;
3530
3531	if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK)
3532	buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
3533	else
3534	buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
3535
3536	switch (max_frl_gbps) {
3537	case 9:
3538	buf |= DP_PCON_ENABLE_MAX_BW_9GBPS;
3539	break;
3540	case 18:
3541	buf |= DP_PCON_ENABLE_MAX_BW_18GBPS;
3542	break;
3543	case 24:
3544	buf |= DP_PCON_ENABLE_MAX_BW_24GBPS;
3545	break;
3546	case 32:
3547	buf |= DP_PCON_ENABLE_MAX_BW_32GBPS;
3548	break;
3549	case 40:
3550	buf |= DP_PCON_ENABLE_MAX_BW_40GBPS;
3551	break;
3552	case 48:
3553	buf |= DP_PCON_ENABLE_MAX_BW_48GBPS;
3554	break;
3555	case 0:
3556	buf |= DP_PCON_ENABLE_MAX_BW_0GBPS;
3557	break;
3558	default:
3559	return -EINVAL;
3560	}
3561
3562	return drm_dp_dpcd_write_byte(aux, DP_PCON_HDMI_LINK_CONFIG_1, value: buf);
3563	}
3564	EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
3565
3566	/**
3567	* drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
3568	* @aux: DisplayPort AUX channel
3569	* @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
3570	* @frl_type : FRL training type, can be Extended, or Normal.
3571	* In Normal FRL training, the PCON tries each frl bw from the max_frl_mask
3572	* starting from min, and stops when link training is successful. In Extended
3573	* FRL training, all frl bw selected in the mask are trained by the PCON.
3574	*
3575	* Returns 0 if success, else returns negative error code.
3576	*/
3577	int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
3578	u8 frl_type)
3579	{
3580	int ret;
3581	u8 buf = max_frl_mask;
3582
3583	if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED)
3584	buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
3585	else
3586	buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
3587
3588	return drm_dp_dpcd_write_byte(aux, DP_PCON_HDMI_LINK_CONFIG_2, value: buf);
3589	if (ret < 0)
3590	return ret;
3591
3592	return 0;
3593	}
3594	EXPORT_SYMBOL(drm_dp_pcon_frl_configure_2);
3595
3596	/**
3597	* drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration.
3598	* @aux: DisplayPort AUX channel
3599	*
3600	* Returns 0 if success, else returns negative error code.
3601	*/
3602	int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux)
3603	{
3604	return drm_dp_dpcd_write_byte(aux, DP_PCON_HDMI_LINK_CONFIG_1, value: 0x0);
3605	}
3606	EXPORT_SYMBOL(drm_dp_pcon_reset_frl_config);
3607
3608	/**
3609	* drm_dp_pcon_frl_enable() - Enable HDMI link through FRL
3610	* @aux: DisplayPort AUX channel
3611	*
3612	* Returns 0 if success, else returns negative error code.
3613	*/
3614	int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux)
3615	{
3616	int ret;
3617	u8 buf = 0;
3618
3619	ret = drm_dp_dpcd_read_byte(aux, DP_PCON_HDMI_LINK_CONFIG_1, valuep: &buf);
3620	if (ret < 0)
3621	return ret;
3622	if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE)) {
3623	drm_dbg_kms(aux->drm_dev, "%s: PCON in Autonomous mode, can't enable FRL\n",
3624	aux->name);
3625	return -EINVAL;
3626	}
3627	buf |= DP_PCON_ENABLE_HDMI_LINK;
3628	return drm_dp_dpcd_write_byte(aux, DP_PCON_HDMI_LINK_CONFIG_1, value: buf);
3629	}
3630	EXPORT_SYMBOL(drm_dp_pcon_frl_enable);
3631
3632	/**
3633	* drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active.
3634	* @aux: DisplayPort AUX channel
3635	*
3636	* Returns true if link is active else returns false.
3637	*/
3638	bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux)
3639	{
3640	u8 buf;
3641	int ret;
3642
3643	ret = drm_dp_dpcd_read_byte(aux, DP_PCON_HDMI_TX_LINK_STATUS, valuep: &buf);
3644	if (ret < 0)
3645	return false;
3646
3647	return buf & DP_PCON_HDMI_TX_LINK_ACTIVE;
3648	}
3649	EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_active);
3650
3651	/**
3652	* drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE
3653	* @aux: DisplayPort AUX channel
3654	* @frl_trained_mask: pointer to store bitmask of the trained bw configuration.
3655	* Valid only if the MODE returned is FRL. For Normal Link training mode
3656	* only 1 of the bits will be set, but in case of Extended mode, more than
3657	* one bits can be set.
3658	*
3659	* Returns the link mode : TMDS or FRL on success, else returns negative error
3660	* code.
3661	*/
3662	int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask)
3663	{
3664	u8 buf;
3665	int mode;
3666	int ret;
3667
3668	ret = drm_dp_dpcd_read_byte(aux, DP_PCON_HDMI_POST_FRL_STATUS, valuep: &buf);
3669	if (ret < 0)
3670	return ret;
3671
3672	mode = buf & DP_PCON_HDMI_LINK_MODE;
3673
3674	if (frl_trained_mask && DP_PCON_HDMI_MODE_FRL == mode)
3675	*frl_trained_mask = (buf & DP_PCON_HDMI_FRL_TRAINED_BW) >> 1;
3676
3677	return mode;
3678	}
3679	EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode);
3680
3681	/**
3682	* drm_dp_pcon_hdmi_frl_link_error_count() - print the error count per lane
3683	* during link failure between PCON and HDMI sink
3684	* @aux: DisplayPort AUX channel
3685	* @connector: DRM connector
3686	* code.
3687	**/
3688
3689	void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
3690	struct drm_connector *connector)
3691	{
3692	u8 buf, error_count;
3693	int i, num_error;
3694	struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3695
3696	for (i = 0; i < hdmi->max_lanes; i++) {
3697	if (drm_dp_dpcd_read_byte(aux, DP_PCON_HDMI_ERROR_STATUS_LN0 + i, valuep: &buf) < 0)
3698	return;
3699
3700	error_count = buf & DP_PCON_HDMI_ERROR_COUNT_MASK;
3701	switch (error_count) {
3702	case DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS:
3703	num_error = 100;
3704	break;
3705	case DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS:
3706	num_error = 10;
3707	break;
3708	case DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS:
3709	num_error = 3;
3710	break;
3711	default:
3712	num_error = 0;
3713	}
3714
3715	drm_err(aux->drm_dev, "%s: More than %d errors since the last read for lane %d",
3716	aux->name, num_error, i);
3717	}
3718	}
3719	EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count);
3720
3721	/*
3722	* drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2
3723	* @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3724	*
3725	* Returns true is PCON encoder is DSC 1.2 else returns false.
3726	*/
3727	bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3728	{
3729	u8 buf;
3730	u8 major_v, minor_v;
3731
3732	buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION - DP_PCON_DSC_ENCODER];
3733	major_v = (buf & DP_PCON_DSC_MAJOR_MASK) >> DP_PCON_DSC_MAJOR_SHIFT;
3734	minor_v = (buf & DP_PCON_DSC_MINOR_MASK) >> DP_PCON_DSC_MINOR_SHIFT;
3735
3736	if (major_v == 1 && minor_v == 2)
3737	return true;
3738
3739	return false;
3740	}
3741	EXPORT_SYMBOL(drm_dp_pcon_enc_is_dsc_1_2);
3742
3743	/*
3744	* drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder
3745	* @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3746	*
3747	* Returns maximum no. of slices supported by the PCON DSC Encoder.
3748	*/
3749	int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3750	{
3751	u8 slice_cap1, slice_cap2;
3752
3753	slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 - DP_PCON_DSC_ENCODER];
3754	slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 - DP_PCON_DSC_ENCODER];
3755
3756	if (slice_cap2 & DP_PCON_DSC_24_PER_DSC_ENC)
3757	return 24;
3758	if (slice_cap2 & DP_PCON_DSC_20_PER_DSC_ENC)
3759	return 20;
3760	if (slice_cap2 & DP_PCON_DSC_16_PER_DSC_ENC)
3761	return 16;
3762	if (slice_cap1 & DP_PCON_DSC_12_PER_DSC_ENC)
3763	return 12;
3764	if (slice_cap1 & DP_PCON_DSC_10_PER_DSC_ENC)
3765	return 10;
3766	if (slice_cap1 & DP_PCON_DSC_8_PER_DSC_ENC)
3767	return 8;
3768	if (slice_cap1 & DP_PCON_DSC_6_PER_DSC_ENC)
3769	return 6;
3770	if (slice_cap1 & DP_PCON_DSC_4_PER_DSC_ENC)
3771	return 4;
3772	if (slice_cap1 & DP_PCON_DSC_2_PER_DSC_ENC)
3773	return 2;
3774	if (slice_cap1 & DP_PCON_DSC_1_PER_DSC_ENC)
3775	return 1;
3776
3777	return 0;
3778	}
3779	EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slices);
3780
3781	/*
3782	* drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder
3783	* @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3784	*
3785	* Returns maximum width of the slices in pixel width i.e. no. of pixels x 320.
3786	*/
3787	int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3788	{
3789	u8 buf;
3790
3791	buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH - DP_PCON_DSC_ENCODER];
3792
3793	return buf * DP_DSC_SLICE_WIDTH_MULTIPLIER;
3794	}
3795	EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slice_width);
3796
3797	/*
3798	* drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder
3799	* @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3800	*
3801	* Returns the bpp precision supported by the PCON encoder.
3802	*/
3803	int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3804	{
3805	u8 buf;
3806
3807	buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR - DP_PCON_DSC_ENCODER];
3808
3809	switch (buf & DP_PCON_DSC_BPP_INCR_MASK) {
3810	case DP_PCON_DSC_ONE_16TH_BPP:
3811	return 16;
3812	case DP_PCON_DSC_ONE_8TH_BPP:
3813	return 8;
3814	case DP_PCON_DSC_ONE_4TH_BPP:
3815	return 4;
3816	case DP_PCON_DSC_ONE_HALF_BPP:
3817	return 2;
3818	case DP_PCON_DSC_ONE_BPP:
3819	return 1;
3820	}
3821
3822	return 0;
3823	}
3824	EXPORT_SYMBOL(drm_dp_pcon_dsc_bpp_incr);
3825
3826	static
3827	int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config)
3828	{
3829	u8 buf;
3830	int ret;
3831
3832	ret = drm_dp_dpcd_read_byte(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, valuep: &buf);
3833	if (ret < 0)
3834	return ret;
3835
3836	buf |= DP_PCON_ENABLE_DSC_ENCODER;
3837
3838	if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER) {
3839	buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK;
3840	buf |= pps_buf_config << 2;
3841	}
3842
3843	return drm_dp_dpcd_write_byte(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, value: buf);
3844	}
3845
3846	/**
3847	* drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters
3848	* for DSC1.2 between PCON & HDMI2.1 sink
3849	* @aux: DisplayPort AUX channel
3850	*
3851	* Returns 0 on success, else returns negative error code.
3852	*/
3853	int drm_dp_pcon_pps_default(struct drm_dp_aux *aux)
3854	{
3855	return drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_DISABLED);
3856	}
3857	EXPORT_SYMBOL(drm_dp_pcon_pps_default);
3858
3859	/**
3860	* drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for
3861	* HDMI sink
3862	* @aux: DisplayPort AUX channel
3863	* @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON.
3864	*
3865	* Returns 0 on success, else returns negative error code.
3866	*/
3867	int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128])
3868	{
3869	int ret;
3870
3871	ret = drm_dp_dpcd_write_data(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE, buffer: &pps_buf, size: 128);
3872	if (ret < 0)
3873	return ret;
3874
3875	return drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
3876	}
3877	EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf);
3878
3879	/*
3880	* drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder
3881	* override registers
3882	* @aux: DisplayPort AUX channel
3883	* @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height,
3884	* bits_per_pixel.
3885	*
3886	* Returns 0 on success, else returns negative error code.
3887	*/
3888	int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6])
3889	{
3890	int ret;
3891
3892	ret = drm_dp_dpcd_write_data(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, buffer: &pps_param[0], size: 2);
3893	if (ret < 0)
3894	return ret;
3895	ret = drm_dp_dpcd_write_data(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, buffer: &pps_param[2], size: 2);
3896	if (ret < 0)
3897	return ret;
3898	ret = drm_dp_dpcd_write_data(aux, DP_PCON_HDMI_PPS_OVRD_BPP, buffer: &pps_param[4], size: 2);
3899	if (ret < 0)
3900	return ret;
3901
3902	return drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
3903	}
3904	EXPORT_SYMBOL(drm_dp_pcon_pps_override_param);
3905
3906	/*
3907	* drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert RGB to Ycbcr
3908	* @aux: displayPort AUX channel
3909	* @color_spc: Color-space/s for which conversion is to be enabled, 0 for disable.
3910	*
3911	* Returns 0 on success, else returns negative error code.
3912	*/
3913	int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc)
3914	{
3915	int ret;
3916	u8 buf;
3917
3918	ret = drm_dp_dpcd_read_byte(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, valuep: &buf);
3919	if (ret < 0)
3920	return ret;
3921
3922	if (color_spc & DP_CONVERSION_RGB_YCBCR_MASK)
3923	buf |= (color_spc & DP_CONVERSION_RGB_YCBCR_MASK);
3924	else
3925	buf &= ~DP_CONVERSION_RGB_YCBCR_MASK;
3926
3927	return drm_dp_dpcd_write_byte(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, value: buf);
3928	}
3929	EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);
3930
3931	/**
3932	* drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX
3933	* @aux: The DP AUX channel to use
3934	* @bl: Backlight capability info from drm_edp_backlight_init()
3935	* @level: The brightness level to set
3936	*
3937	* Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must
3938	* already have been enabled by the driver by calling drm_edp_backlight_enable().
3939	*
3940	* Returns: %0 on success, negative error code on failure
3941	*/
3942	int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
3943	u16 level)
3944	{
3945	int ret;
3946	u8 buf[2] = { 0 };
3947
3948	/* The panel uses the PWM for controlling brightness levels */
3949	if (!bl->aux_set)
3950	return 0;
3951
3952	if (bl->lsb_reg_used) {
3953	buf[0] = (level & 0xff00) >> 8;
3954	buf[1] = (level & 0x00ff);
3955	} else {
3956	buf[0] = level;
3957	}
3958
3959	ret = drm_dp_dpcd_write_data(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buffer: buf, size: sizeof(buf));
3960	if (ret < 0) {
3961	drm_err(aux->drm_dev,
3962	"%s: Failed to write aux backlight level: %d\n",
3963	aux->name, ret);
3964	return ret;
3965	}
3966
3967	return 0;
3968	}
3969	EXPORT_SYMBOL(drm_edp_backlight_set_level);
3970
3971	static int
3972	drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
3973	bool enable)
3974	{
3975	int ret;
3976	u8 buf;
3977
3978	/* This panel uses the EDP_BL_PWR GPIO for enablement */
3979	if (!bl->aux_enable)
3980	return 0;
3981
3982	ret = drm_dp_dpcd_read_byte(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, valuep: &buf);
3983	if (ret < 0) {
3984	drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n",
3985	aux->name, ret);
3986	return ret;
3987	}
3988	if (enable)
3989	buf |= DP_EDP_BACKLIGHT_ENABLE;
3990	else
3991	buf &= ~DP_EDP_BACKLIGHT_ENABLE;
3992
3993	ret = drm_dp_dpcd_write_byte(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, value: buf);
3994	if (ret < 0) {
3995	drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n",
3996	aux->name, ret);
3997	return ret;
3998	}
3999
4000	return 0;
4001	}
4002
4003	/**
4004	* drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD
4005	* @aux: The DP AUX channel to use
4006	* @bl: Backlight capability info from drm_edp_backlight_init()
4007	* @level: The initial backlight level to set via AUX, if there is one
4008	*
4009	* This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally
4010	* restoring any important backlight state such as the given backlight level, the brightness byte
4011	* count, backlight frequency, etc.
4012	*
4013	* Note that certain panels do not support being enabled or disabled via DPCD, but instead require
4014	* that the driver handle enabling/disabling the panel through implementation-specific means using
4015	* the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false,
4016	* this function becomes a no-op, and the driver is expected to handle powering the panel on using
4017	* the EDP_BL_PWR GPIO.
4018	*
4019	* Returns: %0 on success, negative error code on failure.
4020	*/
4021	int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
4022	const u16 level)
4023	{
4024	int ret;
4025	u8 dpcd_buf;
4026
4027	if (bl->aux_set)
4028	dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
4029	else
4030	dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_PWM;
4031
4032	if (bl->pwmgen_bit_count) {
4033	ret = drm_dp_dpcd_write_byte(aux, DP_EDP_PWMGEN_BIT_COUNT, value: bl->pwmgen_bit_count);
4034	if (ret < 0)
4035	drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
4036	aux->name, ret);
4037	}
4038
4039	if (bl->pwm_freq_pre_divider) {
4040	ret = drm_dp_dpcd_write_byte(aux, DP_EDP_BACKLIGHT_FREQ_SET,
4041	value: bl->pwm_freq_pre_divider);
4042	if (ret < 0)
4043	drm_dbg_kms(aux->drm_dev,
4044	"%s: Failed to write aux backlight frequency: %d\n",
4045	aux->name, ret);
4046	else
4047	dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
4048	}
4049
4050	ret = drm_dp_dpcd_write_byte(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, value: dpcd_buf);
4051	if (ret < 0) {
4052	drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n",
4053	aux->name, ret);
4054	return ret < 0 ? ret : -EIO;
4055	}
4056
4057	ret = drm_edp_backlight_set_level(aux, bl, level);
4058	if (ret < 0)
4059	return ret;
4060	ret = drm_edp_backlight_set_enable(aux, bl, enable: true);
4061	if (ret < 0)
4062	return ret;
4063
4064	return 0;
4065	}
4066	EXPORT_SYMBOL(drm_edp_backlight_enable);
4067
4068	/**
4069	* drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported
4070	* @aux: The DP AUX channel to use
4071	* @bl: Backlight capability info from drm_edp_backlight_init()
4072	*
4073	* This function handles disabling DPCD backlight controls on a panel over AUX.
4074	*
4075	* Note that certain panels do not support being enabled or disabled via DPCD, but instead require
4076	* that the driver handle enabling/disabling the panel through implementation-specific means using
4077	* the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false,
4078	* this function becomes a no-op, and the driver is expected to handle powering the panel off using
4079	* the EDP_BL_PWR GPIO.
4080	*
4081	* Returns: %0 on success or no-op, negative error code on failure.
4082	*/
4083	int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl)
4084	{
4085	int ret;
4086
4087	ret = drm_edp_backlight_set_enable(aux, bl, enable: false);
4088	if (ret < 0)
4089	return ret;
4090
4091	return 0;
4092	}
4093	EXPORT_SYMBOL(drm_edp_backlight_disable);
4094
4095	static inline int
4096	drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
4097	u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
4098	{
4099	int fxp, fxp_min, fxp_max, fxp_actual, f = 1;
4100	int ret;
4101	u8 pn, pn_min, pn_max;
4102
4103	if (!bl->aux_set)
4104	return 0;
4105
4106	ret = drm_dp_dpcd_read_byte(aux, DP_EDP_PWMGEN_BIT_COUNT, valuep: &pn);
4107	if (ret < 0) {
4108	drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n",
4109	aux->name, ret);
4110	return -ENODEV;
4111	}
4112
4113	pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
4114	bl->max = (1 << pn) - 1;
4115	if (!driver_pwm_freq_hz)
4116	return 0;
4117
4118	/*
4119	* Set PWM Frequency divider to match desired frequency provided by the driver.
4120	* The PWM Frequency is calculated as 27Mhz / (F x P).
4121	* - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
4122	* EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
4123	* - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
4124	* EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
4125	*/
4126
4127	/* Find desired value of (F x P)
4128	* Note that, if F x P is out of supported range, the maximum value or minimum value will
4129	* applied automatically. So no need to check that.
4130	*/
4131	fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz);
4132
4133	/* Use highest possible value of Pn for more granularity of brightness adjustment while
4134	* satisfying the conditions below.
4135	* - Pn is in the range of Pn_min and Pn_max
4136	* - F is in the range of 1 and 255
4137	* - FxP is within 25% of desired value.
4138	* Note: 25% is arbitrary value and may need some tweak.
4139	*/
4140	ret = drm_dp_dpcd_read_byte(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, valuep: &pn_min);
4141	if (ret < 0) {
4142	drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n",
4143	aux->name, ret);
4144	return 0;
4145	}
4146	ret = drm_dp_dpcd_read_byte(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, valuep: &pn_max);
4147	if (ret < 0) {
4148	drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n",
4149	aux->name, ret);
4150	return 0;
4151	}
4152	pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
4153	pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
4154
4155	/* Ensure frequency is within 25% of desired value */
4156	fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
4157	fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
4158	if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
4159	drm_dbg_kms(aux->drm_dev,
4160	"%s: Driver defined backlight frequency (%d) out of range\n",
4161	aux->name, driver_pwm_freq_hz);
4162	return 0;
4163	}
4164
4165	for (pn = pn_max; pn >= pn_min; pn--) {
4166	f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
4167	fxp_actual = f << pn;
4168	if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
4169	break;
4170	}
4171
4172	ret = drm_dp_dpcd_write_byte(aux, DP_EDP_PWMGEN_BIT_COUNT, value: pn);
4173	if (ret < 0) {
4174	drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
4175	aux->name, ret);
4176	return 0;
4177	}
4178	bl->pwmgen_bit_count = pn;
4179	bl->max = (1 << pn) - 1;
4180
4181	if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) {
4182	bl->pwm_freq_pre_divider = f;
4183	drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n",
4184	aux->name, driver_pwm_freq_hz);
4185	}
4186
4187	return 0;
4188	}
4189
4190	static inline int
4191	drm_edp_backlight_probe_state(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
4192	u8 *current_mode)
4193	{
4194	int ret;
4195	u8 buf[2];
4196	u8 mode_reg;
4197
4198	ret = drm_dp_dpcd_read_byte(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, valuep: &mode_reg);
4199	if (ret < 0) {
4200	drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n",
4201	aux->name, ret);
4202	return ret < 0 ? ret : -EIO;
4203	}
4204
4205	*current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK);
4206	if (!bl->aux_set)
4207	return 0;
4208
4209	if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
4210	int size = 1 + bl->lsb_reg_used;
4211
4212	ret = drm_dp_dpcd_read_data(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buffer: buf, size);
4213	if (ret < 0) {
4214	drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n",
4215	aux->name, ret);
4216	return ret;
4217	}
4218
4219	if (bl->lsb_reg_used)
4220	return (buf[0] << 8) | buf[1];
4221	else
4222	return buf[0];
4223	}
4224
4225	/*
4226	* If we're not in DPCD control mode yet, the programmed brightness value is meaningless and
4227	* the driver should assume max brightness
4228	*/
4229	return bl->max;
4230	}
4231
4232	/**
4233	* drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight
4234	* interface.
4235	* @aux: The DP aux device to use for probing
4236	* @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight
4237	* @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz
4238	* @edp_dpcd: A cached copy of the eDP DPCD
4239	* @current_level: Where to store the probed brightness level, if any
4240	* @current_mode: Where to store the currently set backlight control mode
4241	*
4242	* Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities,
4243	* along with also probing the current and maximum supported brightness levels.
4244	*
4245	* If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the
4246	* default frequency from the panel is used.
4247	*
4248	* Returns: %0 on success, negative error code on failure.
4249	*/
4250	int
4251	drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
4252	u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
4253	u16 *current_level, u8 *current_mode)
4254	{
4255	int ret;
4256
4257	if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
4258	bl->aux_enable = true;
4259	if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)
4260	bl->aux_set = true;
4261	if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
4262	bl->lsb_reg_used = true;
4263
4264	/* Sanity check caps */
4265	if (!bl->aux_set && !(edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) {
4266	drm_dbg_kms(aux->drm_dev,
4267	"%s: Panel supports neither AUX or PWM brightness control? Aborting\n",
4268	aux->name);
4269	return -EINVAL;
4270	}
4271
4272	ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd);
4273	if (ret < 0)
4274	return ret;
4275
4276	ret = drm_edp_backlight_probe_state(aux, bl, current_mode);
4277	if (ret < 0)
4278	return ret;
4279	*current_level = ret;
4280
4281	drm_dbg_kms(aux->drm_dev,
4282	"%s: Found backlight: aux_set=%d aux_enable=%d mode=%d\n",
4283	aux->name, bl->aux_set, bl->aux_enable, *current_mode);
4284	if (bl->aux_set) {
4285	drm_dbg_kms(aux->drm_dev,
4286	"%s: Backlight caps: level=%d/%d pwm_freq_pre_divider=%d lsb_reg_used=%d\n",
4287	aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider,
4288	bl->lsb_reg_used);
4289	}
4290
4291	return 0;
4292	}
4293	EXPORT_SYMBOL(drm_edp_backlight_init);
4294
4295	#if IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
4296	(IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))
4297
4298	static int dp_aux_backlight_update_status(struct backlight_device *bd)
4299	{
4300	struct dp_aux_backlight *bl = bl_get_data(bl_dev: bd);
4301	u16 brightness = backlight_get_brightness(bd);
4302	int ret = 0;
4303
4304	if (!backlight_is_blank(bd)) {
4305	if (!bl->enabled) {
4306	drm_edp_backlight_enable(bl->aux, &bl->info, brightness);
4307	bl->enabled = true;
4308	return 0;
4309	}
4310	ret = drm_edp_backlight_set_level(bl->aux, &bl->info, brightness);
4311	} else {
4312	if (bl->enabled) {
4313	drm_edp_backlight_disable(bl->aux, &bl->info);
4314	bl->enabled = false;
4315	}
4316	}
4317
4318	return ret;
4319	}
4320
4321	static const struct backlight_ops dp_aux_bl_ops = {
4322	.update_status = dp_aux_backlight_update_status,
4323	};
4324
4325	/**
4326	* drm_panel_dp_aux_backlight - create and use DP AUX backlight
4327	* @panel: DRM panel
4328	* @aux: The DP AUX channel to use
4329	*
4330	* Use this function to create and handle backlight if your panel
4331	* supports backlight control over DP AUX channel using DPCD
4332	* registers as per VESA's standard backlight control interface.
4333	*
4334	* When the panel is enabled backlight will be enabled after a
4335	* successful call to &drm_panel_funcs.enable()
4336	*
4337	* When the panel is disabled backlight will be disabled before the
4338	* call to &drm_panel_funcs.disable().
4339	*
4340	* A typical implementation for a panel driver supporting backlight
4341	* control over DP AUX will call this function at probe time.
4342	* Backlight will then be handled transparently without requiring
4343	* any intervention from the driver.
4344	*
4345	* drm_panel_dp_aux_backlight() must be called after the call to drm_panel_init().
4346	*
4347	* Return: 0 on success or a negative error code on failure.
4348	*/
4349	int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
4350	{
4351	struct dp_aux_backlight *bl;
4352	struct backlight_properties props = { 0 };
4353	u16 current_level;
4354	u8 current_mode;
4355	u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
4356	int ret;
4357
4358	if (!panel || !panel->dev || !aux)
4359	return -EINVAL;
4360
4361	ret = drm_dp_dpcd_read_data(aux, DP_EDP_DPCD_REV, buffer: edp_dpcd,
4362	EDP_DISPLAY_CTL_CAP_SIZE);
4363	if (ret < 0)
4364	return ret;
4365
4366	if (!drm_edp_backlight_supported(edp_dpcd)) {
4367	DRM_DEV_INFO(panel->dev, "DP AUX backlight is not supported\n");
4368	return 0;
4369	}
4370
4371	bl = devm_kzalloc(dev: panel->dev, size: sizeof(*bl), GFP_KERNEL);
4372	if (!bl)
4373	return -ENOMEM;
4374
4375	bl->aux = aux;
4376
4377	ret = drm_edp_backlight_init(aux, &bl->info, 0, edp_dpcd,
4378	&current_level, &current_mode);
4379	if (ret < 0)
4380	return ret;
4381
4382	props.type = BACKLIGHT_RAW;
4383	props.brightness = current_level;
4384	props.max_brightness = bl->info.max;
4385
4386	bl->base = devm_backlight_device_register(dev: panel->dev, name: "dp_aux_backlight",
4387	parent: panel->dev, devdata: bl,
4388	ops: &dp_aux_bl_ops, props: &props);
4389	if (IS_ERR(ptr: bl->base))
4390	return PTR_ERR(ptr: bl->base);
4391
4392	backlight_disable(bd: bl->base);
4393
4394	panel->backlight = bl->base;
4395
4396	return 0;
4397	}
4398	EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
4399
4400	#endif
4401
4402	/* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
4403	static int drm_dp_link_data_symbol_cycles(int lane_count, int pixels,
4404	int bpp_x16, int symbol_size,
4405	bool is_mst)
4406	{
4407	int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
4408	int align = is_mst ? 4 / lane_count : 1;
4409
4410	return ALIGN(cycles, align);
4411	}
4412
4413	/**
4414	* drm_dp_link_symbol_cycles - calculate the link symbol count with/without dsc
4415	* @lane_count: DP link lane count
4416	* @pixels: number of pixels in a scanline
4417	* @dsc_slice_count: number of slices for DSC or '0' for non-DSC
4418	* @bpp_x16: bits per pixel in .4 binary fixed format
4419	* @symbol_size: DP symbol size
4420	* @is_mst: %true for MST and %false for SST
4421	*
4422	* Calculate the link symbol cycles for both DSC (@dsc_slice_count !=0) and
4423	* non-DSC case (@dsc_slice_count == 0) and return the count.
4424	*/
4425	int drm_dp_link_symbol_cycles(int lane_count, int pixels, int dsc_slice_count,
4426	int bpp_x16, int symbol_size, bool is_mst)
4427	{
4428	int slice_count = dsc_slice_count ? : 1;
4429	int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
4430	int slice_data_cycles = drm_dp_link_data_symbol_cycles(lane_count,
4431	pixels: slice_pixels,
4432	bpp_x16,
4433	symbol_size,
4434	is_mst);
4435	int slice_eoc_cycles = 0;
4436
4437	if (dsc_slice_count)
4438	slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
4439
4440	return slice_count * (slice_data_cycles + slice_eoc_cycles);
4441	}
4442	EXPORT_SYMBOL(drm_dp_link_symbol_cycles);
4443
4444	/**
4445	* drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
4446	* @lane_count: DP link lane count
4447	* @hactive: pixel count of the active period in one scanline of the stream
4448	* @dsc_slice_count: number of slices for DSC or '0' for non-DSC
4449	* @bpp_x16: bits per pixel in .4 binary fixed point
4450	* @flags: DRM_DP_OVERHEAD_x flags
4451	*
4452	* Calculate the BW allocation overhead of a DP link stream, depending
4453	* on the link's
4454	* - @lane_count
4455	* - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
4456	* - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
4457	* - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
4458	* - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
4459	* as well as the stream's
4460	* - @hactive timing
4461	* - @bpp_x16 color depth
4462	* - compression mode (@dsc_slice_count != 0)
4463	* Note that this overhead doesn't account for the 8b/10b, 128b/132b
4464	* channel coding efficiency, for that see
4465	* @drm_dp_link_bw_channel_coding_efficiency().
4466	*
4467	* Returns the overhead as 100% + overhead% in 1ppm units.
4468	*/
4469	int drm_dp_bw_overhead(int lane_count, int hactive,
4470	int dsc_slice_count,
4471	int bpp_x16, unsigned long flags)
4472	{
4473	int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8;
4474	bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;
4475	u32 overhead = 1000000;
4476	int symbol_cycles;
4477
4478	if (lane_count == 0 || hactive == 0 || bpp_x16 == 0) {
4479	DRM_DEBUG_KMS("Invalid BW overhead params: lane_count %d, hactive %d, bpp_x16 " FXP_Q4_FMT "\n",
4480	lane_count, hactive,
4481	FXP_Q4_ARGS(bpp_x16));
4482	return 0;
4483	}
4484
4485	/*
4486	* DP Standard v2.1 2.6.4.1
4487	* SSC downspread and ref clock variation margin:
4488	* 5300ppm + 300ppm ~ 0.6%
4489	*/
4490	if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK)
4491	overhead += 6000;
4492
4493	/*
4494	* DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4:
4495	* FEC symbol insertions for 8b/10b channel coding:
4496	* After each 250 data symbols on 2-4 lanes:
4497	* 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block)
4498	* After each 2 x 250 data symbols on 1 lane:
4499	* 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block)
4500	* After 256 (2-4 lanes) or 128 (1 lane) FEC blocks:
4501	* 256 * 256 bytes + 1 FEC_PM
4502	* or
4503	* 128 * 512 bytes + 1 FEC_PM
4504	* (256 * 6 + 1) / (256 * 250) = 2.4015625 %
4505	*/
4506	if (flags & DRM_DP_BW_OVERHEAD_FEC)
4507	overhead += 24016;
4508
4509	/*
4510	* DP Standard v2.1 2.7.9, 5.9.7
4511	* The FEC overhead for UHBR is accounted for in its 96.71% channel
4512	* coding efficiency.
4513	*/
4514	WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
4515	(flags & DRM_DP_BW_OVERHEAD_FEC));
4516
4517	symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
4518	dsc_slice_count,
4519	bpp_x16, symbol_size,
4520	is_mst);
4521
4522	return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
4523	overhead * 16),
4524	hactive * bpp_x16);
4525	}
4526	EXPORT_SYMBOL(drm_dp_bw_overhead);
4527
4528	/**
4529	* drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
4530	* @is_uhbr: Whether the link has a 128b/132b channel coding
4531	*
4532	* Return the channel coding efficiency of the given DP link type, which is
4533	* either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes
4534	* the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
4535	* and for 128b/132b any link or PHY level control symbol insertion overhead
4536	* (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the
4537	* corresponding FEC overhead is BW allocation specific, included in the value
4538	* returned by drm_dp_bw_overhead().
4539	*
4540	* Returns the efficiency in the 100%/coding-overhead% ratio in
4541	* 1ppm units.
4542	*/
4543	int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
4544	{
4545	if (is_uhbr)
4546	return 967100;
4547	else
4548	/*
4549	* Note that on 8b/10b MST the efficiency is only
4550	* 78.75% due to the 1 out of 64 MTPH packet overhead,
4551	* not accounted for here.
4552	*/
4553	return 800000;
4554	}
4555	EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
4556
4557	/**
4558	* drm_dp_max_dprx_data_rate - Get the max data bandwidth of a DPRX sink
4559	* @max_link_rate: max DPRX link rate in 10kbps units
4560	* @max_lanes: max DPRX lane count
4561	*
4562	* Given a link rate and lanes, get the data bandwidth.
4563	*
4564	* Data bandwidth is the actual payload rate, which depends on the data
4565	* bandwidth efficiency and the link rate.
4566	*
4567	* Note that protocol layers above the DPRX link level considered here can
4568	* further limit the maximum data rate. Such layers are the MST topology (with
4569	* limits on the link between the source and first branch device as well as on
4570	* the whole MST path until the DPRX link) and (Thunderbolt) DP tunnels -
4571	* which in turn can encapsulate an MST link with its own limit - with each
4572	* SST or MST encapsulated tunnel sharing the BW of a tunnel group.
4573	*
4574	* Returns the maximum data rate in kBps units.
4575	*/
4576	int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes)
4577	{
4578	int ch_coding_efficiency =
4579	drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(link_rate: max_link_rate));
4580
4581	return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate * 10 * max_lanes,
4582	ch_coding_efficiency),
4583	1000000 * 8);
4584	}
4585	EXPORT_SYMBOL(drm_dp_max_dprx_data_rate);
4586