| 1 | #ifndef STATE_XML |
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| 2 | #define STATE_XML |
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| 3 | |
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| 4 | /* Autogenerated file, DO NOT EDIT manually! |
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| 5 | |
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| 6 | This file was generated by the rules-ng-ng headergen tool in this git repository: |
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| 7 | http://0x04.net/cgit/index.cgi/rules-ng-ng |
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| 8 | git clone git://0x04.net/rules-ng-ng |
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| 9 | |
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| 10 | The rules-ng-ng source files this header was generated from are: |
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| 11 | - state.xml ( 26087 bytes, from 2017-12-18 16:51:59) |
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| 12 | - common.xml ( 35468 bytes, from 2018-01-22 13:48:54) |
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| 13 | - common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59) |
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| 14 | - state_hi.xml ( 30232 bytes, from 2018-02-15 15:48:01) |
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| 15 | - copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56) |
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| 16 | - state_2d.xml ( 51552 bytes, from 2016-12-08 16:37:56) |
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| 17 | - state_3d.xml ( 79992 bytes, from 2017-12-18 16:51:59) |
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| 18 | - state_blt.xml ( 13405 bytes, from 2017-12-18 16:51:59) |
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| 19 | - state_vg.xml ( 5975 bytes, from 2016-12-08 16:37:56) |
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| 20 | |
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| 21 | Copyright (C) 2012-2017 by the following authors: |
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| 22 | - Wladimir J. van der Laan <laanwj@gmail.com> |
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| 23 | - Christian Gmeiner <christian.gmeiner@gmail.com> |
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| 24 | - Lucas Stach <l.stach@pengutronix.de> |
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| 25 | - Russell King <rmk@arm.linux.org.uk> |
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| 26 | |
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| 27 | Permission is hereby granted, free of charge, to any person obtaining a |
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| 28 | copy of this software and associated documentation files (the "Software"), |
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| 29 | to deal in the Software without restriction, including without limitation |
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| 30 | the rights to use, copy, modify, merge, publish, distribute, sub license, |
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| 31 | and/or sell copies of the Software, and to permit persons to whom the |
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| 32 | Software is furnished to do so, subject to the following conditions: |
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| 33 | |
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| 34 | The above copyright notice and this permission notice (including the |
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| 35 | next paragraph) shall be included in all copies or substantial portions |
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| 36 | of the Software. |
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| 37 | |
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| 38 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 39 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 40 | FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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| 41 | THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 42 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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| 43 | FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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| 44 | DEALINGS IN THE SOFTWARE. |
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| 45 | */ |
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| 46 | |
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| 47 | |
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| 48 | #define VARYING_COMPONENT_USE_UNUSED 0x00000000 |
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| 49 | #define VARYING_COMPONENT_USE_USED 0x00000001 |
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| 50 | #define VARYING_COMPONENT_USE_POINTCOORD_X 0x00000002 |
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| 51 | #define VARYING_COMPONENT_USE_POINTCOORD_Y 0x00000003 |
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| 52 | #define FE_DATA_TYPE_BYTE 0x00000000 |
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| 53 | #define FE_DATA_TYPE_UNSIGNED_BYTE 0x00000001 |
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| 54 | #define FE_DATA_TYPE_SHORT 0x00000002 |
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| 55 | #define FE_DATA_TYPE_UNSIGNED_SHORT 0x00000003 |
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| 56 | #define FE_DATA_TYPE_INT 0x00000004 |
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| 57 | #define FE_DATA_TYPE_UNSIGNED_INT 0x00000005 |
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| 58 | #define FE_DATA_TYPE_FLOAT 0x00000008 |
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| 59 | #define FE_DATA_TYPE_HALF_FLOAT 0x00000009 |
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| 60 | #define FE_DATA_TYPE_FIXED 0x0000000b |
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| 61 | #define FE_DATA_TYPE_INT_10_10_10_2 0x0000000c |
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| 62 | #define FE_DATA_TYPE_UNSIGNED_INT_10_10_10_2 0x0000000d |
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| 63 | #define FE_DATA_TYPE_BYTE_I 0x0000000e |
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| 64 | #define FE_DATA_TYPE_SHORT_I 0x0000000f |
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| 65 | #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK 0x000000ff |
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| 66 | #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT 0 |
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| 67 | #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(x) (((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK) |
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| 68 | #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK 0x00ff0000 |
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| 69 | #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT 16 |
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| 70 | #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR(x) (((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK) |
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| 71 | #define VIVS_FE 0x00000000 |
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| 72 | |
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| 73 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0) (0x00000600 + 0x4*(i0)) |
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| 74 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG__ESIZE 0x00000004 |
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| 75 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN 0x00000010 |
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| 76 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK 0x0000000f |
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| 77 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT 0 |
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| 78 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK) |
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| 79 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK 0x00000030 |
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| 80 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT 4 |
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| 81 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK) |
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| 82 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE 0x00000080 |
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| 83 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK 0x00000700 |
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| 84 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT 8 |
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| 85 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK) |
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| 86 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK 0x00003000 |
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| 87 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT 12 |
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| 88 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK) |
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| 89 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__MASK 0x0000c000 |
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| 90 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__SHIFT 14 |
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| 91 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF 0x00000000 |
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| 92 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_ON 0x00008000 |
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| 93 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK 0x00ff0000 |
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| 94 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT 16 |
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| 95 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK) |
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| 96 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK 0xff000000 |
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| 97 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT 24 |
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| 98 | #define VIVS_FE_VERTEX_ELEMENT_CONFIG_END(x) (((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK) |
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| 99 | |
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| 100 | #define VIVS_FE_CMD_STREAM_BASE_ADDR 0x00000640 |
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| 101 | |
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| 102 | #define VIVS_FE_INDEX_STREAM_BASE_ADDR 0x00000644 |
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| 103 | |
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| 104 | #define VIVS_FE_INDEX_STREAM_CONTROL 0x00000648 |
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| 105 | #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE__MASK 0x00000003 |
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| 106 | #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE__SHIFT 0 |
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| 107 | #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_CHAR 0x00000000 |
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| 108 | #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_SHORT 0x00000001 |
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| 109 | #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_INT 0x00000002 |
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| 110 | #define VIVS_FE_INDEX_STREAM_CONTROL_PRIMITIVE_RESTART 0x00000100 |
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| 111 | |
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| 112 | #define VIVS_FE_VERTEX_STREAM_BASE_ADDR 0x0000064c |
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| 113 | |
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| 114 | #define VIVS_FE_VERTEX_STREAM_CONTROL 0x00000650 |
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| 115 | |
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| 116 | #define VIVS_FE_COMMAND_ADDRESS 0x00000654 |
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| 117 | |
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| 118 | #define VIVS_FE_COMMAND_CONTROL 0x00000658 |
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| 119 | #define VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK 0x0000ffff |
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| 120 | #define VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT 0 |
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| 121 | #define VIVS_FE_COMMAND_CONTROL_PREFETCH(x) (((x) << VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT) & VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK) |
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| 122 | #define VIVS_FE_COMMAND_CONTROL_ENABLE 0x00010000 |
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| 123 | |
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| 124 | #define VIVS_FE_DMA_STATUS 0x0000065c |
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| 125 | |
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| 126 | #define VIVS_FE_DMA_DEBUG_STATE 0x00000660 |
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| 127 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__MASK 0x0000001f |
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| 128 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__SHIFT 0 |
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| 129 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_IDLE 0x00000000 |
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| 130 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DEC 0x00000001 |
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| 131 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR0 0x00000002 |
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| 132 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD0 0x00000003 |
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| 133 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR1 0x00000004 |
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| 134 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD1 0x00000005 |
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| 135 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DADR 0x00000006 |
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| 136 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCMD 0x00000007 |
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| 137 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCNTL 0x00000008 |
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| 138 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DIDXCNTL 0x00000009 |
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| 139 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_INITREQDMA 0x0000000a |
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| 140 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAWIDX 0x0000000b |
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| 141 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAW 0x0000000c |
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| 142 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT0 0x0000000d |
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| 143 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT1 0x0000000e |
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| 144 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA0 0x0000000f |
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| 145 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA1 0x00000010 |
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| 146 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAITFIFO 0x00000011 |
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| 147 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAIT 0x00000012 |
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| 148 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LINK 0x00000013 |
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| 149 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_END 0x00000014 |
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| 150 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_STALL 0x00000015 |
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| 151 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__MASK 0x00000300 |
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| 152 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__SHIFT 8 |
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| 153 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_IDLE 0x00000000 |
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| 154 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_START 0x00000100 |
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| 155 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_REQ 0x00000200 |
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| 156 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_END 0x00000300 |
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| 157 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__MASK 0x00000c00 |
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| 158 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__SHIFT 10 |
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| 159 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_IDLE 0x00000000 |
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| 160 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_RAMVALID 0x00000400 |
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| 161 | #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_VALID 0x00000800 |
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| 162 | #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__MASK 0x00003000 |
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| 163 | #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__SHIFT 12 |
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| 164 | #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_IDLE 0x00000000 |
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| 165 | #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_WAITIDX 0x00001000 |
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| 166 | #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_CAL 0x00002000 |
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| 167 | #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__MASK 0x0000c000 |
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| 168 | #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__SHIFT 14 |
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| 169 | #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDLE 0x00000000 |
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| 170 | #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_LDADR 0x00004000 |
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| 171 | #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDXCALC 0x00008000 |
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| 172 | #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__MASK 0x00030000 |
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| 173 | #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__SHIFT 16 |
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| 174 | #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_IDLE 0x00000000 |
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| 175 | #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_CKCACHE 0x00010000 |
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| 176 | #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_MISS 0x00020000 |
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| 177 | |
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| 178 | #define VIVS_FE_DMA_ADDRESS 0x00000664 |
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| 179 | |
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| 180 | #define VIVS_FE_DMA_LOW 0x00000668 |
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| 181 | |
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| 182 | #define VIVS_FE_DMA_HIGH 0x0000066c |
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| 183 | |
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| 184 | #define VIVS_FE_AUTO_FLUSH 0x00000670 |
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| 185 | |
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| 186 | #define VIVS_FE_PRIMITIVE_RESTART_INDEX 0x00000674 |
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| 187 | |
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| 188 | #define VIVS_FE_UNK00678 0x00000678 |
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| 189 | |
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| 190 | #define VIVS_FE_UNK0067C 0x0000067c |
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| 191 | |
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| 192 | #define VIVS_FE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) |
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| 193 | #define VIVS_FE_VERTEX_STREAMS__ESIZE 0x00000004 |
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| 194 | #define VIVS_FE_VERTEX_STREAMS__LEN 0x00000008 |
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| 195 | |
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| 196 | #define VIVS_FE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00000680 + 0x4*(i0)) |
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| 197 | |
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| 198 | #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0)) |
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| 199 | |
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| 200 | #define VIVS_FE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0)) |
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| 201 | #define VIVS_FE_GENERIC_ATTRIB__ESIZE 0x00000004 |
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| 202 | #define VIVS_FE_GENERIC_ATTRIB__LEN 0x00000010 |
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| 203 | |
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| 204 | #define VIVS_FE_GENERIC_ATTRIB_UNK006C0(i0) (0x000006c0 + 0x4*(i0)) |
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| 205 | |
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| 206 | #define VIVS_FE_GENERIC_ATTRIB_UNK00700(i0) (0x00000700 + 0x4*(i0)) |
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| 207 | |
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| 208 | #define VIVS_FE_GENERIC_ATTRIB_UNK00740(i0) (0x00000740 + 0x4*(i0)) |
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| 209 | |
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| 210 | #define VIVS_FE_GENERIC_ATTRIB_SCALE(i0) (0x00000780 + 0x4*(i0)) |
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| 211 | |
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| 212 | #define VIVS_FE_HALTI5_UNK007C4 0x000007c4 |
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| 213 | |
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| 214 | #define VIVS_FE_HALTI5_UNK007D0(i0) (0x000007d0 + 0x4*(i0)) |
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| 215 | #define VIVS_FE_HALTI5_UNK007D0__ESIZE 0x00000004 |
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| 216 | #define VIVS_FE_HALTI5_UNK007D0__LEN 0x00000002 |
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| 217 | |
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| 218 | #define VIVS_FE_HALTI5_UNK007D8 0x000007d8 |
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| 219 | |
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| 220 | #define VIVS_FE_DESC_START 0x000007dc |
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| 221 | |
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| 222 | #define VIVS_FE_DESC_END 0x000007e0 |
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| 223 | |
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| 224 | #define VIVS_FE_DESC_AVAIL 0x000007e4 |
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| 225 | #define VIVS_FE_DESC_AVAIL_COUNT__MASK 0x0000007f |
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| 226 | #define VIVS_FE_DESC_AVAIL_COUNT__SHIFT 0 |
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| 227 | #define VIVS_FE_DESC_AVAIL_COUNT(x) (((x) << VIVS_FE_DESC_AVAIL_COUNT__SHIFT) & VIVS_FE_DESC_AVAIL_COUNT__MASK) |
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| 228 | |
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| 229 | #define VIVS_FE_FENCE_WAIT_DATA_LOW 0x000007e8 |
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| 230 | |
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| 231 | #define VIVS_FE_FENCE_WAIT_DATA_HIGH 0x000007f4 |
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| 232 | |
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| 233 | #define VIVS_FE_ROBUSTNESS_UNK007F8 0x000007f8 |
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| 234 | |
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| 235 | #define VIVS_GL 0x00000000 |
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| 236 | |
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| 237 | #define VIVS_GL_PIPE_SELECT 0x00003800 |
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| 238 | #define VIVS_GL_PIPE_SELECT_PIPE__MASK 0x00000001 |
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| 239 | #define VIVS_GL_PIPE_SELECT_PIPE__SHIFT 0 |
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| 240 | #define VIVS_GL_PIPE_SELECT_PIPE(x) (((x) << VIVS_GL_PIPE_SELECT_PIPE__SHIFT) & VIVS_GL_PIPE_SELECT_PIPE__MASK) |
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| 241 | |
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| 242 | #define VIVS_GL_EVENT 0x00003804 |
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| 243 | #define VIVS_GL_EVENT_EVENT_ID__MASK 0x0000001f |
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| 244 | #define VIVS_GL_EVENT_EVENT_ID__SHIFT 0 |
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| 245 | #define VIVS_GL_EVENT_EVENT_ID(x) (((x) << VIVS_GL_EVENT_EVENT_ID__SHIFT) & VIVS_GL_EVENT_EVENT_ID__MASK) |
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| 246 | #define VIVS_GL_EVENT_FROM_FE 0x00000020 |
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| 247 | #define VIVS_GL_EVENT_FROM_PE 0x00000040 |
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| 248 | #define VIVS_GL_EVENT_FROM_BLT 0x00000080 |
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| 249 | #define VIVS_GL_EVENT_SOURCE__MASK 0x00001f00 |
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| 250 | #define VIVS_GL_EVENT_SOURCE__SHIFT 8 |
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| 251 | #define VIVS_GL_EVENT_SOURCE(x) (((x) << VIVS_GL_EVENT_SOURCE__SHIFT) & VIVS_GL_EVENT_SOURCE__MASK) |
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| 252 | |
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| 253 | #define VIVS_GL_SEMAPHORE_TOKEN 0x00003808 |
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| 254 | #define VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK 0x0000001f |
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| 255 | #define VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT 0 |
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| 256 | #define VIVS_GL_SEMAPHORE_TOKEN_FROM(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK) |
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| 257 | #define VIVS_GL_SEMAPHORE_TOKEN_TO__MASK 0x00001f00 |
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| 258 | #define VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT 8 |
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| 259 | #define VIVS_GL_SEMAPHORE_TOKEN_TO(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_TO__MASK) |
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| 260 | #define VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK 0x30000000 |
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| 261 | #define VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT 28 |
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| 262 | #define VIVS_GL_SEMAPHORE_TOKEN_UNK28(x) (((x) << VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK) |
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| 263 | |
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| 264 | #define VIVS_GL_FLUSH_CACHE 0x0000380c |
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| 265 | #define VIVS_GL_FLUSH_CACHE_DEPTH 0x00000001 |
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| 266 | #define VIVS_GL_FLUSH_CACHE_COLOR 0x00000002 |
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| 267 | #define VIVS_GL_FLUSH_CACHE_TEXTURE 0x00000004 |
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| 268 | #define VIVS_GL_FLUSH_CACHE_PE2D 0x00000008 |
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| 269 | #define VIVS_GL_FLUSH_CACHE_TEXTUREVS 0x00000010 |
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| 270 | #define VIVS_GL_FLUSH_CACHE_SHADER_L1 0x00000020 |
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| 271 | #define VIVS_GL_FLUSH_CACHE_SHADER_L2 0x00000040 |
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| 272 | #define VIVS_GL_FLUSH_CACHE_UNK10 0x00000400 |
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| 273 | #define VIVS_GL_FLUSH_CACHE_UNK11 0x00000800 |
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| 274 | #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12 0x00001000 |
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| 275 | #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13 0x00002000 |
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| 276 | |
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| 277 | #define VIVS_GL_FLUSH_MMU 0x00003810 |
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| 278 | #define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU 0x00000001 |
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| 279 | #define VIVS_GL_FLUSH_MMU_FLUSH_UNK1 0x00000002 |
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| 280 | #define VIVS_GL_FLUSH_MMU_FLUSH_UNK2 0x00000004 |
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| 281 | #define VIVS_GL_FLUSH_MMU_FLUSH_PEMMU 0x00000008 |
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| 282 | #define VIVS_GL_FLUSH_MMU_FLUSH_UNK4 0x00000010 |
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| 283 | |
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| 284 | #define VIVS_GL_VERTEX_ELEMENT_CONFIG 0x00003814 |
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| 285 | |
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| 286 | #define VIVS_GL_MULTI_SAMPLE_CONFIG 0x00003818 |
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| 287 | #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__MASK 0x00000003 |
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| 288 | #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__SHIFT 0 |
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| 289 | #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE 0x00000000 |
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| 290 | #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X 0x00000001 |
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| 291 | #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X 0x00000002 |
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| 292 | #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_MASK 0x00000008 |
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| 293 | #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK 0x000000f0 |
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| 294 | #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT 4 |
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| 295 | #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES(x) (((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK) |
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| 296 | #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES_MASK 0x00000100 |
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| 297 | #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK 0x00007000 |
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| 298 | #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT 12 |
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| 299 | #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12(x) (((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK) |
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| 300 | #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12_MASK 0x00008000 |
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| 301 | #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK 0x00030000 |
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| 302 | #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT 16 |
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| 303 | #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16(x) (((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK) |
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| 304 | #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16_MASK 0x00080000 |
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| 305 | |
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| 306 | #define VIVS_GL_VARYING_TOTAL_COMPONENTS 0x0000381c |
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| 307 | #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK 0x000000ff |
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| 308 | #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT 0 |
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| 309 | #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(x) (((x) << VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT) & VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK) |
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| 310 | |
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| 311 | #define VIVS_GL_VARYING_NUM_COMPONENTS 0x00003820 |
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| 312 | |
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| 313 | #define VIVS_GL_OCCLUSION_QUERY_ADDR 0x00003824 |
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| 314 | |
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| 315 | #define VIVS_GL_VARYING_COMPONENT_USE(i0) (0x00003828 + 0x4*(i0)) |
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| 316 | #define VIVS_GL_VARYING_COMPONENT_USE__ESIZE 0x00000004 |
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| 317 | #define VIVS_GL_VARYING_COMPONENT_USE__LEN 0x00000002 |
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| 318 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK 0x00000003 |
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| 319 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT 0 |
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| 320 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP0(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK) |
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| 321 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK 0x0000000c |
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| 322 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT 2 |
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| 323 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP1(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK) |
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| 324 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK 0x00000030 |
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| 325 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT 4 |
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| 326 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP2(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK) |
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| 327 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK 0x000000c0 |
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| 328 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT 6 |
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| 329 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP3(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK) |
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| 330 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK 0x00000300 |
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| 331 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT 8 |
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| 332 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP4(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK) |
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| 333 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK 0x00000c00 |
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| 334 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT 10 |
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| 335 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP5(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK) |
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| 336 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK 0x00003000 |
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| 337 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT 12 |
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| 338 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP6(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK) |
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| 339 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK 0x0000c000 |
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| 340 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT 14 |
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| 341 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP7(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK) |
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| 342 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK 0x00030000 |
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| 343 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT 16 |
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| 344 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP8(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK) |
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| 345 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK 0x000c0000 |
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| 346 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT 18 |
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| 347 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP9(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK) |
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| 348 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK 0x00300000 |
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| 349 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT 20 |
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| 350 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP10(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK) |
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| 351 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK 0x00c00000 |
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| 352 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT 22 |
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| 353 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP11(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK) |
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| 354 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK 0x03000000 |
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| 355 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT 24 |
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| 356 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP12(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK) |
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| 357 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK 0x0c000000 |
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| 358 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT 26 |
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| 359 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP13(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK) |
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| 360 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK 0x30000000 |
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| 361 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT 28 |
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| 362 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP14(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK) |
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| 363 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK 0xc0000000 |
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| 364 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT 30 |
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| 365 | #define VIVS_GL_VARYING_COMPONENT_USE_COMP15(x) (((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK) |
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| 366 | |
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| 367 | #define VIVS_GL_UNK0382C 0x0000382c |
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| 368 | |
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| 369 | #define VIVS_GL_OCCLUSION_QUERY_CONTROL 0x00003830 |
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| 370 | |
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| 371 | #define VIVS_GL_UNK03834 0x00003834 |
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| 372 | |
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| 373 | #define VIVS_GL_UNK03838 0x00003838 |
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| 374 | |
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| 375 | #define VIVS_GL_API_MODE 0x0000384c |
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| 376 | #define VIVS_GL_API_MODE_OPENGL 0x00000000 |
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| 377 | #define VIVS_GL_API_MODE_OPENVG 0x00000001 |
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| 378 | #define VIVS_GL_API_MODE_OPENCL 0x00000002 |
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| 379 | |
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| 380 | #define VIVS_GL_CONTEXT_POINTER 0x00003850 |
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| 381 | |
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| 382 | #define VIVS_GL_UNK03854 0x00003854 |
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| 383 | |
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| 384 | #define VIVS_GL_BUG_FIXES 0x00003860 |
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| 385 | |
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| 386 | #define VIVS_GL_FENCE_OUT_ADDRESS 0x00003868 |
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| 387 | |
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| 388 | #define VIVS_GL_FENCE_OUT_DATA_LOW 0x0000386c |
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| 389 | |
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| 390 | #define VIVS_GL_HALTI5_UNK03884 0x00003884 |
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| 391 | |
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| 392 | #define VIVS_GL_HALTI5_SH_SPECIALS 0x00003888 |
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| 393 | #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK 0x0000007f |
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| 394 | #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT 0 |
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| 395 | #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK) |
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| 396 | #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK 0x00007f00 |
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| 397 | #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT 8 |
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| 398 | #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK) |
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| 399 | #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK 0x007f0000 |
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| 400 | #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT 16 |
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| 401 | #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK) |
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| 402 | #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK 0xff000000 |
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| 403 | #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT 24 |
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| 404 | #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24(x) (((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK) |
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| 405 | |
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| 406 | #define VIVS_GL_GS_UNK0388C 0x0000388c |
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| 407 | |
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| 408 | #define VIVS_GL_FENCE_OUT_DATA_HIGH 0x00003898 |
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| 409 | |
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| 410 | #define VIVS_GL_SHADER_INDEX 0x0000389c |
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| 411 | |
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| 412 | #define VIVS_GL_GS_UNK038A0(i0) (0x000038a0 + 0x4*(i0)) |
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| 413 | #define VIVS_GL_GS_UNK038A0__ESIZE 0x00000004 |
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| 414 | #define VIVS_GL_GS_UNK038A0__LEN 0x00000008 |
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| 415 | |
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| 416 | #define VIVS_GL_HALTI5_UNK038C0(i0) (0x000038c0 + 0x4*(i0)) |
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| 417 | #define VIVS_GL_HALTI5_UNK038C0__ESIZE 0x00000004 |
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| 418 | #define VIVS_GL_HALTI5_UNK038C0__LEN 0x00000010 |
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| 419 | |
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| 420 | #define VIVS_GL_SECURITY_UNK3900 0x00003900 |
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| 421 | |
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| 422 | #define VIVS_GL_SECURITY_UNK3904 0x00003904 |
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| 423 | |
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| 424 | #define VIVS_GL_UNK03A00 0x00003a00 |
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| 425 | |
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| 426 | #define VIVS_GL_UNK03A04 0x00003a04 |
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| 427 | |
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| 428 | #define VIVS_GL_UNK03A08 0x00003a08 |
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| 429 | |
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| 430 | #define VIVS_GL_UNK03A0C 0x00003a0c |
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| 431 | |
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| 432 | #define VIVS_GL_UNK03A10 0x00003a10 |
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| 433 | |
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| 434 | #define VIVS_GL_STALL_TOKEN 0x00003c00 |
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| 435 | #define VIVS_GL_STALL_TOKEN_FROM__MASK 0x0000001f |
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| 436 | #define VIVS_GL_STALL_TOKEN_FROM__SHIFT 0 |
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| 437 | #define VIVS_GL_STALL_TOKEN_FROM(x) (((x) << VIVS_GL_STALL_TOKEN_FROM__SHIFT) & VIVS_GL_STALL_TOKEN_FROM__MASK) |
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| 438 | #define VIVS_GL_STALL_TOKEN_TO__MASK 0x00001f00 |
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| 439 | #define VIVS_GL_STALL_TOKEN_TO__SHIFT 8 |
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| 440 | #define VIVS_GL_STALL_TOKEN_TO(x) (((x) << VIVS_GL_STALL_TOKEN_TO__SHIFT) & VIVS_GL_STALL_TOKEN_TO__MASK) |
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| 441 | #define VIVS_GL_STALL_TOKEN_FLIP0 0x40000000 |
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| 442 | #define VIVS_GL_STALL_TOKEN_FLIP1 0x80000000 |
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| 443 | |
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| 444 | #define VIVS_NFE 0x00000000 |
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| 445 | |
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| 446 | #define VIVS_NFE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) |
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| 447 | #define VIVS_NFE_VERTEX_STREAMS__ESIZE 0x00000004 |
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| 448 | #define VIVS_NFE_VERTEX_STREAMS__LEN 0x00000010 |
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| 449 | |
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| 450 | #define VIVS_NFE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00014600 + 0x4*(i0)) |
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| 451 | |
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| 452 | #define VIVS_NFE_VERTEX_STREAMS_CONTROL(i0) (0x00014640 + 0x4*(i0)) |
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| 453 | |
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| 454 | #define VIVS_NFE_VERTEX_STREAMS_UNK14680(i0) (0x00014680 + 0x4*(i0)) |
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| 455 | |
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| 456 | #define VIVS_NFE_VERTEX_STREAMS_ROBUSTNESS_UNK146C0(i0) (0x000146c0 + 0x4*(i0)) |
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| 457 | |
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| 458 | #define VIVS_NFE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0)) |
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| 459 | #define VIVS_NFE_GENERIC_ATTRIB__ESIZE 0x00000004 |
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| 460 | #define VIVS_NFE_GENERIC_ATTRIB__LEN 0x00000020 |
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| 461 | |
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| 462 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0(i0) (0x00017800 + 0x4*(i0)) |
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| 463 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK 0x0000000f |
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| 464 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT 0 |
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| 465 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK) |
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| 466 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK 0x00000030 |
|---|
| 467 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT 4 |
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| 468 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK) |
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| 469 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK 0x00000700 |
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| 470 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT 8 |
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| 471 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK) |
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| 472 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK 0x00003000 |
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| 473 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT 12 |
|---|
| 474 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK) |
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| 475 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__MASK 0x0000c000 |
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| 476 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__SHIFT 14 |
|---|
| 477 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_OFF 0x00000000 |
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| 478 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_ON 0x00008000 |
|---|
| 479 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK 0x00ff0000 |
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| 480 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT 16 |
|---|
| 481 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK) |
|---|
| 482 | |
|---|
| 483 | #define VIVS_NFE_GENERIC_ATTRIB_UNK17880(i0) (0x00017880 + 0x4*(i0)) |
|---|
| 484 | |
|---|
| 485 | #define VIVS_NFE_GENERIC_ATTRIB_UNK17900(i0) (0x00017900 + 0x4*(i0)) |
|---|
| 486 | |
|---|
| 487 | #define VIVS_NFE_GENERIC_ATTRIB_UNK17980(i0) (0x00017980 + 0x4*(i0)) |
|---|
| 488 | |
|---|
| 489 | #define VIVS_NFE_GENERIC_ATTRIB_SCALE(i0) (0x00017a00 + 0x4*(i0)) |
|---|
| 490 | |
|---|
| 491 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1(i0) (0x00017a80 + 0x4*(i0)) |
|---|
| 492 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK 0x000000ff |
|---|
| 493 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT 0 |
|---|
| 494 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(x) (((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK) |
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| 495 | #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE 0x00000800 |
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| 496 | |
|---|
| 497 | #define VIVS_DUMMY 0x00000000 |
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| 498 | |
|---|
| 499 | #define VIVS_DUMMY_DUMMY 0x0003fffc |
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| 500 | |
|---|
| 501 | |
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| 502 | #endif /* STATE_XML */ |
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| 503 | |
|---|
