1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Copyright (c) 2014 Samsung Electronics Co., Ltd. |
4 | * Author: Ajay Kumar <ajaykumar.rs@samsung.com> |
5 | */ |
6 | |
7 | #ifndef EXYNOS_REGS_DECON7_H |
8 | #define EXYNOS_REGS_DECON7_H |
9 | |
10 | /* VIDCON0 */ |
11 | #define VIDCON0 0x00 |
12 | |
13 | #define VIDCON0_SWRESET (1 << 28) |
14 | #define VIDCON0_DECON_STOP_STATUS (1 << 2) |
15 | #define VIDCON0_ENVID (1 << 1) |
16 | #define VIDCON0_ENVID_F (1 << 0) |
17 | |
18 | /* VIDOUTCON0 */ |
19 | #define VIDOUTCON0 0x4 |
20 | |
21 | #define VIDOUTCON0_DUAL_MASK (0x3 << 24) |
22 | #define VIDOUTCON0_DUAL_ON (0x3 << 24) |
23 | #define VIDOUTCON0_DISP_IF_1_ON (0x2 << 24) |
24 | #define VIDOUTCON0_DISP_IF_0_ON (0x1 << 24) |
25 | #define VIDOUTCON0_DUAL_OFF (0x0 << 24) |
26 | #define VIDOUTCON0_IF_SHIFT 23 |
27 | #define VIDOUTCON0_IF_MASK (0x1 << 23) |
28 | #define VIDOUTCON0_RGBIF (0x0 << 23) |
29 | #define VIDOUTCON0_I80IF (0x1 << 23) |
30 | |
31 | /* VIDCON3 */ |
32 | #define VIDCON3 0x8 |
33 | |
34 | /* VIDCON4 */ |
35 | #define VIDCON4 0xC |
36 | #define VIDCON4_FIFOCNT_START_EN (1 << 0) |
37 | |
38 | /* VCLKCON0 */ |
39 | #define VCLKCON0 0x10 |
40 | #define VCLKCON0_CLKVALUP (1 << 8) |
41 | #define VCLKCON0_VCLKFREE (1 << 0) |
42 | |
43 | /* VCLKCON */ |
44 | #define VCLKCON1 0x14 |
45 | #define VCLKCON1_CLKVAL_NUM_VCLK(val) (((val) & 0xff) << 0) |
46 | #define VCLKCON2 0x18 |
47 | |
48 | /* SHADOWCON */ |
49 | #define SHADOWCON 0x30 |
50 | |
51 | #define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win))) |
52 | |
53 | /* WINCONx */ |
54 | #define WINCON(_win) (0x50 + ((_win) * 4)) |
55 | |
56 | #define WINCONx_BUFSTATUS (0x3 << 30) |
57 | #define WINCONx_BUFSEL_MASK (0x3 << 28) |
58 | #define WINCONx_BUFSEL_SHIFT 28 |
59 | #define WINCONx_TRIPLE_BUF_MODE (0x1 << 18) |
60 | #define WINCONx_DOUBLE_BUF_MODE (0x0 << 18) |
61 | #define WINCONx_BURSTLEN_16WORD (0x0 << 11) |
62 | #define WINCONx_BURSTLEN_8WORD (0x1 << 11) |
63 | #define WINCONx_BURSTLEN_MASK (0x1 << 11) |
64 | #define WINCONx_BURSTLEN_SHIFT 11 |
65 | #define WINCONx_BLD_PLANE (0 << 8) |
66 | #define WINCONx_BLD_PIX (1 << 8) |
67 | #define WINCONx_ALPHA_MUL (1 << 7) |
68 | |
69 | #define WINCONx_BPPMODE_MASK (0xf << 2) |
70 | #define WINCONx_BPPMODE_SHIFT 2 |
71 | #define WINCONx_BPPMODE_16BPP_565 (0x8 << 2) |
72 | #define WINCONx_BPPMODE_24BPP_BGRx (0x7 << 2) |
73 | #define WINCONx_BPPMODE_24BPP_RGBx (0x6 << 2) |
74 | #define WINCONx_BPPMODE_24BPP_xBGR (0x5 << 2) |
75 | #define WINCONx_BPPMODE_24BPP_xRGB (0x4 << 2) |
76 | #define WINCONx_BPPMODE_32BPP_BGRA (0x3 << 2) |
77 | #define WINCONx_BPPMODE_32BPP_RGBA (0x2 << 2) |
78 | #define WINCONx_BPPMODE_32BPP_ABGR (0x1 << 2) |
79 | #define WINCONx_BPPMODE_32BPP_ARGB (0x0 << 2) |
80 | #define WINCONx_ALPHA_SEL (1 << 1) |
81 | #define WINCONx_ENWIN (1 << 0) |
82 | |
83 | #define WINCON1_ALPHA_MUL_F (1 << 7) |
84 | #define WINCON2_ALPHA_MUL_F (1 << 7) |
85 | #define WINCON3_ALPHA_MUL_F (1 << 7) |
86 | #define WINCON4_ALPHA_MUL_F (1 << 7) |
87 | |
88 | /* VIDOSDxH: The height for the OSD image(READ ONLY)*/ |
89 | #define VIDOSD_H(_x) (0x80 + ((_x) * 4)) |
90 | |
91 | /* Frame buffer start addresses: VIDWxxADD0n */ |
92 | #define VIDW_BUF_START(_win) (0x80 + ((_win) * 0x10)) |
93 | #define VIDW_BUF_START1(_win) (0x84 + ((_win) * 0x10)) |
94 | #define VIDW_BUF_START2(_win) (0x88 + ((_win) * 0x10)) |
95 | |
96 | #define VIDW_WHOLE_X(_win) (0x0130 + ((_win) * 8)) |
97 | #define VIDW_WHOLE_Y(_win) (0x0134 + ((_win) * 8)) |
98 | #define VIDW_OFFSET_X(_win) (0x0170 + ((_win) * 8)) |
99 | #define VIDW_OFFSET_Y(_win) (0x0174 + ((_win) * 8)) |
100 | #define VIDW_BLKOFFSET(_win) (0x01B0 + ((_win) * 4)) |
101 | #define VIDW_BLKSIZE(win) (0x0200 + ((_win) * 4)) |
102 | |
103 | /* Interrupt controls register */ |
104 | #define VIDINTCON2 0x228 |
105 | |
106 | #define (1 << 1) |
107 | #define (1 << 0) |
108 | |
109 | /* Interrupt controls and status register */ |
110 | #define VIDINTCON3 0x22C |
111 | |
112 | #define (1 << 1) |
113 | #define (1 << 0) |
114 | |
115 | /* VIDOSDxA ~ VIDOSDxE */ |
116 | #define VIDOSD_BASE 0x230 |
117 | |
118 | #define OSD_STRIDE 0x20 |
119 | |
120 | #define VIDOSD_A(_win) (VIDOSD_BASE + \ |
121 | ((_win) * OSD_STRIDE) + 0x00) |
122 | #define VIDOSD_B(_win) (VIDOSD_BASE + \ |
123 | ((_win) * OSD_STRIDE) + 0x04) |
124 | #define VIDOSD_C(_win) (VIDOSD_BASE + \ |
125 | ((_win) * OSD_STRIDE) + 0x08) |
126 | #define VIDOSD_D(_win) (VIDOSD_BASE + \ |
127 | ((_win) * OSD_STRIDE) + 0x0C) |
128 | #define VIDOSD_E(_win) (VIDOSD_BASE + \ |
129 | ((_win) * OSD_STRIDE) + 0x10) |
130 | |
131 | #define VIDOSDxA_TOPLEFT_X_MASK (0x1fff << 13) |
132 | #define VIDOSDxA_TOPLEFT_X_SHIFT 13 |
133 | #define VIDOSDxA_TOPLEFT_X_LIMIT 0x1fff |
134 | #define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x1fff) << 13) |
135 | |
136 | #define VIDOSDxA_TOPLEFT_Y_MASK (0x1fff << 0) |
137 | #define VIDOSDxA_TOPLEFT_Y_SHIFT 0 |
138 | #define VIDOSDxA_TOPLEFT_Y_LIMIT 0x1fff |
139 | #define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x1fff) << 0) |
140 | |
141 | #define VIDOSDxB_BOTRIGHT_X_MASK (0x1fff << 13) |
142 | #define VIDOSDxB_BOTRIGHT_X_SHIFT 13 |
143 | #define VIDOSDxB_BOTRIGHT_X_LIMIT 0x1fff |
144 | #define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x1fff) << 13) |
145 | |
146 | #define VIDOSDxB_BOTRIGHT_Y_MASK (0x1fff << 0) |
147 | #define VIDOSDxB_BOTRIGHT_Y_SHIFT 0 |
148 | #define VIDOSDxB_BOTRIGHT_Y_LIMIT 0x1fff |
149 | #define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x1fff) << 0) |
150 | |
151 | #define VIDOSDxC_ALPHA0_R_F(_x) (((_x) & 0xFF) << 16) |
152 | #define VIDOSDxC_ALPHA0_G_F(_x) (((_x) & 0xFF) << 8) |
153 | #define VIDOSDxC_ALPHA0_B_F(_x) (((_x) & 0xFF) << 0) |
154 | |
155 | #define VIDOSDxD_ALPHA1_R_F(_x) (((_x) & 0xFF) << 16) |
156 | #define VIDOSDxD_ALPHA1_G_F(_x) (((_x) & 0xFF) << 8) |
157 | #define VIDOSDxD_ALPHA1_B_F(_x) (((_x) & 0xFF) >> 0) |
158 | |
159 | /* Window MAP (Color map) */ |
160 | #define WINxMAP(_win) (0x340 + ((_win) * 4)) |
161 | |
162 | #define WINxMAP_MAP (1 << 24) |
163 | #define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0) |
164 | #define WINxMAP_MAP_COLOUR_SHIFT 0 |
165 | #define WINxMAP_MAP_COLOUR_LIMIT 0xffffff |
166 | #define WINxMAP_MAP_COLOUR(_x) ((_x) << 0) |
167 | |
168 | /* Window colour-key control registers */ |
169 | #define WKEYCON 0x370 |
170 | |
171 | #define WKEYCON0 0x00 |
172 | #define WKEYCON1 0x04 |
173 | #define WxKEYCON0_KEYBL_EN (1 << 26) |
174 | #define WxKEYCON0_KEYEN_F (1 << 25) |
175 | #define WxKEYCON0_DIRCON (1 << 24) |
176 | #define WxKEYCON0_COMPKEY_MASK (0xffffff << 0) |
177 | #define WxKEYCON0_COMPKEY_SHIFT 0 |
178 | #define WxKEYCON0_COMPKEY_LIMIT 0xffffff |
179 | #define WxKEYCON0_COMPKEY(_x) ((_x) << 0) |
180 | #define WxKEYCON1_COLVAL_MASK (0xffffff << 0) |
181 | #define WxKEYCON1_COLVAL_SHIFT 0 |
182 | #define WxKEYCON1_COLVAL_LIMIT 0xffffff |
183 | #define WxKEYCON1_COLVAL(_x) ((_x) << 0) |
184 | |
185 | /* color key control register for hardware window 1 ~ 4. */ |
186 | #define WKEYCON0_BASE(x) ((WKEYCON + WKEYCON0) + ((x - 1) * 8)) |
187 | /* color key value register for hardware window 1 ~ 4. */ |
188 | #define WKEYCON1_BASE(x) ((WKEYCON + WKEYCON1) + ((x - 1) * 8)) |
189 | |
190 | /* Window KEY Alpha value */ |
191 | #define WxKEYALPHA(_win) (0x3A0 + (((_win) - 1) * 0x4)) |
192 | |
193 | #define Wx_KEYALPHA_R_F_SHIFT 16 |
194 | #define Wx_KEYALPHA_G_F_SHIFT 8 |
195 | #define Wx_KEYALPHA_B_F_SHIFT 0 |
196 | |
197 | /* Blending equation */ |
198 | #define BLENDE(_win) (0x03C0 + ((_win) * 4)) |
199 | #define BLENDE_COEF_ZERO 0x0 |
200 | #define BLENDE_COEF_ONE 0x1 |
201 | #define BLENDE_COEF_ALPHA_A 0x2 |
202 | #define BLENDE_COEF_ONE_MINUS_ALPHA_A 0x3 |
203 | #define BLENDE_COEF_ALPHA_B 0x4 |
204 | #define BLENDE_COEF_ONE_MINUS_ALPHA_B 0x5 |
205 | #define BLENDE_COEF_ALPHA0 0x6 |
206 | #define BLENDE_COEF_A 0xA |
207 | #define BLENDE_COEF_ONE_MINUS_A 0xB |
208 | #define BLENDE_COEF_B 0xC |
209 | #define BLENDE_COEF_ONE_MINUS_B 0xD |
210 | #define BLENDE_Q_FUNC(_v) ((_v) << 18) |
211 | #define BLENDE_P_FUNC(_v) ((_v) << 12) |
212 | #define BLENDE_B_FUNC(_v) ((_v) << 6) |
213 | #define BLENDE_A_FUNC(_v) ((_v) << 0) |
214 | |
215 | /* Blending equation control */ |
216 | #define BLENDCON 0x3D8 |
217 | #define BLENDCON_NEW_MASK (1 << 0) |
218 | #define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0) |
219 | #define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0) |
220 | |
221 | /* Interrupt control register */ |
222 | #define VIDINTCON0 0x500 |
223 | |
224 | #define VIDINTCON0_WAKEUP_MASK (0x3f << 26) |
225 | #define (1 << 21) |
226 | |
227 | #define VIDINTCON0_FRAMESEL0_SHIFT 15 |
228 | #define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15) |
229 | #define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15) |
230 | #define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15) |
231 | #define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15) |
232 | #define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15) |
233 | |
234 | #define VIDINTCON0_INT_FRAME (1 << 11) |
235 | |
236 | #define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 3) |
237 | #define VIDINTCON0_FIFOLEVEL_SHIFT 3 |
238 | #define VIDINTCON0_FIFOLEVEL_EMPTY (0x0 << 3) |
239 | #define VIDINTCON0_FIFOLEVEL_TO25PC (0x1 << 3) |
240 | #define VIDINTCON0_FIFOLEVEL_TO50PC (0x2 << 3) |
241 | #define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 3) |
242 | |
243 | #define VIDINTCON0_FIFOSEL_MAIN_EN (1 << 1) |
244 | #define VIDINTCON0_INT_FIFO (1 << 1) |
245 | |
246 | #define VIDINTCON0_INT_ENABLE (1 << 0) |
247 | |
248 | /* Interrupt controls and status register */ |
249 | #define VIDINTCON1 0x504 |
250 | |
251 | #define (1 << 3) |
252 | #define VIDINTCON1_INT_I80 (1 << 2) |
253 | #define VIDINTCON1_INT_FRAME (1 << 1) |
254 | #define VIDINTCON1_INT_FIFO (1 << 0) |
255 | |
256 | /* VIDCON1 */ |
257 | #define VIDCON1(_x) (0x0600 + ((_x) * 0x50)) |
258 | #define VIDCON1_LINECNT_GET(_v) (((_v) >> 17) & 0x1fff) |
259 | #define VIDCON1_VCLK_MASK (0x3 << 9) |
260 | #define VIDCON1_VCLK_HOLD (0x0 << 9) |
261 | #define VIDCON1_VCLK_RUN (0x1 << 9) |
262 | #define VIDCON1_VCLK_RUN_VDEN_DISABLE (0x3 << 9) |
263 | #define VIDCON1_RGB_ORDER_O_MASK (0x7 << 4) |
264 | #define VIDCON1_RGB_ORDER_O_RGB (0x0 << 4) |
265 | #define VIDCON1_RGB_ORDER_O_GBR (0x1 << 4) |
266 | #define VIDCON1_RGB_ORDER_O_BRG (0x2 << 4) |
267 | #define VIDCON1_RGB_ORDER_O_BGR (0x4 << 4) |
268 | #define VIDCON1_RGB_ORDER_O_RBG (0x5 << 4) |
269 | #define VIDCON1_RGB_ORDER_O_GRB (0x6 << 4) |
270 | |
271 | /* VIDTCON0 */ |
272 | #define VIDTCON0 0x610 |
273 | |
274 | #define VIDTCON0_VBPD_MASK (0xffff << 16) |
275 | #define VIDTCON0_VBPD_SHIFT 16 |
276 | #define VIDTCON0_VBPD_LIMIT 0xffff |
277 | #define VIDTCON0_VBPD(_x) ((_x) << 16) |
278 | |
279 | #define VIDTCON0_VFPD_MASK (0xffff << 0) |
280 | #define VIDTCON0_VFPD_SHIFT 0 |
281 | #define VIDTCON0_VFPD_LIMIT 0xffff |
282 | #define VIDTCON0_VFPD(_x) ((_x) << 0) |
283 | |
284 | /* VIDTCON1 */ |
285 | #define VIDTCON1 0x614 |
286 | |
287 | #define VIDTCON1_VSPW_MASK (0xffff << 16) |
288 | #define VIDTCON1_VSPW_SHIFT 16 |
289 | #define VIDTCON1_VSPW_LIMIT 0xffff |
290 | #define VIDTCON1_VSPW(_x) ((_x) << 16) |
291 | |
292 | /* VIDTCON2 */ |
293 | #define VIDTCON2 0x618 |
294 | |
295 | #define VIDTCON2_HBPD_MASK (0xffff << 16) |
296 | #define VIDTCON2_HBPD_SHIFT 16 |
297 | #define VIDTCON2_HBPD_LIMIT 0xffff |
298 | #define VIDTCON2_HBPD(_x) ((_x) << 16) |
299 | |
300 | #define VIDTCON2_HFPD_MASK (0xffff << 0) |
301 | #define VIDTCON2_HFPD_SHIFT 0 |
302 | #define VIDTCON2_HFPD_LIMIT 0xffff |
303 | #define VIDTCON2_HFPD(_x) ((_x) << 0) |
304 | |
305 | /* VIDTCON3 */ |
306 | #define VIDTCON3 0x61C |
307 | |
308 | #define VIDTCON3_HSPW_MASK (0xffff << 16) |
309 | #define VIDTCON3_HSPW_SHIFT 16 |
310 | #define VIDTCON3_HSPW_LIMIT 0xffff |
311 | #define VIDTCON3_HSPW(_x) ((_x) << 16) |
312 | |
313 | /* VIDTCON4 */ |
314 | #define VIDTCON4 0x620 |
315 | |
316 | #define VIDTCON4_LINEVAL_MASK (0xfff << 16) |
317 | #define VIDTCON4_LINEVAL_SHIFT 16 |
318 | #define VIDTCON4_LINEVAL_LIMIT 0xfff |
319 | #define VIDTCON4_LINEVAL(_x) (((_x) & 0xfff) << 16) |
320 | |
321 | #define VIDTCON4_HOZVAL_MASK (0xfff << 0) |
322 | #define VIDTCON4_HOZVAL_SHIFT 0 |
323 | #define VIDTCON4_HOZVAL_LIMIT 0xfff |
324 | #define VIDTCON4_HOZVAL(_x) (((_x) & 0xfff) << 0) |
325 | |
326 | /* LINECNT OP THRSHOLD*/ |
327 | #define LINECNT_OP_THRESHOLD 0x630 |
328 | |
329 | /* CRCCTRL */ |
330 | #define CRCCTRL 0x6C8 |
331 | #define CRCCTRL_CRCCLKEN (0x1 << 2) |
332 | #define CRCCTRL_CRCSTART_F (0x1 << 1) |
333 | #define CRCCTRL_CRCEN (0x1 << 0) |
334 | |
335 | /* DECON_CMU */ |
336 | #define DECON_CMU 0x704 |
337 | |
338 | #define DECON_CMU_ALL_CLKGATE_ENABLE 0x3 |
339 | #define DECON_CMU_SE_CLKGATE_ENABLE (0x1 << 2) |
340 | #define DECON_CMU_SFR_CLKGATE_ENABLE (0x1 << 1) |
341 | #define DECON_CMU_MEM_CLKGATE_ENABLE (0x1 << 0) |
342 | |
343 | /* DECON_UPDATE */ |
344 | #define DECON_UPDATE 0x710 |
345 | |
346 | #define DECON_UPDATE_SLAVE_SYNC (1 << 4) |
347 | #define DECON_UPDATE_STANDALONE_F (1 << 0) |
348 | |
349 | #endif /* EXYNOS_REGS_DECON7_H */ |
350 | |