| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* drivers/gpu/drm/exynos/regs-fimc.h |
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| 3 | * |
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| 4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. |
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| 5 | * http://www.samsung.com/ |
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| 6 | * |
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| 7 | * Register definition file for Samsung Camera Interface (FIMC) driver |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef EXYNOS_REGS_FIMC_H |
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| 11 | #define EXYNOS_REGS_FIMC_H |
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| 12 | |
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| 13 | /* |
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| 14 | * Register part |
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| 15 | */ |
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| 16 | /* Input source format */ |
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| 17 | #define EXYNOS_CISRCFMT (0x00) |
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| 18 | /* Window offset */ |
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| 19 | #define EXYNOS_CIWDOFST (0x04) |
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| 20 | /* Global control */ |
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| 21 | #define EXYNOS_CIGCTRL (0x08) |
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| 22 | /* Window offset 2 */ |
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| 23 | #define EXYNOS_CIWDOFST2 (0x14) |
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| 24 | /* Y 1st frame start address for output DMA */ |
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| 25 | #define EXYNOS_CIOYSA1 (0x18) |
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| 26 | /* Y 2nd frame start address for output DMA */ |
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| 27 | #define EXYNOS_CIOYSA2 (0x1c) |
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| 28 | /* Y 3rd frame start address for output DMA */ |
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| 29 | #define EXYNOS_CIOYSA3 (0x20) |
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| 30 | /* Y 4th frame start address for output DMA */ |
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| 31 | #define EXYNOS_CIOYSA4 (0x24) |
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| 32 | /* Cb 1st frame start address for output DMA */ |
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| 33 | #define EXYNOS_CIOCBSA1 (0x28) |
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| 34 | /* Cb 2nd frame start address for output DMA */ |
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| 35 | #define EXYNOS_CIOCBSA2 (0x2c) |
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| 36 | /* Cb 3rd frame start address for output DMA */ |
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| 37 | #define EXYNOS_CIOCBSA3 (0x30) |
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| 38 | /* Cb 4th frame start address for output DMA */ |
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| 39 | #define EXYNOS_CIOCBSA4 (0x34) |
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| 40 | /* Cr 1st frame start address for output DMA */ |
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| 41 | #define EXYNOS_CIOCRSA1 (0x38) |
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| 42 | /* Cr 2nd frame start address for output DMA */ |
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| 43 | #define EXYNOS_CIOCRSA2 (0x3c) |
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| 44 | /* Cr 3rd frame start address for output DMA */ |
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| 45 | #define EXYNOS_CIOCRSA3 (0x40) |
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| 46 | /* Cr 4th frame start address for output DMA */ |
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| 47 | #define EXYNOS_CIOCRSA4 (0x44) |
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| 48 | /* Target image format */ |
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| 49 | #define EXYNOS_CITRGFMT (0x48) |
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| 50 | /* Output DMA control */ |
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| 51 | #define EXYNOS_CIOCTRL (0x4c) |
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| 52 | /* Pre-scaler control 1 */ |
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| 53 | #define EXYNOS_CISCPRERATIO (0x50) |
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| 54 | /* Pre-scaler control 2 */ |
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| 55 | #define EXYNOS_CISCPREDST (0x54) |
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| 56 | /* Main scaler control */ |
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| 57 | #define EXYNOS_CISCCTRL (0x58) |
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| 58 | /* Target area */ |
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| 59 | #define EXYNOS_CITAREA (0x5c) |
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| 60 | /* Status */ |
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| 61 | #define EXYNOS_CISTATUS (0x64) |
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| 62 | /* Status2 */ |
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| 63 | #define EXYNOS_CISTATUS2 (0x68) |
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| 64 | /* Image capture enable command */ |
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| 65 | #define EXYNOS_CIIMGCPT (0xc0) |
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| 66 | /* Capture sequence */ |
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| 67 | #define EXYNOS_CICPTSEQ (0xc4) |
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| 68 | /* Image effects */ |
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| 69 | #define EXYNOS_CIIMGEFF (0xd0) |
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| 70 | /* Y frame start address for input DMA */ |
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| 71 | #define EXYNOS_CIIYSA0 (0xd4) |
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| 72 | /* Cb frame start address for input DMA */ |
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| 73 | #define EXYNOS_CIICBSA0 (0xd8) |
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| 74 | /* Cr frame start address for input DMA */ |
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| 75 | #define EXYNOS_CIICRSA0 (0xdc) |
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| 76 | /* Input DMA Y Line Skip */ |
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| 77 | #define EXYNOS_CIILINESKIP_Y (0xec) |
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| 78 | /* Input DMA Cb Line Skip */ |
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| 79 | #define EXYNOS_CIILINESKIP_CB (0xf0) |
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| 80 | /* Input DMA Cr Line Skip */ |
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| 81 | #define EXYNOS_CIILINESKIP_CR (0xf4) |
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| 82 | /* Real input DMA image size */ |
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| 83 | #define EXYNOS_CIREAL_ISIZE (0xf8) |
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| 84 | /* Input DMA control */ |
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| 85 | #define EXYNOS_MSCTRL (0xfc) |
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| 86 | /* Y frame start address for input DMA */ |
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| 87 | #define EXYNOS_CIIYSA1 (0x144) |
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| 88 | /* Cb frame start address for input DMA */ |
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| 89 | #define EXYNOS_CIICBSA1 (0x148) |
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| 90 | /* Cr frame start address for input DMA */ |
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| 91 | #define EXYNOS_CIICRSA1 (0x14c) |
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| 92 | /* Output DMA Y offset */ |
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| 93 | #define EXYNOS_CIOYOFF (0x168) |
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| 94 | /* Output DMA CB offset */ |
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| 95 | #define EXYNOS_CIOCBOFF (0x16c) |
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| 96 | /* Output DMA CR offset */ |
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| 97 | #define EXYNOS_CIOCROFF (0x170) |
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| 98 | /* Input DMA Y offset */ |
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| 99 | #define EXYNOS_CIIYOFF (0x174) |
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| 100 | /* Input DMA CB offset */ |
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| 101 | #define EXYNOS_CIICBOFF (0x178) |
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| 102 | /* Input DMA CR offset */ |
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| 103 | #define EXYNOS_CIICROFF (0x17c) |
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| 104 | /* Input DMA original image size */ |
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| 105 | #define EXYNOS_ORGISIZE (0x180) |
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| 106 | /* Output DMA original image size */ |
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| 107 | #define EXYNOS_ORGOSIZE (0x184) |
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| 108 | /* Real output DMA image size */ |
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| 109 | #define EXYNOS_CIEXTEN (0x188) |
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| 110 | /* DMA parameter */ |
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| 111 | #define EXYNOS_CIDMAPARAM (0x18c) |
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| 112 | /* MIPI CSI image format */ |
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| 113 | #define EXYNOS_CSIIMGFMT (0x194) |
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| 114 | /* FIMC Clock Source Select */ |
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| 115 | #define EXYNOS_MISC_FIMC (0x198) |
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| 116 | |
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| 117 | /* Add for FIMC v5.1 */ |
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| 118 | /* Output Frame Buffer Sequence */ |
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| 119 | #define EXYNOS_CIFCNTSEQ (0x1fc) |
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| 120 | /* Y 5th frame start address for output DMA */ |
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| 121 | #define EXYNOS_CIOYSA5 (0x200) |
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| 122 | /* Y 6th frame start address for output DMA */ |
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| 123 | #define EXYNOS_CIOYSA6 (0x204) |
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| 124 | /* Y 7th frame start address for output DMA */ |
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| 125 | #define EXYNOS_CIOYSA7 (0x208) |
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| 126 | /* Y 8th frame start address for output DMA */ |
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| 127 | #define EXYNOS_CIOYSA8 (0x20c) |
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| 128 | /* Y 9th frame start address for output DMA */ |
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| 129 | #define EXYNOS_CIOYSA9 (0x210) |
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| 130 | /* Y 10th frame start address for output DMA */ |
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| 131 | #define EXYNOS_CIOYSA10 (0x214) |
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| 132 | /* Y 11th frame start address for output DMA */ |
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| 133 | #define EXYNOS_CIOYSA11 (0x218) |
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| 134 | /* Y 12th frame start address for output DMA */ |
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| 135 | #define EXYNOS_CIOYSA12 (0x21c) |
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| 136 | /* Y 13th frame start address for output DMA */ |
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| 137 | #define EXYNOS_CIOYSA13 (0x220) |
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| 138 | /* Y 14th frame start address for output DMA */ |
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| 139 | #define EXYNOS_CIOYSA14 (0x224) |
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| 140 | /* Y 15th frame start address for output DMA */ |
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| 141 | #define EXYNOS_CIOYSA15 (0x228) |
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| 142 | /* Y 16th frame start address for output DMA */ |
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| 143 | #define EXYNOS_CIOYSA16 (0x22c) |
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| 144 | /* Y 17th frame start address for output DMA */ |
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| 145 | #define EXYNOS_CIOYSA17 (0x230) |
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| 146 | /* Y 18th frame start address for output DMA */ |
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| 147 | #define EXYNOS_CIOYSA18 (0x234) |
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| 148 | /* Y 19th frame start address for output DMA */ |
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| 149 | #define EXYNOS_CIOYSA19 (0x238) |
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| 150 | /* Y 20th frame start address for output DMA */ |
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| 151 | #define EXYNOS_CIOYSA20 (0x23c) |
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| 152 | /* Y 21th frame start address for output DMA */ |
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| 153 | #define EXYNOS_CIOYSA21 (0x240) |
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| 154 | /* Y 22th frame start address for output DMA */ |
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| 155 | #define EXYNOS_CIOYSA22 (0x244) |
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| 156 | /* Y 23th frame start address for output DMA */ |
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| 157 | #define EXYNOS_CIOYSA23 (0x248) |
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| 158 | /* Y 24th frame start address for output DMA */ |
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| 159 | #define EXYNOS_CIOYSA24 (0x24c) |
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| 160 | /* Y 25th frame start address for output DMA */ |
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| 161 | #define EXYNOS_CIOYSA25 (0x250) |
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| 162 | /* Y 26th frame start address for output DMA */ |
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| 163 | #define EXYNOS_CIOYSA26 (0x254) |
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| 164 | /* Y 27th frame start address for output DMA */ |
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| 165 | #define EXYNOS_CIOYSA27 (0x258) |
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| 166 | /* Y 28th frame start address for output DMA */ |
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| 167 | #define EXYNOS_CIOYSA28 (0x25c) |
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| 168 | /* Y 29th frame start address for output DMA */ |
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| 169 | #define EXYNOS_CIOYSA29 (0x260) |
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| 170 | /* Y 30th frame start address for output DMA */ |
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| 171 | #define EXYNOS_CIOYSA30 (0x264) |
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| 172 | /* Y 31th frame start address for output DMA */ |
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| 173 | #define EXYNOS_CIOYSA31 (0x268) |
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| 174 | /* Y 32th frame start address for output DMA */ |
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| 175 | #define EXYNOS_CIOYSA32 (0x26c) |
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| 176 | |
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| 177 | /* CB 5th frame start address for output DMA */ |
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| 178 | #define EXYNOS_CIOCBSA5 (0x270) |
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| 179 | /* CB 6th frame start address for output DMA */ |
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| 180 | #define EXYNOS_CIOCBSA6 (0x274) |
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| 181 | /* CB 7th frame start address for output DMA */ |
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| 182 | #define EXYNOS_CIOCBSA7 (0x278) |
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| 183 | /* CB 8th frame start address for output DMA */ |
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| 184 | #define EXYNOS_CIOCBSA8 (0x27c) |
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| 185 | /* CB 9th frame start address for output DMA */ |
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| 186 | #define EXYNOS_CIOCBSA9 (0x280) |
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| 187 | /* CB 10th frame start address for output DMA */ |
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| 188 | #define EXYNOS_CIOCBSA10 (0x284) |
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| 189 | /* CB 11th frame start address for output DMA */ |
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| 190 | #define EXYNOS_CIOCBSA11 (0x288) |
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| 191 | /* CB 12th frame start address for output DMA */ |
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| 192 | #define EXYNOS_CIOCBSA12 (0x28c) |
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| 193 | /* CB 13th frame start address for output DMA */ |
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| 194 | #define EXYNOS_CIOCBSA13 (0x290) |
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| 195 | /* CB 14th frame start address for output DMA */ |
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| 196 | #define EXYNOS_CIOCBSA14 (0x294) |
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| 197 | /* CB 15th frame start address for output DMA */ |
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| 198 | #define EXYNOS_CIOCBSA15 (0x298) |
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| 199 | /* CB 16th frame start address for output DMA */ |
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| 200 | #define EXYNOS_CIOCBSA16 (0x29c) |
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| 201 | /* CB 17th frame start address for output DMA */ |
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| 202 | #define EXYNOS_CIOCBSA17 (0x2a0) |
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| 203 | /* CB 18th frame start address for output DMA */ |
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| 204 | #define EXYNOS_CIOCBSA18 (0x2a4) |
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| 205 | /* CB 19th frame start address for output DMA */ |
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| 206 | #define EXYNOS_CIOCBSA19 (0x2a8) |
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| 207 | /* CB 20th frame start address for output DMA */ |
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| 208 | #define EXYNOS_CIOCBSA20 (0x2ac) |
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| 209 | /* CB 21th frame start address for output DMA */ |
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| 210 | #define EXYNOS_CIOCBSA21 (0x2b0) |
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| 211 | /* CB 22th frame start address for output DMA */ |
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| 212 | #define EXYNOS_CIOCBSA22 (0x2b4) |
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| 213 | /* CB 23th frame start address for output DMA */ |
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| 214 | #define EXYNOS_CIOCBSA23 (0x2b8) |
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| 215 | /* CB 24th frame start address for output DMA */ |
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| 216 | #define EXYNOS_CIOCBSA24 (0x2bc) |
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| 217 | /* CB 25th frame start address for output DMA */ |
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| 218 | #define EXYNOS_CIOCBSA25 (0x2c0) |
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| 219 | /* CB 26th frame start address for output DMA */ |
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| 220 | #define EXYNOS_CIOCBSA26 (0x2c4) |
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| 221 | /* CB 27th frame start address for output DMA */ |
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| 222 | #define EXYNOS_CIOCBSA27 (0x2c8) |
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| 223 | /* CB 28th frame start address for output DMA */ |
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| 224 | #define EXYNOS_CIOCBSA28 (0x2cc) |
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| 225 | /* CB 29th frame start address for output DMA */ |
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| 226 | #define EXYNOS_CIOCBSA29 (0x2d0) |
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| 227 | /* CB 30th frame start address for output DMA */ |
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| 228 | #define EXYNOS_CIOCBSA30 (0x2d4) |
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| 229 | /* CB 31th frame start address for output DMA */ |
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| 230 | #define EXYNOS_CIOCBSA31 (0x2d8) |
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| 231 | /* CB 32th frame start address for output DMA */ |
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| 232 | #define EXYNOS_CIOCBSA32 (0x2dc) |
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| 233 | |
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| 234 | /* CR 5th frame start address for output DMA */ |
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| 235 | #define EXYNOS_CIOCRSA5 (0x2e0) |
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| 236 | /* CR 6th frame start address for output DMA */ |
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| 237 | #define EXYNOS_CIOCRSA6 (0x2e4) |
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| 238 | /* CR 7th frame start address for output DMA */ |
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| 239 | #define EXYNOS_CIOCRSA7 (0x2e8) |
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| 240 | /* CR 8th frame start address for output DMA */ |
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| 241 | #define EXYNOS_CIOCRSA8 (0x2ec) |
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| 242 | /* CR 9th frame start address for output DMA */ |
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| 243 | #define EXYNOS_CIOCRSA9 (0x2f0) |
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| 244 | /* CR 10th frame start address for output DMA */ |
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| 245 | #define EXYNOS_CIOCRSA10 (0x2f4) |
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| 246 | /* CR 11th frame start address for output DMA */ |
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| 247 | #define EXYNOS_CIOCRSA11 (0x2f8) |
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| 248 | /* CR 12th frame start address for output DMA */ |
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| 249 | #define EXYNOS_CIOCRSA12 (0x2fc) |
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| 250 | /* CR 13th frame start address for output DMA */ |
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| 251 | #define EXYNOS_CIOCRSA13 (0x300) |
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| 252 | /* CR 14th frame start address for output DMA */ |
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| 253 | #define EXYNOS_CIOCRSA14 (0x304) |
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| 254 | /* CR 15th frame start address for output DMA */ |
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| 255 | #define EXYNOS_CIOCRSA15 (0x308) |
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| 256 | /* CR 16th frame start address for output DMA */ |
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| 257 | #define EXYNOS_CIOCRSA16 (0x30c) |
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| 258 | /* CR 17th frame start address for output DMA */ |
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| 259 | #define EXYNOS_CIOCRSA17 (0x310) |
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| 260 | /* CR 18th frame start address for output DMA */ |
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| 261 | #define EXYNOS_CIOCRSA18 (0x314) |
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| 262 | /* CR 19th frame start address for output DMA */ |
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| 263 | #define EXYNOS_CIOCRSA19 (0x318) |
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| 264 | /* CR 20th frame start address for output DMA */ |
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| 265 | #define EXYNOS_CIOCRSA20 (0x31c) |
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| 266 | /* CR 21th frame start address for output DMA */ |
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| 267 | #define EXYNOS_CIOCRSA21 (0x320) |
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| 268 | /* CR 22th frame start address for output DMA */ |
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| 269 | #define EXYNOS_CIOCRSA22 (0x324) |
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| 270 | /* CR 23th frame start address for output DMA */ |
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| 271 | #define EXYNOS_CIOCRSA23 (0x328) |
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| 272 | /* CR 24th frame start address for output DMA */ |
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| 273 | #define EXYNOS_CIOCRSA24 (0x32c) |
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| 274 | /* CR 25th frame start address for output DMA */ |
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| 275 | #define EXYNOS_CIOCRSA25 (0x330) |
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| 276 | /* CR 26th frame start address for output DMA */ |
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| 277 | #define EXYNOS_CIOCRSA26 (0x334) |
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| 278 | /* CR 27th frame start address for output DMA */ |
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| 279 | #define EXYNOS_CIOCRSA27 (0x338) |
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| 280 | /* CR 28th frame start address for output DMA */ |
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| 281 | #define EXYNOS_CIOCRSA28 (0x33c) |
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| 282 | /* CR 29th frame start address for output DMA */ |
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| 283 | #define EXYNOS_CIOCRSA29 (0x340) |
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| 284 | /* CR 30th frame start address for output DMA */ |
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| 285 | #define EXYNOS_CIOCRSA30 (0x344) |
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| 286 | /* CR 31th frame start address for output DMA */ |
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| 287 | #define EXYNOS_CIOCRSA31 (0x348) |
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| 288 | /* CR 32th frame start address for output DMA */ |
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| 289 | #define EXYNOS_CIOCRSA32 (0x34c) |
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| 290 | |
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| 291 | /* |
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| 292 | * Macro part |
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| 293 | */ |
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| 294 | /* frame start address 1 ~ 4, 5 ~ 32 */ |
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| 295 | /* Number of Default PingPong Memory */ |
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| 296 | #define DEF_PP 4 |
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| 297 | #define EXYNOS_CIOYSA(__x) \ |
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| 298 | (((__x) < DEF_PP) ? \ |
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| 299 | (EXYNOS_CIOYSA1 + (__x) * 4) : \ |
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| 300 | (EXYNOS_CIOYSA5 + ((__x) - DEF_PP) * 4)) |
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| 301 | #define EXYNOS_CIOCBSA(__x) \ |
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| 302 | (((__x) < DEF_PP) ? \ |
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| 303 | (EXYNOS_CIOCBSA1 + (__x) * 4) : \ |
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| 304 | (EXYNOS_CIOCBSA5 + ((__x) - DEF_PP) * 4)) |
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| 305 | #define EXYNOS_CIOCRSA(__x) \ |
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| 306 | (((__x) < DEF_PP) ? \ |
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| 307 | (EXYNOS_CIOCRSA1 + (__x) * 4) : \ |
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| 308 | (EXYNOS_CIOCRSA5 + ((__x) - DEF_PP) * 4)) |
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| 309 | /* Number of Default PingPong Memory */ |
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| 310 | #define DEF_IPP 1 |
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| 311 | #define EXYNOS_CIIYSA(__x) \ |
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| 312 | (((__x) < DEF_IPP) ? \ |
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| 313 | (EXYNOS_CIIYSA0) : (EXYNOS_CIIYSA1)) |
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| 314 | #define EXYNOS_CIICBSA(__x) \ |
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| 315 | (((__x) < DEF_IPP) ? \ |
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| 316 | (EXYNOS_CIICBSA0) : (EXYNOS_CIICBSA1)) |
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| 317 | #define EXYNOS_CIICRSA(__x) \ |
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| 318 | (((__x) < DEF_IPP) ? \ |
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| 319 | (EXYNOS_CIICRSA0) : (EXYNOS_CIICRSA1)) |
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| 320 | |
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| 321 | #define EXYNOS_CISRCFMT_SOURCEHSIZE(x) ((x) << 16) |
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| 322 | #define EXYNOS_CISRCFMT_SOURCEVSIZE(x) ((x) << 0) |
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| 323 | |
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| 324 | #define EXYNOS_CIWDOFST_WINHOROFST(x) ((x) << 16) |
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| 325 | #define EXYNOS_CIWDOFST_WINVEROFST(x) ((x) << 0) |
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| 326 | |
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| 327 | #define EXYNOS_CIWDOFST2_WINHOROFST2(x) ((x) << 16) |
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| 328 | #define EXYNOS_CIWDOFST2_WINVEROFST2(x) ((x) << 0) |
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| 329 | |
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| 330 | #define EXYNOS_CITRGFMT_TARGETHSIZE(x) (((x) & 0x1fff) << 16) |
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| 331 | #define EXYNOS_CITRGFMT_TARGETVSIZE(x) (((x) & 0x1fff) << 0) |
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| 332 | |
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| 333 | #define EXYNOS_CISCPRERATIO_SHFACTOR(x) ((x) << 28) |
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| 334 | #define EXYNOS_CISCPRERATIO_PREHORRATIO(x) ((x) << 16) |
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| 335 | #define EXYNOS_CISCPRERATIO_PREVERRATIO(x) ((x) << 0) |
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| 336 | |
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| 337 | #define EXYNOS_CISCPREDST_PREDSTWIDTH(x) ((x) << 16) |
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| 338 | #define EXYNOS_CISCPREDST_PREDSTHEIGHT(x) ((x) << 0) |
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| 339 | |
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| 340 | #define EXYNOS_CISCCTRL_MAINHORRATIO(x) ((x) << 16) |
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| 341 | #define EXYNOS_CISCCTRL_MAINVERRATIO(x) ((x) << 0) |
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| 342 | |
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| 343 | #define EXYNOS_CITAREA_TARGET_AREA(x) ((x) << 0) |
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| 344 | |
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| 345 | #define EXYNOS_CISTATUS_GET_FRAME_COUNT(x) (((x) >> 26) & 0x3) |
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| 346 | #define EXYNOS_CISTATUS_GET_FRAME_END(x) (((x) >> 17) & 0x1) |
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| 347 | #define EXYNOS_CISTATUS_GET_LAST_CAPTURE_END(x) (((x) >> 16) & 0x1) |
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| 348 | #define EXYNOS_CISTATUS_GET_LCD_STATUS(x) (((x) >> 9) & 0x1) |
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| 349 | #define EXYNOS_CISTATUS_GET_ENVID_STATUS(x) (((x) >> 8) & 0x1) |
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| 350 | |
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| 351 | #define EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(x) (((x) >> 7) & 0x3f) |
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| 352 | #define EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(x) ((x) & 0x3f) |
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| 353 | |
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| 354 | #define EXYNOS_CIIMGEFF_FIN(x) ((x & 0x7) << 26) |
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| 355 | #define EXYNOS_CIIMGEFF_PAT_CB(x) ((x) << 13) |
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| 356 | #define EXYNOS_CIIMGEFF_PAT_CR(x) ((x) << 0) |
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| 357 | |
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| 358 | #define EXYNOS_CIILINESKIP(x) (((x) & 0xf) << 24) |
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| 359 | |
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| 360 | #define EXYNOS_CIREAL_ISIZE_HEIGHT(x) ((x) << 16) |
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| 361 | #define EXYNOS_CIREAL_ISIZE_WIDTH(x) ((x) << 0) |
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| 362 | |
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| 363 | #define EXYNOS_MSCTRL_SUCCESSIVE_COUNT(x) ((x) << 24) |
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| 364 | #define EXYNOS_MSCTRL_GET_INDMA_STATUS(x) ((x) & 0x1) |
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| 365 | |
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| 366 | #define EXYNOS_CIOYOFF_VERTICAL(x) ((x) << 16) |
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| 367 | #define EXYNOS_CIOYOFF_HORIZONTAL(x) ((x) << 0) |
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| 368 | |
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| 369 | #define EXYNOS_CIOCBOFF_VERTICAL(x) ((x) << 16) |
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| 370 | #define EXYNOS_CIOCBOFF_HORIZONTAL(x) ((x) << 0) |
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| 371 | |
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| 372 | #define EXYNOS_CIOCROFF_VERTICAL(x) ((x) << 16) |
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| 373 | #define EXYNOS_CIOCROFF_HORIZONTAL(x) ((x) << 0) |
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| 374 | |
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| 375 | #define EXYNOS_CIIYOFF_VERTICAL(x) ((x) << 16) |
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| 376 | #define EXYNOS_CIIYOFF_HORIZONTAL(x) ((x) << 0) |
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| 377 | |
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| 378 | #define EXYNOS_CIICBOFF_VERTICAL(x) ((x) << 16) |
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| 379 | #define EXYNOS_CIICBOFF_HORIZONTAL(x) ((x) << 0) |
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| 380 | |
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| 381 | #define EXYNOS_CIICROFF_VERTICAL(x) ((x) << 16) |
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| 382 | #define EXYNOS_CIICROFF_HORIZONTAL(x) ((x) << 0) |
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| 383 | |
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| 384 | #define EXYNOS_ORGISIZE_VERTICAL(x) ((x) << 16) |
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| 385 | #define EXYNOS_ORGISIZE_HORIZONTAL(x) ((x) << 0) |
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| 386 | |
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| 387 | #define EXYNOS_ORGOSIZE_VERTICAL(x) ((x) << 16) |
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| 388 | #define EXYNOS_ORGOSIZE_HORIZONTAL(x) ((x) << 0) |
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| 389 | |
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| 390 | #define EXYNOS_CIEXTEN_TARGETH_EXT(x) ((((x) & 0x2000) >> 13) << 26) |
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| 391 | #define EXYNOS_CIEXTEN_TARGETV_EXT(x) ((((x) & 0x2000) >> 13) << 24) |
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| 392 | #define EXYNOS_CIEXTEN_MAINHORRATIO_EXT(x) (((x) & 0x3F) << 10) |
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| 393 | #define EXYNOS_CIEXTEN_MAINVERRATIO_EXT(x) ((x) & 0x3F) |
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| 394 | |
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| 395 | /* |
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| 396 | * Bit definition part |
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| 397 | */ |
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| 398 | /* Source format register */ |
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| 399 | #define EXYNOS_CISRCFMT_ITU601_8BIT (1 << 31) |
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| 400 | #define EXYNOS_CISRCFMT_ITU656_8BIT (0 << 31) |
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| 401 | #define EXYNOS_CISRCFMT_ITU601_16BIT (1 << 29) |
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| 402 | #define EXYNOS_CISRCFMT_ORDER422_YCBYCR (0 << 14) |
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| 403 | #define EXYNOS_CISRCFMT_ORDER422_YCRYCB (1 << 14) |
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| 404 | #define EXYNOS_CISRCFMT_ORDER422_CBYCRY (2 << 14) |
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| 405 | #define EXYNOS_CISRCFMT_ORDER422_CRYCBY (3 << 14) |
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| 406 | /* ITU601 16bit only */ |
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| 407 | #define EXYNOS_CISRCFMT_ORDER422_Y4CBCRCBCR (0 << 14) |
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| 408 | /* ITU601 16bit only */ |
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| 409 | #define EXYNOS_CISRCFMT_ORDER422_Y4CRCBCRCB (1 << 14) |
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| 410 | |
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| 411 | /* Window offset register */ |
|---|
| 412 | #define EXYNOS_CIWDOFST_WINOFSEN (1 << 31) |
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| 413 | #define EXYNOS_CIWDOFST_CLROVFIY (1 << 30) |
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| 414 | #define EXYNOS_CIWDOFST_CLROVRLB (1 << 29) |
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| 415 | #define EXYNOS_CIWDOFST_WINHOROFST_MASK (0x7ff << 16) |
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| 416 | #define EXYNOS_CIWDOFST_CLROVFICB (1 << 15) |
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| 417 | #define EXYNOS_CIWDOFST_CLROVFICR (1 << 14) |
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| 418 | #define EXYNOS_CIWDOFST_WINVEROFST_MASK (0xfff << 0) |
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| 419 | |
|---|
| 420 | /* Global control register */ |
|---|
| 421 | #define EXYNOS_CIGCTRL_SWRST (1 << 31) |
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| 422 | #define EXYNOS_CIGCTRL_CAMRST_A (1 << 30) |
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| 423 | #define EXYNOS_CIGCTRL_SELCAM_ITU_B (0 << 29) |
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| 424 | #define EXYNOS_CIGCTRL_SELCAM_ITU_A (1 << 29) |
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| 425 | #define EXYNOS_CIGCTRL_SELCAM_ITU_MASK (1 << 29) |
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| 426 | #define EXYNOS_CIGCTRL_TESTPATTERN_NORMAL (0 << 27) |
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| 427 | #define EXYNOS_CIGCTRL_TESTPATTERN_COLOR_BAR (1 << 27) |
|---|
| 428 | #define EXYNOS_CIGCTRL_TESTPATTERN_HOR_INC (2 << 27) |
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| 429 | #define EXYNOS_CIGCTRL_TESTPATTERN_VER_INC (3 << 27) |
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| 430 | #define EXYNOS_CIGCTRL_TESTPATTERN_MASK (3 << 27) |
|---|
| 431 | #define EXYNOS_CIGCTRL_TESTPATTERN_SHIFT (27) |
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| 432 | #define EXYNOS_CIGCTRL_INVPOLPCLK (1 << 26) |
|---|
| 433 | #define EXYNOS_CIGCTRL_INVPOLVSYNC (1 << 25) |
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| 434 | #define EXYNOS_CIGCTRL_INVPOLHREF (1 << 24) |
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| 435 | #define EXYNOS_CIGCTRL_IRQ_OVFEN (1 << 22) |
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| 436 | #define EXYNOS_CIGCTRL_HREF_MASK (1 << 21) |
|---|
| 437 | #define EXYNOS_CIGCTRL_IRQ_EDGE (0 << 20) |
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| 438 | #define EXYNOS_CIGCTRL_IRQ_LEVEL (1 << 20) |
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| 439 | #define EXYNOS_CIGCTRL_IRQ_CLR (1 << 19) |
|---|
| 440 | #define EXYNOS_CIGCTRL_IRQ_END_DISABLE (1 << 18) |
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| 441 | #define EXYNOS_CIGCTRL_IRQ_DISABLE (0 << 16) |
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| 442 | #define EXYNOS_CIGCTRL_IRQ_ENABLE (1 << 16) |
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| 443 | #define EXYNOS_CIGCTRL_SHADOW_DISABLE (1 << 12) |
|---|
| 444 | #define EXYNOS_CIGCTRL_CAM_JPEG (1 << 8) |
|---|
| 445 | #define EXYNOS_CIGCTRL_SELCAM_MIPI_B (0 << 7) |
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| 446 | #define EXYNOS_CIGCTRL_SELCAM_MIPI_A (1 << 7) |
|---|
| 447 | #define EXYNOS_CIGCTRL_SELCAM_MIPI_MASK (1 << 7) |
|---|
| 448 | #define EXYNOS_CIGCTRL_SELWB_CAMIF_CAMERA (0 << 6) |
|---|
| 449 | #define EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK (1 << 6) |
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| 450 | #define EXYNOS_CIGCTRL_SELWRITEBACK_MASK (1 << 10) |
|---|
| 451 | #define EXYNOS_CIGCTRL_SELWRITEBACK_A (1 << 10) |
|---|
| 452 | #define EXYNOS_CIGCTRL_SELWRITEBACK_B (0 << 10) |
|---|
| 453 | #define EXYNOS_CIGCTRL_SELWB_CAMIF_MASK (1 << 6) |
|---|
| 454 | #define EXYNOS_CIGCTRL_CSC_ITU601 (0 << 5) |
|---|
| 455 | #define EXYNOS_CIGCTRL_CSC_ITU709 (1 << 5) |
|---|
| 456 | #define EXYNOS_CIGCTRL_CSC_MASK (1 << 5) |
|---|
| 457 | #define EXYNOS_CIGCTRL_INVPOLHSYNC (1 << 4) |
|---|
| 458 | #define EXYNOS_CIGCTRL_SELCAM_FIMC_ITU (0 << 3) |
|---|
| 459 | #define EXYNOS_CIGCTRL_SELCAM_FIMC_MIPI (1 << 3) |
|---|
| 460 | #define EXYNOS_CIGCTRL_SELCAM_FIMC_MASK (1 << 3) |
|---|
| 461 | #define EXYNOS_CIGCTRL_PROGRESSIVE (0 << 0) |
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| 462 | #define EXYNOS_CIGCTRL_INTERLACE (1 << 0) |
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| 463 | |
|---|
| 464 | /* Window offset2 register */ |
|---|
| 465 | #define EXYNOS_CIWDOFST_WINHOROFST2_MASK (0xfff << 16) |
|---|
| 466 | #define EXYNOS_CIWDOFST_WINVEROFST2_MASK (0xfff << 16) |
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| 467 | |
|---|
| 468 | /* Target format register */ |
|---|
| 469 | #define EXYNOS_CITRGFMT_INROT90_CLOCKWISE (1 << 31) |
|---|
| 470 | #define EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420 (0 << 29) |
|---|
| 471 | #define EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422 (1 << 29) |
|---|
| 472 | #define EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE (2 << 29) |
|---|
| 473 | #define EXYNOS_CITRGFMT_OUTFORMAT_RGB (3 << 29) |
|---|
| 474 | #define EXYNOS_CITRGFMT_OUTFORMAT_MASK (3 << 29) |
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| 475 | #define EXYNOS_CITRGFMT_FLIP_SHIFT (14) |
|---|
| 476 | #define EXYNOS_CITRGFMT_FLIP_NORMAL (0 << 14) |
|---|
| 477 | #define EXYNOS_CITRGFMT_FLIP_X_MIRROR (1 << 14) |
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| 478 | #define EXYNOS_CITRGFMT_FLIP_Y_MIRROR (2 << 14) |
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| 479 | #define EXYNOS_CITRGFMT_FLIP_180 (3 << 14) |
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| 480 | #define EXYNOS_CITRGFMT_FLIP_MASK (3 << 14) |
|---|
| 481 | #define EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE (1 << 13) |
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| 482 | #define EXYNOS_CITRGFMT_TARGETV_MASK (0x1fff << 0) |
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| 483 | #define EXYNOS_CITRGFMT_TARGETH_MASK (0x1fff << 16) |
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| 484 | |
|---|
| 485 | /* Output DMA control register */ |
|---|
| 486 | #define EXYNOS_CIOCTRL_WEAVE_OUT (1 << 31) |
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| 487 | #define EXYNOS_CIOCTRL_WEAVE_MASK (1 << 31) |
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| 488 | #define EXYNOS_CIOCTRL_LASTENDEN (1 << 30) |
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| 489 | #define EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR (0 << 24) |
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| 490 | #define EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB (1 << 24) |
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| 491 | #define EXYNOS_CIOCTRL_ORDER2P_MSB_CRCB (2 << 24) |
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| 492 | #define EXYNOS_CIOCTRL_ORDER2P_MSB_CBCR (3 << 24) |
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| 493 | #define EXYNOS_CIOCTRL_ORDER2P_SHIFT (24) |
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| 494 | #define EXYNOS_CIOCTRL_ORDER2P_MASK (3 << 24) |
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| 495 | #define EXYNOS_CIOCTRL_YCBCR_3PLANE (0 << 3) |
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| 496 | #define EXYNOS_CIOCTRL_YCBCR_2PLANE (1 << 3) |
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| 497 | #define EXYNOS_CIOCTRL_YCBCR_PLANE_MASK (1 << 3) |
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| 498 | #define EXYNOS_CIOCTRL_LASTIRQ_ENABLE (1 << 2) |
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| 499 | #define EXYNOS_CIOCTRL_ALPHA_OUT (0xff << 4) |
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| 500 | #define EXYNOS_CIOCTRL_ORDER422_YCBYCR (0 << 0) |
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| 501 | #define EXYNOS_CIOCTRL_ORDER422_YCRYCB (1 << 0) |
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| 502 | #define EXYNOS_CIOCTRL_ORDER422_CBYCRY (2 << 0) |
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| 503 | #define EXYNOS_CIOCTRL_ORDER422_CRYCBY (3 << 0) |
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| 504 | #define EXYNOS_CIOCTRL_ORDER422_MASK (3 << 0) |
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| 505 | |
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| 506 | /* Main scaler control register */ |
|---|
| 507 | #define EXYNOS_CISCCTRL_SCALERBYPASS (1 << 31) |
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| 508 | #define EXYNOS_CISCCTRL_SCALEUP_H (1 << 30) |
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| 509 | #define EXYNOS_CISCCTRL_SCALEUP_V (1 << 29) |
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| 510 | #define EXYNOS_CISCCTRL_CSCR2Y_NARROW (0 << 28) |
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| 511 | #define EXYNOS_CISCCTRL_CSCR2Y_WIDE (1 << 28) |
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| 512 | #define EXYNOS_CISCCTRL_CSCY2R_NARROW (0 << 27) |
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| 513 | #define EXYNOS_CISCCTRL_CSCY2R_WIDE (1 << 27) |
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| 514 | #define EXYNOS_CISCCTRL_LCDPATHEN_FIFO (1 << 26) |
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| 515 | #define EXYNOS_CISCCTRL_PROGRESSIVE (0 << 25) |
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| 516 | #define EXYNOS_CISCCTRL_INTERLACE (1 << 25) |
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| 517 | #define EXYNOS_CISCCTRL_SCAN_MASK (1 << 25) |
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| 518 | #define EXYNOS_CISCCTRL_SCALERSTART (1 << 15) |
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| 519 | #define EXYNOS_CISCCTRL_INRGB_FMT_RGB565 (0 << 13) |
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| 520 | #define EXYNOS_CISCCTRL_INRGB_FMT_RGB666 (1 << 13) |
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| 521 | #define EXYNOS_CISCCTRL_INRGB_FMT_RGB888 (2 << 13) |
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| 522 | #define EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK (3 << 13) |
|---|
| 523 | #define EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11) |
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| 524 | #define EXYNOS_CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11) |
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| 525 | #define EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11) |
|---|
| 526 | #define EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK (3 << 11) |
|---|
| 527 | #define EXYNOS_CISCCTRL_EXTRGB_NORMAL (0 << 10) |
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| 528 | #define EXYNOS_CISCCTRL_EXTRGB_EXTENSION (1 << 10) |
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| 529 | #define EXYNOS_CISCCTRL_ONE2ONE (1 << 9) |
|---|
| 530 | #define EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK (0x1ff << 0) |
|---|
| 531 | #define EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK (0x1ff << 16) |
|---|
| 532 | |
|---|
| 533 | /* Status register */ |
|---|
| 534 | #define EXYNOS_CISTATUS_OVFIY (1 << 31) |
|---|
| 535 | #define EXYNOS_CISTATUS_OVFICB (1 << 30) |
|---|
| 536 | #define EXYNOS_CISTATUS_OVFICR (1 << 29) |
|---|
| 537 | #define EXYNOS_CISTATUS_VSYNC (1 << 28) |
|---|
| 538 | #define EXYNOS_CISTATUS_SCALERSTART (1 << 26) |
|---|
| 539 | #define EXYNOS_CISTATUS_WINOFSTEN (1 << 25) |
|---|
| 540 | #define EXYNOS_CISTATUS_IMGCPTEN (1 << 22) |
|---|
| 541 | #define EXYNOS_CISTATUS_IMGCPTENSC (1 << 21) |
|---|
| 542 | #define EXYNOS_CISTATUS_VSYNC_A (1 << 20) |
|---|
| 543 | #define EXYNOS_CISTATUS_VSYNC_B (1 << 19) |
|---|
| 544 | #define EXYNOS_CISTATUS_OVRLB (1 << 18) |
|---|
| 545 | #define EXYNOS_CISTATUS_FRAMEEND (1 << 17) |
|---|
| 546 | #define EXYNOS_CISTATUS_LASTCAPTUREEND (1 << 16) |
|---|
| 547 | #define EXYNOS_CISTATUS_VVALID_A (1 << 15) |
|---|
| 548 | #define EXYNOS_CISTATUS_VVALID_B (1 << 14) |
|---|
| 549 | |
|---|
| 550 | /* Image capture enable register */ |
|---|
| 551 | #define EXYNOS_CIIMGCPT_IMGCPTEN (1 << 31) |
|---|
| 552 | #define EXYNOS_CIIMGCPT_IMGCPTEN_SC (1 << 30) |
|---|
| 553 | #define EXYNOS_CIIMGCPT_CPT_FREN_ENABLE (1 << 25) |
|---|
| 554 | #define EXYNOS_CIIMGCPT_CPT_FRMOD_EN (0 << 18) |
|---|
| 555 | #define EXYNOS_CIIMGCPT_CPT_FRMOD_CNT (1 << 18) |
|---|
| 556 | |
|---|
| 557 | /* Image effects register */ |
|---|
| 558 | #define EXYNOS_CIIMGEFF_IE_DISABLE (0 << 30) |
|---|
| 559 | #define EXYNOS_CIIMGEFF_IE_ENABLE (1 << 30) |
|---|
| 560 | #define EXYNOS_CIIMGEFF_IE_SC_BEFORE (0 << 29) |
|---|
| 561 | #define EXYNOS_CIIMGEFF_IE_SC_AFTER (1 << 29) |
|---|
| 562 | #define EXYNOS_CIIMGEFF_FIN_BYPASS (0 << 26) |
|---|
| 563 | #define EXYNOS_CIIMGEFF_FIN_ARBITRARY (1 << 26) |
|---|
| 564 | #define EXYNOS_CIIMGEFF_FIN_NEGATIVE (2 << 26) |
|---|
| 565 | #define EXYNOS_CIIMGEFF_FIN_ARTFREEZE (3 << 26) |
|---|
| 566 | #define EXYNOS_CIIMGEFF_FIN_EMBOSSING (4 << 26) |
|---|
| 567 | #define EXYNOS_CIIMGEFF_FIN_SILHOUETTE (5 << 26) |
|---|
| 568 | #define EXYNOS_CIIMGEFF_FIN_MASK (7 << 26) |
|---|
| 569 | #define EXYNOS_CIIMGEFF_PAT_CBCR_MASK ((0xff << 13) | (0xff << 0)) |
|---|
| 570 | |
|---|
| 571 | /* Real input DMA size register */ |
|---|
| 572 | #define EXYNOS_CIREAL_ISIZE_AUTOLOAD_ENABLE (1 << 31) |
|---|
| 573 | #define EXYNOS_CIREAL_ISIZE_ADDR_CH_DISABLE (1 << 30) |
|---|
| 574 | #define EXYNOS_CIREAL_ISIZE_HEIGHT_MASK (0x3FFF << 16) |
|---|
| 575 | #define EXYNOS_CIREAL_ISIZE_WIDTH_MASK (0x3FFF << 0) |
|---|
| 576 | |
|---|
| 577 | /* Input DMA control register */ |
|---|
| 578 | #define EXYNOS_MSCTRL_FIELD_MASK (1 << 31) |
|---|
| 579 | #define EXYNOS_MSCTRL_FIELD_WEAVE (1 << 31) |
|---|
| 580 | #define EXYNOS_MSCTRL_FIELD_NORMAL (0 << 31) |
|---|
| 581 | #define EXYNOS_MSCTRL_BURST_CNT (24) |
|---|
| 582 | #define EXYNOS_MSCTRL_BURST_CNT_MASK (0xf << 24) |
|---|
| 583 | #define EXYNOS_MSCTRL_ORDER2P_LSB_CBCR (0 << 16) |
|---|
| 584 | #define EXYNOS_MSCTRL_ORDER2P_LSB_CRCB (1 << 16) |
|---|
| 585 | #define EXYNOS_MSCTRL_ORDER2P_MSB_CRCB (2 << 16) |
|---|
| 586 | #define EXYNOS_MSCTRL_ORDER2P_MSB_CBCR (3 << 16) |
|---|
| 587 | #define EXYNOS_MSCTRL_ORDER2P_SHIFT (16) |
|---|
| 588 | #define EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK (0x3 << 16) |
|---|
| 589 | #define EXYNOS_MSCTRL_C_INT_IN_3PLANE (0 << 15) |
|---|
| 590 | #define EXYNOS_MSCTRL_C_INT_IN_2PLANE (1 << 15) |
|---|
| 591 | #define EXYNOS_MSCTRL_FLIP_SHIFT (13) |
|---|
| 592 | #define EXYNOS_MSCTRL_FLIP_NORMAL (0 << 13) |
|---|
| 593 | #define EXYNOS_MSCTRL_FLIP_X_MIRROR (1 << 13) |
|---|
| 594 | #define EXYNOS_MSCTRL_FLIP_Y_MIRROR (2 << 13) |
|---|
| 595 | #define EXYNOS_MSCTRL_FLIP_180 (3 << 13) |
|---|
| 596 | #define EXYNOS_MSCTRL_FLIP_MASK (3 << 13) |
|---|
| 597 | #define EXYNOS_MSCTRL_ORDER422_CRYCBY (0 << 4) |
|---|
| 598 | #define EXYNOS_MSCTRL_ORDER422_YCRYCB (1 << 4) |
|---|
| 599 | #define EXYNOS_MSCTRL_ORDER422_CBYCRY (2 << 4) |
|---|
| 600 | #define EXYNOS_MSCTRL_ORDER422_YCBYCR (3 << 4) |
|---|
| 601 | #define EXYNOS_MSCTRL_INPUT_EXTCAM (0 << 3) |
|---|
| 602 | #define EXYNOS_MSCTRL_INPUT_MEMORY (1 << 3) |
|---|
| 603 | #define EXYNOS_MSCTRL_INPUT_MASK (1 << 3) |
|---|
| 604 | #define EXYNOS_MSCTRL_INFORMAT_YCBCR420 (0 << 1) |
|---|
| 605 | #define EXYNOS_MSCTRL_INFORMAT_YCBCR422 (1 << 1) |
|---|
| 606 | #define EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE (2 << 1) |
|---|
| 607 | #define EXYNOS_MSCTRL_INFORMAT_RGB (3 << 1) |
|---|
| 608 | #define EXYNOS_MSCTRL_ENVID (1 << 0) |
|---|
| 609 | |
|---|
| 610 | /* DMA parameter register */ |
|---|
| 611 | #define EXYNOS_CIDMAPARAM_R_MODE_LINEAR (0 << 29) |
|---|
| 612 | #define EXYNOS_CIDMAPARAM_R_MODE_CONFTILE (1 << 29) |
|---|
| 613 | #define EXYNOS_CIDMAPARAM_R_MODE_16X16 (2 << 29) |
|---|
| 614 | #define EXYNOS_CIDMAPARAM_R_MODE_64X32 (3 << 29) |
|---|
| 615 | #define EXYNOS_CIDMAPARAM_R_MODE_MASK (3 << 29) |
|---|
| 616 | #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_64 (0 << 24) |
|---|
| 617 | #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_128 (1 << 24) |
|---|
| 618 | #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_256 (2 << 24) |
|---|
| 619 | #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_512 (3 << 24) |
|---|
| 620 | #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_1024 (4 << 24) |
|---|
| 621 | #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_2048 (5 << 24) |
|---|
| 622 | #define EXYNOS_CIDMAPARAM_R_TILE_HSIZE_4096 (6 << 24) |
|---|
| 623 | #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_1 (0 << 20) |
|---|
| 624 | #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_2 (1 << 20) |
|---|
| 625 | #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_4 (2 << 20) |
|---|
| 626 | #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_8 (3 << 20) |
|---|
| 627 | #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_16 (4 << 20) |
|---|
| 628 | #define EXYNOS_CIDMAPARAM_R_TILE_VSIZE_32 (5 << 20) |
|---|
| 629 | #define EXYNOS_CIDMAPARAM_W_MODE_LINEAR (0 << 13) |
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| 630 | #define EXYNOS_CIDMAPARAM_W_MODE_CONFTILE (1 << 13) |
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| 631 | #define EXYNOS_CIDMAPARAM_W_MODE_16X16 (2 << 13) |
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| 632 | #define EXYNOS_CIDMAPARAM_W_MODE_64X32 (3 << 13) |
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| 633 | #define EXYNOS_CIDMAPARAM_W_MODE_MASK (3 << 13) |
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| 634 | #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_64 (0 << 8) |
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| 635 | #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_128 (1 << 8) |
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| 636 | #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_256 (2 << 8) |
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| 637 | #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_512 (3 << 8) |
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| 638 | #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_1024 (4 << 8) |
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| 639 | #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_2048 (5 << 8) |
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| 640 | #define EXYNOS_CIDMAPARAM_W_TILE_HSIZE_4096 (6 << 8) |
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| 641 | #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_1 (0 << 4) |
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| 642 | #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_2 (1 << 4) |
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| 643 | #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_4 (2 << 4) |
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| 644 | #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_8 (3 << 4) |
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| 645 | #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_16 (4 << 4) |
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| 646 | #define EXYNOS_CIDMAPARAM_W_TILE_VSIZE_32 (5 << 4) |
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| 647 | |
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| 648 | /* Gathering Extension register */ |
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| 649 | #define EXYNOS_CIEXTEN_TARGETH_EXT_MASK (1 << 26) |
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| 650 | #define EXYNOS_CIEXTEN_TARGETV_EXT_MASK (1 << 24) |
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| 651 | #define EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK (0x3F << 10) |
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| 652 | #define EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK (0x3F) |
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| 653 | #define EXYNOS_CIEXTEN_YUV444_OUT (1 << 22) |
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| 654 | |
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| 655 | /* FIMC Clock Source Select register */ |
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| 656 | #define EXYNOS_CLKSRC_HCLK (0 << 1) |
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| 657 | #define EXYNOS_CLKSRC_HCLK_MASK (1 << 1) |
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| 658 | #define EXYNOS_CLKSRC_SCLK (1 << 1) |
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| 659 | |
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| 660 | /* SYSREG for FIMC writeback */ |
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| 661 | #define SYSREG_CAMERA_BLK (0x0218) |
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| 662 | #define SYSREG_FIMD0WB_DEST_MASK (0x3 << 23) |
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| 663 | #define SYSREG_FIMD0WB_DEST_SHIFT 23 |
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| 664 | |
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| 665 | #endif /* EXYNOS_REGS_FIMC_H */ |
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| 666 | |
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