| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * |
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| 4 | * Cloned from drivers/media/video/s5p-tv/regs-hdmi.h |
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| 5 | * |
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| 6 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
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| 7 | * http://www.samsung.com/ |
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| 8 | * |
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| 9 | * HDMI register header file for Samsung TVOUT driver |
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| 10 | */ |
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| 11 | |
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| 12 | #ifndef SAMSUNG_REGS_HDMI_H |
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| 13 | #define SAMSUNG_REGS_HDMI_H |
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| 14 | |
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| 15 | /* |
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| 16 | * Register part |
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| 17 | */ |
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| 18 | |
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| 19 | /* HDMI Version 1.3 & Common */ |
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| 20 | #define HDMI_CTRL_BASE(x) ((x) + 0x00000000) |
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| 21 | #define HDMI_CORE_BASE(x) ((x) + 0x00010000) |
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| 22 | #define HDMI_I2S_BASE(x) ((x) + 0x00040000) |
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| 23 | #define HDMI_TG_BASE(x) ((x) + 0x00050000) |
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| 24 | |
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| 25 | /* Control registers */ |
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| 26 | #define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000) |
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| 27 | #define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004) |
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| 28 | #define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C) |
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| 29 | #define HDMI_V13_PHY_RSTOUT HDMI_CTRL_BASE(0x0014) |
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| 30 | #define HDMI_V13_PHY_VPLL HDMI_CTRL_BASE(0x0018) |
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| 31 | #define HDMI_V13_PHY_CMU HDMI_CTRL_BASE(0x001C) |
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| 32 | #define HDMI_V13_CORE_RSTOUT HDMI_CTRL_BASE(0x0020) |
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| 33 | |
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| 34 | /* Core registers */ |
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| 35 | #define HDMI_CON_0 HDMI_CORE_BASE(0x0000) |
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| 36 | #define HDMI_CON_1 HDMI_CORE_BASE(0x0004) |
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| 37 | #define HDMI_CON_2 HDMI_CORE_BASE(0x0008) |
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| 38 | #define HDMI_SYS_STATUS HDMI_CORE_BASE(0x0010) |
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| 39 | #define HDMI_V13_PHY_STATUS HDMI_CORE_BASE(0x0014) |
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| 40 | #define HDMI_STATUS_EN HDMI_CORE_BASE(0x0020) |
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| 41 | #define HDMI_HPD HDMI_CORE_BASE(0x0030) |
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| 42 | #define HDMI_MODE_SEL HDMI_CORE_BASE(0x0040) |
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| 43 | #define HDMI_ENC_EN HDMI_CORE_BASE(0x0044) |
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| 44 | #define HDMI_V13_BLUE_SCREEN_0 HDMI_CORE_BASE(0x0050) |
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| 45 | #define HDMI_V13_BLUE_SCREEN_1 HDMI_CORE_BASE(0x0054) |
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| 46 | #define HDMI_V13_BLUE_SCREEN_2 HDMI_CORE_BASE(0x0058) |
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| 47 | #define HDMI_H_BLANK_0 HDMI_CORE_BASE(0x00A0) |
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| 48 | #define HDMI_H_BLANK_1 HDMI_CORE_BASE(0x00A4) |
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| 49 | #define HDMI_V13_V_BLANK_0 HDMI_CORE_BASE(0x00B0) |
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| 50 | #define HDMI_V13_V_BLANK_1 HDMI_CORE_BASE(0x00B4) |
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| 51 | #define HDMI_V13_V_BLANK_2 HDMI_CORE_BASE(0x00B8) |
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| 52 | #define HDMI_V13_H_V_LINE_0 HDMI_CORE_BASE(0x00C0) |
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| 53 | #define HDMI_V13_H_V_LINE_1 HDMI_CORE_BASE(0x00C4) |
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| 54 | #define HDMI_V13_H_V_LINE_2 HDMI_CORE_BASE(0x00C8) |
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| 55 | #define HDMI_VSYNC_POL HDMI_CORE_BASE(0x00E4) |
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| 56 | #define HDMI_INT_PRO_MODE HDMI_CORE_BASE(0x00E8) |
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| 57 | #define HDMI_V13_V_BLANK_F_0 HDMI_CORE_BASE(0x0110) |
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| 58 | #define HDMI_V13_V_BLANK_F_1 HDMI_CORE_BASE(0x0114) |
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| 59 | #define HDMI_V13_V_BLANK_F_2 HDMI_CORE_BASE(0x0118) |
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| 60 | #define HDMI_V13_H_SYNC_GEN_0 HDMI_CORE_BASE(0x0120) |
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| 61 | #define HDMI_V13_H_SYNC_GEN_1 HDMI_CORE_BASE(0x0124) |
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| 62 | #define HDMI_V13_H_SYNC_GEN_2 HDMI_CORE_BASE(0x0128) |
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| 63 | #define HDMI_V13_V_SYNC_GEN_1_0 HDMI_CORE_BASE(0x0130) |
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| 64 | #define HDMI_V13_V_SYNC_GEN_1_1 HDMI_CORE_BASE(0x0134) |
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| 65 | #define HDMI_V13_V_SYNC_GEN_1_2 HDMI_CORE_BASE(0x0138) |
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| 66 | #define HDMI_V13_V_SYNC_GEN_2_0 HDMI_CORE_BASE(0x0140) |
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| 67 | #define HDMI_V13_V_SYNC_GEN_2_1 HDMI_CORE_BASE(0x0144) |
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| 68 | #define HDMI_V13_V_SYNC_GEN_2_2 HDMI_CORE_BASE(0x0148) |
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| 69 | #define HDMI_V13_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150) |
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| 70 | #define HDMI_V13_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154) |
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| 71 | #define HDMI_V13_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158) |
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| 72 | #define HDMI_V13_AVI_CON HDMI_CORE_BASE(0x0300) |
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| 73 | #define HDMI_V13_AVI_BYTE(n) HDMI_CORE_BASE(0x0320 + 4 * (n)) |
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| 74 | #define HDMI_V13_DC_CONTROL HDMI_CORE_BASE(0x05C0) |
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| 75 | #define HDMI_V13_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4) |
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| 76 | #define HDMI_V13_HPD_GEN HDMI_CORE_BASE(0x05C8) |
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| 77 | #define HDMI_V13_AUI_CON HDMI_CORE_BASE(0x0360) |
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| 78 | #define HDMI_V13_SPD_CON HDMI_CORE_BASE(0x0400) |
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| 79 | |
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| 80 | /* Timing generator registers */ |
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| 81 | #define HDMI_TG_CMD HDMI_TG_BASE(0x0000) |
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| 82 | #define HDMI_TG_H_FSZ_L HDMI_TG_BASE(0x0018) |
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| 83 | #define HDMI_TG_H_FSZ_H HDMI_TG_BASE(0x001C) |
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| 84 | #define HDMI_TG_HACT_ST_L HDMI_TG_BASE(0x0020) |
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| 85 | #define HDMI_TG_HACT_ST_H HDMI_TG_BASE(0x0024) |
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| 86 | #define HDMI_TG_HACT_SZ_L HDMI_TG_BASE(0x0028) |
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| 87 | #define HDMI_TG_HACT_SZ_H HDMI_TG_BASE(0x002C) |
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| 88 | #define HDMI_TG_V_FSZ_L HDMI_TG_BASE(0x0030) |
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| 89 | #define HDMI_TG_V_FSZ_H HDMI_TG_BASE(0x0034) |
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| 90 | #define HDMI_TG_VSYNC_L HDMI_TG_BASE(0x0038) |
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| 91 | #define HDMI_TG_VSYNC_H HDMI_TG_BASE(0x003C) |
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| 92 | #define HDMI_TG_VSYNC2_L HDMI_TG_BASE(0x0040) |
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| 93 | #define HDMI_TG_VSYNC2_H HDMI_TG_BASE(0x0044) |
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| 94 | #define HDMI_TG_VACT_ST_L HDMI_TG_BASE(0x0048) |
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| 95 | #define HDMI_TG_VACT_ST_H HDMI_TG_BASE(0x004C) |
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| 96 | #define HDMI_TG_VACT_SZ_L HDMI_TG_BASE(0x0050) |
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| 97 | #define HDMI_TG_VACT_SZ_H HDMI_TG_BASE(0x0054) |
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| 98 | #define HDMI_TG_FIELD_CHG_L HDMI_TG_BASE(0x0058) |
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| 99 | #define HDMI_TG_FIELD_CHG_H HDMI_TG_BASE(0x005C) |
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| 100 | #define HDMI_TG_VACT_ST2_L HDMI_TG_BASE(0x0060) |
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| 101 | #define HDMI_TG_VACT_ST2_H HDMI_TG_BASE(0x0064) |
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| 102 | #define HDMI_TG_VSYNC_TOP_HDMI_L HDMI_TG_BASE(0x0078) |
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| 103 | #define HDMI_TG_VSYNC_TOP_HDMI_H HDMI_TG_BASE(0x007C) |
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| 104 | #define HDMI_TG_VSYNC_BOT_HDMI_L HDMI_TG_BASE(0x0080) |
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| 105 | #define HDMI_TG_VSYNC_BOT_HDMI_H HDMI_TG_BASE(0x0084) |
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| 106 | #define HDMI_TG_FIELD_TOP_HDMI_L HDMI_TG_BASE(0x0088) |
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| 107 | #define HDMI_TG_FIELD_TOP_HDMI_H HDMI_TG_BASE(0x008C) |
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| 108 | #define HDMI_TG_FIELD_BOT_HDMI_L HDMI_TG_BASE(0x0090) |
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| 109 | #define HDMI_TG_FIELD_BOT_HDMI_H HDMI_TG_BASE(0x0094) |
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| 110 | |
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| 111 | /* |
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| 112 | * Bit definition part |
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| 113 | */ |
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| 114 | |
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| 115 | /* HDMI_INTC_CON */ |
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| 116 | #define HDMI_INTC_EN_GLOBAL (1 << 6) |
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| 117 | #define HDMI_INTC_EN_HPD_PLUG (1 << 3) |
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| 118 | #define HDMI_INTC_EN_HPD_UNPLUG (1 << 2) |
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| 119 | |
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| 120 | /* HDMI_INTC_FLAG */ |
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| 121 | #define HDMI_INTC_FLAG_HPD_PLUG (1 << 3) |
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| 122 | #define HDMI_INTC_FLAG_HPD_UNPLUG (1 << 2) |
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| 123 | |
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| 124 | /* HDMI_PHY_RSTOUT */ |
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| 125 | #define HDMI_PHY_SW_RSTOUT (1 << 0) |
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| 126 | |
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| 127 | /* HDMI_CORE_RSTOUT */ |
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| 128 | #define HDMI_CORE_SW_RSTOUT (1 << 0) |
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| 129 | |
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| 130 | /* HDMI_CON_0 */ |
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| 131 | #define HDMI_BLUE_SCR_EN (1 << 5) |
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| 132 | #define HDMI_ASP_EN (1 << 2) |
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| 133 | #define HDMI_ASP_DIS (0 << 2) |
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| 134 | #define HDMI_ASP_MASK (1 << 2) |
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| 135 | #define HDMI_EN (1 << 0) |
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| 136 | |
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| 137 | /* HDMI_CON_2 */ |
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| 138 | #define HDMI_VID_PREAMBLE_DIS (1 << 5) |
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| 139 | #define HDMI_GUARD_BAND_DIS (1 << 1) |
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| 140 | |
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| 141 | /* HDMI_PHY_STATUS */ |
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| 142 | #define HDMI_PHY_STATUS_READY (1 << 0) |
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| 143 | |
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| 144 | /* HDMI_MODE_SEL */ |
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| 145 | #define HDMI_MODE_HDMI_EN (1 << 1) |
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| 146 | #define HDMI_MODE_DVI_EN (1 << 0) |
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| 147 | #define HDMI_MODE_MASK (3 << 0) |
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| 148 | |
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| 149 | /* HDMI_TG_CMD */ |
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| 150 | #define HDMI_TG_EN (1 << 0) |
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| 151 | #define HDMI_FIELD_EN (1 << 1) |
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| 152 | |
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| 153 | |
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| 154 | /* HDMI Version 1.4 */ |
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| 155 | /* Control registers */ |
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| 156 | /* #define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000) */ |
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| 157 | /* #define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004) */ |
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| 158 | #define HDMI_HDCP_KEY_LOAD HDMI_CTRL_BASE(0x0008) |
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| 159 | /* #define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C) */ |
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| 160 | #define HDMI_INTC_CON_1 HDMI_CTRL_BASE(0x0010) |
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| 161 | #define HDMI_INTC_FLAG_1 HDMI_CTRL_BASE(0x0014) |
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| 162 | #define HDMI_PHY_STATUS_0 HDMI_CTRL_BASE(0x0020) |
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| 163 | #define HDMI_PHY_STATUS_CMU HDMI_CTRL_BASE(0x0024) |
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| 164 | #define HDMI_PHY_STATUS_PLL HDMI_CTRL_BASE(0x0028) |
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| 165 | #define HDMI_PHY_CON_0 HDMI_CTRL_BASE(0x0030) |
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| 166 | #define HDMI_HPD_CTRL HDMI_CTRL_BASE(0x0040) |
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| 167 | #define HDMI_HPD_ST HDMI_CTRL_BASE(0x0044) |
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| 168 | #define HDMI_HPD_TH_X HDMI_CTRL_BASE(0x0050) |
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| 169 | #define HDMI_AUDIO_CLKSEL HDMI_CTRL_BASE(0x0070) |
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| 170 | #define HDMI_V14_PHY_RSTOUT HDMI_CTRL_BASE(0x0074) |
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| 171 | #define HDMI_PHY_VPLL HDMI_CTRL_BASE(0x0078) |
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| 172 | #define HDMI_PHY_CMU HDMI_CTRL_BASE(0x007C) |
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| 173 | #define HDMI_CORE_RSTOUT HDMI_CTRL_BASE(0x0080) |
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| 174 | |
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| 175 | /* PHY Control bit definition */ |
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| 176 | |
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| 177 | /* HDMI_PHY_CON_0 */ |
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| 178 | #define HDMI_PHY_POWER_OFF_EN (1 << 0) |
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| 179 | |
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| 180 | /* Video related registers */ |
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| 181 | #define HDMI_YMAX HDMI_CORE_BASE(0x0060) |
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| 182 | #define HDMI_YMIN HDMI_CORE_BASE(0x0064) |
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| 183 | #define HDMI_CMAX HDMI_CORE_BASE(0x0068) |
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| 184 | #define HDMI_CMIN HDMI_CORE_BASE(0x006C) |
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| 185 | |
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| 186 | #define HDMI_V2_BLANK_0 HDMI_CORE_BASE(0x00B0) |
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| 187 | #define HDMI_V2_BLANK_1 HDMI_CORE_BASE(0x00B4) |
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| 188 | #define HDMI_V1_BLANK_0 HDMI_CORE_BASE(0x00B8) |
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| 189 | #define HDMI_V1_BLANK_1 HDMI_CORE_BASE(0x00BC) |
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| 190 | |
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| 191 | #define HDMI_V_LINE_0 HDMI_CORE_BASE(0x00C0) |
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| 192 | #define HDMI_V_LINE_1 HDMI_CORE_BASE(0x00C4) |
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| 193 | #define HDMI_H_LINE_0 HDMI_CORE_BASE(0x00C8) |
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| 194 | #define HDMI_H_LINE_1 HDMI_CORE_BASE(0x00CC) |
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| 195 | |
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| 196 | #define HDMI_HSYNC_POL HDMI_CORE_BASE(0x00E0) |
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| 197 | |
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| 198 | #define HDMI_V_BLANK_F0_0 HDMI_CORE_BASE(0x0110) |
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| 199 | #define HDMI_V_BLANK_F0_1 HDMI_CORE_BASE(0x0114) |
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| 200 | #define HDMI_V_BLANK_F1_0 HDMI_CORE_BASE(0x0118) |
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| 201 | #define HDMI_V_BLANK_F1_1 HDMI_CORE_BASE(0x011C) |
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| 202 | |
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| 203 | #define HDMI_H_SYNC_START_0 HDMI_CORE_BASE(0x0120) |
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| 204 | #define HDMI_H_SYNC_START_1 HDMI_CORE_BASE(0x0124) |
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| 205 | #define HDMI_H_SYNC_END_0 HDMI_CORE_BASE(0x0128) |
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| 206 | #define HDMI_H_SYNC_END_1 HDMI_CORE_BASE(0x012C) |
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| 207 | |
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| 208 | #define HDMI_V_SYNC_LINE_BEF_2_0 HDMI_CORE_BASE(0x0130) |
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| 209 | #define HDMI_V_SYNC_LINE_BEF_2_1 HDMI_CORE_BASE(0x0134) |
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| 210 | #define HDMI_V_SYNC_LINE_BEF_1_0 HDMI_CORE_BASE(0x0138) |
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| 211 | #define HDMI_V_SYNC_LINE_BEF_1_1 HDMI_CORE_BASE(0x013C) |
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| 212 | |
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| 213 | #define HDMI_V_SYNC_LINE_AFT_2_0 HDMI_CORE_BASE(0x0140) |
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| 214 | #define HDMI_V_SYNC_LINE_AFT_2_1 HDMI_CORE_BASE(0x0144) |
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| 215 | #define HDMI_V_SYNC_LINE_AFT_1_0 HDMI_CORE_BASE(0x0148) |
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| 216 | #define HDMI_V_SYNC_LINE_AFT_1_1 HDMI_CORE_BASE(0x014C) |
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| 217 | |
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| 218 | #define HDMI_V_SYNC_LINE_AFT_PXL_2_0 HDMI_CORE_BASE(0x0150) |
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| 219 | #define HDMI_V_SYNC_LINE_AFT_PXL_2_1 HDMI_CORE_BASE(0x0154) |
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| 220 | #define HDMI_V_SYNC_LINE_AFT_PXL_1_0 HDMI_CORE_BASE(0x0158) |
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| 221 | #define HDMI_V_SYNC_LINE_AFT_PXL_1_1 HDMI_CORE_BASE(0x015C) |
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| 222 | |
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| 223 | #define HDMI_V_BLANK_F2_0 HDMI_CORE_BASE(0x0160) |
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| 224 | #define HDMI_V_BLANK_F2_1 HDMI_CORE_BASE(0x0164) |
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| 225 | #define HDMI_V_BLANK_F3_0 HDMI_CORE_BASE(0x0168) |
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| 226 | #define HDMI_V_BLANK_F3_1 HDMI_CORE_BASE(0x016C) |
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| 227 | #define HDMI_V_BLANK_F4_0 HDMI_CORE_BASE(0x0170) |
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| 228 | #define HDMI_V_BLANK_F4_1 HDMI_CORE_BASE(0x0174) |
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| 229 | #define HDMI_V_BLANK_F5_0 HDMI_CORE_BASE(0x0178) |
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| 230 | #define HDMI_V_BLANK_F5_1 HDMI_CORE_BASE(0x017C) |
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| 231 | |
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| 232 | #define HDMI_V_SYNC_LINE_AFT_3_0 HDMI_CORE_BASE(0x0180) |
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| 233 | #define HDMI_V_SYNC_LINE_AFT_3_1 HDMI_CORE_BASE(0x0184) |
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| 234 | #define HDMI_V_SYNC_LINE_AFT_4_0 HDMI_CORE_BASE(0x0188) |
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| 235 | #define HDMI_V_SYNC_LINE_AFT_4_1 HDMI_CORE_BASE(0x018C) |
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| 236 | #define HDMI_V_SYNC_LINE_AFT_5_0 HDMI_CORE_BASE(0x0190) |
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| 237 | #define HDMI_V_SYNC_LINE_AFT_5_1 HDMI_CORE_BASE(0x0194) |
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| 238 | #define HDMI_V_SYNC_LINE_AFT_6_0 HDMI_CORE_BASE(0x0198) |
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| 239 | #define HDMI_V_SYNC_LINE_AFT_6_1 HDMI_CORE_BASE(0x019C) |
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| 240 | |
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| 241 | #define HDMI_V_SYNC_LINE_AFT_PXL_3_0 HDMI_CORE_BASE(0x01A0) |
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| 242 | #define HDMI_V_SYNC_LINE_AFT_PXL_3_1 HDMI_CORE_BASE(0x01A4) |
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| 243 | #define HDMI_V_SYNC_LINE_AFT_PXL_4_0 HDMI_CORE_BASE(0x01A8) |
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| 244 | #define HDMI_V_SYNC_LINE_AFT_PXL_4_1 HDMI_CORE_BASE(0x01AC) |
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| 245 | #define HDMI_V_SYNC_LINE_AFT_PXL_5_0 HDMI_CORE_BASE(0x01B0) |
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| 246 | #define HDMI_V_SYNC_LINE_AFT_PXL_5_1 HDMI_CORE_BASE(0x01B4) |
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| 247 | #define HDMI_V_SYNC_LINE_AFT_PXL_6_0 HDMI_CORE_BASE(0x01B8) |
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| 248 | #define HDMI_V_SYNC_LINE_AFT_PXL_6_1 HDMI_CORE_BASE(0x01BC) |
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| 249 | |
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| 250 | #define HDMI_VACT_SPACE_1_0 HDMI_CORE_BASE(0x01C0) |
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| 251 | #define HDMI_VACT_SPACE_1_1 HDMI_CORE_BASE(0x01C4) |
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| 252 | #define HDMI_VACT_SPACE_2_0 HDMI_CORE_BASE(0x01C8) |
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| 253 | #define HDMI_VACT_SPACE_2_1 HDMI_CORE_BASE(0x01CC) |
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| 254 | #define HDMI_VACT_SPACE_3_0 HDMI_CORE_BASE(0x01D0) |
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| 255 | #define HDMI_VACT_SPACE_3_1 HDMI_CORE_BASE(0x01D4) |
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| 256 | #define HDMI_VACT_SPACE_4_0 HDMI_CORE_BASE(0x01D8) |
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| 257 | #define HDMI_VACT_SPACE_4_1 HDMI_CORE_BASE(0x01DC) |
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| 258 | #define HDMI_VACT_SPACE_5_0 HDMI_CORE_BASE(0x01E0) |
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| 259 | #define HDMI_VACT_SPACE_5_1 HDMI_CORE_BASE(0x01E4) |
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| 260 | #define HDMI_VACT_SPACE_6_0 HDMI_CORE_BASE(0x01E8) |
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| 261 | #define HDMI_VACT_SPACE_6_1 HDMI_CORE_BASE(0x01EC) |
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| 262 | |
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| 263 | #define HDMI_GCP_CON HDMI_CORE_BASE(0x0200) |
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| 264 | #define HDMI_GCP_BYTE1 HDMI_CORE_BASE(0x0210) |
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| 265 | #define HDMI_GCP_BYTE2 HDMI_CORE_BASE(0x0214) |
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| 266 | #define HDMI_GCP_BYTE3 HDMI_CORE_BASE(0x0218) |
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| 267 | |
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| 268 | /* Audio related registers */ |
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| 269 | #define HDMI_ASP_CON HDMI_CORE_BASE(0x0300) |
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| 270 | #define HDMI_ASP_SP_FLAT HDMI_CORE_BASE(0x0304) |
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| 271 | #define HDMI_ASP_CHCFG0 HDMI_CORE_BASE(0x0310) |
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| 272 | #define HDMI_ASP_CHCFG1 HDMI_CORE_BASE(0x0314) |
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| 273 | #define HDMI_ASP_CHCFG2 HDMI_CORE_BASE(0x0318) |
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| 274 | #define HDMI_ASP_CHCFG3 HDMI_CORE_BASE(0x031C) |
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| 275 | |
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| 276 | #define HDMI_V13_ACR_CON HDMI_CORE_BASE(0x0180) |
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| 277 | #define HDMI_V13_ACR_MCTS0 HDMI_CORE_BASE(0x0184) |
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| 278 | #define HDMI_V13_ACR_MCTS1 HDMI_CORE_BASE(0x0188) |
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| 279 | #define HDMI_V13_ACR_MCTS2 HDMI_CORE_BASE(0x018C) |
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| 280 | #define HDMI_V13_ACR_CTS0 HDMI_CORE_BASE(0x0190) |
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| 281 | #define HDMI_V13_ACR_CTS1 HDMI_CORE_BASE(0x0194) |
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| 282 | #define HDMI_V13_ACR_CTS2 HDMI_CORE_BASE(0x0198) |
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| 283 | #define HDMI_V13_ACR_N0 HDMI_CORE_BASE(0x01A0) |
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| 284 | #define HDMI_V13_ACR_N1 HDMI_CORE_BASE(0x01A4) |
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| 285 | #define HDMI_V13_ACR_N2 HDMI_CORE_BASE(0x01A8) |
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| 286 | #define HDMI_V14_ACR_CON HDMI_CORE_BASE(0x0400) |
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| 287 | #define HDMI_V14_ACR_MCTS0 HDMI_CORE_BASE(0x0410) |
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| 288 | #define HDMI_V14_ACR_MCTS1 HDMI_CORE_BASE(0x0414) |
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| 289 | #define HDMI_V14_ACR_MCTS2 HDMI_CORE_BASE(0x0418) |
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| 290 | #define HDMI_V14_ACR_CTS0 HDMI_CORE_BASE(0x0420) |
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| 291 | #define HDMI_V14_ACR_CTS1 HDMI_CORE_BASE(0x0424) |
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| 292 | #define HDMI_V14_ACR_CTS2 HDMI_CORE_BASE(0x0428) |
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| 293 | #define HDMI_V14_ACR_N0 HDMI_CORE_BASE(0x0430) |
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| 294 | #define HDMI_V14_ACR_N1 HDMI_CORE_BASE(0x0434) |
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| 295 | #define HDMI_V14_ACR_N2 HDMI_CORE_BASE(0x0438) |
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| 296 | |
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| 297 | /* Packet related registers */ |
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| 298 | #define HDMI_ACP_CON HDMI_CORE_BASE(0x0500) |
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| 299 | #define HDMI_ACP_TYPE HDMI_CORE_BASE(0x0514) |
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| 300 | #define HDMI_ACP_DATA(n) HDMI_CORE_BASE(0x0520 + 4 * (n)) |
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| 301 | |
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| 302 | #define HDMI_ISRC_CON HDMI_CORE_BASE(0x0600) |
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| 303 | #define HDMI_CORE_BASE(0x0614) |
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| 304 | #define HDMI_ISRC1_DATA(n) HDMI_CORE_BASE(0x0620 + 4 * (n)) |
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| 305 | #define HDMI_ISRC2_DATA(n) HDMI_CORE_BASE(0x06A0 + 4 * (n)) |
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| 306 | |
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| 307 | #define HDMI_AVI_CON HDMI_CORE_BASE(0x0700) |
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| 308 | #define HDMI_CORE_BASE(0x0710) |
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| 309 | #define HDMI_CORE_BASE(0x0714) |
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| 310 | #define HDMI_CORE_BASE(0x0718) |
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| 311 | #define HDMI_AVI_CHECK_SUM HDMI_CORE_BASE(0x071C) |
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| 312 | #define HDMI_AVI_BYTE(n) HDMI_CORE_BASE(0x0720 + 4 * (n-1)) |
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| 313 | |
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| 314 | #define HDMI_AUI_CON HDMI_CORE_BASE(0x0800) |
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| 315 | #define HDMI_CORE_BASE(0x0810) |
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| 316 | #define HDMI_CORE_BASE(0x0814) |
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| 317 | #define HDMI_CORE_BASE(0x0818) |
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| 318 | #define HDMI_AUI_CHECK_SUM HDMI_CORE_BASE(0x081C) |
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| 319 | #define HDMI_AUI_BYTE(n) HDMI_CORE_BASE(0x0820 + 4 * (n-1)) |
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| 320 | |
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| 321 | #define HDMI_MPG_CON HDMI_CORE_BASE(0x0900) |
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| 322 | #define HDMI_MPG_CHECK_SUM HDMI_CORE_BASE(0x091C) |
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| 323 | #define HDMI_MPG_DATA(n) HDMI_CORE_BASE(0x0920 + 4 * (n)) |
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| 324 | |
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| 325 | #define HDMI_SPD_CON HDMI_CORE_BASE(0x0A00) |
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| 326 | #define HDMI_CORE_BASE(0x0A10) |
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| 327 | #define HDMI_CORE_BASE(0x0A14) |
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| 328 | #define HDMI_CORE_BASE(0x0A18) |
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| 329 | #define HDMI_SPD_DATA(n) HDMI_CORE_BASE(0x0A20 + 4 * (n)) |
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| 330 | |
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| 331 | #define HDMI_GAMUT_CON HDMI_CORE_BASE(0x0B00) |
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| 332 | #define HDMI_CORE_BASE(0x0B10) |
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| 333 | #define HDMI_CORE_BASE(0x0B14) |
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| 334 | #define HDMI_CORE_BASE(0x0B18) |
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| 335 | #define HDMI_GAMUT_METADATA(n) HDMI_CORE_BASE(0x0B20 + 4 * (n)) |
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| 336 | |
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| 337 | #define HDMI_VSI_CON HDMI_CORE_BASE(0x0C00) |
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| 338 | #define HDMI_CORE_BASE(0x0C10) |
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| 339 | #define HDMI_CORE_BASE(0x0C14) |
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| 340 | #define HDMI_CORE_BASE(0x0C18) |
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| 341 | #define HDMI_VSI_DATA(n) HDMI_CORE_BASE(0x0C20 + 4 * (n)) |
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| 342 | |
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| 343 | #define HDMI_DC_CONTROL HDMI_CORE_BASE(0x0D00) |
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| 344 | #define HDMI_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x0D04) |
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| 345 | |
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| 346 | #define HDMI_AN_SEED_SEL HDMI_CORE_BASE(0x0E48) |
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| 347 | #define HDMI_AN_SEED_0 HDMI_CORE_BASE(0x0E58) |
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| 348 | #define HDMI_AN_SEED_1 HDMI_CORE_BASE(0x0E5C) |
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| 349 | #define HDMI_AN_SEED_2 HDMI_CORE_BASE(0x0E60) |
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| 350 | #define HDMI_AN_SEED_3 HDMI_CORE_BASE(0x0E64) |
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| 351 | |
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| 352 | /* AVI bit definition */ |
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| 353 | #define HDMI_AVI_CON_DO_NOT_TRANSMIT (0 << 1) |
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| 354 | #define HDMI_AVI_CON_EVERY_VSYNC (1 << 1) |
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| 355 | |
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| 356 | #define AVI_ACTIVE_FORMAT_VALID (1 << 4) |
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| 357 | #define AVI_UNDERSCANNED_DISPLAY_VALID (1 << 1) |
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| 358 | |
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| 359 | /* AUI bit definition */ |
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| 360 | #define HDMI_AUI_CON_NO_TRAN (0 << 0) |
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| 361 | #define HDMI_AUI_CON_EVERY_VSYNC (1 << 1) |
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| 362 | |
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| 363 | /* VSI bit definition */ |
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| 364 | #define HDMI_VSI_CON_DO_NOT_TRANSMIT (0 << 0) |
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| 365 | #define HDMI_VSI_CON_EVERY_VSYNC (1 << 1) |
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| 366 | |
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| 367 | /* HDCP related registers */ |
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| 368 | #define HDMI_HDCP_SHA1(n) HDMI_CORE_BASE(0x7000 + 4 * (n)) |
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| 369 | #define HDMI_HDCP_KSV_LIST(n) HDMI_CORE_BASE(0x7050 + 4 * (n)) |
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| 370 | |
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| 371 | #define HDMI_HDCP_KSV_LIST_CON HDMI_CORE_BASE(0x7064) |
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| 372 | #define HDMI_HDCP_SHA_RESULT HDMI_CORE_BASE(0x7070) |
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| 373 | #define HDMI_HDCP_CTRL1 HDMI_CORE_BASE(0x7080) |
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| 374 | #define HDMI_HDCP_CTRL2 HDMI_CORE_BASE(0x7084) |
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| 375 | #define HDMI_HDCP_CHECK_RESULT HDMI_CORE_BASE(0x7090) |
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| 376 | #define HDMI_HDCP_BKSV(n) HDMI_CORE_BASE(0x70A0 + 4 * (n)) |
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| 377 | #define HDMI_HDCP_AKSV(n) HDMI_CORE_BASE(0x70C0 + 4 * (n)) |
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| 378 | #define HDMI_HDCP_AN(n) HDMI_CORE_BASE(0x70E0 + 4 * (n)) |
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| 379 | |
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| 380 | #define HDMI_HDCP_BCAPS HDMI_CORE_BASE(0x7100) |
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| 381 | #define HDMI_HDCP_BSTATUS_0 HDMI_CORE_BASE(0x7110) |
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| 382 | #define HDMI_HDCP_BSTATUS_1 HDMI_CORE_BASE(0x7114) |
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| 383 | #define HDMI_HDCP_RI_0 HDMI_CORE_BASE(0x7140) |
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| 384 | #define HDMI_HDCP_RI_1 HDMI_CORE_BASE(0x7144) |
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| 385 | #define HDMI_HDCP_I2C_INT HDMI_CORE_BASE(0x7180) |
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| 386 | #define HDMI_HDCP_AN_INT HDMI_CORE_BASE(0x7190) |
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| 387 | #define HDMI_HDCP_WDT_INT HDMI_CORE_BASE(0x71A0) |
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| 388 | #define HDMI_HDCP_RI_INT HDMI_CORE_BASE(0x71B0) |
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| 389 | #define HDMI_HDCP_RI_COMPARE_0 HDMI_CORE_BASE(0x71D0) |
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| 390 | #define HDMI_HDCP_RI_COMPARE_1 HDMI_CORE_BASE(0x71D4) |
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| 391 | #define HDMI_HDCP_FRAME_COUNT HDMI_CORE_BASE(0x71E0) |
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| 392 | |
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| 393 | #define HDMI_RGB_ROUND_EN HDMI_CORE_BASE(0xD500) |
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| 394 | #define HDMI_VACT_SPACE_R_0 HDMI_CORE_BASE(0xD504) |
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| 395 | #define HDMI_VACT_SPACE_R_1 HDMI_CORE_BASE(0xD508) |
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| 396 | #define HDMI_VACT_SPACE_G_0 HDMI_CORE_BASE(0xD50C) |
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| 397 | #define HDMI_VACT_SPACE_G_1 HDMI_CORE_BASE(0xD510) |
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| 398 | #define HDMI_VACT_SPACE_B_0 HDMI_CORE_BASE(0xD514) |
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| 399 | #define HDMI_VACT_SPACE_B_1 HDMI_CORE_BASE(0xD518) |
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| 400 | |
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| 401 | #define HDMI_BLUE_SCREEN_B_0 HDMI_CORE_BASE(0xD520) |
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| 402 | #define HDMI_BLUE_SCREEN_B_1 HDMI_CORE_BASE(0xD524) |
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| 403 | #define HDMI_BLUE_SCREEN_G_0 HDMI_CORE_BASE(0xD528) |
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| 404 | #define HDMI_BLUE_SCREEN_G_1 HDMI_CORE_BASE(0xD52C) |
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| 405 | #define HDMI_BLUE_SCREEN_R_0 HDMI_CORE_BASE(0xD530) |
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| 406 | #define HDMI_BLUE_SCREEN_R_1 HDMI_CORE_BASE(0xD534) |
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| 407 | |
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| 408 | /* HDMI I2S register */ |
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| 409 | #define HDMI_I2S_CLK_CON HDMI_I2S_BASE(0x000) |
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| 410 | #define HDMI_I2S_CON_1 HDMI_I2S_BASE(0x004) |
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| 411 | #define HDMI_I2S_CON_2 HDMI_I2S_BASE(0x008) |
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| 412 | #define HDMI_I2S_PIN_SEL_0 HDMI_I2S_BASE(0x00c) |
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| 413 | #define HDMI_I2S_PIN_SEL_1 HDMI_I2S_BASE(0x010) |
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| 414 | #define HDMI_I2S_PIN_SEL_2 HDMI_I2S_BASE(0x014) |
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| 415 | #define HDMI_I2S_PIN_SEL_3 HDMI_I2S_BASE(0x018) |
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| 416 | #define HDMI_I2S_DSD_CON HDMI_I2S_BASE(0x01c) |
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| 417 | #define HDMI_I2S_MUX_CON HDMI_I2S_BASE(0x020) |
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| 418 | #define HDMI_I2S_CH_ST_CON HDMI_I2S_BASE(0x024) |
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| 419 | /* n must be within range 0...(HDMI_I2S_CH_ST_MAXNUM - 1) */ |
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| 420 | #define HDMI_I2S_CH_ST_MAXNUM 5 |
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| 421 | #define HDMI_I2S_CH_ST(n) HDMI_I2S_BASE(0x028 + 4 * (n)) |
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| 422 | #define HDMI_I2S_CH_ST_SH_0 HDMI_I2S_BASE(0x03c) |
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| 423 | #define HDMI_I2S_CH_ST_SH_1 HDMI_I2S_BASE(0x040) |
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| 424 | #define HDMI_I2S_CH_ST_SH_2 HDMI_I2S_BASE(0x044) |
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| 425 | #define HDMI_I2S_CH_ST_SH_3 HDMI_I2S_BASE(0x048) |
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| 426 | #define HDMI_I2S_CH_ST_SH_4 HDMI_I2S_BASE(0x04c) |
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| 427 | #define HDMI_I2S_MUX_CH HDMI_I2S_BASE(0x054) |
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| 428 | #define HDMI_I2S_MUX_CUV HDMI_I2S_BASE(0x058) |
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| 429 | |
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| 430 | /* I2S bit definition */ |
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| 431 | |
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| 432 | /* I2S_CLK_CON */ |
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| 433 | #define HDMI_I2S_CLK_DIS (0) |
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| 434 | #define HDMI_I2S_CLK_EN (1) |
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| 435 | |
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| 436 | /* I2S_CON_1 */ |
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| 437 | #define HDMI_I2S_SCLK_FALLING_EDGE (0 << 1) |
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| 438 | #define HDMI_I2S_SCLK_RISING_EDGE (1 << 1) |
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| 439 | #define HDMI_I2S_L_CH_LOW_POL (0) |
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| 440 | #define HDMI_I2S_L_CH_HIGH_POL (1) |
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| 441 | |
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| 442 | /* I2S_CON_2 */ |
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| 443 | #define HDMI_I2S_MSB_FIRST_MODE (0 << 6) |
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| 444 | #define HDMI_I2S_LSB_FIRST_MODE (1 << 6) |
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| 445 | #define HDMI_I2S_BIT_CH_32FS (0 << 4) |
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| 446 | #define HDMI_I2S_BIT_CH_48FS (1 << 4) |
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| 447 | #define HDMI_I2S_BIT_CH_RESERVED (2 << 4) |
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| 448 | #define HDMI_I2S_SDATA_16BIT (1 << 2) |
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| 449 | #define HDMI_I2S_SDATA_20BIT (2 << 2) |
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| 450 | #define HDMI_I2S_SDATA_24BIT (3 << 2) |
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| 451 | #define HDMI_I2S_BASIC_FORMAT (0) |
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| 452 | #define HDMI_I2S_L_JUST_FORMAT (2) |
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| 453 | #define HDMI_I2S_R_JUST_FORMAT (3) |
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| 454 | #define HDMI_I2S_CON_2_CLR (~(0xFF)) |
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| 455 | #define HDMI_I2S_SET_BIT_CH(x) (((x) & 0x7) << 4) |
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| 456 | #define HDMI_I2S_SET_SDATA_BIT(x) (((x) & 0x7) << 2) |
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| 457 | |
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| 458 | /* I2S_PIN_SEL_0 */ |
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| 459 | #define HDMI_I2S_SEL_SCLK(x) (((x) & 0x7) << 4) |
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| 460 | #define HDMI_I2S_SEL_LRCK(x) ((x) & 0x7) |
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| 461 | |
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| 462 | /* I2S_PIN_SEL_1 */ |
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| 463 | #define HDMI_I2S_SEL_SDATA1(x) (((x) & 0x7) << 4) |
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| 464 | #define HDMI_I2S_SEL_SDATA0(x) ((x) & 0x7) |
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| 465 | |
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| 466 | /* I2S_PIN_SEL_2 */ |
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| 467 | #define HDMI_I2S_SEL_SDATA3(x) (((x) & 0x7) << 4) |
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| 468 | #define HDMI_I2S_SEL_SDATA2(x) ((x) & 0x7) |
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| 469 | |
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| 470 | /* I2S_PIN_SEL_3 */ |
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| 471 | #define HDMI_I2S_SEL_DSD(x) ((x) & 0x7) |
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| 472 | |
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| 473 | /* I2S_DSD_CON */ |
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| 474 | #define HDMI_I2S_DSD_CLK_RI_EDGE (1 << 1) |
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| 475 | #define HDMI_I2S_DSD_CLK_FA_EDGE (0 << 1) |
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| 476 | #define HDMI_I2S_DSD_ENABLE (1) |
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| 477 | #define HDMI_I2S_DSD_DISABLE (0) |
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| 478 | |
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| 479 | /* I2S_MUX_CON */ |
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| 480 | #define HDMI_I2S_NOISE_FILTER_ZERO (0 << 5) |
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| 481 | #define HDMI_I2S_NOISE_FILTER_2_STAGE (1 << 5) |
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| 482 | #define HDMI_I2S_NOISE_FILTER_3_STAGE (2 << 5) |
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| 483 | #define HDMI_I2S_NOISE_FILTER_4_STAGE (3 << 5) |
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| 484 | #define HDMI_I2S_NOISE_FILTER_5_STAGE (4 << 5) |
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| 485 | #define HDMI_I2S_IN_DISABLE (1 << 4) |
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| 486 | #define HDMI_I2S_IN_ENABLE (0 << 4) |
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| 487 | #define HDMI_I2S_AUD_SPDIF (0 << 2) |
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| 488 | #define HDMI_I2S_AUD_I2S (1 << 2) |
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| 489 | #define HDMI_I2S_AUD_DSD (2 << 2) |
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| 490 | #define HDMI_I2S_CUV_SPDIF_ENABLE (0 << 1) |
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| 491 | #define HDMI_I2S_CUV_I2S_ENABLE (1 << 1) |
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| 492 | #define HDMI_I2S_MUX_DISABLE (0) |
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| 493 | #define HDMI_I2S_MUX_ENABLE (1) |
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| 494 | #define HDMI_I2S_MUX_CON_CLR (~(0xFF)) |
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| 495 | |
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| 496 | /* I2S_CH_ST_CON */ |
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| 497 | #define HDMI_I2S_CH_STATUS_RELOAD (1) |
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| 498 | #define HDMI_I2S_CH_ST_CON_CLR (~(1)) |
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| 499 | |
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| 500 | /* I2S_CH_ST_0 / I2S_CH_ST_SH_0 */ |
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| 501 | #define HDMI_I2S_CH_STATUS_MODE_0 (0 << 6) |
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| 502 | #define HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH (0 << 3) |
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| 503 | #define HDMI_I2S_2AUD_CH_WITH_PREEMPH (1 << 3) |
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| 504 | #define HDMI_I2S_DEFAULT_EMPHASIS (0 << 3) |
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| 505 | #define HDMI_I2S_COPYRIGHT (0 << 2) |
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| 506 | #define HDMI_I2S_NO_COPYRIGHT (1 << 2) |
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| 507 | #define HDMI_I2S_LINEAR_PCM (0 << 1) |
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| 508 | #define HDMI_I2S_NO_LINEAR_PCM (1 << 1) |
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| 509 | #define HDMI_I2S_CONSUMER_FORMAT (0) |
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| 510 | #define HDMI_I2S_PROF_FORMAT (1) |
|---|
| 511 | #define HDMI_I2S_CH_ST_0_CLR (~(0xFF)) |
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| 512 | |
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| 513 | /* I2S_CH_ST_1 / I2S_CH_ST_SH_1 */ |
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| 514 | #define HDMI_I2S_CD_PLAYER (0x00) |
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| 515 | #define HDMI_I2S_DAT_PLAYER (0x03) |
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| 516 | #define HDMI_I2S_DCC_PLAYER (0x43) |
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| 517 | #define HDMI_I2S_MINI_DISC_PLAYER (0x49) |
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| 518 | |
|---|
| 519 | /* I2S_CH_ST_2 / I2S_CH_ST_SH_2 */ |
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| 520 | #define HDMI_I2S_CHANNEL_NUM_MASK (0xF << 4) |
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| 521 | #define HDMI_I2S_SOURCE_NUM_MASK (0xF) |
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| 522 | #define HDMI_I2S_SET_CHANNEL_NUM(x) (((x) & (0xF)) << 4) |
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| 523 | #define HDMI_I2S_SET_SOURCE_NUM(x) ((x) & (0xF)) |
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| 524 | |
|---|
| 525 | /* I2S_CH_ST_3 / I2S_CH_ST_SH_3 */ |
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| 526 | #define HDMI_I2S_CLK_ACCUR_LEVEL_1 (1 << 4) |
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| 527 | #define HDMI_I2S_CLK_ACCUR_LEVEL_2 (0 << 4) |
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| 528 | #define HDMI_I2S_CLK_ACCUR_LEVEL_3 (2 << 4) |
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| 529 | #define HDMI_I2S_SMP_FREQ_44_1 (0x0) |
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| 530 | #define HDMI_I2S_SMP_FREQ_48 (0x2) |
|---|
| 531 | #define HDMI_I2S_SMP_FREQ_32 (0x3) |
|---|
| 532 | #define HDMI_I2S_SMP_FREQ_96 (0xA) |
|---|
| 533 | #define HDMI_I2S_SET_SMP_FREQ(x) ((x) & (0xF)) |
|---|
| 534 | |
|---|
| 535 | /* I2S_CH_ST_4 / I2S_CH_ST_SH_4 */ |
|---|
| 536 | #define HDMI_I2S_ORG_SMP_FREQ_44_1 (0xF << 4) |
|---|
| 537 | #define HDMI_I2S_ORG_SMP_FREQ_88_2 (0x7 << 4) |
|---|
| 538 | #define HDMI_I2S_ORG_SMP_FREQ_22_05 (0xB << 4) |
|---|
| 539 | #define HDMI_I2S_ORG_SMP_FREQ_176_4 (0x3 << 4) |
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| 540 | #define HDMI_I2S_WORD_LEN_NOT_DEFINE (0x0 << 1) |
|---|
| 541 | #define HDMI_I2S_WORD_LEN_MAX24_20BITS (0x1 << 1) |
|---|
| 542 | #define HDMI_I2S_WORD_LEN_MAX24_22BITS (0x2 << 1) |
|---|
| 543 | #define HDMI_I2S_WORD_LEN_MAX24_23BITS (0x4 << 1) |
|---|
| 544 | #define HDMI_I2S_WORD_LEN_MAX24_24BITS (0x5 << 1) |
|---|
| 545 | #define HDMI_I2S_WORD_LEN_MAX24_21BITS (0x6 << 1) |
|---|
| 546 | #define HDMI_I2S_WORD_LEN_MAX20_16BITS (0x1 << 1) |
|---|
| 547 | #define HDMI_I2S_WORD_LEN_MAX20_18BITS (0x2 << 1) |
|---|
| 548 | #define HDMI_I2S_WORD_LEN_MAX20_19BITS (0x4 << 1) |
|---|
| 549 | #define HDMI_I2S_WORD_LEN_MAX20_20BITS (0x5 << 1) |
|---|
| 550 | #define HDMI_I2S_WORD_LEN_MAX20_17BITS (0x6 << 1) |
|---|
| 551 | #define HDMI_I2S_WORD_LEN_MAX_24BITS (1) |
|---|
| 552 | #define HDMI_I2S_WORD_LEN_MAX_20BITS (0) |
|---|
| 553 | |
|---|
| 554 | /* I2S_MUX_CH */ |
|---|
| 555 | #define HDMI_I2S_CH3_R_EN (1 << 7) |
|---|
| 556 | #define HDMI_I2S_CH3_L_EN (1 << 6) |
|---|
| 557 | #define HDMI_I2S_CH3_EN (3 << 6) |
|---|
| 558 | #define HDMI_I2S_CH2_R_EN (1 << 5) |
|---|
| 559 | #define HDMI_I2S_CH2_L_EN (1 << 4) |
|---|
| 560 | #define HDMI_I2S_CH2_EN (3 << 4) |
|---|
| 561 | #define HDMI_I2S_CH1_R_EN (1 << 3) |
|---|
| 562 | #define HDMI_I2S_CH1_L_EN (1 << 2) |
|---|
| 563 | #define HDMI_I2S_CH1_EN (3 << 2) |
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| 564 | #define HDMI_I2S_CH0_R_EN (1 << 1) |
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| 565 | #define HDMI_I2S_CH0_L_EN (1) |
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| 566 | #define HDMI_I2S_CH0_EN (3) |
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| 567 | #define HDMI_I2S_CH_ALL_EN (0xFF) |
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| 568 | #define HDMI_I2S_MUX_CH_CLR (~HDMI_I2S_CH_ALL_EN) |
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| 569 | |
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| 570 | /* I2S_MUX_CUV */ |
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| 571 | #define HDMI_I2S_CUV_R_EN (1 << 1) |
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| 572 | #define HDMI_I2S_CUV_L_EN (1) |
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| 573 | #define HDMI_I2S_CUV_RL_EN (0x03) |
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| 574 | |
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| 575 | /* I2S_CUV_L_R */ |
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| 576 | #define HDMI_I2S_CUV_R_DATA_MASK (0x7 << 4) |
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| 577 | #define HDMI_I2S_CUV_L_DATA_MASK (0x7) |
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| 578 | |
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| 579 | /* Timing generator registers */ |
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| 580 | /* TG configure/status registers */ |
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| 581 | #define HDMI_TG_VACT_ST3_L HDMI_TG_BASE(0x0068) |
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| 582 | #define HDMI_TG_VACT_ST3_H HDMI_TG_BASE(0x006c) |
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| 583 | #define HDMI_TG_VACT_ST4_L HDMI_TG_BASE(0x0070) |
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| 584 | #define HDMI_TG_VACT_ST4_H HDMI_TG_BASE(0x0074) |
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| 585 | #define HDMI_TG_3D HDMI_TG_BASE(0x00F0) |
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| 586 | #define HDMI_TG_DECON_EN HDMI_TG_BASE(0x01e0) |
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| 587 | |
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| 588 | /* HDMI PHY Registers Offsets*/ |
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| 589 | #define HDMIPHY_POWER 0x74 |
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| 590 | #define HDMIPHY_MODE_SET_DONE 0x7c |
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| 591 | #define HDMIPHY5433_MODE_SET_DONE 0x84 |
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| 592 | |
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| 593 | /* HDMI PHY Values */ |
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| 594 | #define HDMI_PHY_POWER_ON 0x80 |
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| 595 | #define HDMI_PHY_POWER_OFF 0xff |
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| 596 | |
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| 597 | /* HDMI PHY Values */ |
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| 598 | #define HDMI_PHY_DISABLE_MODE_SET 0x80 |
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| 599 | #define HDMI_PHY_ENABLE_MODE_SET 0x00 |
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| 600 | |
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| 601 | /* PMU Registers for PHY */ |
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| 602 | #define PMU_HDMI_PHY_CONTROL 0x700 |
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| 603 | #define PMU_HDMI_PHY_ENABLE_BIT BIT(0) |
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| 604 | |
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| 605 | #define EXYNOS5433_SYSREG_DISP_HDMI_PHY 0x1008 |
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| 606 | #define SYSREG_HDMI_REFCLK_INT_CLK 1 |
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| 607 | |
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| 608 | #endif /* SAMSUNG_REGS_HDMI_H */ |
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| 609 | |
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