1 | /* SPDX-License-Identifier: MIT */ |
2 | /* |
3 | * Copyright © 2022 Intel Corporation |
4 | */ |
5 | |
6 | #ifndef __INTEL_DMC_REGS_H__ |
7 | #define __INTEL_DMC_REGS_H__ |
8 | |
9 | #include "i915_reg_defs.h" |
10 | |
11 | #define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4) |
12 | #define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0 |
13 | |
14 | #define _PIPEDMC_CONTROL_A 0x45250 |
15 | #define _PIPEDMC_CONTROL_B 0x45254 |
16 | #define PIPEDMC_CONTROL(pipe) _MMIO_PIPE(pipe, \ |
17 | _PIPEDMC_CONTROL_A, \ |
18 | _PIPEDMC_CONTROL_B) |
19 | #define PIPEDMC_ENABLE REG_BIT(0) |
20 | |
21 | #define MTL_PIPEDMC_CONTROL _MMIO(0x45250) |
22 | #define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4) |
23 | |
24 | #define _ADLP_PIPEDMC_REG_MMIO_BASE_A 0x5f000 |
25 | #define _TGL_PIPEDMC_REG_MMIO_BASE_A 0x92000 |
26 | |
27 | #define __PIPEDMC_REG_MMIO_BASE(i915, dmc_id) \ |
28 | ((DISPLAY_VER(i915) >= 13 ? _ADLP_PIPEDMC_REG_MMIO_BASE_A : \ |
29 | _TGL_PIPEDMC_REG_MMIO_BASE_A) + \ |
30 | 0x400 * ((dmc_id) - 1)) |
31 | |
32 | #define __DMC_REG_MMIO_BASE 0x8f000 |
33 | |
34 | #define _DMC_REG_MMIO_BASE(i915, dmc_id) \ |
35 | ((dmc_id) == DMC_FW_MAIN ? __DMC_REG_MMIO_BASE : \ |
36 | __PIPEDMC_REG_MMIO_BASE(i915, dmc_id)) |
37 | |
38 | #define _DMC_REG(i915, dmc_id, reg) \ |
39 | ((reg) - __DMC_REG_MMIO_BASE + _DMC_REG_MMIO_BASE(i915, dmc_id)) |
40 | |
41 | #define DMC_EVENT_HANDLER_COUNT_GEN12 8 |
42 | |
43 | #define _DMC_EVT_HTP_0 0x8f004 |
44 | |
45 | #define DMC_EVT_HTP(i915, dmc_id, handler) \ |
46 | _MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_HTP_0) + 4 * (handler)) |
47 | |
48 | #define _DMC_EVT_CTL_0 0x8f034 |
49 | |
50 | #define DMC_EVT_CTL(i915, dmc_id, handler) \ |
51 | _MMIO(_DMC_REG(i915, dmc_id, _DMC_EVT_CTL_0) + 4 * (handler)) |
52 | |
53 | #define DMC_EVT_CTL_ENABLE REG_BIT(31) |
54 | #define DMC_EVT_CTL_RECURRING REG_BIT(30) |
55 | #define DMC_EVT_CTL_TYPE_MASK REG_GENMASK(17, 16) |
56 | #define DMC_EVT_CTL_TYPE_LEVEL_0 0 |
57 | #define DMC_EVT_CTL_TYPE_LEVEL_1 1 |
58 | #define DMC_EVT_CTL_TYPE_EDGE_1_0 2 |
59 | #define DMC_EVT_CTL_TYPE_EDGE_0_1 3 |
60 | |
61 | #define DMC_EVT_CTL_EVENT_ID_MASK REG_GENMASK(15, 8) |
62 | #define DMC_EVT_CTL_EVENT_ID_FALSE 0x01 |
63 | #define DMC_EVT_CTL_EVENT_ID_VBLANK_A 0x32 /* main DMC */ |
64 | /* An event handler scheduled to run at a 1 kHz frequency. */ |
65 | #define DMC_EVT_CTL_EVENT_ID_CLK_MSEC 0xbf |
66 | |
67 | #define DMC_HTP_ADDR_SKL 0x00500034 |
68 | #define DMC_SSP_BASE _MMIO(0x8F074) |
69 | #define DMC_HTP_SKL _MMIO(0x8F004) |
70 | #define DMC_LAST_WRITE _MMIO(0x8F034) |
71 | #define DMC_LAST_WRITE_VALUE 0xc003b400 |
72 | #define DMC_MMIO_START_RANGE 0x80000 |
73 | #define DMC_MMIO_END_RANGE 0x8FFFF |
74 | #define DMC_V1_MMIO_START_RANGE 0x80000 |
75 | #define TGL_MAIN_MMIO_START 0x8F000 |
76 | #define TGL_MAIN_MMIO_END 0x8FFFF |
77 | #define _TGL_PIPEA_MMIO_START 0x92000 |
78 | #define _TGL_PIPEA_MMIO_END 0x93FFF |
79 | #define _TGL_PIPEB_MMIO_START 0x96000 |
80 | #define _TGL_PIPEB_MMIO_END 0x97FFF |
81 | #define ADLP_PIPE_MMIO_START 0x5F000 |
82 | #define ADLP_PIPE_MMIO_END 0x5FFFF |
83 | |
84 | #define TGL_PIPE_MMIO_START(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_START,\ |
85 | _TGL_PIPEB_MMIO_START) |
86 | |
87 | #define TGL_PIPE_MMIO_END(dmc_id) _PICK_EVEN(((dmc_id) - 1), _TGL_PIPEA_MMIO_END,\ |
88 | _TGL_PIPEB_MMIO_END) |
89 | |
90 | #define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030) |
91 | #define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C) |
92 | #define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038) |
93 | #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084) |
94 | #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088) |
95 | #define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154) |
96 | |
97 | #define TGL_DMC_DEBUG3 _MMIO(0x101090) |
98 | #define DG1_DMC_DEBUG3 _MMIO(0x13415c) |
99 | |
100 | #endif /* __INTEL_DMC_REGS_H__ */ |
101 | |