| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2014-2018 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef _INTEL_LRC_REG_H_ |
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| 7 | #define _INTEL_LRC_REG_H_ |
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| 8 | |
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| 9 | #include <linux/types.h> |
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| 10 | |
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| 11 | #define CTX_DESC_FORCE_RESTORE BIT_ULL(2) |
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| 12 | |
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| 13 | /* GEN8 to GEN12 Reg State Context */ |
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| 14 | #define CTX_CONTEXT_CONTROL (0x02 + 1) |
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| 15 | #define CTX_RING_HEAD (0x04 + 1) |
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| 16 | #define CTX_RING_TAIL (0x06 + 1) |
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| 17 | #define CTX_RING_START (0x08 + 1) |
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| 18 | #define CTX_RING_CTL (0x0a + 1) |
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| 19 | #define CTX_BB_STATE (0x10 + 1) |
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| 20 | #define CTX_TIMESTAMP (0x22 + 1) |
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| 21 | #define CTX_PDP3_UDW (0x24 + 1) |
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| 22 | #define CTX_PDP3_LDW (0x26 + 1) |
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| 23 | #define CTX_PDP2_UDW (0x28 + 1) |
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| 24 | #define CTX_PDP2_LDW (0x2a + 1) |
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| 25 | #define CTX_PDP1_UDW (0x2c + 1) |
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| 26 | #define CTX_PDP1_LDW (0x2e + 1) |
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| 27 | #define CTX_PDP0_UDW (0x30 + 1) |
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| 28 | #define CTX_PDP0_LDW (0x32 + 1) |
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| 29 | #define CTX_R_PWR_CLK_STATE (0x42 + 1) |
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| 30 | |
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| 31 | #define GEN9_CTX_RING_MI_MODE 0x54 |
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| 32 | |
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| 33 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ |
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| 34 | u32 *reg_state__ = (reg_state); \ |
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| 35 | const u64 addr__ = i915_page_dir_dma_addr((ppgtt), (n)); \ |
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| 36 | (reg_state__)[CTX_PDP ## n ## _UDW] = upper_32_bits(addr__); \ |
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| 37 | (reg_state__)[CTX_PDP ## n ## _LDW] = lower_32_bits(addr__); \ |
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| 38 | } while (0) |
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| 39 | |
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| 40 | #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ |
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| 41 | u32 *reg_state__ = (reg_state); \ |
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| 42 | const u64 addr__ = px_dma((ppgtt)->pd); \ |
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| 43 | (reg_state__)[CTX_PDP0_UDW] = upper_32_bits(addr__); \ |
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| 44 | (reg_state__)[CTX_PDP0_LDW] = lower_32_bits(addr__); \ |
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| 45 | } while (0) |
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| 46 | |
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| 47 | #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
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| 48 | #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 |
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| 49 | #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x19 |
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| 50 | #define GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x1A |
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| 51 | #define GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0xD |
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| 52 | |
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| 53 | #define GEN8_EXECLISTS_STATUS_BUF 0x370 |
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| 54 | #define GEN11_EXECLISTS_STATUS_BUF2 0x3c0 |
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| 55 | |
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| 56 | /* |
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| 57 | * The docs specify that the write pointer wraps around after 5h, "After status |
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| 58 | * is written out to the last available status QW at offset 5h, this pointer |
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| 59 | * wraps to 0." |
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| 60 | * |
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| 61 | * Therefore, one must infer than even though there are 3 bits available, 6 and |
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| 62 | * 7 appear to be * reserved. |
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| 63 | */ |
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| 64 | #define GEN8_CSB_ENTRIES 6 |
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| 65 | #define GEN8_CSB_PTR_MASK 0x7 |
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| 66 | #define GEN8_CSB_READ_PTR_MASK (GEN8_CSB_PTR_MASK << 8) |
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| 67 | #define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0) |
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| 68 | |
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| 69 | #define GEN11_CSB_ENTRIES 12 |
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| 70 | #define GEN11_CSB_PTR_MASK 0xf |
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| 71 | #define GEN11_CSB_READ_PTR_MASK (GEN11_CSB_PTR_MASK << 8) |
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| 72 | #define GEN11_CSB_WRITE_PTR_MASK (GEN11_CSB_PTR_MASK << 0) |
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| 73 | |
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| 74 | #define MAX_CONTEXT_HW_ID (1 << 21) /* exclusive */ |
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| 75 | #define GEN11_MAX_CONTEXT_HW_ID (1 << 11) /* exclusive */ |
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| 76 | /* in Gen12 ID 0x7FF is reserved to indicate idle */ |
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| 77 | #define GEN12_MAX_CONTEXT_HW_ID (GEN11_MAX_CONTEXT_HW_ID - 1) |
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| 78 | /* in Xe_HP ID 0xFFFF is reserved to indicate "invalid context" */ |
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| 79 | #define XEHP_MAX_CONTEXT_HW_ID 0xFFFF |
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| 80 | |
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| 81 | #endif /* _INTEL_LRC_REG_H_ */ |
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| 82 | |
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