1 | /* SPDX-License-Identifier: MIT */ |
2 | /* |
3 | * Copyright © 2015 Intel Corporation |
4 | */ |
5 | |
6 | #ifndef INTEL_MOCS_H |
7 | #define INTEL_MOCS_H |
8 | |
9 | /** |
10 | * DOC: Memory Objects Control State (MOCS) |
11 | * |
12 | * Motivation: |
13 | * In previous Gens the MOCS settings was a value that was set by user land as |
14 | * part of the batch. In Gen9 this has changed to be a single table (per ring) |
15 | * that all batches now reference by index instead of programming the MOCS |
16 | * directly. |
17 | * |
18 | * The one wrinkle in this is that only PART of the MOCS tables are included |
19 | * in context (The GFX_MOCS_0 - GFX_MOCS_64 and the LNCFCMOCS0 - LNCFCMOCS32 |
20 | * registers). The rest are not (the settings for the other rings). |
21 | * |
22 | * This table needs to be set at system start-up because the way the table |
23 | * interacts with the contexts and the GmmLib interface. |
24 | * |
25 | * |
26 | * Implementation: |
27 | * |
28 | * The tables (one per supported platform) are defined in intel_mocs.c |
29 | * and are programmed in the first batch after the context is loaded |
30 | * (with the hardware workarounds). This will then let the usual |
31 | * context handling keep the MOCS in step. |
32 | */ |
33 | |
34 | struct intel_engine_cs; |
35 | struct intel_gt; |
36 | |
37 | void intel_mocs_init(struct intel_gt *gt); |
38 | void intel_mocs_init_engine(struct intel_engine_cs *engine); |
39 | void intel_set_mocs_index(struct intel_gt *gt); |
40 | |
41 | #endif |
42 | |