1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Zhi Wang <zhi.a.wang@intel.com>
26 *
27 * Contributors:
28 * Min he <min.he@intel.com>
29 *
30 */
31
32#ifndef _GVT_INTERRUPT_H_
33#define _GVT_INTERRUPT_H_
34
35#include <linux/bitops.h>
36
37struct intel_gvt;
38struct intel_gvt_irq;
39struct intel_gvt_irq_info;
40struct intel_gvt_irq_map;
41struct intel_vgpu;
42
43enum intel_gvt_event_type {
44 RCS_MI_USER_INTERRUPT = 0,
45 RCS_DEBUG,
46 RCS_MMIO_SYNC_FLUSH,
47 RCS_CMD_STREAMER_ERR,
48 RCS_PIPE_CONTROL,
49 RCS_L3_PARITY_ERR,
50 RCS_WATCHDOG_EXCEEDED,
51 RCS_PAGE_DIRECTORY_FAULT,
52 RCS_AS_CONTEXT_SWITCH,
53 RCS_MONITOR_BUFF_HALF_FULL,
54
55 VCS_MI_USER_INTERRUPT,
56 VCS_MMIO_SYNC_FLUSH,
57 VCS_CMD_STREAMER_ERR,
58 VCS_MI_FLUSH_DW,
59 VCS_WATCHDOG_EXCEEDED,
60 VCS_PAGE_DIRECTORY_FAULT,
61 VCS_AS_CONTEXT_SWITCH,
62
63 VCS2_MI_USER_INTERRUPT,
64 VCS2_MI_FLUSH_DW,
65 VCS2_AS_CONTEXT_SWITCH,
66
67 BCS_MI_USER_INTERRUPT,
68 BCS_MMIO_SYNC_FLUSH,
69 BCS_CMD_STREAMER_ERR,
70 BCS_MI_FLUSH_DW,
71 BCS_PAGE_DIRECTORY_FAULT,
72 BCS_AS_CONTEXT_SWITCH,
73
74 VECS_MI_USER_INTERRUPT,
75 VECS_MI_FLUSH_DW,
76 VECS_AS_CONTEXT_SWITCH,
77
78 PIPE_A_FIFO_UNDERRUN,
79 PIPE_B_FIFO_UNDERRUN,
80 PIPE_A_CRC_ERR,
81 PIPE_B_CRC_ERR,
82 PIPE_A_CRC_DONE,
83 PIPE_B_CRC_DONE,
84 PIPE_A_ODD_FIELD,
85 PIPE_B_ODD_FIELD,
86 PIPE_A_EVEN_FIELD,
87 PIPE_B_EVEN_FIELD,
88 PIPE_A_LINE_COMPARE,
89 PIPE_B_LINE_COMPARE,
90 PIPE_C_LINE_COMPARE,
91 PIPE_A_VBLANK,
92 PIPE_B_VBLANK,
93 PIPE_C_VBLANK,
94 PIPE_A_VSYNC,
95 PIPE_B_VSYNC,
96 PIPE_C_VSYNC,
97 PRIMARY_A_FLIP_DONE,
98 PRIMARY_B_FLIP_DONE,
99 PRIMARY_C_FLIP_DONE,
100 SPRITE_A_FLIP_DONE,
101 SPRITE_B_FLIP_DONE,
102 SPRITE_C_FLIP_DONE,
103
104 PCU_THERMAL,
105 PCU_PCODE2DRIVER_MAILBOX,
106
107 DPST_PHASE_IN,
108 DPST_HISTOGRAM,
109 GSE,
110 DP_A_HOTPLUG,
111 AUX_CHANNEL_A,
112 PERF_COUNTER,
113 POISON,
114 GTT_FAULT,
115 ERROR_INTERRUPT_COMBINED,
116
117 FDI_RX_INTERRUPTS_TRANSCODER_A,
118 AUDIO_CP_CHANGE_TRANSCODER_A,
119 AUDIO_CP_REQUEST_TRANSCODER_A,
120 FDI_RX_INTERRUPTS_TRANSCODER_B,
121 AUDIO_CP_CHANGE_TRANSCODER_B,
122 AUDIO_CP_REQUEST_TRANSCODER_B,
123 FDI_RX_INTERRUPTS_TRANSCODER_C,
124 AUDIO_CP_CHANGE_TRANSCODER_C,
125 AUDIO_CP_REQUEST_TRANSCODER_C,
126 ERR_AND_DBG,
127 GMBUS,
128 SDVO_B_HOTPLUG,
129 CRT_HOTPLUG,
130 DP_B_HOTPLUG,
131 DP_C_HOTPLUG,
132 DP_D_HOTPLUG,
133 AUX_CHANNEL_B,
134 AUX_CHANNEL_C,
135 AUX_CHANNEL_D,
136 AUDIO_POWER_STATE_CHANGE_B,
137 AUDIO_POWER_STATE_CHANGE_C,
138 AUDIO_POWER_STATE_CHANGE_D,
139
140 INTEL_GVT_EVENT_RESERVED,
141 INTEL_GVT_EVENT_MAX,
142};
143
144typedef void (*gvt_event_virt_handler_t)(struct intel_gvt_irq *irq,
145 enum intel_gvt_event_type event, struct intel_vgpu *vgpu);
146
147struct intel_gvt_irq_ops {
148 void (*init_irq)(struct intel_gvt_irq *irq);
149 void (*check_pending_irq)(struct intel_vgpu *vgpu);
150};
151
152/* the list of physical interrupt control register groups */
153enum intel_gvt_irq_type {
154 INTEL_GVT_IRQ_INFO_GT,
155 INTEL_GVT_IRQ_INFO_DPY,
156 INTEL_GVT_IRQ_INFO_PCH,
157 INTEL_GVT_IRQ_INFO_PM,
158
159 INTEL_GVT_IRQ_INFO_MASTER,
160 INTEL_GVT_IRQ_INFO_GT0,
161 INTEL_GVT_IRQ_INFO_GT1,
162 INTEL_GVT_IRQ_INFO_GT2,
163 INTEL_GVT_IRQ_INFO_GT3,
164 INTEL_GVT_IRQ_INFO_DE_PIPE_A,
165 INTEL_GVT_IRQ_INFO_DE_PIPE_B,
166 INTEL_GVT_IRQ_INFO_DE_PIPE_C,
167 INTEL_GVT_IRQ_INFO_DE_PORT,
168 INTEL_GVT_IRQ_INFO_DE_MISC,
169 INTEL_GVT_IRQ_INFO_AUD,
170 INTEL_GVT_IRQ_INFO_PCU,
171
172 INTEL_GVT_IRQ_INFO_MAX,
173};
174
175#define INTEL_GVT_IRQ_BITWIDTH 32
176
177/* per-event information */
178struct intel_gvt_event_info {
179 int bit; /* map to register bit */
180 struct intel_gvt_irq_info *info; /* register info */
181 gvt_event_virt_handler_t v_handler; /* for v_event */
182};
183
184/* structure containing device specific IRQ state */
185struct intel_gvt_irq {
186 const struct intel_gvt_irq_ops *ops;
187 struct intel_gvt_irq_info *info[INTEL_GVT_IRQ_INFO_MAX];
188 DECLARE_BITMAP(irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX);
189 struct intel_gvt_event_info events[INTEL_GVT_EVENT_MAX];
190 struct intel_gvt_irq_map *irq_map;
191};
192
193int intel_gvt_init_irq(struct intel_gvt *gvt);
194
195void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
196 enum intel_gvt_event_type event);
197
198int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
199 void *p_data, unsigned int bytes);
200int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
201 unsigned int reg, void *p_data, unsigned int bytes);
202int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
203 unsigned int reg, void *p_data, unsigned int bytes);
204int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu,
205 unsigned int reg, void *p_data, unsigned int bytes);
206
207int gvt_ring_id_to_pipe_control_notify_event(int ring_id);
208int gvt_ring_id_to_mi_flush_dw_event(int ring_id);
209int gvt_ring_id_to_mi_user_interrupt_event(int ring_id);
210
211#endif /* _GVT_INTERRUPT_H_ */
212

source code of linux/drivers/gpu/drm/i915/gvt/interrupt.h