| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | /* |
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| 3 | * Copyright © 2022 Intel Corporation |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __INTEL_PERF_OA_REGS__ |
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| 7 | #define __INTEL_PERF_OA_REGS__ |
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| 8 | |
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| 9 | #include "i915_reg_defs.h" |
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| 10 | |
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| 11 | #define GEN7_OACONTROL _MMIO(0x2360) |
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| 12 | #define GEN7_OACONTROL_CTX_MASK 0xFFFFF000 |
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| 13 | #define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F |
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| 14 | #define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6 |
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| 15 | #define GEN7_OACONTROL_TIMER_ENABLE (1 << 5) |
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| 16 | #define GEN7_OACONTROL_FORMAT_A13 (0 << 2) |
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| 17 | #define GEN7_OACONTROL_FORMAT_A29 (1 << 2) |
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| 18 | #define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2 << 2) |
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| 19 | #define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3 << 2) |
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| 20 | #define GEN7_OACONTROL_FORMAT_B4_C8 (4 << 2) |
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| 21 | #define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5 << 2) |
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| 22 | #define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6 << 2) |
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| 23 | #define GEN7_OACONTROL_FORMAT_C4_B8 (7 << 2) |
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| 24 | #define GEN7_OACONTROL_FORMAT_SHIFT 2 |
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| 25 | #define GEN7_OACONTROL_PER_CTX_ENABLE (1 << 1) |
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| 26 | #define GEN7_OACONTROL_ENABLE (1 << 0) |
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| 27 | |
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| 28 | #define GEN8_OACTXID _MMIO(0x2364) |
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| 29 | |
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| 30 | #define GEN8_OA_DEBUG _MMIO(0x2B04) |
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| 31 | #define GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5) |
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| 32 | #define GEN9_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6) |
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| 33 | #define GEN9_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2) |
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| 34 | #define GEN9_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1) |
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| 35 | |
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| 36 | #define GEN8_OACONTROL _MMIO(0x2B00) |
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| 37 | #define GEN8_OA_REPORT_FORMAT_A12 (0 << 2) |
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| 38 | #define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2 << 2) |
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| 39 | #define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5 << 2) |
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| 40 | #define GEN8_OA_REPORT_FORMAT_C4_B8 (7 << 2) |
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| 41 | #define GEN8_OA_REPORT_FORMAT_SHIFT 2 |
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| 42 | #define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1 << 1) |
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| 43 | #define GEN8_OA_COUNTER_ENABLE (1 << 0) |
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| 44 | |
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| 45 | #define GEN8_OACTXCONTROL _MMIO(0x2360) |
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| 46 | #define GEN8_OA_TIMER_PERIOD_MASK 0x3F |
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| 47 | #define GEN8_OA_TIMER_PERIOD_SHIFT 2 |
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| 48 | #define GEN8_OA_TIMER_ENABLE (1 << 1) |
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| 49 | #define GEN8_OA_COUNTER_RESUME (1 << 0) |
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| 50 | |
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| 51 | #define GEN7_OABUFFER _MMIO(0x23B0) /* R/W */ |
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| 52 | #define GEN7_OABUFFER_OVERRUN_DISABLE (1 << 3) |
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| 53 | #define GEN7_OABUFFER_EDGE_TRIGGER (1 << 2) |
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| 54 | #define GEN7_OABUFFER_STOP_RESUME_ENABLE (1 << 1) |
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| 55 | #define GEN7_OABUFFER_RESUME (1 << 0) |
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| 56 | |
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| 57 | #define GEN8_OABUFFER_UDW _MMIO(0x23b4) |
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| 58 | #define GEN8_OABUFFER _MMIO(0x2b14) |
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| 59 | #define GEN8_OABUFFER_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */ |
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| 60 | |
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| 61 | #define GEN7_OASTATUS1 _MMIO(0x2364) |
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| 62 | #define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0 |
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| 63 | #define GEN7_OASTATUS1_COUNTER_OVERFLOW (1 << 2) |
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| 64 | #define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1 << 1) |
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| 65 | #define GEN7_OASTATUS1_REPORT_LOST (1 << 0) |
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| 66 | |
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| 67 | #define GEN7_OASTATUS2 _MMIO(0x2368) |
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| 68 | #define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0 |
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| 69 | #define GEN7_OASTATUS2_MEM_SELECT_GGTT (1 << 0) /* 0: PPGTT, 1: GGTT */ |
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| 70 | |
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| 71 | #define GEN8_OASTATUS _MMIO(0x2b08) |
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| 72 | #define GEN8_OASTATUS_TAIL_POINTER_WRAP (1 << 17) |
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| 73 | #define GEN8_OASTATUS_HEAD_POINTER_WRAP (1 << 16) |
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| 74 | #define GEN8_OASTATUS_OVERRUN_STATUS (1 << 3) |
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| 75 | #define GEN8_OASTATUS_COUNTER_OVERFLOW (1 << 2) |
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| 76 | #define GEN8_OASTATUS_OABUFFER_OVERFLOW (1 << 1) |
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| 77 | #define GEN8_OASTATUS_REPORT_LOST (1 << 0) |
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| 78 | |
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| 79 | #define GEN8_OAHEADPTR _MMIO(0x2B0C) |
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| 80 | #define GEN8_OAHEADPTR_MASK 0xffffffc0 |
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| 81 | #define GEN8_OATAILPTR _MMIO(0x2B10) |
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| 82 | #define GEN8_OATAILPTR_MASK 0xffffffc0 |
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| 83 | |
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| 84 | #define OABUFFER_SIZE_128K (0 << 3) |
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| 85 | #define OABUFFER_SIZE_256K (1 << 3) |
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| 86 | #define OABUFFER_SIZE_512K (2 << 3) |
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| 87 | #define OABUFFER_SIZE_1M (3 << 3) |
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| 88 | #define OABUFFER_SIZE_2M (4 << 3) |
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| 89 | #define OABUFFER_SIZE_4M (5 << 3) |
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| 90 | #define OABUFFER_SIZE_8M (6 << 3) |
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| 91 | #define OABUFFER_SIZE_16M (7 << 3) |
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| 92 | |
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| 93 | #define GEN12_OA_TLB_INV_CR _MMIO(0xceec) |
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| 94 | |
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| 95 | /* Gen12 OAR unit */ |
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| 96 | #define GEN12_OAR_OACONTROL _MMIO(0x2960) |
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| 97 | #define GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT 1 |
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| 98 | #define GEN12_OAR_OACONTROL_COUNTER_ENABLE (1 << 0) |
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| 99 | |
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| 100 | #define GEN12_OACTXCONTROL(base) _MMIO((base) + 0x360) |
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| 101 | #define GEN12_OAR_OASTATUS _MMIO(0x2968) |
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| 102 | |
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| 103 | /* Gen12 OAG unit */ |
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| 104 | #define GEN12_OAG_OAHEADPTR _MMIO(0xdb00) |
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| 105 | #define GEN12_OAG_OAHEADPTR_MASK 0xffffffc0 |
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| 106 | #define GEN12_OAG_OATAILPTR _MMIO(0xdb04) |
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| 107 | #define GEN12_OAG_OATAILPTR_MASK 0xffffffc0 |
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| 108 | |
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| 109 | #define GEN12_OAG_OABUFFER _MMIO(0xdb08) |
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| 110 | #define GEN12_OAG_OABUFFER_BUFFER_SIZE_MASK (0x7) |
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| 111 | #define GEN12_OAG_OABUFFER_BUFFER_SIZE_SHIFT (3) |
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| 112 | #define GEN12_OAG_OABUFFER_MEMORY_SELECT (1 << 0) /* 0: PPGTT, 1: GGTT */ |
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| 113 | |
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| 114 | #define GEN12_OAG_OAGLBCTXCTRL _MMIO(0x2b28) |
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| 115 | #define GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT 2 |
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| 116 | #define GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE (1 << 1) |
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| 117 | #define GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME (1 << 0) |
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| 118 | |
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| 119 | #define GEN12_OAG_OACONTROL _MMIO(0xdaf4) |
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| 120 | #define GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT 2 |
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| 121 | #define GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE (1 << 0) |
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| 122 | |
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| 123 | #define GEN12_OAG_OA_DEBUG _MMIO(0xdaf8) |
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| 124 | #define GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO (1 << 6) |
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| 125 | #define GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS (1 << 5) |
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| 126 | #define GEN12_OAG_OA_DEBUG_DISABLE_GO_1_0_REPORTS (1 << 2) |
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| 127 | #define GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS (1 << 1) |
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| 128 | |
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| 129 | #define GEN12_OAG_OASTATUS _MMIO(0xdafc) |
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| 130 | #define GEN12_OAG_OASTATUS_COUNTER_OVERFLOW (1 << 2) |
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| 131 | #define GEN12_OAG_OASTATUS_BUFFER_OVERFLOW (1 << 1) |
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| 132 | #define GEN12_OAG_OASTATUS_REPORT_LOST (1 << 0) |
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| 133 | |
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| 134 | #define GDT_CHICKEN_BITS _MMIO(0x9840) |
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| 135 | #define GT_NOA_ENABLE 0x00000080 |
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| 136 | |
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| 137 | /* Gen12 OAM unit */ |
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| 138 | #define GEN12_OAM_HEAD_POINTER_OFFSET (0x1a0) |
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| 139 | #define GEN12_OAM_HEAD_POINTER_MASK 0xffffffc0 |
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| 140 | |
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| 141 | #define GEN12_OAM_TAIL_POINTER_OFFSET (0x1a4) |
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| 142 | #define GEN12_OAM_TAIL_POINTER_MASK 0xffffffc0 |
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| 143 | |
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| 144 | #define GEN12_OAM_BUFFER_OFFSET (0x1a8) |
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| 145 | #define GEN12_OAM_BUFFER_SIZE_MASK (0x7) |
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| 146 | #define GEN12_OAM_BUFFER_SIZE_SHIFT (3) |
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| 147 | #define GEN12_OAM_BUFFER_MEMORY_SELECT REG_BIT(0) /* 0: PPGTT, 1: GGTT */ |
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| 148 | |
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| 149 | #define GEN12_OAM_CONTEXT_CONTROL_OFFSET (0x1bc) |
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| 150 | #define GEN12_OAM_CONTEXT_CONTROL_TIMER_PERIOD_SHIFT 2 |
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| 151 | #define GEN12_OAM_CONTEXT_CONTROL_TIMER_ENABLE REG_BIT(1) |
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| 152 | #define GEN12_OAM_CONTEXT_CONTROL_COUNTER_RESUME REG_BIT(0) |
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| 153 | |
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| 154 | #define GEN12_OAM_CONTROL_OFFSET (0x194) |
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| 155 | #define GEN12_OAM_CONTROL_COUNTER_FORMAT_SHIFT 1 |
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| 156 | #define GEN12_OAM_CONTROL_COUNTER_ENABLE REG_BIT(0) |
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| 157 | |
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| 158 | #define GEN12_OAM_DEBUG_OFFSET (0x198) |
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| 159 | #define GEN12_OAM_DEBUG_BUFFER_SIZE_SELECT REG_BIT(12) |
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| 160 | #define GEN12_OAM_DEBUG_INCLUDE_CLK_RATIO REG_BIT(6) |
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| 161 | #define GEN12_OAM_DEBUG_DISABLE_CLK_RATIO_REPORTS REG_BIT(5) |
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| 162 | #define GEN12_OAM_DEBUG_DISABLE_GO_1_0_REPORTS REG_BIT(2) |
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| 163 | #define GEN12_OAM_DEBUG_DISABLE_CTX_SWITCH_REPORTS REG_BIT(1) |
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| 164 | |
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| 165 | #define GEN12_OAM_STATUS_OFFSET (0x19c) |
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| 166 | #define GEN12_OAM_STATUS_COUNTER_OVERFLOW REG_BIT(2) |
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| 167 | #define GEN12_OAM_STATUS_BUFFER_OVERFLOW REG_BIT(1) |
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| 168 | #define GEN12_OAM_STATUS_REPORT_LOST REG_BIT(0) |
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| 169 | |
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| 170 | #define GEN12_OAM_MMIO_TRG_OFFSET (0x1d0) |
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| 171 | |
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| 172 | #define GEN12_OAM_MMIO_TRG(base) \ |
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| 173 | _MMIO((base) + GEN12_OAM_MMIO_TRG_OFFSET) |
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| 174 | |
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| 175 | #define GEN12_OAM_HEAD_POINTER(base) \ |
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| 176 | _MMIO((base) + GEN12_OAM_HEAD_POINTER_OFFSET) |
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| 177 | #define GEN12_OAM_TAIL_POINTER(base) \ |
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| 178 | _MMIO((base) + GEN12_OAM_TAIL_POINTER_OFFSET) |
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| 179 | #define GEN12_OAM_BUFFER(base) \ |
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| 180 | _MMIO((base) + GEN12_OAM_BUFFER_OFFSET) |
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| 181 | #define GEN12_OAM_CONTEXT_CONTROL(base) \ |
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| 182 | _MMIO((base) + GEN12_OAM_CONTEXT_CONTROL_OFFSET) |
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| 183 | #define GEN12_OAM_CONTROL(base) \ |
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| 184 | _MMIO((base) + GEN12_OAM_CONTROL_OFFSET) |
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| 185 | #define GEN12_OAM_DEBUG(base) \ |
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| 186 | _MMIO((base) + GEN12_OAM_DEBUG_OFFSET) |
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| 187 | #define GEN12_OAM_STATUS(base) \ |
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| 188 | _MMIO((base) + GEN12_OAM_STATUS_OFFSET) |
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| 189 | |
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| 190 | #define GEN12_OAM_CEC0_0_OFFSET (0x40) |
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| 191 | #define GEN12_OAM_CEC7_1_OFFSET (0x7c) |
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| 192 | #define GEN12_OAM_CEC0_0(base) \ |
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| 193 | _MMIO((base) + GEN12_OAM_CEC0_0_OFFSET) |
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| 194 | #define GEN12_OAM_CEC7_1(base) \ |
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| 195 | _MMIO((base) + GEN12_OAM_CEC7_1_OFFSET) |
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| 196 | |
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| 197 | #define GEN12_OAM_STARTTRIG1_OFFSET (0x00) |
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| 198 | #define GEN12_OAM_STARTTRIG8_OFFSET (0x1c) |
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| 199 | #define GEN12_OAM_STARTTRIG1(base) \ |
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| 200 | _MMIO((base) + GEN12_OAM_STARTTRIG1_OFFSET) |
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| 201 | #define GEN12_OAM_STARTTRIG8(base) \ |
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| 202 | _MMIO((base) + GEN12_OAM_STARTTRIG8_OFFSET) |
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| 203 | |
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| 204 | #define GEN12_OAM_REPORTTRIG1_OFFSET (0x20) |
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| 205 | #define GEN12_OAM_REPORTTRIG8_OFFSET (0x3c) |
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| 206 | #define GEN12_OAM_REPORTTRIG1(base) \ |
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| 207 | _MMIO((base) + GEN12_OAM_REPORTTRIG1_OFFSET) |
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| 208 | #define GEN12_OAM_REPORTTRIG8(base) \ |
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| 209 | _MMIO((base) + GEN12_OAM_REPORTTRIG8_OFFSET) |
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| 210 | |
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| 211 | #define GEN12_OAM_PERF_COUNTER_B0_OFFSET (0x84) |
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| 212 | #define GEN12_OAM_PERF_COUNTER_B(base, idx) \ |
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| 213 | _MMIO((base) + GEN12_OAM_PERF_COUNTER_B0_OFFSET + 4 * (idx)) |
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| 214 | |
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| 215 | #endif /* __INTEL_PERF_OA_REGS__ */ |
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| 216 | |
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