| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | // |
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| 3 | // Ingenic JZ47xx IPU - Register definitions and private API |
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| 4 | // |
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| 5 | // Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net> |
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| 6 | |
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| 7 | #ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_IPU_H |
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| 8 | #define DRIVERS_GPU_DRM_INGENIC_INGENIC_IPU_H |
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| 9 | |
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| 10 | #include <linux/bitops.h> |
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| 11 | |
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| 12 | #define JZ_REG_IPU_CTRL 0x00 |
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| 13 | #define JZ_REG_IPU_STATUS 0x04 |
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| 14 | #define JZ_REG_IPU_D_FMT 0x08 |
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| 15 | #define JZ_REG_IPU_Y_ADDR 0x0c |
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| 16 | #define JZ_REG_IPU_U_ADDR 0x10 |
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| 17 | #define JZ_REG_IPU_V_ADDR 0x14 |
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| 18 | #define JZ_REG_IPU_IN_GS 0x18 |
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| 19 | #define JZ_REG_IPU_Y_STRIDE 0x1c |
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| 20 | #define JZ_REG_IPU_UV_STRIDE 0x20 |
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| 21 | #define JZ_REG_IPU_OUT_ADDR 0x24 |
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| 22 | #define JZ_REG_IPU_OUT_GS 0x28 |
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| 23 | #define JZ_REG_IPU_OUT_STRIDE 0x2c |
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| 24 | #define JZ_REG_IPU_RSZ_COEF_INDEX 0x30 |
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| 25 | #define JZ_REG_IPU_CSC_C0_COEF 0x34 |
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| 26 | #define JZ_REG_IPU_CSC_C1_COEF 0x38 |
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| 27 | #define JZ_REG_IPU_CSC_C2_COEF 0x3c |
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| 28 | #define JZ_REG_IPU_CSC_C3_COEF 0x40 |
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| 29 | #define JZ_REG_IPU_CSC_C4_COEF 0x44 |
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| 30 | #define JZ_REG_IPU_HRSZ_COEF_LUT 0x48 |
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| 31 | #define JZ_REG_IPU_VRSZ_COEF_LUT 0x4c |
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| 32 | #define JZ_REG_IPU_CSC_OFFSET 0x50 |
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| 33 | #define JZ_REG_IPU_Y_PHY_T_ADDR 0x54 |
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| 34 | #define JZ_REG_IPU_U_PHY_T_ADDR 0x58 |
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| 35 | #define JZ_REG_IPU_V_PHY_T_ADDR 0x5c |
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| 36 | #define JZ_REG_IPU_OUT_PHY_T_ADDR 0x60 |
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| 37 | |
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| 38 | #define JZ_IPU_CTRL_ADDR_SEL BIT(20) |
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| 39 | #define JZ_IPU_CTRL_ZOOM_SEL BIT(18) |
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| 40 | #define JZ_IPU_CTRL_DFIX_SEL BIT(17) |
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| 41 | #define JZ_IPU_CTRL_LCDC_SEL BIT(11) |
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| 42 | #define JZ_IPU_CTRL_SPKG_SEL BIT(10) |
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| 43 | #define JZ_IPU_CTRL_VSCALE BIT(9) |
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| 44 | #define JZ_IPU_CTRL_HSCALE BIT(8) |
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| 45 | #define JZ_IPU_CTRL_STOP BIT(7) |
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| 46 | #define JZ_IPU_CTRL_RST BIT(6) |
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| 47 | #define JZ_IPU_CTRL_FM_IRQ_EN BIT(5) |
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| 48 | #define JZ_IPU_CTRL_CSC_EN BIT(4) |
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| 49 | #define JZ_IPU_CTRL_VRSZ_EN BIT(3) |
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| 50 | #define JZ_IPU_CTRL_HRSZ_EN BIT(2) |
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| 51 | #define JZ_IPU_CTRL_RUN BIT(1) |
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| 52 | #define JZ_IPU_CTRL_CHIP_EN BIT(0) |
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| 53 | |
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| 54 | #define JZ_IPU_STATUS_OUT_END BIT(0) |
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| 55 | |
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| 56 | #define JZ_IPU_IN_GS_H_LSB 0x0 |
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| 57 | #define JZ_IPU_IN_GS_W_LSB 0x10 |
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| 58 | #define JZ_IPU_OUT_GS_H_LSB 0x0 |
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| 59 | #define JZ_IPU_OUT_GS_W_LSB 0x10 |
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| 60 | |
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| 61 | #define JZ_IPU_Y_STRIDE_Y_LSB 0 |
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| 62 | #define JZ_IPU_UV_STRIDE_U_LSB 16 |
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| 63 | #define JZ_IPU_UV_STRIDE_V_LSB 0 |
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| 64 | |
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| 65 | #define JZ_IPU_D_FMT_IN_FMT_LSB 0 |
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| 66 | #define JZ_IPU_D_FMT_IN_FMT_RGB555 (0x0 << JZ_IPU_D_FMT_IN_FMT_LSB) |
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| 67 | #define JZ_IPU_D_FMT_IN_FMT_YUV420 (0x0 << JZ_IPU_D_FMT_IN_FMT_LSB) |
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| 68 | #define JZ_IPU_D_FMT_IN_FMT_YUV422 (0x1 << JZ_IPU_D_FMT_IN_FMT_LSB) |
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| 69 | #define JZ_IPU_D_FMT_IN_FMT_RGB888 (0x2 << JZ_IPU_D_FMT_IN_FMT_LSB) |
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| 70 | #define JZ_IPU_D_FMT_IN_FMT_YUV444 (0x2 << JZ_IPU_D_FMT_IN_FMT_LSB) |
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| 71 | #define JZ_IPU_D_FMT_IN_FMT_RGB565 (0x3 << JZ_IPU_D_FMT_IN_FMT_LSB) |
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| 72 | |
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| 73 | #define JZ_IPU_D_FMT_YUV_FMT_LSB 2 |
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| 74 | #define JZ_IPU_D_FMT_YUV_Y1UY0V (0x0 << JZ_IPU_D_FMT_YUV_FMT_LSB) |
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| 75 | #define JZ_IPU_D_FMT_YUV_Y1VY0U (0x1 << JZ_IPU_D_FMT_YUV_FMT_LSB) |
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| 76 | #define JZ_IPU_D_FMT_YUV_UY1VY0 (0x2 << JZ_IPU_D_FMT_YUV_FMT_LSB) |
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| 77 | #define JZ_IPU_D_FMT_YUV_VY1UY0 (0x3 << JZ_IPU_D_FMT_YUV_FMT_LSB) |
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| 78 | #define JZ_IPU_D_FMT_IN_FMT_YUV411 (0x3 << JZ_IPU_D_FMT_IN_FMT_LSB) |
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| 79 | |
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| 80 | #define JZ_IPU_D_FMT_OUT_FMT_LSB 19 |
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| 81 | #define JZ_IPU_D_FMT_OUT_FMT_RGB555 (0x0 << JZ_IPU_D_FMT_OUT_FMT_LSB) |
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| 82 | #define JZ_IPU_D_FMT_OUT_FMT_RGB565 (0x1 << JZ_IPU_D_FMT_OUT_FMT_LSB) |
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| 83 | #define JZ_IPU_D_FMT_OUT_FMT_RGB888 (0x2 << JZ_IPU_D_FMT_OUT_FMT_LSB) |
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| 84 | #define JZ_IPU_D_FMT_OUT_FMT_YUV422 (0x3 << JZ_IPU_D_FMT_OUT_FMT_LSB) |
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| 85 | #define JZ_IPU_D_FMT_OUT_FMT_RGBAAA (0x4 << JZ_IPU_D_FMT_OUT_FMT_LSB) |
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| 86 | |
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| 87 | #define JZ_IPU_D_FMT_RGB_OUT_OFT_LSB 22 |
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| 88 | #define JZ_IPU_D_FMT_RGB_OUT_OFT_RGB (0x0 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB) |
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| 89 | #define JZ_IPU_D_FMT_RGB_OUT_OFT_RBG (0x1 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB) |
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| 90 | #define JZ_IPU_D_FMT_RGB_OUT_OFT_GBR (0x2 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB) |
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| 91 | #define JZ_IPU_D_FMT_RGB_OUT_OFT_GRB (0x3 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB) |
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| 92 | #define JZ_IPU_D_FMT_RGB_OUT_OFT_BRG (0x4 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB) |
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| 93 | #define JZ_IPU_D_FMT_RGB_OUT_OFT_BGR (0x5 << JZ_IPU_D_FMT_RGB_OUT_OFT_LSB) |
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| 94 | |
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| 95 | #define JZ4725B_IPU_RSZ_LUT_COEF_LSB 2 |
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| 96 | #define JZ4725B_IPU_RSZ_LUT_COEF_MASK 0x7ff |
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| 97 | #define JZ4725B_IPU_RSZ_LUT_IN_EN BIT(1) |
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| 98 | #define JZ4725B_IPU_RSZ_LUT_OUT_EN BIT(0) |
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| 99 | |
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| 100 | #define JZ4760_IPU_RSZ_COEF20_LSB 6 |
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| 101 | #define JZ4760_IPU_RSZ_COEF31_LSB 17 |
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| 102 | #define JZ4760_IPU_RSZ_COEF_MASK 0x7ff |
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| 103 | #define JZ4760_IPU_RSZ_OFFSET_LSB 1 |
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| 104 | #define JZ4760_IPU_RSZ_OFFSET_MASK 0x1f |
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| 105 | |
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| 106 | #define JZ_IPU_CSC_OFFSET_CHROMA_LSB 16 |
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| 107 | #define JZ_IPU_CSC_OFFSET_LUMA_LSB 16 |
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| 108 | |
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| 109 | #endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_IPU_H */ |
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| 110 | |
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