| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* Copyright 2010-2017 ARM Limited. All rights reserved. |
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| 3 | * Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> |
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| 4 | */ |
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| 5 | |
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| 6 | #ifndef __LIMA_REGS_H__ |
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| 7 | #define __LIMA_REGS_H__ |
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| 8 | |
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| 9 | /* This file's register definition is collected from the |
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| 10 | * official ARM Mali Utgard GPU kernel driver source code |
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| 11 | */ |
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| 12 | |
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| 13 | /* PMU regs */ |
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| 14 | #define LIMA_PMU_POWER_UP 0x00 |
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| 15 | #define LIMA_PMU_POWER_DOWN 0x04 |
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| 16 | #define LIMA_PMU_POWER_GP0_MASK BIT(0) |
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| 17 | #define LIMA_PMU_POWER_L2_MASK BIT(1) |
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| 18 | #define LIMA_PMU_POWER_PP_MASK(i) BIT(2 + i) |
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| 19 | |
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| 20 | /* |
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| 21 | * On Mali450 each block automatically starts up its corresponding L2 |
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| 22 | * and the PPs are not fully independent controllable. |
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| 23 | * Instead PP0, PP1-3 and PP4-7 can be turned on or off. |
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| 24 | */ |
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| 25 | #define LIMA450_PMU_POWER_PP0_MASK BIT(1) |
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| 26 | #define LIMA450_PMU_POWER_PP13_MASK BIT(2) |
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| 27 | #define LIMA450_PMU_POWER_PP47_MASK BIT(3) |
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| 28 | |
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| 29 | #define LIMA_PMU_STATUS 0x08 |
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| 30 | #define LIMA_PMU_INT_MASK 0x0C |
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| 31 | #define LIMA_PMU_INT_RAWSTAT 0x10 |
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| 32 | #define LIMA_PMU_INT_CLEAR 0x18 |
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| 33 | #define LIMA_PMU_INT_CMD_MASK BIT(0) |
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| 34 | #define LIMA_PMU_SW_DELAY 0x1C |
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| 35 | |
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| 36 | /* L2 cache regs */ |
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| 37 | #define LIMA_L2_CACHE_SIZE 0x0004 |
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| 38 | #define LIMA_L2_CACHE_STATUS 0x0008 |
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| 39 | #define LIMA_L2_CACHE_STATUS_COMMAND_BUSY BIT(0) |
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| 40 | #define LIMA_L2_CACHE_STATUS_DATA_BUSY BIT(1) |
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| 41 | #define LIMA_L2_CACHE_COMMAND 0x0010 |
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| 42 | #define LIMA_L2_CACHE_COMMAND_CLEAR_ALL BIT(0) |
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| 43 | #define LIMA_L2_CACHE_CLEAR_PAGE 0x0014 |
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| 44 | #define LIMA_L2_CACHE_MAX_READS 0x0018 |
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| 45 | #define LIMA_L2_CACHE_ENABLE 0x001C |
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| 46 | #define LIMA_L2_CACHE_ENABLE_ACCESS BIT(0) |
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| 47 | #define LIMA_L2_CACHE_ENABLE_READ_ALLOCATE BIT(1) |
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| 48 | #define LIMA_L2_CACHE_PERFCNT_SRC0 0x0020 |
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| 49 | #define LIMA_L2_CACHE_PERFCNT_VAL0 0x0024 |
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| 50 | #define LIMA_L2_CACHE_PERFCNT_SRC1 0x0028 |
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| 51 | #define LIMA_L2_CACHE_ERFCNT_VAL1 0x002C |
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| 52 | |
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| 53 | /* GP regs */ |
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| 54 | #define LIMA_GP_VSCL_START_ADDR 0x00 |
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| 55 | #define LIMA_GP_VSCL_END_ADDR 0x04 |
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| 56 | #define LIMA_GP_PLBUCL_START_ADDR 0x08 |
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| 57 | #define LIMA_GP_PLBUCL_END_ADDR 0x0c |
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| 58 | #define LIMA_GP_PLBU_ALLOC_START_ADDR 0x10 |
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| 59 | #define LIMA_GP_PLBU_ALLOC_END_ADDR 0x14 |
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| 60 | #define LIMA_GP_CMD 0x20 |
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| 61 | #define LIMA_GP_CMD_START_VS BIT(0) |
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| 62 | #define LIMA_GP_CMD_START_PLBU BIT(1) |
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| 63 | #define LIMA_GP_CMD_UPDATE_PLBU_ALLOC BIT(4) |
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| 64 | #define LIMA_GP_CMD_RESET BIT(5) |
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| 65 | #define LIMA_GP_CMD_FORCE_HANG BIT(6) |
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| 66 | #define LIMA_GP_CMD_STOP_BUS BIT(9) |
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| 67 | #define LIMA_GP_CMD_SOFT_RESET BIT(10) |
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| 68 | #define LIMA_GP_INT_RAWSTAT 0x24 |
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| 69 | #define LIMA_GP_INT_CLEAR 0x28 |
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| 70 | #define LIMA_GP_INT_MASK 0x2C |
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| 71 | #define LIMA_GP_INT_STAT 0x30 |
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| 72 | #define LIMA_GP_IRQ_VS_END_CMD_LST BIT(0) |
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| 73 | #define LIMA_GP_IRQ_PLBU_END_CMD_LST BIT(1) |
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| 74 | #define LIMA_GP_IRQ_PLBU_OUT_OF_MEM BIT(2) |
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| 75 | #define LIMA_GP_IRQ_VS_SEM_IRQ BIT(3) |
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| 76 | #define LIMA_GP_IRQ_PLBU_SEM_IRQ BIT(4) |
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| 77 | #define LIMA_GP_IRQ_HANG BIT(5) |
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| 78 | #define LIMA_GP_IRQ_FORCE_HANG BIT(6) |
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| 79 | #define LIMA_GP_IRQ_PERF_CNT_0_LIMIT BIT(7) |
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| 80 | #define LIMA_GP_IRQ_PERF_CNT_1_LIMIT BIT(8) |
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| 81 | #define LIMA_GP_IRQ_WRITE_BOUND_ERR BIT(9) |
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| 82 | #define LIMA_GP_IRQ_SYNC_ERROR BIT(10) |
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| 83 | #define LIMA_GP_IRQ_AXI_BUS_ERROR BIT(11) |
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| 84 | #define LIMA_GP_IRQ_AXI_BUS_STOPPED BIT(12) |
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| 85 | #define LIMA_GP_IRQ_VS_INVALID_CMD BIT(13) |
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| 86 | #define LIMA_GP_IRQ_PLB_INVALID_CMD BIT(14) |
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| 87 | #define LIMA_GP_IRQ_RESET_COMPLETED BIT(19) |
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| 88 | #define LIMA_GP_IRQ_SEMAPHORE_UNDERFLOW BIT(20) |
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| 89 | #define LIMA_GP_IRQ_SEMAPHORE_OVERFLOW BIT(21) |
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| 90 | #define LIMA_GP_IRQ_PTR_ARRAY_OUT_OF_BOUNDS BIT(22) |
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| 91 | #define LIMA_GP_WRITE_BOUND_LOW 0x34 |
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| 92 | #define LIMA_GP_PERF_CNT_0_ENABLE 0x3C |
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| 93 | #define LIMA_GP_PERF_CNT_1_ENABLE 0x40 |
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| 94 | #define LIMA_GP_PERF_CNT_0_SRC 0x44 |
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| 95 | #define LIMA_GP_PERF_CNT_1_SRC 0x48 |
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| 96 | #define LIMA_GP_PERF_CNT_0_VALUE 0x4C |
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| 97 | #define LIMA_GP_PERF_CNT_1_VALUE 0x50 |
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| 98 | #define LIMA_GP_PERF_CNT_0_LIMIT 0x54 |
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| 99 | #define LIMA_GP_STATUS 0x68 |
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| 100 | #define LIMA_GP_STATUS_VS_ACTIVE BIT(1) |
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| 101 | #define LIMA_GP_STATUS_BUS_STOPPED BIT(2) |
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| 102 | #define LIMA_GP_STATUS_PLBU_ACTIVE BIT(3) |
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| 103 | #define LIMA_GP_STATUS_BUS_ERROR BIT(6) |
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| 104 | #define LIMA_GP_STATUS_WRITE_BOUND_ERR BIT(8) |
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| 105 | #define LIMA_GP_VERSION 0x6C |
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| 106 | #define LIMA_GP_VSCL_START_ADDR_READ 0x80 |
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| 107 | #define LIMA_GP_PLBCL_START_ADDR_READ 0x84 |
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| 108 | #define LIMA_GP_CONTR_AXI_BUS_ERROR_STAT 0x94 |
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| 109 | |
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| 110 | #define LIMA_GP_IRQ_MASK_ALL \ |
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| 111 | ( \ |
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| 112 | LIMA_GP_IRQ_VS_END_CMD_LST | \ |
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| 113 | LIMA_GP_IRQ_PLBU_END_CMD_LST | \ |
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| 114 | LIMA_GP_IRQ_PLBU_OUT_OF_MEM | \ |
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| 115 | LIMA_GP_IRQ_VS_SEM_IRQ | \ |
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| 116 | LIMA_GP_IRQ_PLBU_SEM_IRQ | \ |
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| 117 | LIMA_GP_IRQ_HANG | \ |
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| 118 | LIMA_GP_IRQ_FORCE_HANG | \ |
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| 119 | LIMA_GP_IRQ_PERF_CNT_0_LIMIT | \ |
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| 120 | LIMA_GP_IRQ_PERF_CNT_1_LIMIT | \ |
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| 121 | LIMA_GP_IRQ_WRITE_BOUND_ERR | \ |
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| 122 | LIMA_GP_IRQ_SYNC_ERROR | \ |
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| 123 | LIMA_GP_IRQ_AXI_BUS_ERROR | \ |
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| 124 | LIMA_GP_IRQ_AXI_BUS_STOPPED | \ |
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| 125 | LIMA_GP_IRQ_VS_INVALID_CMD | \ |
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| 126 | LIMA_GP_IRQ_PLB_INVALID_CMD | \ |
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| 127 | LIMA_GP_IRQ_RESET_COMPLETED | \ |
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| 128 | LIMA_GP_IRQ_SEMAPHORE_UNDERFLOW | \ |
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| 129 | LIMA_GP_IRQ_SEMAPHORE_OVERFLOW | \ |
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| 130 | LIMA_GP_IRQ_PTR_ARRAY_OUT_OF_BOUNDS) |
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| 131 | |
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| 132 | #define LIMA_GP_IRQ_MASK_ERROR \ |
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| 133 | ( \ |
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| 134 | LIMA_GP_IRQ_PLBU_OUT_OF_MEM | \ |
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| 135 | LIMA_GP_IRQ_FORCE_HANG | \ |
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| 136 | LIMA_GP_IRQ_WRITE_BOUND_ERR | \ |
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| 137 | LIMA_GP_IRQ_SYNC_ERROR | \ |
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| 138 | LIMA_GP_IRQ_AXI_BUS_ERROR | \ |
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| 139 | LIMA_GP_IRQ_VS_INVALID_CMD | \ |
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| 140 | LIMA_GP_IRQ_PLB_INVALID_CMD | \ |
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| 141 | LIMA_GP_IRQ_SEMAPHORE_UNDERFLOW | \ |
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| 142 | LIMA_GP_IRQ_SEMAPHORE_OVERFLOW | \ |
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| 143 | LIMA_GP_IRQ_PTR_ARRAY_OUT_OF_BOUNDS) |
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| 144 | |
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| 145 | #define LIMA_GP_IRQ_MASK_USED \ |
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| 146 | ( \ |
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| 147 | LIMA_GP_IRQ_VS_END_CMD_LST | \ |
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| 148 | LIMA_GP_IRQ_PLBU_END_CMD_LST | \ |
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| 149 | LIMA_GP_IRQ_MASK_ERROR) |
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| 150 | |
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| 151 | /* PP regs */ |
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| 152 | #define LIMA_PP_FRAME 0x0000 |
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| 153 | #define LIMA_PP_RSW 0x0004 |
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| 154 | #define LIMA_PP_STACK 0x0030 |
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| 155 | #define LIMA_PP_STACK_SIZE 0x0034 |
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| 156 | #define LIMA_PP_ORIGIN_OFFSET_X 0x0040 |
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| 157 | #define LIMA_PP_WB(i) (0x0100 * (i + 1)) |
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| 158 | #define LIMA_PP_WB_SOURCE_SELECT 0x0000 |
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| 159 | #define LIMA_PP_WB_SOURCE_ADDR 0x0004 |
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| 160 | |
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| 161 | #define LIMA_PP_VERSION 0x1000 |
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| 162 | #define LIMA_PP_CURRENT_REND_LIST_ADDR 0x1004 |
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| 163 | #define LIMA_PP_STATUS 0x1008 |
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| 164 | #define LIMA_PP_STATUS_RENDERING_ACTIVE BIT(0) |
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| 165 | #define LIMA_PP_STATUS_BUS_STOPPED BIT(4) |
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| 166 | #define LIMA_PP_CTRL 0x100c |
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| 167 | #define LIMA_PP_CTRL_STOP_BUS BIT(0) |
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| 168 | #define LIMA_PP_CTRL_FLUSH_CACHES BIT(3) |
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| 169 | #define LIMA_PP_CTRL_FORCE_RESET BIT(5) |
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| 170 | #define LIMA_PP_CTRL_START_RENDERING BIT(6) |
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| 171 | #define LIMA_PP_CTRL_SOFT_RESET BIT(7) |
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| 172 | #define LIMA_PP_INT_RAWSTAT 0x1020 |
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| 173 | #define LIMA_PP_INT_CLEAR 0x1024 |
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| 174 | #define LIMA_PP_INT_MASK 0x1028 |
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| 175 | #define LIMA_PP_INT_STATUS 0x102c |
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| 176 | #define LIMA_PP_IRQ_END_OF_FRAME BIT(0) |
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| 177 | #define LIMA_PP_IRQ_END_OF_TILE BIT(1) |
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| 178 | #define LIMA_PP_IRQ_HANG BIT(2) |
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| 179 | #define LIMA_PP_IRQ_FORCE_HANG BIT(3) |
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| 180 | #define LIMA_PP_IRQ_BUS_ERROR BIT(4) |
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| 181 | #define LIMA_PP_IRQ_BUS_STOP BIT(5) |
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| 182 | #define LIMA_PP_IRQ_CNT_0_LIMIT BIT(6) |
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| 183 | #define LIMA_PP_IRQ_CNT_1_LIMIT BIT(7) |
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| 184 | #define LIMA_PP_IRQ_WRITE_BOUNDARY_ERROR BIT(8) |
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| 185 | #define LIMA_PP_IRQ_INVALID_PLIST_COMMAND BIT(9) |
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| 186 | #define LIMA_PP_IRQ_CALL_STACK_UNDERFLOW BIT(10) |
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| 187 | #define LIMA_PP_IRQ_CALL_STACK_OVERFLOW BIT(11) |
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| 188 | #define LIMA_PP_IRQ_RESET_COMPLETED BIT(12) |
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| 189 | #define LIMA_PP_WRITE_BOUNDARY_LOW 0x1044 |
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| 190 | #define LIMA_PP_BUS_ERROR_STATUS 0x1050 |
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| 191 | #define LIMA_PP_PERF_CNT_0_ENABLE 0x1080 |
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| 192 | #define LIMA_PP_PERF_CNT_0_SRC 0x1084 |
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| 193 | #define LIMA_PP_PERF_CNT_0_LIMIT 0x1088 |
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| 194 | #define LIMA_PP_PERF_CNT_0_VALUE 0x108c |
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| 195 | #define LIMA_PP_PERF_CNT_1_ENABLE 0x10a0 |
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| 196 | #define LIMA_PP_PERF_CNT_1_SRC 0x10a4 |
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| 197 | #define LIMA_PP_PERF_CNT_1_LIMIT 0x10a8 |
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| 198 | #define LIMA_PP_PERF_CNT_1_VALUE 0x10ac |
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| 199 | #define LIMA_PP_PERFMON_CONTR 0x10b0 |
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| 200 | #define LIMA_PP_PERFMON_BASE 0x10b4 |
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| 201 | |
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| 202 | #define LIMA_PP_IRQ_MASK_ALL \ |
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| 203 | ( \ |
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| 204 | LIMA_PP_IRQ_END_OF_FRAME | \ |
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| 205 | LIMA_PP_IRQ_END_OF_TILE | \ |
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| 206 | LIMA_PP_IRQ_HANG | \ |
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| 207 | LIMA_PP_IRQ_FORCE_HANG | \ |
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| 208 | LIMA_PP_IRQ_BUS_ERROR | \ |
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| 209 | LIMA_PP_IRQ_BUS_STOP | \ |
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| 210 | LIMA_PP_IRQ_CNT_0_LIMIT | \ |
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| 211 | LIMA_PP_IRQ_CNT_1_LIMIT | \ |
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| 212 | LIMA_PP_IRQ_WRITE_BOUNDARY_ERROR | \ |
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| 213 | LIMA_PP_IRQ_INVALID_PLIST_COMMAND | \ |
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| 214 | LIMA_PP_IRQ_CALL_STACK_UNDERFLOW | \ |
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| 215 | LIMA_PP_IRQ_CALL_STACK_OVERFLOW | \ |
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| 216 | LIMA_PP_IRQ_RESET_COMPLETED) |
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| 217 | |
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| 218 | #define LIMA_PP_IRQ_MASK_ERROR \ |
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| 219 | ( \ |
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| 220 | LIMA_PP_IRQ_FORCE_HANG | \ |
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| 221 | LIMA_PP_IRQ_BUS_ERROR | \ |
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| 222 | LIMA_PP_IRQ_WRITE_BOUNDARY_ERROR | \ |
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| 223 | LIMA_PP_IRQ_INVALID_PLIST_COMMAND | \ |
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| 224 | LIMA_PP_IRQ_CALL_STACK_UNDERFLOW | \ |
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| 225 | LIMA_PP_IRQ_CALL_STACK_OVERFLOW) |
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| 226 | |
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| 227 | #define LIMA_PP_IRQ_MASK_USED \ |
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| 228 | ( \ |
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| 229 | LIMA_PP_IRQ_END_OF_FRAME | \ |
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| 230 | LIMA_PP_IRQ_MASK_ERROR) |
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| 231 | |
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| 232 | /* MMU regs */ |
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| 233 | #define LIMA_MMU_DTE_ADDR 0x0000 |
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| 234 | #define LIMA_MMU_STATUS 0x0004 |
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| 235 | #define LIMA_MMU_STATUS_PAGING_ENABLED BIT(0) |
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| 236 | #define LIMA_MMU_STATUS_PAGE_FAULT_ACTIVE BIT(1) |
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| 237 | #define LIMA_MMU_STATUS_STALL_ACTIVE BIT(2) |
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| 238 | #define LIMA_MMU_STATUS_IDLE BIT(3) |
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| 239 | #define LIMA_MMU_STATUS_REPLAY_BUFFER_EMPTY BIT(4) |
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| 240 | #define LIMA_MMU_STATUS_PAGE_FAULT_IS_WRITE BIT(5) |
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| 241 | #define LIMA_MMU_STATUS_BUS_ID(x) ((x >> 6) & 0x1F) |
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| 242 | #define LIMA_MMU_STATUS_STALL_NOT_ACTIVE BIT(31) |
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| 243 | #define LIMA_MMU_COMMAND 0x0008 |
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| 244 | #define LIMA_MMU_COMMAND_ENABLE_PAGING 0x00 |
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| 245 | #define LIMA_MMU_COMMAND_DISABLE_PAGING 0x01 |
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| 246 | #define LIMA_MMU_COMMAND_ENABLE_STALL 0x02 |
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| 247 | #define LIMA_MMU_COMMAND_DISABLE_STALL 0x03 |
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| 248 | #define LIMA_MMU_COMMAND_ZAP_CACHE 0x04 |
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| 249 | #define LIMA_MMU_COMMAND_PAGE_FAULT_DONE 0x05 |
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| 250 | #define LIMA_MMU_COMMAND_HARD_RESET 0x06 |
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| 251 | #define LIMA_MMU_PAGE_FAULT_ADDR 0x000C |
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| 252 | #define LIMA_MMU_ZAP_ONE_LINE 0x0010 |
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| 253 | #define LIMA_MMU_INT_RAWSTAT 0x0014 |
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| 254 | #define LIMA_MMU_INT_CLEAR 0x0018 |
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| 255 | #define LIMA_MMU_INT_MASK 0x001C |
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| 256 | #define LIMA_MMU_INT_PAGE_FAULT BIT(0) |
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| 257 | #define LIMA_MMU_INT_READ_BUS_ERROR BIT(1) |
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| 258 | #define LIMA_MMU_INT_STATUS 0x0020 |
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| 259 | |
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| 260 | #define LIMA_VM_FLAG_PRESENT BIT(0) |
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| 261 | #define LIMA_VM_FLAG_READ_PERMISSION BIT(1) |
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| 262 | #define LIMA_VM_FLAG_WRITE_PERMISSION BIT(2) |
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| 263 | #define LIMA_VM_FLAG_OVERRIDE_CACHE BIT(3) |
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| 264 | #define LIMA_VM_FLAG_WRITE_CACHEABLE BIT(4) |
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| 265 | #define LIMA_VM_FLAG_WRITE_ALLOCATE BIT(5) |
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| 266 | #define LIMA_VM_FLAG_WRITE_BUFFERABLE BIT(6) |
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| 267 | #define LIMA_VM_FLAG_READ_CACHEABLE BIT(7) |
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| 268 | #define LIMA_VM_FLAG_READ_ALLOCATE BIT(8) |
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| 269 | #define LIMA_VM_FLAG_MASK 0x1FF |
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| 270 | |
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| 271 | #define LIMA_VM_FLAGS_CACHE ( \ |
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| 272 | LIMA_VM_FLAG_PRESENT | \ |
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| 273 | LIMA_VM_FLAG_READ_PERMISSION | \ |
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| 274 | LIMA_VM_FLAG_WRITE_PERMISSION | \ |
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| 275 | LIMA_VM_FLAG_OVERRIDE_CACHE | \ |
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| 276 | LIMA_VM_FLAG_WRITE_CACHEABLE | \ |
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| 277 | LIMA_VM_FLAG_WRITE_BUFFERABLE | \ |
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| 278 | LIMA_VM_FLAG_READ_CACHEABLE | \ |
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| 279 | LIMA_VM_FLAG_READ_ALLOCATE) |
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| 280 | |
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| 281 | #define LIMA_VM_FLAGS_UNCACHE ( \ |
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| 282 | LIMA_VM_FLAG_PRESENT | \ |
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| 283 | LIMA_VM_FLAG_READ_PERMISSION | \ |
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| 284 | LIMA_VM_FLAG_WRITE_PERMISSION) |
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| 285 | |
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| 286 | /* DLBU regs */ |
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| 287 | #define LIMA_DLBU_MASTER_TLLIST_PHYS_ADDR 0x0000 |
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| 288 | #define LIMA_DLBU_MASTER_TLLIST_VADDR 0x0004 |
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| 289 | #define LIMA_DLBU_TLLIST_VBASEADDR 0x0008 |
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| 290 | #define LIMA_DLBU_FB_DIM 0x000C |
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| 291 | #define LIMA_DLBU_TLLIST_CONF 0x0010 |
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| 292 | #define LIMA_DLBU_START_TILE_POS 0x0014 |
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| 293 | #define LIMA_DLBU_PP_ENABLE_MASK 0x0018 |
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| 294 | |
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| 295 | /* BCAST regs */ |
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| 296 | #define LIMA_BCAST_BROADCAST_MASK 0x0 |
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| 297 | #define LIMA_BCAST_INTERRUPT_MASK 0x4 |
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| 298 | |
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| 299 | #endif |
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| 300 | |
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