| 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2019-2022 Bootlin |
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| 4 | * Author: Paul Kocialkowski <paul.kocialkowski@bootlin.com> |
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| 5 | * |
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| 6 | * Copyright (C) 2014 Xylon d.o.o. |
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| 7 | * Author: Davor Joja <davor.joja@logicbricks.com> |
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| 8 | */ |
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| 9 | |
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| 10 | #ifndef _LOGICVC_REGS_H_ |
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| 11 | #define _LOGICVC_REGS_H_ |
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| 12 | |
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| 13 | #define LOGICVC_DIMENSIONS_MAX (BIT(16) - 1) |
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| 14 | |
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| 15 | #define LOGICVC_HSYNC_FRONT_PORCH_REG 0x00 |
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| 16 | #define LOGICVC_HSYNC_REG 0x08 |
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| 17 | #define LOGICVC_HSYNC_BACK_PORCH_REG 0x10 |
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| 18 | #define LOGICVC_HRES_REG 0x18 |
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| 19 | #define LOGICVC_VSYNC_FRONT_PORCH_REG 0x20 |
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| 20 | #define LOGICVC_VSYNC_REG 0x28 |
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| 21 | #define LOGICVC_VSYNC_BACK_PORCH_REG 0x30 |
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| 22 | #define LOGICVC_VRES_REG 0x38 |
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| 23 | |
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| 24 | #define LOGICVC_CTRL_REG 0x40 |
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| 25 | #define LOGICVC_CTRL_CLOCK_INVERT BIT(8) |
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| 26 | #define LOGICVC_CTRL_PIXEL_INVERT BIT(7) |
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| 27 | #define LOGICVC_CTRL_DE_INVERT BIT(5) |
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| 28 | #define LOGICVC_CTRL_DE_ENABLE BIT(4) |
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| 29 | #define LOGICVC_CTRL_VSYNC_INVERT BIT(3) |
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| 30 | #define LOGICVC_CTRL_VSYNC_ENABLE BIT(2) |
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| 31 | #define LOGICVC_CTRL_HSYNC_INVERT BIT(1) |
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| 32 | #define LOGICVC_CTRL_HSYNC_ENABLE BIT(0) |
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| 33 | |
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| 34 | #define LOGICVC_DTYPE_REG 0x48 |
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| 35 | #define LOGICVC_BACKGROUND_COLOR_REG 0x50 |
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| 36 | |
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| 37 | #define LOGICVC_BUFFER_SEL_REG 0x58 |
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| 38 | #define LOGICVC_BUFFER_SEL_VALUE(i, v) \ |
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| 39 | (BIT(10 + (i)) | ((v) << (2 * (i)))) |
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| 40 | #define LOGICVC_BUFFER_SEL_MAX 2 |
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| 41 | |
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| 42 | #define LOGICVC_DOUBLE_CLUT_REG 0x60 |
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| 43 | |
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| 44 | #define LOGICVC_INT_STAT_REG 0x68 |
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| 45 | #define LOGICVC_INT_STAT_V_SYNC BIT(5) |
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| 46 | |
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| 47 | #define LOGICVC_INT_MASK_REG 0x70 |
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| 48 | #define LOGICVC_INT_MASK_V_SYNC BIT(5) |
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| 49 | |
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| 50 | #define LOGICVC_POWER_CTRL_REG 0x78 |
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| 51 | #define LOGICVC_POWER_CTRL_BACKLIGHT_ENABLE BIT(0) |
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| 52 | #define LOGICVC_POWER_CTRL_VDD_ENABLE BIT(1) |
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| 53 | #define LOGICVC_POWER_CTRL_VEE_ENABLE BIT(2) |
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| 54 | #define LOGICVC_POWER_CTRL_VIDEO_ENABLE BIT(3) |
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| 55 | |
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| 56 | #define LOGICVC_IP_VERSION_REG 0xf8 |
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| 57 | #define LOGICVC_IP_VERSION_MAJOR_MASK GENMASK(16, 11) |
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| 58 | #define LOGICVC_IP_VERSION_MINOR_MASK GENMASK(10, 5) |
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| 59 | #define LOGICVC_IP_VERSION_LEVEL_MASK GENMASK(4, 0) |
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| 60 | |
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| 61 | #define LOGICVC_LAYER_ADDRESS_REG(i) (0x100 + (i) * 0x80) |
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| 62 | #define LOGICVC_LAYER_HOFFSET_REG(i) (0x100 + (i) * 0x80) |
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| 63 | |
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| 64 | #define LOGICVC_LAYER_VOFFSET_REG(i) (0x108 + (i) * 0x80) |
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| 65 | #define LOGICVC_LAYER_VOFFSET_MAX 4095 |
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| 66 | |
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| 67 | #define LOGICVC_LAYER_HPOSITION_REG(i) (0x110 + (i) * 0x80) |
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| 68 | #define LOGICVC_LAYER_VPOSITION_REG(i) (0x118 + (i) * 0x80) |
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| 69 | #define LOGICVC_LAYER_WIDTH_REG(i) (0x120 + (i) * 0x80) |
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| 70 | #define LOGICVC_LAYER_HEIGHT_REG(i) (0x128 + (i) * 0x80) |
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| 71 | #define LOGICVC_LAYER_ALPHA_REG(i) (0x130 + (i) * 0x80) |
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| 72 | |
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| 73 | #define LOGICVC_LAYER_CTRL_REG(i) (0x138 + (i) * 0x80) |
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| 74 | #define LOGICVC_LAYER_CTRL_ENABLE BIT(0) |
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| 75 | #define LOGICVC_LAYER_CTRL_COLOR_KEY_DISABLE BIT(1) |
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| 76 | #define LOGICVC_LAYER_CTRL_PIXEL_FORMAT_INVERT BIT(4) |
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| 77 | |
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| 78 | #define LOGICVC_LAYER_COLOR_KEY_REG(i) (0x140 + (i) * 0x80) |
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| 79 | |
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| 80 | #endif |
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| 81 | |
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