1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | #ifndef __DRM_MCDE_DSI_REGS |
3 | #define __DRM_MCDE_DSI_REGS |
4 | |
5 | #define DSI_MCTL_INTEGRATION_MODE 0x00000000 |
6 | |
7 | #define DSI_MCTL_MAIN_DATA_CTL 0x00000004 |
8 | #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0) |
9 | #define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE BIT(1) |
10 | #define DSI_MCTL_MAIN_DATA_CTL_VID_EN BIT(2) |
11 | #define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL BIT(3) |
12 | #define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL BIT(4) |
13 | #define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN BIT(5) |
14 | #define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN BIT(6) |
15 | #define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN BIT(7) |
16 | #define DSI_MCTL_MAIN_DATA_CTL_READ_EN BIT(8) |
17 | #define DSI_MCTL_MAIN_DATA_CTL_BTA_EN BIT(9) |
18 | #define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_ECC BIT(10) |
19 | #define DSI_MCTL_MAIN_DATA_CTL_DISP_GEN_CHECKSUM BIT(11) |
20 | #define DSI_MCTL_MAIN_DATA_CTL_HOST_EOT_GEN BIT(12) |
21 | #define DSI_MCTL_MAIN_DATA_CTL_DISP_EOT_GEN BIT(13) |
22 | #define DSI_MCTL_MAIN_DATA_CTL_DLX_REMAP_EN BIT(14) |
23 | #define DSI_MCTL_MAIN_DATA_CTL_TE_POLLING_EN BIT(15) |
24 | |
25 | #define DSI_MCTL_MAIN_PHY_CTL 0x00000008 |
26 | #define DSI_MCTL_MAIN_PHY_CTL_LANE2_EN BIT(0) |
27 | #define DSI_MCTL_MAIN_PHY_CTL_FORCE_STOP_MODE BIT(1) |
28 | #define DSI_MCTL_MAIN_PHY_CTL_CLK_CONTINUOUS BIT(2) |
29 | #define DSI_MCTL_MAIN_PHY_CTL_CLK_ULPM_EN BIT(3) |
30 | #define DSI_MCTL_MAIN_PHY_CTL_DAT1_ULPM_EN BIT(4) |
31 | #define DSI_MCTL_MAIN_PHY_CTL_DAT2_ULPM_EN BIT(5) |
32 | #define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_SHIFT 6 |
33 | #define DSI_MCTL_MAIN_PHY_CTL_WAIT_BURST_TIME_MASK 0x000003C0 |
34 | #define DSI_MCTL_MAIN_PHY_CTL_CLOCK_FORCE_STOP_MODE BIT(10) |
35 | |
36 | #define DSI_MCTL_PLL_CTL 0x0000000C |
37 | #define DSI_MCTL_LANE_STS 0x00000010 |
38 | |
39 | #define DSI_MCTL_DPHY_TIMEOUT 0x00000014 |
40 | #define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_SHIFT 0 |
41 | #define DSI_MCTL_DPHY_TIMEOUT_CLK_DIV_MASK 0x0000000F |
42 | #define DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_SHIFT 4 |
43 | #define DSI_MCTL_DPHY_TIMEOUT_HSTX_TO_VAL_MASK 0x0003FFF0 |
44 | #define DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_SHIFT 18 |
45 | #define DSI_MCTL_DPHY_TIMEOUT_LPRX_TO_VAL_MASK 0xFFFC0000 |
46 | |
47 | #define DSI_MCTL_ULPOUT_TIME 0x00000018 |
48 | #define DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_SHIFT 0 |
49 | #define DSI_MCTL_ULPOUT_TIME_CKLANE_ULPOUT_TIME_MASK 0x000001FF |
50 | #define DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_SHIFT 9 |
51 | #define DSI_MCTL_ULPOUT_TIME_DATA_ULPOUT_TIME_MASK 0x0003FE00 |
52 | |
53 | #define DSI_MCTL_DPHY_STATIC 0x0000001C |
54 | #define DSI_MCTL_DPHY_STATIC_SWAP_PINS_CLK BIT(0) |
55 | #define DSI_MCTL_DPHY_STATIC_HS_INVERT_CLK BIT(1) |
56 | #define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT1 BIT(2) |
57 | #define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT1 BIT(3) |
58 | #define DSI_MCTL_DPHY_STATIC_SWAP_PINS_DAT2 BIT(4) |
59 | #define DSI_MCTL_DPHY_STATIC_HS_INVERT_DAT2 BIT(5) |
60 | #define DSI_MCTL_DPHY_STATIC_UI_X4_SHIFT 6 |
61 | #define DSI_MCTL_DPHY_STATIC_UI_X4_MASK 0x00000FC0 |
62 | |
63 | #define DSI_MCTL_MAIN_EN 0x00000020 |
64 | #define DSI_MCTL_MAIN_EN_PLL_START BIT(0) |
65 | #define DSI_MCTL_MAIN_EN_CKLANE_EN BIT(3) |
66 | #define DSI_MCTL_MAIN_EN_DAT1_EN BIT(4) |
67 | #define DSI_MCTL_MAIN_EN_DAT2_EN BIT(5) |
68 | #define DSI_MCTL_MAIN_EN_CLKLANE_ULPM_REQ BIT(6) |
69 | #define DSI_MCTL_MAIN_EN_DAT1_ULPM_REQ BIT(7) |
70 | #define DSI_MCTL_MAIN_EN_DAT2_ULPM_REQ BIT(8) |
71 | #define DSI_MCTL_MAIN_EN_IF1_EN BIT(9) |
72 | #define DSI_MCTL_MAIN_EN_IF2_EN BIT(10) |
73 | |
74 | #define DSI_MCTL_MAIN_STS 0x00000024 |
75 | #define DSI_MCTL_MAIN_STS_PLL_LOCK BIT(0) |
76 | #define DSI_MCTL_MAIN_STS_CLKLANE_READY BIT(1) |
77 | #define DSI_MCTL_MAIN_STS_DAT1_READY BIT(2) |
78 | #define DSI_MCTL_MAIN_STS_DAT2_READY BIT(3) |
79 | #define DSI_MCTL_MAIN_STS_HSTX_TO_ERR BIT(4) |
80 | #define DSI_MCTL_MAIN_STS_LPRX_TO_ERR BIT(5) |
81 | #define DSI_MCTL_MAIN_STS_CRS_UNTERM_PCK BIT(6) |
82 | #define DSI_MCTL_MAIN_STS_VRS_UNTERM_PCK BIT(7) |
83 | |
84 | #define DSI_MCTL_DPHY_ERR 0x00000028 |
85 | #define DSI_INT_VID_RDDATA 0x00000030 |
86 | #define DSI_INT_VID_GNT 0x00000034 |
87 | #define DSI_INT_CMD_RDDATA 0x00000038 |
88 | #define DSI_INT_CMD_GNT 0x0000003C |
89 | #define DSI_INT_INTERRUPT_CTL 0x00000040 |
90 | |
91 | #define DSI_CMD_MODE_CTL 0x00000050 |
92 | #define DSI_CMD_MODE_CTL_IF1_ID_SHIFT 0 |
93 | #define DSI_CMD_MODE_CTL_IF1_ID_MASK 0x00000003 |
94 | #define DSI_CMD_MODE_CTL_IF2_ID_SHIFT 2 |
95 | #define DSI_CMD_MODE_CTL_IF2_ID_MASK 0x0000000C |
96 | #define DSI_CMD_MODE_CTL_IF1_LP_EN BIT(4) |
97 | #define DSI_CMD_MODE_CTL_IF2_LP_EN BIT(5) |
98 | #define DSI_CMD_MODE_CTL_ARB_MODE BIT(6) |
99 | #define DSI_CMD_MODE_CTL_ARB_PRI BIT(7) |
100 | #define DSI_CMD_MODE_CTL_FIL_VALUE_SHIFT 8 |
101 | #define DSI_CMD_MODE_CTL_FIL_VALUE_MASK 0x0000FF00 |
102 | #define DSI_CMD_MODE_CTL_TE_TIMEOUT_SHIFT 16 |
103 | #define DSI_CMD_MODE_CTL_TE_TIMEOUT_MASK 0x03FF0000 |
104 | |
105 | #define DSI_CMD_MODE_STS 0x00000054 |
106 | #define DSI_CMD_MODE_STS_ERR_NO_TE BIT(0) |
107 | #define DSI_CMD_MODE_STS_ERR_TE_MISS BIT(1) |
108 | #define DSI_CMD_MODE_STS_ERR_SDI1_UNDERRUN BIT(2) |
109 | #define DSI_CMD_MODE_STS_ERR_SDI2_UNDERRUN BIT(3) |
110 | #define DSI_CMD_MODE_STS_ERR_UNWANTED_RD BIT(4) |
111 | #define DSI_CMD_MODE_STS_CSM_RUNNING BIT(5) |
112 | |
113 | #define DSI_DIRECT_CMD_SEND 0x00000060 |
114 | |
115 | #define DSI_DIRECT_CMD_MAIN_SETTINGS 0x00000064 |
116 | #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_SHIFT 0 |
117 | #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_MASK 0x00000007 |
118 | #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_WRITE 0 |
119 | #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_READ 1 |
120 | #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TE_REQ 4 |
121 | #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_TRIG_REQ 5 |
122 | #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_NAT_BTA_REQ 6 |
123 | #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LONGNOTSHORT BIT(3) |
124 | #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_SHIFT 8 |
125 | #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_HEAD_MASK 0x00003F00 |
126 | #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_ID_SHIFT 14 |
127 | #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_SIZE_SHIFT 16 |
128 | #define DSI_DIRECT_CMD_MAIN_SETTINGS_CMD_LP_EN BIT(21) |
129 | #define DSI_DIRECT_CMD_MAIN_SETTINGS_TRIGGER_VAL_SHIFT 24 |
130 | #define DSI_DIRECT_CMD_MAIN_SETTINGS_TRIGGER_VAL_MASK 0x0F000000 |
131 | |
132 | #define DSI_DIRECT_CMD_STS 0x00000068 |
133 | #define DSI_DIRECT_CMD_STS_CMD_TRANSMISSION BIT(0) |
134 | #define DSI_DIRECT_CMD_STS_WRITE_COMPLETED BIT(1) |
135 | #define DSI_DIRECT_CMD_STS_TRIGGER_COMPLETED BIT(2) |
136 | #define DSI_DIRECT_CMD_STS_READ_COMPLETED BIT(3) |
137 | #define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_RECEIVED_SHIFT BIT(4) |
138 | #define DSI_DIRECT_CMD_STS_ACKNOWLEDGE_WITH_ERR_RECEIVED BIT(5) |
139 | #define DSI_DIRECT_CMD_STS_TRIGGER_RECEIVED BIT(6) |
140 | #define DSI_DIRECT_CMD_STS_TE_RECEIVED BIT(7) |
141 | #define DSI_DIRECT_CMD_STS_BTA_COMPLETED BIT(8) |
142 | #define DSI_DIRECT_CMD_STS_BTA_FINISHED BIT(9) |
143 | #define DSI_DIRECT_CMD_STS_READ_COMPLETED_WITH_ERR BIT(10) |
144 | #define DSI_DIRECT_CMD_STS_TRIGGER_VAL_MASK 0x00007800 |
145 | #define DSI_DIRECT_CMD_STS_TRIGGER_VAL_SHIFT 11 |
146 | #define DSI_DIRECT_CMD_STS_ACK_VAL_SHIFT 16 |
147 | #define DSI_DIRECT_CMD_STS_ACK_VAL_MASK 0xFFFF0000 |
148 | |
149 | #define DSI_DIRECT_CMD_RD_INIT 0x0000006C |
150 | #define DSI_DIRECT_CMD_RD_INIT_RESET_SHIFT 0 |
151 | #define DSI_DIRECT_CMD_RD_INIT_RESET_MASK 0xFFFFFFFF |
152 | |
153 | #define DSI_DIRECT_CMD_WRDAT0 0x00000070 |
154 | #define DSI_DIRECT_CMD_WRDAT1 0x00000074 |
155 | #define DSI_DIRECT_CMD_WRDAT2 0x00000078 |
156 | #define DSI_DIRECT_CMD_WRDAT3 0x0000007C |
157 | |
158 | #define DSI_DIRECT_CMD_RDDAT 0x00000080 |
159 | |
160 | #define DSI_DIRECT_CMD_RD_PROPERTY 0x00000084 |
161 | #define DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_SHIFT 0 |
162 | #define DSI_DIRECT_CMD_RD_PROPERTY_RD_SIZE_MASK 0x0000FFFF |
163 | #define DSI_DIRECT_CMD_RD_PROPERTY_RD_ID_SHIFT 16 |
164 | #define DSI_DIRECT_CMD_RD_PROPERTY_RD_ID_MASK 0x00030000 |
165 | #define DSI_DIRECT_CMD_RD_PROPERTY_RD_DCSNOTGENERIC_SHIFT 18 |
166 | #define DSI_DIRECT_CMD_RD_PROPERTY_RD_DCSNOTGENERIC_MASK 0x00040000 |
167 | |
168 | #define DSI_DIRECT_CMD_RD_STS 0x00000088 |
169 | |
170 | #define DSI_VID_MAIN_CTL 0x00000090 |
171 | #define DSI_VID_MAIN_CTL_START_MODE_SHIFT 0 |
172 | #define DSI_VID_MAIN_CTL_START_MODE_MASK 0x00000003 |
173 | #define DSI_VID_MAIN_CTL_STOP_MODE_SHIFT 2 |
174 | #define DSI_VID_MAIN_CTL_STOP_MODE_MASK 0x0000000C |
175 | #define DSI_VID_MAIN_CTL_VID_ID_SHIFT 4 |
176 | #define DSI_VID_MAIN_CTL_VID_ID_MASK 0x00000030 |
177 | #define DSI_VID_MAIN_CTL_HEADER_SHIFT 6 |
178 | #define DSI_VID_MAIN_CTL_HEADER_MASK 0x00000FC0 |
179 | #define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_16BITS 0 |
180 | #define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS BIT(12) |
181 | #define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_18BITS_LOOSE BIT(13) |
182 | #define DSI_VID_MAIN_CTL_VID_PIXEL_MODE_24BITS (BIT(12) | BIT(13)) |
183 | #define DSI_VID_MAIN_CTL_BURST_MODE BIT(14) |
184 | #define DSI_VID_MAIN_CTL_SYNC_PULSE_ACTIVE BIT(15) |
185 | #define DSI_VID_MAIN_CTL_SYNC_PULSE_HORIZONTAL BIT(16) |
186 | #define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_NULL 0 |
187 | #define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_BLANKING BIT(17) |
188 | #define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_0 BIT(18) |
189 | #define DSI_VID_MAIN_CTL_REG_BLKLINE_MODE_LP_1 (BIT(17) | BIT(18)) |
190 | #define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_NULL 0 |
191 | #define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_BLANKING BIT(19) |
192 | #define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_0 BIT(20) |
193 | #define DSI_VID_MAIN_CTL_REG_BLKEOL_MODE_LP_1 (BIT(19) | BIT(20)) |
194 | #define DSI_VID_MAIN_CTL_RECOVERY_MODE_SHIFT 21 |
195 | #define DSI_VID_MAIN_CTL_RECOVERY_MODE_MASK 0x00600000 |
196 | |
197 | #define DSI_VID_VSIZE 0x00000094 |
198 | #define DSI_VID_VSIZE_VSA_LENGTH_SHIFT 0 |
199 | #define DSI_VID_VSIZE_VSA_LENGTH_MASK 0x0000003F |
200 | #define DSI_VID_VSIZE_VBP_LENGTH_SHIFT 6 |
201 | #define DSI_VID_VSIZE_VBP_LENGTH_MASK 0x00000FC0 |
202 | #define DSI_VID_VSIZE_VFP_LENGTH_SHIFT 12 |
203 | #define DSI_VID_VSIZE_VFP_LENGTH_MASK 0x000FF000 |
204 | #define DSI_VID_VSIZE_VACT_LENGTH_SHIFT 20 |
205 | #define DSI_VID_VSIZE_VACT_LENGTH_MASK 0x7FF00000 |
206 | |
207 | #define DSI_VID_HSIZE1 0x00000098 |
208 | #define DSI_VID_HSIZE1_HSA_LENGTH_SHIFT 0 |
209 | #define DSI_VID_HSIZE1_HSA_LENGTH_MASK 0x000003FF |
210 | #define DSI_VID_HSIZE1_HBP_LENGTH_SHIFT 10 |
211 | #define DSI_VID_HSIZE1_HBP_LENGTH_MASK 0x000FFC00 |
212 | #define DSI_VID_HSIZE1_HFP_LENGTH_SHIFT 20 |
213 | #define DSI_VID_HSIZE1_HFP_LENGTH_MASK 0x7FF00000 |
214 | |
215 | #define DSI_VID_HSIZE2 0x0000009C |
216 | #define DSI_VID_HSIZE2_RGB_SIZE_SHIFT 0 |
217 | #define DSI_VID_HSIZE2_RGB_SIZE_MASK 0x00001FFF |
218 | |
219 | #define DSI_VID_BLKSIZE1 0x000000A0 |
220 | #define DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_SHIFT 0 |
221 | #define DSI_VID_BLKSIZE1_BLKLINE_EVENT_PCK_MASK 0x00001FFF |
222 | #define DSI_VID_BLKSIZE1_BLKEOL_PCK_SHIFT 13 |
223 | #define DSI_VID_BLKSIZE1_BLKEOL_PCK_MASK 0x03FFE000 |
224 | |
225 | #define DSI_VID_BLKSIZE2 0x000000A4 |
226 | #define DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_SHIFT 0 |
227 | #define DSI_VID_BLKSIZE2_BLKLINE_PULSE_PCK_MASK 0x00001FFF |
228 | |
229 | #define DSI_VID_PCK_TIME 0x000000A8 |
230 | #define DSI_VID_PCK_TIME_BLKEOL_DURATION_SHIFT 0 |
231 | #define DSI_VID_PCK_TIME_BLKEOL_DURATION_MASK 0x00000FFF |
232 | |
233 | #define DSI_VID_DPHY_TIME 0x000000AC |
234 | #define DSI_VID_DPHY_TIME_REG_LINE_DURATION_SHIFT 0 |
235 | #define DSI_VID_DPHY_TIME_REG_LINE_DURATION_MASK 0x00001FFF |
236 | #define DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_SHIFT 13 |
237 | #define DSI_VID_DPHY_TIME_REG_WAKEUP_TIME_MASK 0x00FFE000 |
238 | |
239 | #define DSI_VID_MODE_STS 0x000000BC |
240 | #define DSI_VID_MODE_STS_VSG_RUNNING BIT(0) |
241 | #define DSI_VID_MODE_STS_ERR_MISSING_DATA BIT(1) |
242 | #define DSI_VID_MODE_STS_ERR_MISSING_HSYNC BIT(2) |
243 | #define DSI_VID_MODE_STS_ERR_MISSING_VSYNC BIT(3) |
244 | #define DSI_VID_MODE_STS_REG_ERR_SMALL_LENGTH BIT(4) |
245 | #define DSI_VID_MODE_STS_REG_ERR_SMALL_HEIGHT BIT(5) |
246 | #define DSI_VID_MODE_STS_ERR_BURSTWRITE BIT(6) |
247 | #define DSI_VID_MODE_STS_ERR_LINEWRITE BIT(7) |
248 | #define DSI_VID_MODE_STS_ERR_LONGREAD BIT(8) |
249 | #define DSI_VID_MODE_STS_ERR_VRS_WRONG_LENGTH BIT(9) |
250 | #define DSI_VID_MODE_STS_VSG_RECOVERY BIT(10) |
251 | |
252 | #define DSI_VID_VCA_SETTING1 0x000000C0 |
253 | #define DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_SHIFT 0 |
254 | #define DSI_VID_VCA_SETTING1_MAX_BURST_LIMIT_MASK 0x0000FFFF |
255 | #define DSI_VID_VCA_SETTING1_BURST_LP BIT(16) |
256 | |
257 | #define DSI_VID_VCA_SETTING2 0x000000C4 |
258 | #define DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_SHIFT 0 |
259 | #define DSI_VID_VCA_SETTING2_EXACT_BURST_LIMIT_MASK 0x0000FFFF |
260 | #define DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_SHIFT 16 |
261 | #define DSI_VID_VCA_SETTING2_MAX_LINE_LIMIT_MASK 0xFFFF0000 |
262 | |
263 | #define DSI_CMD_MODE_STS_CTL 0x000000F4 |
264 | #define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EN BIT(0) |
265 | #define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EN BIT(1) |
266 | #define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EN BIT(2) |
267 | #define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EN BIT(3) |
268 | #define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EN BIT(4) |
269 | #define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EN BIT(5) |
270 | #define DSI_CMD_MODE_STS_CTL_ERR_NO_TE_EDGE BIT(16) |
271 | #define DSI_CMD_MODE_STS_CTL_ERR_TE_MISS_EDGE BIT(17) |
272 | #define DSI_CMD_MODE_STS_CTL_ERR_SDI1_UNDERRUN_EDGE BIT(18) |
273 | #define DSI_CMD_MODE_STS_CTL_ERR_SDI2_UNDERRUN_EDGE BIT(19) |
274 | #define DSI_CMD_MODE_STS_CTL_ERR_UNWANTED_RD_EDGE BIT(20) |
275 | #define DSI_CMD_MODE_STS_CTL_CSM_RUNNING_EDGE BIT(21) |
276 | |
277 | #define DSI_DIRECT_CMD_STS_CTL 0x000000F8 |
278 | #define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EN BIT(0) |
279 | #define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EN BIT(1) |
280 | #define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EN BIT(2) |
281 | #define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EN BIT(3) |
282 | #define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EN BIT(4) |
283 | #define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EN BIT(5) |
284 | #define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EN BIT(6) |
285 | #define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EN BIT(7) |
286 | #define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EN BIT(8) |
287 | #define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EN BIT(9) |
288 | #define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EN BIT(10) |
289 | #define DSI_DIRECT_CMD_STS_CTL_CMD_TRANSMISSION_EDGE BIT(16) |
290 | #define DSI_DIRECT_CMD_STS_CTL_WRITE_COMPLETED_EDGE BIT(17) |
291 | #define DSI_DIRECT_CMD_STS_CTL_TRIGGER_COMPLETED_EDGE BIT(18) |
292 | #define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_EDGE BIT(19) |
293 | #define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_RECEIVED_EDGE BIT(20) |
294 | #define DSI_DIRECT_CMD_STS_CTL_ACKNOWLEDGE_WITH_ERR_EDGE BIT(21) |
295 | #define DSI_DIRECT_CMD_STS_CTL_TRIGGER_RECEIVED_EDGE BIT(22) |
296 | #define DSI_DIRECT_CMD_STS_CTL_TE_RECEIVED_EDGE BIT(23) |
297 | #define DSI_DIRECT_CMD_STS_CTL_BTA_COMPLETED_EDGE BIT(24) |
298 | #define DSI_DIRECT_CMD_STS_CTL_BTA_FINISHED_EDGE BIT(25) |
299 | #define DSI_DIRECT_CMD_STS_CTL_READ_COMPLETED_WITH_ERR_EDGE BIT(26) |
300 | |
301 | #define DSI_VID_MODE_STS_CTL 0x00000100 |
302 | #define DSI_VID_MODE_STS_CTL_VSG_RUNNING BIT(0) |
303 | #define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA BIT(1) |
304 | #define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC BIT(2) |
305 | #define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC BIT(3) |
306 | #define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH BIT(4) |
307 | #define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT BIT(5) |
308 | #define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE BIT(6) |
309 | #define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE BIT(7) |
310 | #define DSI_VID_MODE_STS_CTL_ERR_LONGREAD BIT(8) |
311 | #define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH BIT(9) |
312 | #define DSI_VID_MODE_STS_CTL_VSG_RUNNING_EDGE BIT(16) |
313 | #define DSI_VID_MODE_STS_CTL_ERR_MISSING_DATA_EDGE BIT(17) |
314 | #define DSI_VID_MODE_STS_CTL_ERR_MISSING_HSYNC_EDGE BIT(18) |
315 | #define DSI_VID_MODE_STS_CTL_ERR_MISSING_VSYNC_EDGE BIT(19) |
316 | #define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_LENGTH_EDGE BIT(20) |
317 | #define DSI_VID_MODE_STS_CTL_REG_ERR_SMALL_HEIGHT_EDGE BIT(21) |
318 | #define DSI_VID_MODE_STS_CTL_ERR_BURSTWRITE_EDGE BIT(22) |
319 | #define DSI_VID_MODE_STS_CTL_ERR_LONGWRITE_EDGE BIT(23) |
320 | #define DSI_VID_MODE_STS_CTL_ERR_LONGREAD_EDGE BIT(24) |
321 | #define DSI_VID_MODE_STS_CTL_ERR_VRS_WRONG_LENGTH_EDGE BIT(25) |
322 | #define DSI_VID_MODE_STS_CTL_VSG_RECOVERY_EDGE BIT(26) |
323 | |
324 | #define DSI_TG_STS_CTL 0x00000104 |
325 | #define DSI_MCTL_DHPY_ERR_CTL 0x00000108 |
326 | #define DSI_MCTL_MAIN_STS_CLR 0x00000110 |
327 | |
328 | #define DSI_CMD_MODE_STS_CLR 0x00000114 |
329 | #define DSI_CMD_MODE_STS_CLR_ERR_NO_TE_CLR BIT(0) |
330 | #define DSI_CMD_MODE_STS_CLR_ERR_TE_MISS_CLR BIT(1) |
331 | #define DSI_CMD_MODE_STS_CLR_ERR_SDI1_UNDERRUN_CLR BIT(2) |
332 | #define DSI_CMD_MODE_STS_CLR_ERR_SDI2_UNDERRUN_CLR BIT(3) |
333 | #define DSI_CMD_MODE_STS_CLR_ERR_UNWANTED_RD_CLR BIT(4) |
334 | #define DSI_CMD_MODE_STS_CLR_CSM_RUNNING_CLR BIT(5) |
335 | |
336 | #define DSI_DIRECT_CMD_STS_CLR 0x00000118 |
337 | #define DSI_DIRECT_CMD_STS_CLR_CMD_TRANSMISSION_CLR BIT(0) |
338 | #define DSI_DIRECT_CMD_STS_CLR_WRITE_COMPLETED_CLR BIT(1) |
339 | #define DSI_DIRECT_CMD_STS_CLR_TRIGGER_COMPLETED_CLR BIT(2) |
340 | #define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_CLR BIT(3) |
341 | #define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_RECEIVED_CLR BIT(4) |
342 | #define DSI_DIRECT_CMD_STS_CLR_ACKNOWLEDGE_WITH_ERR_RECEIVED_CLR BIT(5) |
343 | #define DSI_DIRECT_CMD_STS_CLR_TRIGGER_RECEIVED_CLR BIT(6) |
344 | #define DSI_DIRECT_CMD_STS_CLR_TE_RECEIVED_CLR BIT(7) |
345 | #define DSI_DIRECT_CMD_STS_CLR_BTA_COMPLETED_CLR BIT(8) |
346 | #define DSI_DIRECT_CMD_STS_CLR_BTA_FINISHED_CLR BIT(9) |
347 | #define DSI_DIRECT_CMD_STS_CLR_READ_COMPLETED_WITH_ERR_CLR BIT(10) |
348 | |
349 | #define DSI_DIRECT_CMD_RD_STS_CLR 0x0000011C |
350 | #define DSI_VID_MODE_STS_CLR 0x00000120 |
351 | #define DSI_TG_STS_CLR 0x00000124 |
352 | #define DSI_MCTL_DPHY_ERR_CLR 0x00000128 |
353 | #define DSI_MCTL_MAIN_STS_FLAG 0x00000130 |
354 | #define DSI_CMD_MODE_STS_FLAG 0x00000134 |
355 | #define DSI_DIRECT_CMD_STS_FLAG 0x00000138 |
356 | #define DSI_DIRECT_CMD_RD_STS_FLAG 0x0000013C |
357 | #define DSI_VID_MODE_STS_FLAG 0x00000140 |
358 | #define DSI_TG_STS_FLAG 0x00000144 |
359 | |
360 | #define DSI_DPHY_LANES_TRIM 0x00000150 |
361 | #define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT1_SHIFT 0 |
362 | #define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT1_MASK 0x00000003 |
363 | #define DSI_DPHY_LANES_TRIM_DPHY_CD_OFF_DAT1 BIT(2) |
364 | #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT1 BIT(3) |
365 | #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT1 BIT(4) |
366 | #define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT1 BIT(5) |
367 | #define DSI_DPHY_LANES_TRIM_DPHY_SKEW_CLK_SHIFT 6 |
368 | #define DSI_DPHY_LANES_TRIM_DPHY_SKEW_CLK_MASK 0x000000C0 |
369 | #define DSI_DPHY_LANES_TRIM_DPHY_LP_RX_VIL_CLK_SHIFT 8 |
370 | #define DSI_DPHY_LANES_TRIM_DPHY_LP_RX_VIL_CLK_MASK 0x00000300 |
371 | #define DSI_DPHY_LANES_TRIM_DPHY_LP_TX_SLEWRATE_CLK_SHIFT 10 |
372 | #define DSI_DPHY_LANES_TRIM_DPHY_LP_TX_SLEWRATE_CLK_MASK 0x00000C00 |
373 | #define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_81 0 |
374 | #define DSI_DPHY_LANES_TRIM_DPHY_SPECS_90_81B_0_90 BIT(12) |
375 | #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_CLK BIT(13) |
376 | #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_CLK BIT(14) |
377 | #define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_CLK BIT(15) |
378 | #define DSI_DPHY_LANES_TRIM_DPHY_SKEW_DAT2 BIT(16) |
379 | #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_UP_DAT2 BIT(18) |
380 | #define DSI_DPHY_LANES_TRIM_DPHY_HSTX_SLEWRATE_DOWN_DAT2 BIT(19) |
381 | #define DSI_DPHY_LANES_TRIM_DPHY_TEST_RESERVED_1_DAT2 BIT(20) |
382 | |
383 | #define DSI_ID_REG 0x00000FF0 |
384 | |
385 | #endif /* __DRM_MCDE_DSI_REGS */ |
386 | |