1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* |
3 | * Copyright (C) 2016 BayLibre, SAS |
4 | * Author: Neil Armstrong <narmstrong@baylibre.com> |
5 | * Copyright (C) 2015 Amlogic, Inc. All rights reserved. |
6 | */ |
7 | |
8 | #ifndef __MESON_DW_HDMI_H |
9 | #define __MESON_DW_HDMI_H |
10 | |
11 | /* |
12 | * Bit 15-10: RW Reserved. Default 1 starting from G12A |
13 | * Bit 9 RW sw_reset_i2c starting from G12A |
14 | * Bit 8 RW sw_reset_axiarb starting from G12A |
15 | * Bit 7 RW Reserved. Default 1, sw_reset_emp starting from G12A |
16 | * Bit 6 RW Reserved. Default 1, sw_reset_flt starting from G12A |
17 | * Bit 5 RW Reserved. Default 1, sw_reset_hdcp22 starting from G12A |
18 | * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset. |
19 | * Default 1. |
20 | * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset; |
21 | * 0=Release from reset. |
22 | * Default 1. |
23 | * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset. |
24 | * Default 1. |
25 | * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset; |
26 | * 0=Release from reset. Default 1. |
27 | * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset; |
28 | * 0=Release from reset. Default 1. |
29 | */ |
30 | #define HDMITX_TOP_SW_RESET (0x000) |
31 | |
32 | /* |
33 | * Bit 31 RW free_clk_en: 0=Enable clock gating for power saving; 1= Disable |
34 | * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0. |
35 | * Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0. |
36 | * Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0. |
37 | * Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0. |
38 | * Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0. |
39 | * Bit 7 RW hdcp22_skpclk_en: starting from G12A, 1=enable; 0=disable |
40 | * Bit 6 RW hdcp22_esmclk_en: starting from G12A, 1=enable; 0=disable |
41 | * Bit 5 RW hdcp22_tmdsclk_en: starting from G12A, 1=enable; 0=disable |
42 | * Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. Reserved for G12A |
43 | * Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0. |
44 | * Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0. |
45 | * Bit 1 RW tmds_clk_en: 1=enable tmds_clk; 0=disable. Default 0. |
46 | * Bit 0 RW pixel_clk_en: 1=enable pixel_clk; 0=disable. Default 0. |
47 | */ |
48 | #define HDMITX_TOP_CLK_CNTL (0x001) |
49 | |
50 | /* |
51 | * Bit 31:28 RW rxsense_glitch_width: starting from G12A |
52 | * Bit 27:16 RW rxsense_valid_width: starting from G12A |
53 | * Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024. Default 0. |
54 | * Bit 15:12 RW hpd_glitch_width: filter out glitch <= N. Default 0. |
55 | */ |
56 | #define HDMITX_TOP_HPD_FILTER (0x002) |
57 | |
58 | /* |
59 | * intr_maskn: MASK_N, one bit per interrupt source. |
60 | * 1=Enable interrupt source; 0=Disable interrupt source. Default 0. |
61 | * [ 7] rxsense_fall starting from G12A |
62 | * [ 6] rxsense_rise starting from G12A |
63 | * [ 5] err_i2c_timeout starting from G12A |
64 | * [ 4] hdcp22_rndnum_err |
65 | * [ 3] nonce_rfrsh_rise |
66 | * [ 2] hpd_fall_intr |
67 | * [ 1] hpd_rise_intr |
68 | * [ 0] core_intr |
69 | */ |
70 | #define HDMITX_TOP_INTR_MASKN (0x003) |
71 | |
72 | /* |
73 | * Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt |
74 | * bit, read back the interrupt status. |
75 | * Bit 31 R IP interrupt status |
76 | * Bit 7 RW rxsense_fall starting from G12A |
77 | * Bit 6 RW rxsense_rise starting from G12A |
78 | * Bit 5 RW err_i2c_timeout starting from G12A |
79 | * Bit 2 RW hpd_fall |
80 | * Bit 1 RW hpd_rise |
81 | * Bit 0 RW IP interrupt |
82 | */ |
83 | #define HDMITX_TOP_INTR_STAT (0x004) |
84 | |
85 | /* |
86 | * [7] rxsense_fall starting from G12A |
87 | * [6] rxsense_rise starting from G12A |
88 | * [5] err_i2c_timeout starting from G12A |
89 | * [4] hdcp22_rndnum_err |
90 | * [3] nonce_rfrsh_rise |
91 | * [2] hpd_fall |
92 | * [1] hpd_rise |
93 | * [0] core_intr_rise |
94 | */ |
95 | #define HDMITX_TOP_INTR_STAT_CLR (0x005) |
96 | |
97 | #define HDMITX_TOP_INTR_CORE BIT(0) |
98 | #define HDMITX_TOP_INTR_HPD_RISE BIT(1) |
99 | #define HDMITX_TOP_INTR_HPD_FALL BIT(2) |
100 | #define HDMITX_TOP_INTR_RXSENSE_RISE BIT(6) |
101 | #define HDMITX_TOP_INTR_RXSENSE_FALL BIT(7) |
102 | |
103 | /* |
104 | * Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data; |
105 | * 3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0. |
106 | * Bit 11: 9 RW shift_pttn_repeat: 0=New pattern every clk cycle; 1=New pattern |
107 | * every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0. |
108 | * Bit 8 RW shift_pttn_en: 1= Enable shift pattern generator; 0=Disable. |
109 | * Default 0. |
110 | * Bit 4: 3 RW prbs_pttn_mode: 0=PRBS11; 1=PRBS15; 2=PRBS7; 3=PRBS31. Default 0. |
111 | * Bit 2: 1 RW prbs_pttn_width: 0=idle; 1=output 8-bit pattern; |
112 | * 2=Output 1-bit pattern; 3=output 10-bit pattern. Default 0. |
113 | * Bit 0 RW prbs_pttn_en: 1=Enable PRBS generator; 0=Disable. Default 0. |
114 | */ |
115 | #define HDMITX_TOP_BIST_CNTL (0x006) |
116 | |
117 | /* Bit 29:20 RW shift_pttn_data[59:50]. Default 0. */ |
118 | /* Bit 19:10 RW shift_pttn_data[69:60]. Default 0. */ |
119 | /* Bit 9: 0 RW shift_pttn_data[79:70]. Default 0. */ |
120 | #define HDMITX_TOP_SHIFT_PTTN_012 (0x007) |
121 | |
122 | /* Bit 29:20 RW shift_pttn_data[29:20]. Default 0. */ |
123 | /* Bit 19:10 RW shift_pttn_data[39:30]. Default 0. */ |
124 | /* Bit 9: 0 RW shift_pttn_data[49:40]. Default 0. */ |
125 | #define HDMITX_TOP_SHIFT_PTTN_345 (0x008) |
126 | |
127 | /* Bit 19:10 RW shift_pttn_data[ 9: 0]. Default 0. */ |
128 | /* Bit 9: 0 RW shift_pttn_data[19:10]. Default 0. */ |
129 | #define HDMITX_TOP_SHIFT_PTTN_67 (0x009) |
130 | |
131 | /* Bit 25:16 RW tmds_clk_pttn[19:10]. Default 0. */ |
132 | /* Bit 9: 0 RW tmds_clk_pttn[ 9: 0]. Default 0. */ |
133 | #define HDMITX_TOP_TMDS_CLK_PTTN_01 (0x00A) |
134 | |
135 | /* Bit 25:16 RW tmds_clk_pttn[39:30]. Default 0. */ |
136 | /* Bit 9: 0 RW tmds_clk_pttn[29:20]. Default 0. */ |
137 | #define HDMITX_TOP_TMDS_CLK_PTTN_23 (0x00B) |
138 | |
139 | /* |
140 | * Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern, |
141 | * used when TMDS CLK rate = TMDS character rate /4. Default 0. |
142 | * Bit 0 R Reserved. Default 0. |
143 | * [ 1] shift_tmds_clk_pttn |
144 | * [ 0] load_tmds_clk_pttn |
145 | */ |
146 | #define HDMITX_TOP_TMDS_CLK_PTTN_CNTL (0x00C) |
147 | |
148 | /* |
149 | * Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM |
150 | * failure, write 1 to clear the failure flag. Default 0. |
151 | */ |
152 | #define HDMITX_TOP_REVOCMEM_STAT (0x00D) |
153 | |
154 | /* |
155 | * Bit 1 R filtered RxSense status |
156 | * Bit 0 R filtered HPD status. |
157 | */ |
158 | #define HDMITX_TOP_STAT0 (0x00E) |
159 | |
160 | #endif /* __MESON_DW_HDMI_H */ |
161 | |