| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2016 BayLibre, SAS |
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| 4 | * Author: Neil Armstrong <narmstrong@baylibre.com> |
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| 5 | */ |
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| 6 | |
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| 7 | /* Video Clock */ |
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| 8 | |
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| 9 | #ifndef __MESON_VCLK_H |
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| 10 | #define __MESON_VCLK_H |
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| 11 | |
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| 12 | #include <drm/drm_modes.h> |
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| 13 | |
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| 14 | struct meson_drm; |
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| 15 | |
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| 16 | enum { |
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| 17 | MESON_VCLK_TARGET_CVBS = 0, |
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| 18 | MESON_VCLK_TARGET_HDMI = 1, |
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| 19 | MESON_VCLK_TARGET_DMT = 2, |
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| 20 | }; |
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| 21 | |
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| 22 | /* 27MHz is the CVBS Pixel Clock */ |
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| 23 | #define MESON_VCLK_CVBS 27000 |
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| 24 | |
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| 25 | enum drm_mode_status |
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| 26 | meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq); |
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| 27 | enum drm_mode_status |
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| 28 | meson_vclk_vic_supported_freq(struct meson_drm *priv, unsigned int phy_freq, |
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| 29 | unsigned int vclk_freq); |
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| 30 | |
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| 31 | void meson_vclk_setup(struct meson_drm *priv, unsigned int target, |
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| 32 | unsigned int phy_freq, unsigned int vclk_freq, |
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| 33 | unsigned int venc_freq, unsigned int dac_freq, |
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| 34 | bool hdmi_use_enci); |
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| 35 | |
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| 36 | #endif /* __MESON_VCLK_H */ |
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| 37 | |
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