| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2016 BayLibre, SAS |
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| 4 | * Author: Neil Armstrong <narmstrong@baylibre.com> |
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| 5 | */ |
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| 6 | |
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| 7 | /* Video Input Unit */ |
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| 8 | |
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| 9 | #ifndef __MESON_VIU_H |
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| 10 | #define __MESON_VIU_H |
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| 11 | |
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| 12 | /* OSDx_BLKx_CFG */ |
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| 13 | #define OSD_MALI_SRC_EN BIT(30) |
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| 14 | |
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| 15 | #define OSD_CANVAS_SEL 16 |
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| 16 | |
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| 17 | #define OSD_ENDIANNESS_LE BIT(15) |
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| 18 | #define OSD_ENDIANNESS_BE (0) |
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| 19 | |
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| 20 | #define OSD_BLK_MODE_422 (0x03 << 8) |
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| 21 | #define OSD_BLK_MODE_16 (0x04 << 8) |
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| 22 | #define OSD_BLK_MODE_32 (0x05 << 8) |
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| 23 | #define OSD_BLK_MODE_24 (0x07 << 8) |
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| 24 | |
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| 25 | #define OSD_OUTPUT_COLOR_RGB BIT(7) |
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| 26 | #define OSD_OUTPUT_COLOR_YUV (0) |
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| 27 | |
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| 28 | #define OSD_COLOR_MATRIX_32_RGBA (0x00 << 2) |
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| 29 | #define OSD_COLOR_MATRIX_32_ARGB (0x01 << 2) |
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| 30 | #define OSD_COLOR_MATRIX_32_ABGR (0x02 << 2) |
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| 31 | #define OSD_COLOR_MATRIX_32_BGRA (0x03 << 2) |
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| 32 | |
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| 33 | #define OSD_COLOR_MATRIX_24_RGB (0x00 << 2) |
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| 34 | |
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| 35 | #define OSD_COLOR_MATRIX_16_RGB655 (0x00 << 2) |
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| 36 | #define OSD_COLOR_MATRIX_16_RGB565 (0x04 << 2) |
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| 37 | |
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| 38 | #define OSD_MALI_COLOR_MODE_R8 (0 << 8) |
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| 39 | #define OSD_MALI_COLOR_MODE_YUV422 (1 << 8) |
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| 40 | #define OSD_MALI_COLOR_MODE_RGB565 (2 << 8) |
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| 41 | #define OSD_MALI_COLOR_MODE_RGBA5551 (3 << 8) |
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| 42 | #define OSD_MALI_COLOR_MODE_RGBA4444 (4 << 8) |
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| 43 | #define OSD_MALI_COLOR_MODE_RGBA8888 (5 << 8) |
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| 44 | #define OSD_MALI_COLOR_MODE_RGB888 (7 << 8) |
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| 45 | #define OSD_MALI_COLOR_MODE_YUV422_10B (8 << 8) |
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| 46 | #define OSD_MALI_COLOR_MODE_RGBA1010102 (9 << 8) |
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| 47 | |
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| 48 | #define OSD_INTERLACE_ENABLED BIT(1) |
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| 49 | #define OSD_INTERLACE_ODD BIT(0) |
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| 50 | #define OSD_INTERLACE_EVEN (0) |
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| 51 | |
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| 52 | /* OSDx_CTRL_STAT */ |
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| 53 | #define OSD_ENABLE BIT(21) |
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| 54 | #define OSD_MEM_LINEAR_ADDR BIT(2) |
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| 55 | #define OSD_BLK0_ENABLE BIT(0) |
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| 56 | |
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| 57 | #define OSD_GLOBAL_ALPHA_SHIFT 12 |
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| 58 | |
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| 59 | /* OSDx_CTRL_STAT2 */ |
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| 60 | #define OSD_DPATH_MALI_AFBCD BIT(15) |
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| 61 | #define OSD_REPLACE_EN BIT(14) |
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| 62 | #define OSD_REPLACE_SHIFT 6 |
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| 63 | #define OSD_PENDING_STAT_CLEAN BIT(1) |
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| 64 | |
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| 65 | void meson_viu_osd1_reset(struct meson_drm *priv); |
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| 66 | void meson_viu_g12a_enable_osd1_afbc(struct meson_drm *priv); |
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| 67 | void meson_viu_g12a_disable_osd1_afbc(struct meson_drm *priv); |
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| 68 | void meson_viu_gxm_enable_osd1_afbc(struct meson_drm *priv); |
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| 69 | void meson_viu_gxm_disable_osd1_afbc(struct meson_drm *priv); |
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| 70 | void meson_viu_init(struct meson_drm *priv); |
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| 71 | |
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| 72 | #endif /* __MESON_VIU_H */ |
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| 73 | |
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