| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * MGA Millennium (MGA2064W) functions |
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| 4 | * MGA Mystique (MGA1064SG) functions |
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| 5 | * |
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| 6 | * Copyright 1996 The XFree86 Project, Inc. |
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| 7 | * |
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| 8 | * Authors |
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| 9 | * Dirk Hohndel |
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| 10 | * hohndel@XFree86.Org |
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| 11 | * David Dawes |
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| 12 | * dawes@XFree86.Org |
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| 13 | * Contributors: |
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| 14 | * Guy DESBIEF, Aix-en-provence, France |
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| 15 | * g.desbief@aix.pacwan.net |
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| 16 | * MGA1064SG Mystique register file |
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| 17 | */ |
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| 18 | |
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| 19 | #ifndef _MGA_REG_H_ |
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| 20 | #define _MGA_REG_H_ |
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| 21 | |
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| 22 | #include <linux/bits.h> |
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| 23 | |
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| 24 | #define MGAREG_DWGCTL 0x1c00 |
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| 25 | #define MGAREG_MACCESS 0x1c04 |
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| 26 | /* the following is a mystique only register */ |
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| 27 | #define MGAREG_MCTLWTST 0x1c08 |
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| 28 | #define MGAREG_ZORG 0x1c0c |
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| 29 | |
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| 30 | #define MGAREG_PAT0 0x1c10 |
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| 31 | #define MGAREG_PAT1 0x1c14 |
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| 32 | #define MGAREG_PLNWT 0x1c1c |
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| 33 | |
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| 34 | #define MGAREG_BCOL 0x1c20 |
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| 35 | #define MGAREG_FCOL 0x1c24 |
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| 36 | |
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| 37 | #define MGAREG_SRC0 0x1c30 |
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| 38 | #define MGAREG_SRC1 0x1c34 |
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| 39 | #define MGAREG_SRC2 0x1c38 |
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| 40 | #define MGAREG_SRC3 0x1c3c |
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| 41 | |
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| 42 | #define MGAREG_XYSTRT 0x1c40 |
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| 43 | #define MGAREG_XYEND 0x1c44 |
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| 44 | |
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| 45 | #define MGAREG_SHIFT 0x1c50 |
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| 46 | /* the following is a mystique only register */ |
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| 47 | #define MGAREG_DMAPAD 0x1c54 |
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| 48 | #define MGAREG_SGN 0x1c58 |
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| 49 | #define MGAREG_LEN 0x1c5c |
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| 50 | |
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| 51 | #define MGAREG_AR0 0x1c60 |
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| 52 | #define MGAREG_AR1 0x1c64 |
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| 53 | #define MGAREG_AR2 0x1c68 |
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| 54 | #define MGAREG_AR3 0x1c6c |
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| 55 | #define MGAREG_AR4 0x1c70 |
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| 56 | #define MGAREG_AR5 0x1c74 |
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| 57 | #define MGAREG_AR6 0x1c78 |
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| 58 | |
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| 59 | #define MGAREG_CXBNDRY 0x1c80 |
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| 60 | #define MGAREG_FXBNDRY 0x1c84 |
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| 61 | #define MGAREG_YDSTLEN 0x1c88 |
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| 62 | #define MGAREG_PITCH 0x1c8c |
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| 63 | |
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| 64 | #define MGAREG_YDST 0x1c90 |
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| 65 | #define MGAREG_YDSTORG 0x1c94 |
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| 66 | #define MGAREG_YTOP 0x1c98 |
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| 67 | #define MGAREG_YBOT 0x1c9c |
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| 68 | |
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| 69 | #define MGAREG_CXLEFT 0x1ca0 |
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| 70 | #define MGAREG_CXRIGHT 0x1ca4 |
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| 71 | #define MGAREG_FXLEFT 0x1ca8 |
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| 72 | #define MGAREG_FXRIGHT 0x1cac |
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| 73 | |
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| 74 | #define MGAREG_XDST 0x1cb0 |
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| 75 | |
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| 76 | #define MGAREG_DR0 0x1cc0 |
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| 77 | #define MGAREG_DR1 0x1cc4 |
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| 78 | #define MGAREG_DR2 0x1cc8 |
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| 79 | #define MGAREG_DR3 0x1ccc |
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| 80 | |
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| 81 | #define MGAREG_DR4 0x1cd0 |
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| 82 | #define MGAREG_DR5 0x1cd4 |
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| 83 | #define MGAREG_DR6 0x1cd8 |
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| 84 | #define MGAREG_DR7 0x1cdc |
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| 85 | |
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| 86 | #define MGAREG_DR8 0x1ce0 |
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| 87 | #define MGAREG_DR9 0x1ce4 |
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| 88 | #define MGAREG_DR10 0x1ce8 |
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| 89 | #define MGAREG_DR11 0x1cec |
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| 90 | |
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| 91 | #define MGAREG_DR12 0x1cf0 |
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| 92 | #define MGAREG_DR13 0x1cf4 |
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| 93 | #define MGAREG_DR14 0x1cf8 |
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| 94 | #define MGAREG_DR15 0x1cfc |
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| 95 | |
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| 96 | #define MGAREG_SRCORG 0x2cb4 |
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| 97 | #define MGAREG_DSTORG 0x2cb8 |
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| 98 | |
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| 99 | /* add or this to one of the previous "power registers" to start |
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| 100 | the drawing engine */ |
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| 101 | |
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| 102 | #define MGAREG_EXEC 0x0100 |
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| 103 | |
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| 104 | #define MGAREG_FIFOSTATUS 0x1e10 |
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| 105 | #define MGAREG_Status 0x1e14 |
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| 106 | #define MGAREG_CACHEFLUSH 0x1fff |
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| 107 | #define MGAREG_ICLEAR 0x1e18 |
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| 108 | #define MGAREG_IEN 0x1e1c |
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| 109 | |
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| 110 | #define MGAREG_VCOUNT 0x1e20 |
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| 111 | |
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| 112 | #define MGAREG_Reset 0x1e40 |
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| 113 | |
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| 114 | #define MGAREG_OPMODE 0x1e54 |
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| 115 | |
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| 116 | /* Warp Registers */ |
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| 117 | #define MGAREG_WIADDR 0x1dc0 |
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| 118 | #define MGAREG_WIADDR2 0x1dd8 |
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| 119 | #define MGAREG_WGETMSB 0x1dc8 |
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| 120 | #define MGAREG_WVRTXSZ 0x1dcc |
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| 121 | #define MGAREG_WACCEPTSEQ 0x1dd4 |
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| 122 | #define MGAREG_WMISC 0x1e70 |
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| 123 | |
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| 124 | #define MGAREG_MEMCTL 0x2e08 |
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| 125 | |
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| 126 | /* OPMODE register additives */ |
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| 127 | |
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| 128 | #define MGAOPM_DMA_GENERAL (0x00 << 2) |
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| 129 | #define MGAOPM_DMA_BLIT (0x01 << 2) |
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| 130 | #define MGAOPM_DMA_VECTOR (0x10 << 2) |
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| 131 | |
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| 132 | /* MACCESS register additives */ |
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| 133 | #define MGAMAC_PW8 0x00 |
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| 134 | #define MGAMAC_PW16 0x01 |
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| 135 | #define MGAMAC_PW24 0x03 /* not a typo */ |
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| 136 | #define MGAMAC_PW32 0x02 /* not a typo */ |
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| 137 | #define MGAMAC_BYPASS332 0x10000000 |
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| 138 | #define MGAMAC_NODITHER 0x40000000 |
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| 139 | #define MGAMAC_DIT555 0x80000000 |
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| 140 | |
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| 141 | /* DWGCTL register additives */ |
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| 142 | |
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| 143 | /* Lines */ |
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| 144 | |
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| 145 | #define MGADWG_LINE_OPEN 0x00 |
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| 146 | #define MGADWG_AUTOLINE_OPEN 0x01 |
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| 147 | #define MGADWG_LINE_CLOSE 0x02 |
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| 148 | #define MGADWG_AUTOLINE_CLOSE 0x03 |
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| 149 | |
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| 150 | /* Trapezoids */ |
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| 151 | #define MGADWG_TRAP 0x04 |
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| 152 | #define MGADWG_TEXTURE_TRAP 0x06 |
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| 153 | |
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| 154 | /* BitBlts */ |
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| 155 | |
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| 156 | #define MGADWG_BITBLT 0x08 |
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| 157 | #define MGADWG_FBITBLT 0x0c |
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| 158 | #define MGADWG_ILOAD 0x09 |
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| 159 | #define MGADWG_ILOAD_SCALE 0x0d |
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| 160 | #define MGADWG_ILOAD_FILTER 0x0f |
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| 161 | #define MGADWG_ILOAD_HIQH 0x07 |
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| 162 | #define MGADWG_ILOAD_HIQHV 0x0e |
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| 163 | #define MGADWG_IDUMP 0x0a |
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| 164 | |
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| 165 | /* atype access to WRAM */ |
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| 166 | |
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| 167 | #define MGADWG_RPL ( 0x00 << 4 ) |
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| 168 | #define MGADWG_RSTR ( 0x01 << 4 ) |
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| 169 | #define MGADWG_ZI ( 0x03 << 4 ) |
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| 170 | #define MGADWG_BLK ( 0x04 << 4 ) |
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| 171 | #define MGADWG_I ( 0x07 << 4 ) |
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| 172 | |
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| 173 | /* specifies whether bit blits are linear or xy */ |
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| 174 | #define MGADWG_LINEAR ( 0x01 << 7 ) |
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| 175 | |
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| 176 | /* z drawing mode. use MGADWG_NOZCMP for always */ |
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| 177 | |
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| 178 | #define MGADWG_NOZCMP ( 0x00 << 8 ) |
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| 179 | #define MGADWG_ZE ( 0x02 << 8 ) |
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| 180 | #define MGADWG_ZNE ( 0x03 << 8 ) |
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| 181 | #define MGADWG_ZLT ( 0x04 << 8 ) |
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| 182 | #define MGADWG_ZLTE ( 0x05 << 8 ) |
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| 183 | #define MGADWG_GT ( 0x06 << 8 ) |
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| 184 | #define MGADWG_GTE ( 0x07 << 8 ) |
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| 185 | |
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| 186 | /* use this to force colour expansion circuitry to do its stuff */ |
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| 187 | |
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| 188 | #define MGADWG_SOLID ( 0x01 << 11 ) |
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| 189 | |
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| 190 | /* ar register at zero */ |
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| 191 | |
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| 192 | #define MGADWG_ARZERO ( 0x01 << 12 ) |
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| 193 | |
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| 194 | #define MGADWG_SGNZERO ( 0x01 << 13 ) |
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| 195 | |
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| 196 | #define MGADWG_SHIFTZERO ( 0x01 << 14 ) |
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| 197 | |
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| 198 | /* See table on 4-43 for bop ALU operations */ |
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| 199 | |
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| 200 | /* See table on 4-44 for translucidity masks */ |
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| 201 | |
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| 202 | #define MGADWG_BMONOLEF ( 0x00 << 25 ) |
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| 203 | #define MGADWG_BMONOWF ( 0x04 << 25 ) |
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| 204 | #define MGADWG_BPLAN ( 0x01 << 25 ) |
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| 205 | |
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| 206 | /* note that if bfcol is specified and you're doing a bitblt, it causes |
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| 207 | a fbitblt to be performed, so check that you obey the fbitblt rules */ |
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| 208 | |
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| 209 | #define MGADWG_BFCOL ( 0x02 << 25 ) |
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| 210 | #define MGADWG_BUYUV ( 0x0e << 25 ) |
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| 211 | #define MGADWG_BU32BGR ( 0x03 << 25 ) |
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| 212 | #define MGADWG_BU32RGB ( 0x07 << 25 ) |
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| 213 | #define MGADWG_BU24BGR ( 0x0b << 25 ) |
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| 214 | #define MGADWG_BU24RGB ( 0x0f << 25 ) |
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| 215 | |
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| 216 | #define MGADWG_PATTERN ( 0x01 << 29 ) |
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| 217 | #define MGADWG_TRANSC ( 0x01 << 30 ) |
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| 218 | #define MGAREG_MISC_WRITE 0x3c2 |
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| 219 | #define MGAREG_MISC_READ 0x3cc |
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| 220 | #define MGAREG_MEM_MISC_WRITE 0x1fc2 |
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| 221 | #define MGAREG_MEM_MISC_READ 0x1fcc |
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| 222 | |
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| 223 | #define MGAREG_MISC_IOADSEL (0x1 << 0) |
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| 224 | #define MGAREG_MISC_RAMMAPEN (0x1 << 1) |
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| 225 | #define MGAREG_MISC_CLKSEL_MASK GENMASK(3, 2) |
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| 226 | #define MGAREG_MISC_CLKSEL_VGA25 (0x0 << 2) |
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| 227 | #define MGAREG_MISC_CLKSEL_VGA28 (0x1 << 2) |
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| 228 | #define MGAREG_MISC_CLKSEL_MGA (0x3 << 2) |
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| 229 | #define MGAREG_MISC_VIDEO_DIS (0x1 << 4) |
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| 230 | #define MGAREG_MISC_HIGH_PG_SEL (0x1 << 5) |
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| 231 | #define MGAREG_MISC_HSYNCPOL BIT(6) |
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| 232 | #define MGAREG_MISC_VSYNCPOL BIT(7) |
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| 233 | |
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| 234 | /* MMIO VGA registers */ |
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| 235 | #define MGAREG_SEQ_INDEX 0x1fc4 |
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| 236 | #define MGAREG_SEQ_DATA 0x1fc5 |
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| 237 | |
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| 238 | #define MGAREG_SEQ0_ASYNCRST BIT(0) |
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| 239 | #define MGAREG_SEQ0_SYNCRST BIT(1) |
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| 240 | |
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| 241 | #define MGAREG_SEQ1_SCROFF BIT(5) |
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| 242 | |
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| 243 | #define MGAREG_CRTC_INDEX 0x1fd4 |
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| 244 | #define MGAREG_CRTC_DATA 0x1fd5 |
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| 245 | |
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| 246 | #define MGAREG_CRTC11_VINTCLR BIT(4) |
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| 247 | #define MGAREG_CRTC11_VINTEN BIT(5) |
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| 248 | #define MGAREG_CRTC11_CRTCPROTECT BIT(7) |
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| 249 | |
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| 250 | #define MGAREG_CRTCEXT_INDEX 0x1fde |
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| 251 | #define MGAREG_CRTCEXT_DATA 0x1fdf |
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| 252 | |
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| 253 | #define MGAREG_CRTCEXT0_OFFSET_MASK GENMASK(5, 4) |
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| 254 | |
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| 255 | #define MGAREG_CRTCEXT1_VRSTEN BIT(7) |
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| 256 | #define MGAREG_CRTCEXT1_VSYNCOFF BIT(5) |
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| 257 | #define MGAREG_CRTCEXT1_HSYNCOFF BIT(4) |
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| 258 | #define MGAREG_CRTCEXT1_HRSTEN BIT(3) |
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| 259 | |
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| 260 | #define MGAREG_CRTCEXT3_MGAMODE BIT(7) |
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| 261 | |
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| 262 | /* Cursor X and Y position */ |
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| 263 | #define MGA_CURPOSXL 0x3c0c |
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| 264 | #define MGA_CURPOSXH 0x3c0d |
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| 265 | #define MGA_CURPOSYL 0x3c0e |
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| 266 | #define MGA_CURPOSYH 0x3c0f |
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| 267 | |
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| 268 | /* MGA bits for registers PCI_OPTION_REG */ |
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| 269 | #define MGA1064_OPT_SYS_CLK_PCI ( 0x00 << 0 ) |
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| 270 | #define MGA1064_OPT_SYS_CLK_PLL ( 0x01 << 0 ) |
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| 271 | #define MGA1064_OPT_SYS_CLK_EXT ( 0x02 << 0 ) |
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| 272 | #define MGA1064_OPT_SYS_CLK_MSK ( 0x03 << 0 ) |
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| 273 | |
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| 274 | #define MGA1064_OPT_SYS_CLK_DIS ( 0x01 << 2 ) |
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| 275 | #define MGA1064_OPT_G_CLK_DIV_1 ( 0x01 << 3 ) |
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| 276 | #define MGA1064_OPT_M_CLK_DIV_1 ( 0x01 << 4 ) |
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| 277 | |
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| 278 | #define MGA1064_OPT_SYS_PLL_PDN ( 0x01 << 5 ) |
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| 279 | #define MGA1064_OPT_VGA_ION ( 0x01 << 8 ) |
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| 280 | |
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| 281 | /* MGA registers in PCI config space */ |
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| 282 | #define PCI_MGA_INDEX 0x44 |
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| 283 | #define PCI_MGA_DATA 0x48 |
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| 284 | #define PCI_MGA_OPTION 0x40 |
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| 285 | #define PCI_MGA_OPTION2 0x50 |
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| 286 | #define PCI_MGA_OPTION3 0x54 |
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| 287 | |
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| 288 | #define PCI_MGA_OPTION_HARDPWMSK BIT(14) |
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| 289 | |
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| 290 | #define RAMDAC_OFFSET 0x3c00 |
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| 291 | |
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| 292 | /* TVP3026 direct registers */ |
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| 293 | |
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| 294 | #define TVP3026_INDEX 0x00 |
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| 295 | #define TVP3026_WADR_PAL 0x00 |
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| 296 | #define TVP3026_COL_PAL 0x01 |
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| 297 | #define TVP3026_PIX_RD_MSK 0x02 |
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| 298 | #define TVP3026_RADR_PAL 0x03 |
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| 299 | #define TVP3026_CUR_COL_ADDR 0x04 |
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| 300 | #define TVP3026_CUR_COL_DATA 0x05 |
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| 301 | #define TVP3026_DATA 0x0a |
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| 302 | #define TVP3026_CUR_RAM 0x0b |
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| 303 | #define TVP3026_CUR_XLOW 0x0c |
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| 304 | #define TVP3026_CUR_XHI 0x0d |
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| 305 | #define TVP3026_CUR_YLOW 0x0e |
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| 306 | #define TVP3026_CUR_YHI 0x0f |
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| 307 | |
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| 308 | /* TVP3026 indirect registers */ |
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| 309 | |
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| 310 | #define TVP3026_SILICON_REV 0x01 |
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| 311 | #define TVP3026_CURSOR_CTL 0x06 |
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| 312 | #define TVP3026_LATCH_CTL 0x0f |
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| 313 | #define TVP3026_TRUE_COLOR_CTL 0x18 |
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| 314 | #define TVP3026_MUX_CTL 0x19 |
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| 315 | #define TVP3026_CLK_SEL 0x1a |
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| 316 | #define TVP3026_PAL_PAGE 0x1c |
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| 317 | #define TVP3026_GEN_CTL 0x1d |
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| 318 | #define TVP3026_MISC_CTL 0x1e |
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| 319 | #define TVP3026_GEN_IO_CTL 0x2a |
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| 320 | #define TVP3026_GEN_IO_DATA 0x2b |
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| 321 | #define TVP3026_PLL_ADDR 0x2c |
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| 322 | #define TVP3026_PIX_CLK_DATA 0x2d |
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| 323 | #define TVP3026_MEM_CLK_DATA 0x2e |
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| 324 | #define TVP3026_LOAD_CLK_DATA 0x2f |
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| 325 | #define TVP3026_KEY_RED_LOW 0x32 |
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| 326 | #define TVP3026_KEY_RED_HI 0x33 |
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| 327 | #define TVP3026_KEY_GREEN_LOW 0x34 |
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| 328 | #define TVP3026_KEY_GREEN_HI 0x35 |
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| 329 | #define TVP3026_KEY_BLUE_LOW 0x36 |
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| 330 | #define TVP3026_KEY_BLUE_HI 0x37 |
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| 331 | #define TVP3026_KEY_CTL 0x38 |
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| 332 | #define TVP3026_MCLK_CTL 0x39 |
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| 333 | #define TVP3026_SENSE_TEST 0x3a |
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| 334 | #define TVP3026_TEST_DATA 0x3b |
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| 335 | #define TVP3026_CRC_LSB 0x3c |
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| 336 | #define TVP3026_CRC_MSB 0x3d |
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| 337 | #define TVP3026_CRC_CTL 0x3e |
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| 338 | #define TVP3026_ID 0x3f |
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| 339 | #define TVP3026_RESET 0xff |
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| 340 | |
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| 341 | |
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| 342 | /* MGA1064 DAC Register file */ |
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| 343 | /* MGA1064 direct registers */ |
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| 344 | |
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| 345 | #define MGA1064_INDEX 0x00 |
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| 346 | #define MGA1064_WADR_PAL 0x00 |
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| 347 | #define MGA1064_SPAREREG 0x00 |
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| 348 | #define MGA1064_COL_PAL 0x01 |
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| 349 | #define MGA1064_PIX_RD_MSK 0x02 |
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| 350 | #define MGA1064_RADR_PAL 0x03 |
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| 351 | #define MGA1064_DATA 0x0a |
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| 352 | |
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| 353 | #define MGA1064_CUR_XLOW 0x0c |
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| 354 | #define MGA1064_CUR_XHI 0x0d |
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| 355 | #define MGA1064_CUR_YLOW 0x0e |
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| 356 | #define MGA1064_CUR_YHI 0x0f |
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| 357 | |
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| 358 | /* MGA1064 indirect registers */ |
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| 359 | #define MGA1064_DVI_PIPE_CTL 0x03 |
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| 360 | #define MGA1064_CURSOR_BASE_ADR_LOW 0x04 |
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| 361 | #define MGA1064_CURSOR_BASE_ADR_HI 0x05 |
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| 362 | #define MGA1064_CURSOR_CTL 0x06 |
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| 363 | #define MGA1064_CURSOR_COL0_RED 0x08 |
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| 364 | #define MGA1064_CURSOR_COL0_GREEN 0x09 |
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| 365 | #define MGA1064_CURSOR_COL0_BLUE 0x0a |
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| 366 | |
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| 367 | #define MGA1064_CURSOR_COL1_RED 0x0c |
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| 368 | #define MGA1064_CURSOR_COL1_GREEN 0x0d |
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| 369 | #define MGA1064_CURSOR_COL1_BLUE 0x0e |
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| 370 | |
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| 371 | #define MGA1064_CURSOR_COL2_RED 0x010 |
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| 372 | #define MGA1064_CURSOR_COL2_GREEN 0x011 |
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| 373 | #define MGA1064_CURSOR_COL2_BLUE 0x012 |
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| 374 | |
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| 375 | #define MGA1064_VREF_CTL 0x018 |
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| 376 | |
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| 377 | #define MGA1064_MUL_CTL 0x19 |
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| 378 | #define MGA1064_MUL_CTL_8bits 0x0 |
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| 379 | #define MGA1064_MUL_CTL_15bits 0x01 |
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| 380 | #define MGA1064_MUL_CTL_16bits 0x02 |
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| 381 | #define MGA1064_MUL_CTL_24bits 0x03 |
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| 382 | #define MGA1064_MUL_CTL_32bits 0x04 |
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| 383 | #define MGA1064_MUL_CTL_2G8V16bits 0x05 |
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| 384 | #define MGA1064_MUL_CTL_G16V16bits 0x06 |
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| 385 | #define MGA1064_MUL_CTL_32_24bits 0x07 |
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| 386 | |
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| 387 | #define MGA1064_PIX_CLK_CTL 0x1a |
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| 388 | #define MGA1064_PIX_CLK_CTL_CLK_DIS ( 0x01 << 2 ) |
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| 389 | #define MGA1064_PIX_CLK_CTL_CLK_POW_DOWN ( 0x01 << 3 ) |
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| 390 | #define MGA1064_PIX_CLK_CTL_SEL_PCI ( 0x00 << 0 ) |
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| 391 | #define MGA1064_PIX_CLK_CTL_SEL_PLL ( 0x01 << 0 ) |
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| 392 | #define MGA1064_PIX_CLK_CTL_SEL_EXT ( 0x02 << 0 ) |
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| 393 | #define MGA1064_PIX_CLK_CTL_SEL_MSK ( 0x03 << 0 ) |
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| 394 | |
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| 395 | #define MGA1064_GEN_CTL 0x1d |
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| 396 | #define MGA1064_GEN_CTL_SYNC_ON_GREEN_DIS (0x01 << 5) |
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| 397 | #define MGA1064_MISC_CTL 0x1e |
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| 398 | #define MGA1064_MISC_CTL_DAC_EN ( 0x01 << 0 ) |
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| 399 | #define MGA1064_MISC_CTL_VGA ( 0x01 << 1 ) |
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| 400 | #define MGA1064_MISC_CTL_DIS_CON ( 0x03 << 1 ) |
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| 401 | #define MGA1064_MISC_CTL_MAFC ( 0x02 << 1 ) |
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| 402 | #define MGA1064_MISC_CTL_VGA8 ( 0x01 << 3 ) |
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| 403 | #define MGA1064_MISC_CTL_DAC_RAM_CS ( 0x01 << 4 ) |
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| 404 | |
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| 405 | #define MGA1064_GEN_IO_CTL2 0x29 |
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| 406 | #define MGA1064_GEN_IO_CTL 0x2a |
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| 407 | #define MGA1064_GEN_IO_DATA 0x2b |
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| 408 | #define MGA1064_SYS_PLL_M 0x2c |
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| 409 | #define MGA1064_SYS_PLL_N 0x2d |
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| 410 | #define MGA1064_SYS_PLL_P 0x2e |
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| 411 | #define MGA1064_SYS_PLL_STAT 0x2f |
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| 412 | |
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| 413 | #define MGA1064_REMHEADCTL 0x30 |
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| 414 | #define MGA1064_REMHEADCTL_CLKDIS ( 0x01 << 0 ) |
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| 415 | #define MGA1064_REMHEADCTL_CLKSL_OFF ( 0x00 << 1 ) |
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| 416 | #define MGA1064_REMHEADCTL_CLKSL_PLL ( 0x01 << 1 ) |
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| 417 | #define MGA1064_REMHEADCTL_CLKSL_PCI ( 0x02 << 1 ) |
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| 418 | #define MGA1064_REMHEADCTL_CLKSL_MSK ( 0x03 << 1 ) |
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| 419 | |
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| 420 | #define MGA1064_REMHEADCTL2 0x31 |
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| 421 | |
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| 422 | #define MGA1064_ZOOM_CTL 0x38 |
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| 423 | #define MGA1064_SENSE_TST 0x3a |
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| 424 | |
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| 425 | #define MGA1064_CRC_LSB 0x3c |
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| 426 | #define MGA1064_CRC_MSB 0x3d |
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| 427 | #define MGA1064_CRC_CTL 0x3e |
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| 428 | #define MGA1064_COL_KEY_MSK_LSB 0x40 |
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| 429 | #define MGA1064_COL_KEY_MSK_MSB 0x41 |
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| 430 | #define MGA1064_COL_KEY_LSB 0x42 |
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| 431 | #define MGA1064_COL_KEY_MSB 0x43 |
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| 432 | #define MGA1064_PIX_PLLA_M 0x44 |
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| 433 | #define MGA1064_PIX_PLLA_N 0x45 |
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| 434 | #define MGA1064_PIX_PLLA_P 0x46 |
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| 435 | #define MGA1064_PIX_PLLB_M 0x48 |
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| 436 | #define MGA1064_PIX_PLLB_N 0x49 |
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| 437 | #define MGA1064_PIX_PLLB_P 0x4a |
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| 438 | #define MGA1064_PIX_PLLC_M 0x4c |
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| 439 | #define MGA1064_PIX_PLLC_N 0x4d |
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| 440 | #define MGA1064_PIX_PLLC_P 0x4e |
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| 441 | |
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| 442 | #define MGA1064_PIX_PLL_STAT 0x4f |
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| 443 | |
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| 444 | /*Added for G450 dual head*/ |
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| 445 | |
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| 446 | #define MGA1064_VID_PLL_STAT 0x8c |
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| 447 | #define MGA1064_VID_PLL_P 0x8D |
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| 448 | #define MGA1064_VID_PLL_M 0x8E |
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| 449 | #define MGA1064_VID_PLL_N 0x8F |
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| 450 | |
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| 451 | /* Modified PLL for G200 Winbond (G200WB) */ |
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| 452 | #define MGA1064_WB_PIX_PLLC_M 0xb7 |
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| 453 | #define MGA1064_WB_PIX_PLLC_N 0xb6 |
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| 454 | #define MGA1064_WB_PIX_PLLC_P 0xb8 |
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| 455 | |
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| 456 | /* Modified PLL for G200 Maxim (G200EV) */ |
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| 457 | #define MGA1064_EV_PIX_PLLC_M 0xb6 |
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| 458 | #define MGA1064_EV_PIX_PLLC_N 0xb7 |
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| 459 | #define MGA1064_EV_PIX_PLLC_P 0xb8 |
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| 460 | |
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| 461 | /* Modified PLL for G200 EH */ |
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| 462 | #define MGA1064_EH_PIX_PLLC_M 0xb6 |
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| 463 | #define MGA1064_EH_PIX_PLLC_N 0xb7 |
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| 464 | #define MGA1064_EH_PIX_PLLC_P 0xb8 |
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| 465 | |
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| 466 | /* Modified PLL for G200 Maxim (G200ER) */ |
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| 467 | #define MGA1064_ER_PIX_PLLC_M 0xb7 |
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| 468 | #define MGA1064_ER_PIX_PLLC_N 0xb6 |
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| 469 | #define MGA1064_ER_PIX_PLLC_P 0xb8 |
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| 470 | |
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| 471 | #define MGA1064_DISP_CTL 0x8a |
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| 472 | #define MGA1064_DISP_CTL_DAC1OUTSEL_MASK 0x01 |
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| 473 | #define MGA1064_DISP_CTL_DAC1OUTSEL_DIS 0x00 |
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| 474 | #define MGA1064_DISP_CTL_DAC1OUTSEL_EN 0x01 |
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| 475 | #define MGA1064_DISP_CTL_DAC2OUTSEL_MASK (0x03 << 2) |
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| 476 | #define MGA1064_DISP_CTL_DAC2OUTSEL_DIS 0x00 |
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| 477 | #define MGA1064_DISP_CTL_DAC2OUTSEL_CRTC1 (0x01 << 2) |
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| 478 | #define MGA1064_DISP_CTL_DAC2OUTSEL_CRTC2 (0x02 << 2) |
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| 479 | #define MGA1064_DISP_CTL_DAC2OUTSEL_TVE (0x03 << 2) |
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| 480 | #define MGA1064_DISP_CTL_PANOUTSEL_MASK (0x03 << 5) |
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| 481 | #define MGA1064_DISP_CTL_PANOUTSEL_DIS 0x00 |
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| 482 | #define MGA1064_DISP_CTL_PANOUTSEL_CRTC1 (0x01 << 5) |
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| 483 | #define MGA1064_DISP_CTL_PANOUTSEL_CRTC2RGB (0x02 << 5) |
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| 484 | #define MGA1064_DISP_CTL_PANOUTSEL_CRTC2656 (0x03 << 5) |
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| 485 | |
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| 486 | #define MGA1064_SYNC_CTL 0x8b |
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| 487 | |
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| 488 | #define MGA1064_PWR_CTL 0xa0 |
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| 489 | #define MGA1064_PWR_CTL_DAC2_EN (0x01 << 0) |
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| 490 | #define MGA1064_PWR_CTL_VID_PLL_EN (0x01 << 1) |
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| 491 | #define MGA1064_PWR_CTL_PANEL_EN (0x01 << 2) |
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| 492 | #define MGA1064_PWR_CTL_RFIFO_EN (0x01 << 3) |
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| 493 | #define MGA1064_PWR_CTL_CFIFO_EN (0x01 << 4) |
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| 494 | |
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| 495 | #define MGA1064_PAN_CTL 0xa2 |
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| 496 | |
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| 497 | /* Using crtc2 */ |
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| 498 | #define MGAREG2_C2CTL 0x10 |
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| 499 | #define MGAREG2_C2HPARAM 0x14 |
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| 500 | #define MGAREG2_C2HSYNC 0x18 |
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| 501 | #define MGAREG2_C2VPARAM 0x1c |
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| 502 | #define MGAREG2_C2VSYNC 0x20 |
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| 503 | #define MGAREG2_C2STARTADD0 0x28 |
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| 504 | |
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| 505 | #define MGAREG2_C2OFFSET 0x40 |
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| 506 | #define MGAREG2_C2DATACTL 0x4c |
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| 507 | |
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| 508 | #define MGAREG_C2CTL 0x3c10 |
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| 509 | #define MGAREG_C2CTL_C2_EN 0x01 |
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| 510 | |
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| 511 | #define MGAREG_C2_HIPRILVL_M (0x07 << 4) |
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| 512 | #define MGAREG_C2_MAXHIPRI_M (0x07 << 8) |
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| 513 | |
|---|
| 514 | #define MGAREG_C2CTL_PIXCLKSEL_MASK (0x03 << 1) |
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| 515 | #define MGAREG_C2CTL_PIXCLKSELH_MASK (0x01 << 14) |
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| 516 | #define MGAREG_C2CTL_PIXCLKSEL_PCICLK 0x00 |
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| 517 | #define MGAREG_C2CTL_PIXCLKSEL_VDOCLK (0x01 << 1) |
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| 518 | #define MGAREG_C2CTL_PIXCLKSEL_PIXELPLL (0x02 << 1) |
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| 519 | #define MGAREG_C2CTL_PIXCLKSEL_VIDEOPLL (0x03 << 1) |
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| 520 | #define MGAREG_C2CTL_PIXCLKSEL_VDCLK (0x01 << 14) |
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| 521 | |
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| 522 | #define MGAREG_C2CTL_PIXCLKSEL_CRISTAL (0x01 << 1) | (0x01 << 14) |
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| 523 | #define MGAREG_C2CTL_PIXCLKSEL_SYSTEMPLL (0x02 << 1) | (0x01 << 14) |
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| 524 | |
|---|
| 525 | #define MGAREG_C2CTL_PIXCLKDIS_MASK (0x01 << 3) |
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| 526 | #define MGAREG_C2CTL_PIXCLKDIS_DISABLE (0x01 << 3) |
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| 527 | |
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| 528 | #define MGAREG_C2CTL_CRTCDACSEL_MASK (0x01 << 20) |
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| 529 | #define MGAREG_C2CTL_CRTCDACSEL_CRTC1 0x00 |
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| 530 | #define MGAREG_C2CTL_CRTCDACSEL_CRTC2 (0x01 << 20) |
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| 531 | |
|---|
| 532 | #define MGAREG_C2HPARAM 0x3c14 |
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| 533 | #define MGAREG_C2HSYNC 0x3c18 |
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| 534 | #define MGAREG_C2VPARAM 0x3c1c |
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| 535 | #define MGAREG_C2VSYNC 0x3c20 |
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| 536 | #define MGAREG_C2STARTADD0 0x3c28 |
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| 537 | |
|---|
| 538 | #define MGAREG_C2OFFSET 0x3c40 |
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| 539 | #define MGAREG_C2DATACTL 0x3c4c |
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| 540 | |
|---|
| 541 | /* video register */ |
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| 542 | |
|---|
| 543 | #define MGAREG_BESA1C3ORG 0x3d60 |
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| 544 | #define MGAREG_BESA1CORG 0x3d10 |
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| 545 | #define MGAREG_BESA1ORG 0x3d00 |
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| 546 | #define MGAREG_BESCTL 0x3d20 |
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| 547 | #define MGAREG_BESGLOBCTL 0x3dc0 |
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| 548 | #define MGAREG_BESHCOORD 0x3d28 |
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| 549 | #define MGAREG_BESHISCAL 0x3d30 |
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| 550 | #define MGAREG_BESHSRCEND 0x3d3c |
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| 551 | #define MGAREG_BESHSRCLST 0x3d50 |
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| 552 | #define MGAREG_BESHSRCST 0x3d38 |
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| 553 | #define MGAREG_BESLUMACTL 0x3d40 |
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| 554 | #define MGAREG_BESPITCH 0x3d24 |
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| 555 | #define MGAREG_BESV1SRCLST 0x3d54 |
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| 556 | #define MGAREG_BESV1WGHT 0x3d48 |
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| 557 | #define MGAREG_BESVCOORD 0x3d2c |
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| 558 | #define MGAREG_BESVISCAL 0x3d34 |
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| 559 | |
|---|
| 560 | /* texture engine registers */ |
|---|
| 561 | |
|---|
| 562 | #define MGAREG_TMR0 0x2c00 |
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| 563 | #define MGAREG_TMR1 0x2c04 |
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| 564 | #define MGAREG_TMR2 0x2c08 |
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| 565 | #define MGAREG_TMR3 0x2c0c |
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| 566 | #define MGAREG_TMR4 0x2c10 |
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| 567 | #define MGAREG_TMR5 0x2c14 |
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| 568 | #define MGAREG_TMR6 0x2c18 |
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| 569 | #define MGAREG_TMR7 0x2c1c |
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| 570 | #define MGAREG_TMR8 0x2c20 |
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| 571 | #define MGAREG_TEXORG 0x2c24 |
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| 572 | #define MGAREG_TEXWIDTH 0x2c28 |
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| 573 | #define MGAREG_TEXHEIGHT 0x2c2c |
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| 574 | #define MGAREG_TEXCTL 0x2c30 |
|---|
| 575 | # define MGA_TW4 (0x00000000) |
|---|
| 576 | # define MGA_TW8 (0x00000001) |
|---|
| 577 | # define MGA_TW15 (0x00000002) |
|---|
| 578 | # define MGA_TW16 (0x00000003) |
|---|
| 579 | # define MGA_TW12 (0x00000004) |
|---|
| 580 | # define MGA_TW32 (0x00000006) |
|---|
| 581 | # define MGA_TW8A (0x00000007) |
|---|
| 582 | # define MGA_TW8AL (0x00000008) |
|---|
| 583 | # define MGA_TW422 (0x0000000A) |
|---|
| 584 | # define MGA_TW422UYVY (0x0000000B) |
|---|
| 585 | # define MGA_PITCHLIN (0x00000100) |
|---|
| 586 | # define MGA_NOPERSPECTIVE (0x00200000) |
|---|
| 587 | # define MGA_TAKEY (0x02000000) |
|---|
| 588 | # define MGA_TAMASK (0x04000000) |
|---|
| 589 | # define MGA_CLAMPUV (0x18000000) |
|---|
| 590 | # define MGA_TEXMODULATE (0x20000000) |
|---|
| 591 | #define MGAREG_TEXCTL2 0x2c3c |
|---|
| 592 | # define MGA_G400_TC2_MAGIC (0x00008000) |
|---|
| 593 | # define MGA_TC2_DECALBLEND (0x00000001) |
|---|
| 594 | # define MGA_TC2_IDECAL (0x00000002) |
|---|
| 595 | # define MGA_TC2_DECALDIS (0x00000004) |
|---|
| 596 | # define MGA_TC2_CKSTRANSDIS (0x00000010) |
|---|
| 597 | # define MGA_TC2_BORDEREN (0x00000020) |
|---|
| 598 | # define MGA_TC2_SPECEN (0x00000040) |
|---|
| 599 | # define MGA_TC2_DUALTEX (0x00000080) |
|---|
| 600 | # define MGA_TC2_TABLEFOG (0x00000100) |
|---|
| 601 | # define MGA_TC2_BUMPMAP (0x00000200) |
|---|
| 602 | # define MGA_TC2_SELECT_TMU1 (0x80000000) |
|---|
| 603 | #define 0x2c34 |
|---|
| 604 | #define 0x2c38 |
|---|
| 605 | #define MGAREG_TEXFILTER 0x2c58 |
|---|
| 606 | # define MGA_MIN_NRST (0x00000000) |
|---|
| 607 | # define MGA_MIN_BILIN (0x00000002) |
|---|
| 608 | # define MGA_MIN_ANISO (0x0000000D) |
|---|
| 609 | # define MGA_MAG_NRST (0x00000000) |
|---|
| 610 | # define MGA_MAG_BILIN (0x00000020) |
|---|
| 611 | # define MGA_FILTERALPHA (0x00100000) |
|---|
| 612 | #define MGAREG_ALPHASTART 0x2c70 |
|---|
| 613 | #define MGAREG_ALPHAXINC 0x2c74 |
|---|
| 614 | #define MGAREG_ALPHAYINC 0x2c78 |
|---|
| 615 | #define MGAREG_ALPHACTRL 0x2c7c |
|---|
| 616 | # define MGA_SRC_ZERO (0x00000000) |
|---|
| 617 | # define MGA_SRC_ONE (0x00000001) |
|---|
| 618 | # define MGA_SRC_DST_COLOR (0x00000002) |
|---|
| 619 | # define MGA_SRC_ONE_MINUS_DST_COLOR (0x00000003) |
|---|
| 620 | # define MGA_SRC_ALPHA (0x00000004) |
|---|
| 621 | # define MGA_SRC_ONE_MINUS_SRC_ALPHA (0x00000005) |
|---|
| 622 | # define MGA_SRC_DST_ALPHA (0x00000006) |
|---|
| 623 | # define MGA_SRC_ONE_MINUS_DST_ALPHA (0x00000007) |
|---|
| 624 | # define MGA_SRC_SRC_ALPHA_SATURATE (0x00000008) |
|---|
| 625 | # define MGA_SRC_BLEND_MASK (0x0000000f) |
|---|
| 626 | # define MGA_DST_ZERO (0x00000000) |
|---|
| 627 | # define MGA_DST_ONE (0x00000010) |
|---|
| 628 | # define MGA_DST_SRC_COLOR (0x00000020) |
|---|
| 629 | # define MGA_DST_ONE_MINUS_SRC_COLOR (0x00000030) |
|---|
| 630 | # define MGA_DST_SRC_ALPHA (0x00000040) |
|---|
| 631 | # define MGA_DST_ONE_MINUS_SRC_ALPHA (0x00000050) |
|---|
| 632 | # define MGA_DST_DST_ALPHA (0x00000060) |
|---|
| 633 | # define MGA_DST_ONE_MINUS_DST_ALPHA (0x00000070) |
|---|
| 634 | # define MGA_DST_BLEND_MASK (0x00000070) |
|---|
| 635 | # define MGA_ALPHACHANNEL (0x00000100) |
|---|
| 636 | # define MGA_VIDEOALPHA (0x00000200) |
|---|
| 637 | # define MGA_DIFFUSEDALPHA (0x01000000) |
|---|
| 638 | # define MGA_MODULATEDALPHA (0x02000000) |
|---|
| 639 | #define MGAREG_TDUALSTAGE0 (0x2CF8) |
|---|
| 640 | #define MGAREG_TDUALSTAGE1 (0x2CFC) |
|---|
| 641 | # define MGA_TDS_COLOR_ARG2_DIFFUSE (0x00000000) |
|---|
| 642 | # define MGA_TDS_COLOR_ARG2_SPECULAR (0x00000001) |
|---|
| 643 | # define MGA_TDS_COLOR_ARG2_FCOL (0x00000002) |
|---|
| 644 | # define MGA_TDS_COLOR_ARG2_PREVSTAGE (0x00000003) |
|---|
| 645 | # define MGA_TDS_COLOR_ALPHA_DIFFUSE (0x00000000) |
|---|
| 646 | # define MGA_TDS_COLOR_ALPHA_FCOL (0x00000004) |
|---|
| 647 | # define MGA_TDS_COLOR_ALPHA_CURRTEX (0x00000008) |
|---|
| 648 | # define MGA_TDS_COLOR_ALPHA_PREVTEX (0x0000000c) |
|---|
| 649 | # define MGA_TDS_COLOR_ALPHA_PREVSTAGE (0x00000010) |
|---|
| 650 | # define MGA_TDS_COLOR_ARG1_REPLICATEALPHA (0x00000020) |
|---|
| 651 | # define MGA_TDS_COLOR_ARG1_INV (0x00000040) |
|---|
| 652 | # define MGA_TDS_COLOR_ARG2_REPLICATEALPHA (0x00000080) |
|---|
| 653 | # define MGA_TDS_COLOR_ARG2_INV (0x00000100) |
|---|
| 654 | # define MGA_TDS_COLOR_ALPHA1INV (0x00000200) |
|---|
| 655 | # define MGA_TDS_COLOR_ALPHA2INV (0x00000400) |
|---|
| 656 | # define MGA_TDS_COLOR_ARG1MUL_ALPHA1 (0x00000800) |
|---|
| 657 | # define MGA_TDS_COLOR_ARG2MUL_ALPHA2 (0x00001000) |
|---|
| 658 | # define MGA_TDS_COLOR_ARG1ADD_MULOUT (0x00002000) |
|---|
| 659 | # define MGA_TDS_COLOR_ARG2ADD_MULOUT (0x00004000) |
|---|
| 660 | # define MGA_TDS_COLOR_MODBRIGHT_2X (0x00008000) |
|---|
| 661 | # define MGA_TDS_COLOR_MODBRIGHT_4X (0x00010000) |
|---|
| 662 | # define MGA_TDS_COLOR_ADD_SUB (0x00000000) |
|---|
| 663 | # define MGA_TDS_COLOR_ADD_ADD (0x00020000) |
|---|
| 664 | # define MGA_TDS_COLOR_ADD2X (0x00040000) |
|---|
| 665 | # define MGA_TDS_COLOR_ADDBIAS (0x00080000) |
|---|
| 666 | # define MGA_TDS_COLOR_BLEND (0x00100000) |
|---|
| 667 | # define MGA_TDS_COLOR_SEL_ARG1 (0x00000000) |
|---|
| 668 | # define MGA_TDS_COLOR_SEL_ARG2 (0x00200000) |
|---|
| 669 | # define MGA_TDS_COLOR_SEL_ADD (0x00400000) |
|---|
| 670 | # define MGA_TDS_COLOR_SEL_MUL (0x00600000) |
|---|
| 671 | # define MGA_TDS_ALPHA_ARG1_INV (0x00800000) |
|---|
| 672 | # define MGA_TDS_ALPHA_ARG2_DIFFUSE (0x00000000) |
|---|
| 673 | # define MGA_TDS_ALPHA_ARG2_FCOL (0x01000000) |
|---|
| 674 | # define MGA_TDS_ALPHA_ARG2_PREVTEX (0x02000000) |
|---|
| 675 | # define MGA_TDS_ALPHA_ARG2_PREVSTAGE (0x03000000) |
|---|
| 676 | # define MGA_TDS_ALPHA_ARG2_INV (0x04000000) |
|---|
| 677 | # define MGA_TDS_ALPHA_ADD (0x08000000) |
|---|
| 678 | # define MGA_TDS_ALPHA_ADDBIAS (0x10000000) |
|---|
| 679 | # define MGA_TDS_ALPHA_ADD2X (0x20000000) |
|---|
| 680 | # define MGA_TDS_ALPHA_SEL_ARG1 (0x00000000) |
|---|
| 681 | # define MGA_TDS_ALPHA_SEL_ARG2 (0x40000000) |
|---|
| 682 | # define MGA_TDS_ALPHA_SEL_ADD (0x80000000) |
|---|
| 683 | # define MGA_TDS_ALPHA_SEL_MUL (0xc0000000) |
|---|
| 684 | |
|---|
| 685 | #define MGAREG_DWGSYNC 0x2c4c |
|---|
| 686 | |
|---|
| 687 | #define MGAREG_AGP_PLL 0x1e4c |
|---|
| 688 | #define MGA_AGP2XPLL_ENABLE 0x1 |
|---|
| 689 | #define MGA_AGP2XPLL_DISABLE 0x0 |
|---|
| 690 | |
|---|
| 691 | #endif |
|---|
| 692 | |
|---|
