1 | #ifndef A3XX_XML |
2 | #define A3XX_XML |
3 | |
4 | /* Autogenerated file, DO NOT EDIT manually! |
5 | |
6 | This file was generated by the rules-ng-ng gen_header.py tool in this git repository: |
7 | http://gitlab.freedesktop.org/mesa/mesa/ |
8 | git clone https://gitlab.freedesktop.org/mesa/mesa.git |
9 | |
10 | The rules-ng-ng source files this header was generated from are: |
11 | |
12 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84323 bytes, from Wed Aug 23 10:39:39 2023) |
13 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023) |
14 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023) |
15 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85691 bytes, from Fri Feb 16 09:49:01 2024) |
16 | |
17 | Copyright (C) 2013-2024 by the following authors: |
18 | - Rob Clark <robdclark@gmail.com> Rob Clark |
19 | - Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin |
20 | |
21 | Permission is hereby granted, free of charge, to any person obtaining |
22 | a copy of this software and associated documentation files (the |
23 | "Software"), to deal in the Software without restriction, including |
24 | without limitation the rights to use, copy, modify, merge, publish, |
25 | distribute, sublicense, and/or sell copies of the Software, and to |
26 | permit persons to whom the Software is furnished to do so, subject to |
27 | the following conditions: |
28 | |
29 | The above copyright notice and this permission notice (including the |
30 | next paragraph) shall be included in all copies or substantial |
31 | portions of the Software. |
32 | |
33 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
34 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
35 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
36 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
37 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
38 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
39 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
40 | |
41 | */ |
42 | |
43 | #ifdef __KERNEL__ |
44 | #include <linux/bug.h> |
45 | #define assert(x) BUG_ON(!(x)) |
46 | #else |
47 | #include <assert.h> |
48 | #endif |
49 | |
50 | #ifdef __cplusplus |
51 | #define __struct_cast(X) |
52 | #else |
53 | #define __struct_cast(X) (struct X) |
54 | #endif |
55 | |
56 | enum a3xx_tile_mode { |
57 | LINEAR = 0, |
58 | TILE_4X4 = 1, |
59 | TILE_32X32 = 2, |
60 | TILE_4X2 = 3, |
61 | }; |
62 | |
63 | enum a3xx_state_block_id { |
64 | HLSQ_BLOCK_ID_TP_TEX = 2, |
65 | HLSQ_BLOCK_ID_TP_MIPMAP = 3, |
66 | HLSQ_BLOCK_ID_SP_VS = 4, |
67 | HLSQ_BLOCK_ID_SP_FS = 6, |
68 | }; |
69 | |
70 | enum a3xx_cache_opcode { |
71 | INVALIDATE = 1, |
72 | }; |
73 | |
74 | enum a3xx_vtx_fmt { |
75 | VFMT_32_FLOAT = 0, |
76 | VFMT_32_32_FLOAT = 1, |
77 | VFMT_32_32_32_FLOAT = 2, |
78 | VFMT_32_32_32_32_FLOAT = 3, |
79 | VFMT_16_FLOAT = 4, |
80 | VFMT_16_16_FLOAT = 5, |
81 | VFMT_16_16_16_FLOAT = 6, |
82 | VFMT_16_16_16_16_FLOAT = 7, |
83 | VFMT_32_FIXED = 8, |
84 | VFMT_32_32_FIXED = 9, |
85 | VFMT_32_32_32_FIXED = 10, |
86 | VFMT_32_32_32_32_FIXED = 11, |
87 | VFMT_16_SINT = 16, |
88 | VFMT_16_16_SINT = 17, |
89 | VFMT_16_16_16_SINT = 18, |
90 | VFMT_16_16_16_16_SINT = 19, |
91 | VFMT_16_UINT = 20, |
92 | VFMT_16_16_UINT = 21, |
93 | VFMT_16_16_16_UINT = 22, |
94 | VFMT_16_16_16_16_UINT = 23, |
95 | VFMT_16_SNORM = 24, |
96 | VFMT_16_16_SNORM = 25, |
97 | VFMT_16_16_16_SNORM = 26, |
98 | VFMT_16_16_16_16_SNORM = 27, |
99 | VFMT_16_UNORM = 28, |
100 | VFMT_16_16_UNORM = 29, |
101 | VFMT_16_16_16_UNORM = 30, |
102 | VFMT_16_16_16_16_UNORM = 31, |
103 | VFMT_32_UINT = 32, |
104 | VFMT_32_32_UINT = 33, |
105 | VFMT_32_32_32_UINT = 34, |
106 | VFMT_32_32_32_32_UINT = 35, |
107 | VFMT_32_SINT = 36, |
108 | VFMT_32_32_SINT = 37, |
109 | VFMT_32_32_32_SINT = 38, |
110 | VFMT_32_32_32_32_SINT = 39, |
111 | VFMT_8_UINT = 40, |
112 | VFMT_8_8_UINT = 41, |
113 | VFMT_8_8_8_UINT = 42, |
114 | VFMT_8_8_8_8_UINT = 43, |
115 | VFMT_8_UNORM = 44, |
116 | VFMT_8_8_UNORM = 45, |
117 | VFMT_8_8_8_UNORM = 46, |
118 | VFMT_8_8_8_8_UNORM = 47, |
119 | VFMT_8_SINT = 48, |
120 | VFMT_8_8_SINT = 49, |
121 | VFMT_8_8_8_SINT = 50, |
122 | VFMT_8_8_8_8_SINT = 51, |
123 | VFMT_8_SNORM = 52, |
124 | VFMT_8_8_SNORM = 53, |
125 | VFMT_8_8_8_SNORM = 54, |
126 | VFMT_8_8_8_8_SNORM = 55, |
127 | VFMT_10_10_10_2_UINT = 56, |
128 | VFMT_10_10_10_2_UNORM = 57, |
129 | VFMT_10_10_10_2_SINT = 58, |
130 | VFMT_10_10_10_2_SNORM = 59, |
131 | VFMT_2_10_10_10_UINT = 60, |
132 | VFMT_2_10_10_10_UNORM = 61, |
133 | VFMT_2_10_10_10_SINT = 62, |
134 | VFMT_2_10_10_10_SNORM = 63, |
135 | VFMT_NONE = 255, |
136 | }; |
137 | |
138 | enum a3xx_tex_fmt { |
139 | TFMT_5_6_5_UNORM = 4, |
140 | TFMT_5_5_5_1_UNORM = 5, |
141 | TFMT_4_4_4_4_UNORM = 7, |
142 | TFMT_Z16_UNORM = 9, |
143 | TFMT_X8Z24_UNORM = 10, |
144 | TFMT_Z32_FLOAT = 11, |
145 | TFMT_UV_64X32 = 16, |
146 | TFMT_VU_64X32 = 17, |
147 | TFMT_Y_64X32 = 18, |
148 | TFMT_NV12_64X32 = 19, |
149 | TFMT_UV_LINEAR = 20, |
150 | TFMT_VU_LINEAR = 21, |
151 | TFMT_Y_LINEAR = 22, |
152 | TFMT_NV12_LINEAR = 23, |
153 | TFMT_I420_Y = 24, |
154 | TFMT_I420_U = 26, |
155 | TFMT_I420_V = 27, |
156 | TFMT_ATC_RGB = 32, |
157 | TFMT_ATC_RGBA_EXPLICIT = 33, |
158 | TFMT_ETC1 = 34, |
159 | TFMT_ATC_RGBA_INTERPOLATED = 35, |
160 | TFMT_DXT1 = 36, |
161 | TFMT_DXT3 = 37, |
162 | TFMT_DXT5 = 38, |
163 | TFMT_2_10_10_10_UNORM = 40, |
164 | TFMT_10_10_10_2_UNORM = 41, |
165 | TFMT_9_9_9_E5_FLOAT = 42, |
166 | TFMT_11_11_10_FLOAT = 43, |
167 | TFMT_A8_UNORM = 44, |
168 | TFMT_L8_UNORM = 45, |
169 | TFMT_L8_A8_UNORM = 47, |
170 | TFMT_8_UNORM = 48, |
171 | TFMT_8_8_UNORM = 49, |
172 | TFMT_8_8_8_UNORM = 50, |
173 | TFMT_8_8_8_8_UNORM = 51, |
174 | TFMT_8_SNORM = 52, |
175 | TFMT_8_8_SNORM = 53, |
176 | TFMT_8_8_8_SNORM = 54, |
177 | TFMT_8_8_8_8_SNORM = 55, |
178 | TFMT_8_UINT = 56, |
179 | TFMT_8_8_UINT = 57, |
180 | TFMT_8_8_8_UINT = 58, |
181 | TFMT_8_8_8_8_UINT = 59, |
182 | TFMT_8_SINT = 60, |
183 | TFMT_8_8_SINT = 61, |
184 | TFMT_8_8_8_SINT = 62, |
185 | TFMT_8_8_8_8_SINT = 63, |
186 | TFMT_16_FLOAT = 64, |
187 | TFMT_16_16_FLOAT = 65, |
188 | TFMT_16_16_16_16_FLOAT = 67, |
189 | TFMT_16_UINT = 68, |
190 | TFMT_16_16_UINT = 69, |
191 | TFMT_16_16_16_16_UINT = 71, |
192 | TFMT_16_SINT = 72, |
193 | TFMT_16_16_SINT = 73, |
194 | TFMT_16_16_16_16_SINT = 75, |
195 | TFMT_16_UNORM = 76, |
196 | TFMT_16_16_UNORM = 77, |
197 | TFMT_16_16_16_16_UNORM = 79, |
198 | TFMT_16_SNORM = 80, |
199 | TFMT_16_16_SNORM = 81, |
200 | TFMT_16_16_16_16_SNORM = 83, |
201 | TFMT_32_FLOAT = 84, |
202 | TFMT_32_32_FLOAT = 85, |
203 | TFMT_32_32_32_32_FLOAT = 87, |
204 | TFMT_32_UINT = 88, |
205 | TFMT_32_32_UINT = 89, |
206 | TFMT_32_32_32_32_UINT = 91, |
207 | TFMT_32_SINT = 92, |
208 | TFMT_32_32_SINT = 93, |
209 | TFMT_32_32_32_32_SINT = 95, |
210 | TFMT_2_10_10_10_UINT = 96, |
211 | TFMT_10_10_10_2_UINT = 97, |
212 | TFMT_ETC2_RG11_SNORM = 112, |
213 | TFMT_ETC2_RG11_UNORM = 113, |
214 | TFMT_ETC2_R11_SNORM = 114, |
215 | TFMT_ETC2_R11_UNORM = 115, |
216 | TFMT_ETC2_RGBA8 = 116, |
217 | TFMT_ETC2_RGB8A1 = 117, |
218 | TFMT_ETC2_RGB8 = 118, |
219 | TFMT_NONE = 255, |
220 | }; |
221 | |
222 | enum a3xx_color_fmt { |
223 | RB_R5G6B5_UNORM = 0, |
224 | RB_R5G5B5A1_UNORM = 1, |
225 | RB_R4G4B4A4_UNORM = 3, |
226 | RB_R8G8B8_UNORM = 4, |
227 | RB_R8G8B8A8_UNORM = 8, |
228 | RB_R8G8B8A8_SNORM = 9, |
229 | RB_R8G8B8A8_UINT = 10, |
230 | RB_R8G8B8A8_SINT = 11, |
231 | RB_R8G8_UNORM = 12, |
232 | RB_R8G8_SNORM = 13, |
233 | RB_R8G8_UINT = 14, |
234 | RB_R8G8_SINT = 15, |
235 | RB_R10G10B10A2_UNORM = 16, |
236 | RB_A2R10G10B10_UNORM = 17, |
237 | RB_R10G10B10A2_UINT = 18, |
238 | RB_A2R10G10B10_UINT = 19, |
239 | RB_A8_UNORM = 20, |
240 | RB_R8_UNORM = 21, |
241 | RB_R16_FLOAT = 24, |
242 | RB_R16G16_FLOAT = 25, |
243 | RB_R16G16B16A16_FLOAT = 27, |
244 | RB_R11G11B10_FLOAT = 28, |
245 | RB_R16_SNORM = 32, |
246 | RB_R16G16_SNORM = 33, |
247 | RB_R16G16B16A16_SNORM = 35, |
248 | RB_R16_UNORM = 36, |
249 | RB_R16G16_UNORM = 37, |
250 | RB_R16G16B16A16_UNORM = 39, |
251 | RB_R16_SINT = 40, |
252 | RB_R16G16_SINT = 41, |
253 | RB_R16G16B16A16_SINT = 43, |
254 | RB_R16_UINT = 44, |
255 | RB_R16G16_UINT = 45, |
256 | RB_R16G16B16A16_UINT = 47, |
257 | RB_R32_FLOAT = 48, |
258 | RB_R32G32_FLOAT = 49, |
259 | RB_R32G32B32A32_FLOAT = 51, |
260 | RB_R32_SINT = 52, |
261 | RB_R32G32_SINT = 53, |
262 | RB_R32G32B32A32_SINT = 55, |
263 | RB_R32_UINT = 56, |
264 | RB_R32G32_UINT = 57, |
265 | RB_R32G32B32A32_UINT = 59, |
266 | RB_NONE = 255, |
267 | }; |
268 | |
269 | enum a3xx_cp_perfcounter_select { |
270 | CP_ALWAYS_COUNT = 0, |
271 | CP_AHB_PFPTRANS_WAIT = 3, |
272 | CP_AHB_NRTTRANS_WAIT = 6, |
273 | CP_CSF_NRT_READ_WAIT = 8, |
274 | CP_CSF_I1_FIFO_FULL = 9, |
275 | CP_CSF_I2_FIFO_FULL = 10, |
276 | CP_CSF_ST_FIFO_FULL = 11, |
277 | CP_RESERVED_12 = 12, |
278 | CP_CSF_RING_ROQ_FULL = 13, |
279 | CP_CSF_I1_ROQ_FULL = 14, |
280 | CP_CSF_I2_ROQ_FULL = 15, |
281 | CP_CSF_ST_ROQ_FULL = 16, |
282 | CP_RESERVED_17 = 17, |
283 | CP_MIU_TAG_MEM_FULL = 18, |
284 | CP_MIU_NRT_WRITE_STALLED = 22, |
285 | CP_MIU_NRT_READ_STALLED = 23, |
286 | CP_ME_REGS_RB_DONE_FIFO_FULL = 26, |
287 | CP_ME_REGS_VS_EVENT_FIFO_FULL = 27, |
288 | CP_ME_REGS_PS_EVENT_FIFO_FULL = 28, |
289 | CP_ME_REGS_CF_EVENT_FIFO_FULL = 29, |
290 | CP_ME_MICRO_RB_STARVED = 30, |
291 | CP_AHB_RBBM_DWORD_SENT = 40, |
292 | CP_ME_BUSY_CLOCKS = 41, |
293 | CP_ME_WAIT_CONTEXT_AVAIL = 42, |
294 | CP_PFP_TYPE0_PACKET = 43, |
295 | CP_PFP_TYPE3_PACKET = 44, |
296 | CP_CSF_RB_WPTR_NEQ_RPTR = 45, |
297 | CP_CSF_I1_SIZE_NEQ_ZERO = 46, |
298 | CP_CSF_I2_SIZE_NEQ_ZERO = 47, |
299 | CP_CSF_RBI1I2_FETCHING = 48, |
300 | }; |
301 | |
302 | enum a3xx_gras_tse_perfcounter_select { |
303 | GRAS_TSEPERF_INPUT_PRIM = 0, |
304 | GRAS_TSEPERF_INPUT_NULL_PRIM = 1, |
305 | GRAS_TSEPERF_TRIVAL_REJ_PRIM = 2, |
306 | GRAS_TSEPERF_CLIPPED_PRIM = 3, |
307 | GRAS_TSEPERF_NEW_PRIM = 4, |
308 | GRAS_TSEPERF_ZERO_AREA_PRIM = 5, |
309 | GRAS_TSEPERF_FACENESS_CULLED_PRIM = 6, |
310 | GRAS_TSEPERF_ZERO_PIXEL_PRIM = 7, |
311 | GRAS_TSEPERF_OUTPUT_NULL_PRIM = 8, |
312 | GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM = 9, |
313 | GRAS_TSEPERF_PRE_CLIP_PRIM = 10, |
314 | GRAS_TSEPERF_POST_CLIP_PRIM = 11, |
315 | GRAS_TSEPERF_WORKING_CYCLES = 12, |
316 | GRAS_TSEPERF_PC_STARVE = 13, |
317 | GRAS_TSERASPERF_STALL = 14, |
318 | }; |
319 | |
320 | enum a3xx_gras_ras_perfcounter_select { |
321 | GRAS_RASPERF_16X16_TILES = 0, |
322 | GRAS_RASPERF_8X8_TILES = 1, |
323 | GRAS_RASPERF_4X4_TILES = 2, |
324 | GRAS_RASPERF_WORKING_CYCLES = 3, |
325 | GRAS_RASPERF_STALL_CYCLES_BY_RB = 4, |
326 | GRAS_RASPERF_STALL_CYCLES_BY_VSC = 5, |
327 | GRAS_RASPERF_STARVE_CYCLES_BY_TSE = 6, |
328 | }; |
329 | |
330 | enum a3xx_hlsq_perfcounter_select { |
331 | HLSQ_PERF_SP_VS_CONSTANT = 0, |
332 | HLSQ_PERF_SP_VS_INSTRUCTIONS = 1, |
333 | HLSQ_PERF_SP_FS_CONSTANT = 2, |
334 | HLSQ_PERF_SP_FS_INSTRUCTIONS = 3, |
335 | HLSQ_PERF_TP_STATE = 4, |
336 | HLSQ_PERF_QUADS = 5, |
337 | HLSQ_PERF_PIXELS = 6, |
338 | HLSQ_PERF_VERTICES = 7, |
339 | HLSQ_PERF_FS8_THREADS = 8, |
340 | HLSQ_PERF_FS16_THREADS = 9, |
341 | HLSQ_PERF_FS32_THREADS = 10, |
342 | HLSQ_PERF_VS8_THREADS = 11, |
343 | HLSQ_PERF_VS16_THREADS = 12, |
344 | HLSQ_PERF_SP_VS_DATA_BYTES = 13, |
345 | HLSQ_PERF_SP_FS_DATA_BYTES = 14, |
346 | HLSQ_PERF_ACTIVE_CYCLES = 15, |
347 | HLSQ_PERF_STALL_CYCLES_SP_STATE = 16, |
348 | HLSQ_PERF_STALL_CYCLES_SP_VS = 17, |
349 | HLSQ_PERF_STALL_CYCLES_SP_FS = 18, |
350 | HLSQ_PERF_STALL_CYCLES_UCHE = 19, |
351 | HLSQ_PERF_RBBM_LOAD_CYCLES = 20, |
352 | HLSQ_PERF_DI_TO_VS_START_SP0 = 21, |
353 | HLSQ_PERF_DI_TO_FS_START_SP0 = 22, |
354 | HLSQ_PERF_VS_START_TO_DONE_SP0 = 23, |
355 | HLSQ_PERF_FS_START_TO_DONE_SP0 = 24, |
356 | HLSQ_PERF_SP_STATE_COPY_CYCLES_VS = 25, |
357 | HLSQ_PERF_SP_STATE_COPY_CYCLES_FS = 26, |
358 | HLSQ_PERF_UCHE_LATENCY_CYCLES = 27, |
359 | HLSQ_PERF_UCHE_LATENCY_COUNT = 28, |
360 | }; |
361 | |
362 | enum a3xx_pc_perfcounter_select { |
363 | PC_PCPERF_VISIBILITY_STREAMS = 0, |
364 | PC_PCPERF_TOTAL_INSTANCES = 1, |
365 | PC_PCPERF_PRIMITIVES_PC_VPC = 2, |
366 | PC_PCPERF_PRIMITIVES_KILLED_BY_VS = 3, |
367 | PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS = 4, |
368 | PC_PCPERF_DRAWCALLS_KILLED_BY_VS = 5, |
369 | PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS = 6, |
370 | PC_PCPERF_VERTICES_TO_VFD = 7, |
371 | PC_PCPERF_REUSED_VERTICES = 8, |
372 | PC_PCPERF_CYCLES_STALLED_BY_VFD = 9, |
373 | PC_PCPERF_CYCLES_STALLED_BY_TSE = 10, |
374 | PC_PCPERF_CYCLES_STALLED_BY_VBIF = 11, |
375 | PC_PCPERF_CYCLES_IS_WORKING = 12, |
376 | }; |
377 | |
378 | enum a3xx_rb_perfcounter_select { |
379 | RB_RBPERF_ACTIVE_CYCLES_ANY = 0, |
380 | RB_RBPERF_ACTIVE_CYCLES_ALL = 1, |
381 | RB_RBPERF_STARVE_CYCLES_BY_SP = 2, |
382 | RB_RBPERF_STARVE_CYCLES_BY_RAS = 3, |
383 | RB_RBPERF_STARVE_CYCLES_BY_MARB = 4, |
384 | RB_RBPERF_STALL_CYCLES_BY_MARB = 5, |
385 | RB_RBPERF_STALL_CYCLES_BY_HLSQ = 6, |
386 | RB_RBPERF_RB_MARB_DATA = 7, |
387 | RB_RBPERF_SP_RB_QUAD = 8, |
388 | RB_RBPERF_RAS_EARLY_Z_QUADS = 9, |
389 | RB_RBPERF_GMEM_CH0_READ = 10, |
390 | RB_RBPERF_GMEM_CH1_READ = 11, |
391 | RB_RBPERF_GMEM_CH0_WRITE = 12, |
392 | RB_RBPERF_GMEM_CH1_WRITE = 13, |
393 | RB_RBPERF_CP_CONTEXT_DONE = 14, |
394 | RB_RBPERF_CP_CACHE_FLUSH = 15, |
395 | RB_RBPERF_CP_ZPASS_DONE = 16, |
396 | }; |
397 | |
398 | enum a3xx_rbbm_perfcounter_select { |
399 | RBBM_ALAWYS_ON = 0, |
400 | RBBM_VBIF_BUSY = 1, |
401 | RBBM_TSE_BUSY = 2, |
402 | RBBM_RAS_BUSY = 3, |
403 | RBBM_PC_DCALL_BUSY = 4, |
404 | RBBM_PC_VSD_BUSY = 5, |
405 | RBBM_VFD_BUSY = 6, |
406 | RBBM_VPC_BUSY = 7, |
407 | RBBM_UCHE_BUSY = 8, |
408 | RBBM_VSC_BUSY = 9, |
409 | RBBM_HLSQ_BUSY = 10, |
410 | RBBM_ANY_RB_BUSY = 11, |
411 | RBBM_ANY_TEX_BUSY = 12, |
412 | RBBM_ANY_USP_BUSY = 13, |
413 | RBBM_ANY_MARB_BUSY = 14, |
414 | RBBM_ANY_ARB_BUSY = 15, |
415 | RBBM_AHB_STATUS_BUSY = 16, |
416 | RBBM_AHB_STATUS_STALLED = 17, |
417 | RBBM_AHB_STATUS_TXFR = 18, |
418 | RBBM_AHB_STATUS_TXFR_SPLIT = 19, |
419 | RBBM_AHB_STATUS_TXFR_ERROR = 20, |
420 | RBBM_AHB_STATUS_LONG_STALL = 21, |
421 | RBBM_RBBM_STATUS_MASKED = 22, |
422 | }; |
423 | |
424 | enum a3xx_sp_perfcounter_select { |
425 | SP_LM_LOAD_INSTRUCTIONS = 0, |
426 | SP_LM_STORE_INSTRUCTIONS = 1, |
427 | SP_LM_ATOMICS = 2, |
428 | SP_UCHE_LOAD_INSTRUCTIONS = 3, |
429 | SP_UCHE_STORE_INSTRUCTIONS = 4, |
430 | SP_UCHE_ATOMICS = 5, |
431 | SP_VS_TEX_INSTRUCTIONS = 6, |
432 | SP_VS_CFLOW_INSTRUCTIONS = 7, |
433 | SP_VS_EFU_INSTRUCTIONS = 8, |
434 | SP_VS_FULL_ALU_INSTRUCTIONS = 9, |
435 | SP_VS_HALF_ALU_INSTRUCTIONS = 10, |
436 | SP_FS_TEX_INSTRUCTIONS = 11, |
437 | SP_FS_CFLOW_INSTRUCTIONS = 12, |
438 | SP_FS_EFU_INSTRUCTIONS = 13, |
439 | SP_FS_FULL_ALU_INSTRUCTIONS = 14, |
440 | SP_FS_HALF_ALU_INSTRUCTIONS = 15, |
441 | SP_FS_BARY_INSTRUCTIONS = 16, |
442 | SP_VS_INSTRUCTIONS = 17, |
443 | SP_FS_INSTRUCTIONS = 18, |
444 | SP_ADDR_LOCK_COUNT = 19, |
445 | SP_UCHE_READ_TRANS = 20, |
446 | SP_UCHE_WRITE_TRANS = 21, |
447 | SP_EXPORT_VPC_TRANS = 22, |
448 | SP_EXPORT_RB_TRANS = 23, |
449 | SP_PIXELS_KILLED = 24, |
450 | SP_ICL1_REQUESTS = 25, |
451 | SP_ICL1_MISSES = 26, |
452 | SP_ICL0_REQUESTS = 27, |
453 | SP_ICL0_MISSES = 28, |
454 | SP_ALU_ACTIVE_CYCLES = 29, |
455 | SP_EFU_ACTIVE_CYCLES = 30, |
456 | SP_STALL_CYCLES_BY_VPC = 31, |
457 | SP_STALL_CYCLES_BY_TP = 32, |
458 | SP_STALL_CYCLES_BY_UCHE = 33, |
459 | SP_STALL_CYCLES_BY_RB = 34, |
460 | SP_ACTIVE_CYCLES_ANY = 35, |
461 | SP_ACTIVE_CYCLES_ALL = 36, |
462 | }; |
463 | |
464 | enum a3xx_tp_perfcounter_select { |
465 | TPL1_TPPERF_L1_REQUESTS = 0, |
466 | TPL1_TPPERF_TP0_L1_REQUESTS = 1, |
467 | TPL1_TPPERF_TP0_L1_MISSES = 2, |
468 | TPL1_TPPERF_TP1_L1_REQUESTS = 3, |
469 | TPL1_TPPERF_TP1_L1_MISSES = 4, |
470 | TPL1_TPPERF_TP2_L1_REQUESTS = 5, |
471 | TPL1_TPPERF_TP2_L1_MISSES = 6, |
472 | TPL1_TPPERF_TP3_L1_REQUESTS = 7, |
473 | TPL1_TPPERF_TP3_L1_MISSES = 8, |
474 | TPL1_TPPERF_OUTPUT_TEXELS_POINT = 9, |
475 | TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR = 10, |
476 | TPL1_TPPERF_OUTPUT_TEXELS_MIP = 11, |
477 | TPL1_TPPERF_OUTPUT_TEXELS_ANISO = 12, |
478 | TPL1_TPPERF_BILINEAR_OPS = 13, |
479 | TPL1_TPPERF_QUADSQUADS_OFFSET = 14, |
480 | TPL1_TPPERF_QUADQUADS_SHADOW = 15, |
481 | TPL1_TPPERF_QUADS_ARRAY = 16, |
482 | TPL1_TPPERF_QUADS_PROJECTION = 17, |
483 | TPL1_TPPERF_QUADS_GRADIENT = 18, |
484 | TPL1_TPPERF_QUADS_1D2D = 19, |
485 | TPL1_TPPERF_QUADS_3DCUBE = 20, |
486 | TPL1_TPPERF_ZERO_LOD = 21, |
487 | TPL1_TPPERF_OUTPUT_TEXELS = 22, |
488 | TPL1_TPPERF_ACTIVE_CYCLES_ANY = 23, |
489 | TPL1_TPPERF_ACTIVE_CYCLES_ALL = 24, |
490 | TPL1_TPPERF_STALL_CYCLES_BY_ARB = 25, |
491 | TPL1_TPPERF_LATENCY = 26, |
492 | TPL1_TPPERF_LATENCY_TRANS = 27, |
493 | }; |
494 | |
495 | enum a3xx_vfd_perfcounter_select { |
496 | VFD_PERF_UCHE_BYTE_FETCHED = 0, |
497 | VFD_PERF_UCHE_TRANS = 1, |
498 | VFD_PERF_VPC_BYPASS_COMPONENTS = 2, |
499 | VFD_PERF_FETCH_INSTRUCTIONS = 3, |
500 | VFD_PERF_DECODE_INSTRUCTIONS = 4, |
501 | VFD_PERF_ACTIVE_CYCLES = 5, |
502 | VFD_PERF_STALL_CYCLES_UCHE = 6, |
503 | VFD_PERF_STALL_CYCLES_HLSQ = 7, |
504 | VFD_PERF_STALL_CYCLES_VPC_BYPASS = 8, |
505 | VFD_PERF_STALL_CYCLES_VPC_ALLOC = 9, |
506 | }; |
507 | |
508 | enum a3xx_vpc_perfcounter_select { |
509 | VPC_PERF_SP_LM_PRIMITIVES = 0, |
510 | VPC_PERF_COMPONENTS_FROM_SP = 1, |
511 | VPC_PERF_SP_LM_COMPONENTS = 2, |
512 | VPC_PERF_ACTIVE_CYCLES = 3, |
513 | VPC_PERF_STALL_CYCLES_LM = 4, |
514 | VPC_PERF_STALL_CYCLES_RAS = 5, |
515 | }; |
516 | |
517 | enum a3xx_uche_perfcounter_select { |
518 | UCHE_UCHEPERF_VBIF_READ_BEATS_TP = 0, |
519 | UCHE_UCHEPERF_VBIF_READ_BEATS_VFD = 1, |
520 | UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ = 2, |
521 | UCHE_UCHEPERF_VBIF_READ_BEATS_MARB = 3, |
522 | UCHE_UCHEPERF_VBIF_READ_BEATS_SP = 4, |
523 | UCHE_UCHEPERF_READ_REQUESTS_TP = 8, |
524 | UCHE_UCHEPERF_READ_REQUESTS_VFD = 9, |
525 | UCHE_UCHEPERF_READ_REQUESTS_HLSQ = 10, |
526 | UCHE_UCHEPERF_READ_REQUESTS_MARB = 11, |
527 | UCHE_UCHEPERF_READ_REQUESTS_SP = 12, |
528 | UCHE_UCHEPERF_WRITE_REQUESTS_MARB = 13, |
529 | UCHE_UCHEPERF_WRITE_REQUESTS_SP = 14, |
530 | UCHE_UCHEPERF_TAG_CHECK_FAILS = 15, |
531 | UCHE_UCHEPERF_EVICTS = 16, |
532 | UCHE_UCHEPERF_FLUSHES = 17, |
533 | UCHE_UCHEPERF_VBIF_LATENCY_CYCLES = 18, |
534 | UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES = 19, |
535 | UCHE_UCHEPERF_ACTIVE_CYCLES = 20, |
536 | }; |
537 | |
538 | enum a3xx_intp_mode { |
539 | SMOOTH = 0, |
540 | FLAT = 1, |
541 | ZERO = 2, |
542 | ONE = 3, |
543 | }; |
544 | |
545 | enum a3xx_repl_mode { |
546 | S = 1, |
547 | T = 2, |
548 | ONE_T = 3, |
549 | }; |
550 | |
551 | enum a3xx_tex_filter { |
552 | A3XX_TEX_NEAREST = 0, |
553 | A3XX_TEX_LINEAR = 1, |
554 | A3XX_TEX_ANISO = 2, |
555 | }; |
556 | |
557 | enum a3xx_tex_clamp { |
558 | A3XX_TEX_REPEAT = 0, |
559 | A3XX_TEX_CLAMP_TO_EDGE = 1, |
560 | A3XX_TEX_MIRROR_REPEAT = 2, |
561 | A3XX_TEX_CLAMP_TO_BORDER = 3, |
562 | A3XX_TEX_MIRROR_CLAMP = 4, |
563 | }; |
564 | |
565 | enum a3xx_tex_aniso { |
566 | A3XX_TEX_ANISO_1 = 0, |
567 | A3XX_TEX_ANISO_2 = 1, |
568 | A3XX_TEX_ANISO_4 = 2, |
569 | A3XX_TEX_ANISO_8 = 3, |
570 | A3XX_TEX_ANISO_16 = 4, |
571 | }; |
572 | |
573 | enum a3xx_tex_swiz { |
574 | A3XX_TEX_X = 0, |
575 | A3XX_TEX_Y = 1, |
576 | A3XX_TEX_Z = 2, |
577 | A3XX_TEX_W = 3, |
578 | A3XX_TEX_ZERO = 4, |
579 | A3XX_TEX_ONE = 5, |
580 | }; |
581 | |
582 | enum a3xx_tex_type { |
583 | A3XX_TEX_1D = 0, |
584 | A3XX_TEX_2D = 1, |
585 | A3XX_TEX_CUBE = 2, |
586 | A3XX_TEX_3D = 3, |
587 | }; |
588 | |
589 | enum a3xx_tex_msaa { |
590 | A3XX_TPL1_MSAA1X = 0, |
591 | A3XX_TPL1_MSAA2X = 1, |
592 | A3XX_TPL1_MSAA4X = 2, |
593 | A3XX_TPL1_MSAA8X = 3, |
594 | }; |
595 | |
596 | #define A3XX_INT0_RBBM_GPU_IDLE 0x00000001 |
597 | #define A3XX_INT0_RBBM_AHB_ERROR 0x00000002 |
598 | #define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004 |
599 | #define A3XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008 |
600 | #define A3XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010 |
601 | #define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020 |
602 | #define A3XX_INT0_VFD_ERROR 0x00000040 |
603 | #define A3XX_INT0_CP_SW_INT 0x00000080 |
604 | #define A3XX_INT0_CP_T0_PACKET_IN_IB 0x00000100 |
605 | #define A3XX_INT0_CP_OPCODE_ERROR 0x00000200 |
606 | #define A3XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400 |
607 | #define A3XX_INT0_CP_HW_FAULT 0x00000800 |
608 | #define A3XX_INT0_CP_DMA 0x00001000 |
609 | #define A3XX_INT0_CP_IB2_INT 0x00002000 |
610 | #define A3XX_INT0_CP_IB1_INT 0x00004000 |
611 | #define A3XX_INT0_CP_RB_INT 0x00008000 |
612 | #define A3XX_INT0_CP_REG_PROTECT_FAULT 0x00010000 |
613 | #define A3XX_INT0_CP_RB_DONE_TS 0x00020000 |
614 | #define A3XX_INT0_CP_VS_DONE_TS 0x00040000 |
615 | #define A3XX_INT0_CP_PS_DONE_TS 0x00080000 |
616 | #define A3XX_INT0_CACHE_FLUSH_TS 0x00100000 |
617 | #define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000 |
618 | #define A3XX_INT0_MISC_HANG_DETECT 0x01000000 |
619 | #define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000 |
620 | |
621 | #define REG_A3XX_RBBM_HW_VERSION 0x00000000 |
622 | |
623 | #define REG_A3XX_RBBM_HW_RELEASE 0x00000001 |
624 | |
625 | #define REG_A3XX_RBBM_HW_CONFIGURATION 0x00000002 |
626 | |
627 | #define REG_A3XX_RBBM_CLOCK_CTL 0x00000010 |
628 | |
629 | #define REG_A3XX_RBBM_SP_HYST_CNT 0x00000012 |
630 | |
631 | #define REG_A3XX_RBBM_SW_RESET_CMD 0x00000018 |
632 | |
633 | #define REG_A3XX_RBBM_AHB_CTL0 0x00000020 |
634 | |
635 | #define REG_A3XX_RBBM_AHB_CTL1 0x00000021 |
636 | |
637 | #define REG_A3XX_RBBM_AHB_CMD 0x00000022 |
638 | |
639 | #define REG_A3XX_RBBM_AHB_ERROR_STATUS 0x00000027 |
640 | |
641 | #define REG_A3XX_RBBM_GPR0_CTL 0x0000002e |
642 | |
643 | #define REG_A3XX_RBBM_STATUS 0x00000030 |
644 | #define A3XX_RBBM_STATUS_HI_BUSY 0x00000001 |
645 | #define A3XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 |
646 | #define A3XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 |
647 | #define A3XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000 |
648 | #define A3XX_RBBM_STATUS_VBIF_BUSY 0x00008000 |
649 | #define A3XX_RBBM_STATUS_TSE_BUSY 0x00010000 |
650 | #define A3XX_RBBM_STATUS_RAS_BUSY 0x00020000 |
651 | #define A3XX_RBBM_STATUS_RB_BUSY 0x00040000 |
652 | #define A3XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 |
653 | #define A3XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 |
654 | #define A3XX_RBBM_STATUS_VFD_BUSY 0x00200000 |
655 | #define A3XX_RBBM_STATUS_VPC_BUSY 0x00400000 |
656 | #define A3XX_RBBM_STATUS_UCHE_BUSY 0x00800000 |
657 | #define A3XX_RBBM_STATUS_SP_BUSY 0x01000000 |
658 | #define A3XX_RBBM_STATUS_TPL1_BUSY 0x02000000 |
659 | #define A3XX_RBBM_STATUS_MARB_BUSY 0x04000000 |
660 | #define A3XX_RBBM_STATUS_VSC_BUSY 0x08000000 |
661 | #define A3XX_RBBM_STATUS_ARB_BUSY 0x10000000 |
662 | #define A3XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 |
663 | #define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000 |
664 | #define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000 |
665 | |
666 | #define REG_A3XX_RBBM_NQWAIT_UNTIL 0x00000040 |
667 | |
668 | #define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033 |
669 | |
670 | #define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050 |
671 | |
672 | #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 0x00000051 |
673 | |
674 | #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 0x00000054 |
675 | |
676 | #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 0x00000057 |
677 | |
678 | #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a |
679 | |
680 | #define REG_A3XX_RBBM_INT_SET_CMD 0x00000060 |
681 | #define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061 |
682 | #define REG_A3XX_RBBM_INT_0_MASK 0x00000063 |
683 | #define REG_A3XX_RBBM_INT_0_STATUS 0x00000064 |
684 | #define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080 |
685 | #define A3XX_RBBM_PERFCTR_CTL_ENABLE 0x00000001 |
686 | |
687 | #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081 |
688 | |
689 | #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1 0x00000082 |
690 | |
691 | #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000084 |
692 | |
693 | #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000085 |
694 | |
695 | #define REG_A3XX_RBBM_PERFCOUNTER0_SELECT 0x00000086 |
696 | |
697 | #define REG_A3XX_RBBM_PERFCOUNTER1_SELECT 0x00000087 |
698 | |
699 | #define REG_A3XX_RBBM_GPU_BUSY_MASKED 0x00000088 |
700 | |
701 | #define REG_A3XX_RBBM_PERFCTR_CP_0_LO 0x00000090 |
702 | |
703 | #define REG_A3XX_RBBM_PERFCTR_CP_0_HI 0x00000091 |
704 | |
705 | #define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO 0x00000092 |
706 | |
707 | #define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI 0x00000093 |
708 | |
709 | #define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO 0x00000094 |
710 | |
711 | #define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI 0x00000095 |
712 | |
713 | #define REG_A3XX_RBBM_PERFCTR_PC_0_LO 0x00000096 |
714 | |
715 | #define REG_A3XX_RBBM_PERFCTR_PC_0_HI 0x00000097 |
716 | |
717 | #define REG_A3XX_RBBM_PERFCTR_PC_1_LO 0x00000098 |
718 | |
719 | #define REG_A3XX_RBBM_PERFCTR_PC_1_HI 0x00000099 |
720 | |
721 | #define REG_A3XX_RBBM_PERFCTR_PC_2_LO 0x0000009a |
722 | |
723 | #define REG_A3XX_RBBM_PERFCTR_PC_2_HI 0x0000009b |
724 | |
725 | #define REG_A3XX_RBBM_PERFCTR_PC_3_LO 0x0000009c |
726 | |
727 | #define REG_A3XX_RBBM_PERFCTR_PC_3_HI 0x0000009d |
728 | |
729 | #define REG_A3XX_RBBM_PERFCTR_VFD_0_LO 0x0000009e |
730 | |
731 | #define REG_A3XX_RBBM_PERFCTR_VFD_0_HI 0x0000009f |
732 | |
733 | #define REG_A3XX_RBBM_PERFCTR_VFD_1_LO 0x000000a0 |
734 | |
735 | #define REG_A3XX_RBBM_PERFCTR_VFD_1_HI 0x000000a1 |
736 | |
737 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000a2 |
738 | |
739 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000a3 |
740 | |
741 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000a4 |
742 | |
743 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000a5 |
744 | |
745 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000a6 |
746 | |
747 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000a7 |
748 | |
749 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000a8 |
750 | |
751 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000a9 |
752 | |
753 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000aa |
754 | |
755 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000ab |
756 | |
757 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000ac |
758 | |
759 | #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000ad |
760 | |
761 | #define REG_A3XX_RBBM_PERFCTR_VPC_0_LO 0x000000ae |
762 | |
763 | #define REG_A3XX_RBBM_PERFCTR_VPC_0_HI 0x000000af |
764 | |
765 | #define REG_A3XX_RBBM_PERFCTR_VPC_1_LO 0x000000b0 |
766 | |
767 | #define REG_A3XX_RBBM_PERFCTR_VPC_1_HI 0x000000b1 |
768 | |
769 | #define REG_A3XX_RBBM_PERFCTR_TSE_0_LO 0x000000b2 |
770 | |
771 | #define REG_A3XX_RBBM_PERFCTR_TSE_0_HI 0x000000b3 |
772 | |
773 | #define REG_A3XX_RBBM_PERFCTR_TSE_1_LO 0x000000b4 |
774 | |
775 | #define REG_A3XX_RBBM_PERFCTR_TSE_1_HI 0x000000b5 |
776 | |
777 | #define REG_A3XX_RBBM_PERFCTR_RAS_0_LO 0x000000b6 |
778 | |
779 | #define REG_A3XX_RBBM_PERFCTR_RAS_0_HI 0x000000b7 |
780 | |
781 | #define REG_A3XX_RBBM_PERFCTR_RAS_1_LO 0x000000b8 |
782 | |
783 | #define REG_A3XX_RBBM_PERFCTR_RAS_1_HI 0x000000b9 |
784 | |
785 | #define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO 0x000000ba |
786 | |
787 | #define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI 0x000000bb |
788 | |
789 | #define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO 0x000000bc |
790 | |
791 | #define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI 0x000000bd |
792 | |
793 | #define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO 0x000000be |
794 | |
795 | #define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI 0x000000bf |
796 | |
797 | #define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO 0x000000c0 |
798 | |
799 | #define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI 0x000000c1 |
800 | |
801 | #define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO 0x000000c2 |
802 | |
803 | #define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI 0x000000c3 |
804 | |
805 | #define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO 0x000000c4 |
806 | |
807 | #define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI 0x000000c5 |
808 | |
809 | #define REG_A3XX_RBBM_PERFCTR_TP_0_LO 0x000000c6 |
810 | |
811 | #define REG_A3XX_RBBM_PERFCTR_TP_0_HI 0x000000c7 |
812 | |
813 | #define REG_A3XX_RBBM_PERFCTR_TP_1_LO 0x000000c8 |
814 | |
815 | #define REG_A3XX_RBBM_PERFCTR_TP_1_HI 0x000000c9 |
816 | |
817 | #define REG_A3XX_RBBM_PERFCTR_TP_2_LO 0x000000ca |
818 | |
819 | #define REG_A3XX_RBBM_PERFCTR_TP_2_HI 0x000000cb |
820 | |
821 | #define REG_A3XX_RBBM_PERFCTR_TP_3_LO 0x000000cc |
822 | |
823 | #define REG_A3XX_RBBM_PERFCTR_TP_3_HI 0x000000cd |
824 | |
825 | #define REG_A3XX_RBBM_PERFCTR_TP_4_LO 0x000000ce |
826 | |
827 | #define REG_A3XX_RBBM_PERFCTR_TP_4_HI 0x000000cf |
828 | |
829 | #define REG_A3XX_RBBM_PERFCTR_TP_5_LO 0x000000d0 |
830 | |
831 | #define REG_A3XX_RBBM_PERFCTR_TP_5_HI 0x000000d1 |
832 | |
833 | #define REG_A3XX_RBBM_PERFCTR_SP_0_LO 0x000000d2 |
834 | |
835 | #define REG_A3XX_RBBM_PERFCTR_SP_0_HI 0x000000d3 |
836 | |
837 | #define REG_A3XX_RBBM_PERFCTR_SP_1_LO 0x000000d4 |
838 | |
839 | #define REG_A3XX_RBBM_PERFCTR_SP_1_HI 0x000000d5 |
840 | |
841 | #define REG_A3XX_RBBM_PERFCTR_SP_2_LO 0x000000d6 |
842 | |
843 | #define REG_A3XX_RBBM_PERFCTR_SP_2_HI 0x000000d7 |
844 | |
845 | #define REG_A3XX_RBBM_PERFCTR_SP_3_LO 0x000000d8 |
846 | |
847 | #define REG_A3XX_RBBM_PERFCTR_SP_3_HI 0x000000d9 |
848 | |
849 | #define REG_A3XX_RBBM_PERFCTR_SP_4_LO 0x000000da |
850 | |
851 | #define REG_A3XX_RBBM_PERFCTR_SP_4_HI 0x000000db |
852 | |
853 | #define REG_A3XX_RBBM_PERFCTR_SP_5_LO 0x000000dc |
854 | |
855 | #define REG_A3XX_RBBM_PERFCTR_SP_5_HI 0x000000dd |
856 | |
857 | #define REG_A3XX_RBBM_PERFCTR_SP_6_LO 0x000000de |
858 | |
859 | #define REG_A3XX_RBBM_PERFCTR_SP_6_HI 0x000000df |
860 | |
861 | #define REG_A3XX_RBBM_PERFCTR_SP_7_LO 0x000000e0 |
862 | |
863 | #define REG_A3XX_RBBM_PERFCTR_SP_7_HI 0x000000e1 |
864 | |
865 | #define REG_A3XX_RBBM_PERFCTR_RB_0_LO 0x000000e2 |
866 | |
867 | #define REG_A3XX_RBBM_PERFCTR_RB_0_HI 0x000000e3 |
868 | |
869 | #define REG_A3XX_RBBM_PERFCTR_RB_1_LO 0x000000e4 |
870 | |
871 | #define REG_A3XX_RBBM_PERFCTR_RB_1_HI 0x000000e5 |
872 | |
873 | #define REG_A3XX_RBBM_PERFCTR_PWR_0_LO 0x000000ea |
874 | |
875 | #define REG_A3XX_RBBM_PERFCTR_PWR_0_HI 0x000000eb |
876 | |
877 | #define REG_A3XX_RBBM_PERFCTR_PWR_1_LO 0x000000ec |
878 | |
879 | #define REG_A3XX_RBBM_PERFCTR_PWR_1_HI 0x000000ed |
880 | |
881 | #define REG_A3XX_RBBM_RBBM_CTL 0x00000100 |
882 | |
883 | #define REG_A3XX_RBBM_DEBUG_BUS_CTL 0x00000111 |
884 | |
885 | #define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS 0x00000112 |
886 | |
887 | #define REG_A3XX_CP_PFP_UCODE_ADDR 0x000001c9 |
888 | |
889 | #define REG_A3XX_CP_PFP_UCODE_DATA 0x000001ca |
890 | |
891 | #define REG_A3XX_CP_ROQ_ADDR 0x000001cc |
892 | |
893 | #define REG_A3XX_CP_ROQ_DATA 0x000001cd |
894 | |
895 | #define REG_A3XX_CP_MERCIU_ADDR 0x000001d1 |
896 | |
897 | #define REG_A3XX_CP_MERCIU_DATA 0x000001d2 |
898 | |
899 | #define REG_A3XX_CP_MERCIU_DATA2 0x000001d3 |
900 | |
901 | #define REG_A3XX_CP_MEQ_ADDR 0x000001da |
902 | |
903 | #define REG_A3XX_CP_MEQ_DATA 0x000001db |
904 | |
905 | #define REG_A3XX_CP_WFI_PEND_CTR 0x000001f5 |
906 | |
907 | #define REG_A3XX_RBBM_PM_OVERRIDE2 0x0000039d |
908 | |
909 | #define REG_A3XX_CP_PERFCOUNTER_SELECT 0x00000445 |
910 | |
911 | #define REG_A3XX_CP_HW_FAULT 0x0000045c |
912 | |
913 | #define REG_A3XX_CP_PROTECT_CTRL 0x0000045e |
914 | |
915 | #define REG_A3XX_CP_PROTECT_STATUS 0x0000045f |
916 | |
917 | #define REG_A3XX_CP_PROTECT(i0) (0x00000460 + 0x1*(i0)) |
918 | |
919 | static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } |
920 | |
921 | #define REG_A3XX_CP_AHB_FAULT 0x0000054d |
922 | |
923 | #define REG_A3XX_SQ_GPR_MANAGEMENT 0x00000d00 |
924 | |
925 | #define REG_A3XX_SQ_INST_STORE_MANAGMENT 0x00000d02 |
926 | |
927 | #define REG_A3XX_TP0_CHICKEN 0x00000e1e |
928 | |
929 | #define REG_A3XX_SP_GLOBAL_MEM_SIZE 0x00000e22 |
930 | |
931 | #define REG_A3XX_SP_GLOBAL_MEM_ADDR 0x00000e23 |
932 | |
933 | #define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040 |
934 | #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000 |
935 | #define A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTER 0x00002000 |
936 | #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTROID 0x00004000 |
937 | #define A3XX_GRAS_CL_CLIP_CNTL_IJ_NON_PERSP_CENTROID 0x00008000 |
938 | #define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 |
939 | #define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000 |
940 | #define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000 |
941 | #define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000 |
942 | #define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000 |
943 | #define A3XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000 |
944 | #define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD 0x00800000 |
945 | #define A3XX_GRAS_CL_CLIP_CNTL_WCOORD 0x01000000 |
946 | #define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE 0x02000000 |
947 | #define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK 0x1c000000 |
948 | #define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT 26 |
949 | static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val) |
950 | { |
951 | return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK; |
952 | } |
953 | |
954 | #define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044 |
955 | #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff |
956 | #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0 |
957 | static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val) |
958 | { |
959 | return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK; |
960 | } |
961 | #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00 |
962 | #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10 |
963 | static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val) |
964 | { |
965 | return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK; |
966 | } |
967 | |
968 | #define REG_A3XX_GRAS_CL_VPORT_XOFFSET 0x00002048 |
969 | #define A3XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff |
970 | #define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0 |
971 | static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val) |
972 | { |
973 | return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK; |
974 | } |
975 | |
976 | #define REG_A3XX_GRAS_CL_VPORT_XSCALE 0x00002049 |
977 | #define A3XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff |
978 | #define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT 0 |
979 | static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val) |
980 | { |
981 | return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK; |
982 | } |
983 | |
984 | #define REG_A3XX_GRAS_CL_VPORT_YOFFSET 0x0000204a |
985 | #define A3XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff |
986 | #define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0 |
987 | static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val) |
988 | { |
989 | return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK; |
990 | } |
991 | |
992 | #define REG_A3XX_GRAS_CL_VPORT_YSCALE 0x0000204b |
993 | #define A3XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff |
994 | #define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT 0 |
995 | static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val) |
996 | { |
997 | return ((fui(val)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_YSCALE__MASK; |
998 | } |
999 | |
1000 | #define REG_A3XX_GRAS_CL_VPORT_ZOFFSET 0x0000204c |
1001 | #define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff |
1002 | #define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0 |
1003 | static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val) |
1004 | { |
1005 | return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK; |
1006 | } |
1007 | |
1008 | #define REG_A3XX_GRAS_CL_VPORT_ZSCALE 0x0000204d |
1009 | #define A3XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff |
1010 | #define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0 |
1011 | static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val) |
1012 | { |
1013 | return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK; |
1014 | } |
1015 | |
1016 | #define REG_A3XX_GRAS_SU_POINT_MINMAX 0x00002068 |
1017 | #define A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff |
1018 | #define A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 |
1019 | static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val) |
1020 | { |
1021 | return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK; |
1022 | } |
1023 | #define A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 |
1024 | #define A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 |
1025 | static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val) |
1026 | { |
1027 | return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK; |
1028 | } |
1029 | |
1030 | #define REG_A3XX_GRAS_SU_POINT_SIZE 0x00002069 |
1031 | #define A3XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff |
1032 | #define A3XX_GRAS_SU_POINT_SIZE__SHIFT 0 |
1033 | static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val) |
1034 | { |
1035 | return ((((int32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT) & A3XX_GRAS_SU_POINT_SIZE__MASK; |
1036 | } |
1037 | |
1038 | #define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000206c |
1039 | #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK 0x00ffffff |
1040 | #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0 |
1041 | static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val) |
1042 | { |
1043 | return ((((int32_t)(val * 1048576.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK; |
1044 | } |
1045 | |
1046 | #define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d |
1047 | #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff |
1048 | #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 |
1049 | static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) |
1050 | { |
1051 | return ((((int32_t)(val * 64.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; |
1052 | } |
1053 | |
1054 | #define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070 |
1055 | #define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001 |
1056 | #define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002 |
1057 | #define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004 |
1058 | #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8 |
1059 | #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3 |
1060 | static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val) |
1061 | { |
1062 | return ((((int32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK; |
1063 | } |
1064 | #define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800 |
1065 | |
1066 | #define REG_A3XX_GRAS_SC_CONTROL 0x00002072 |
1067 | #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x000000f0 |
1068 | #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 4 |
1069 | static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val) |
1070 | { |
1071 | return ((val) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK; |
1072 | } |
1073 | #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000f00 |
1074 | #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 8 |
1075 | static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val) |
1076 | { |
1077 | return ((val) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK; |
1078 | } |
1079 | #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000 |
1080 | #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12 |
1081 | static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val) |
1082 | { |
1083 | return ((val) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK; |
1084 | } |
1085 | |
1086 | #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL 0x00002074 |
1087 | #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 |
1088 | #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff |
1089 | #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 |
1090 | static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) |
1091 | { |
1092 | return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; |
1093 | } |
1094 | #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 |
1095 | #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 |
1096 | static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) |
1097 | { |
1098 | return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; |
1099 | } |
1100 | |
1101 | #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR 0x00002075 |
1102 | #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 |
1103 | #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff |
1104 | #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 |
1105 | static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) |
1106 | { |
1107 | return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; |
1108 | } |
1109 | #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 |
1110 | #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 |
1111 | static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) |
1112 | { |
1113 | return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; |
1114 | } |
1115 | |
1116 | #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL 0x00002079 |
1117 | #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 |
1118 | #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff |
1119 | #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 |
1120 | static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) |
1121 | { |
1122 | return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; |
1123 | } |
1124 | #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 |
1125 | #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 |
1126 | static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) |
1127 | { |
1128 | return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; |
1129 | } |
1130 | |
1131 | #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000207a |
1132 | #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 |
1133 | #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff |
1134 | #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 |
1135 | static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) |
1136 | { |
1137 | return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; |
1138 | } |
1139 | #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 |
1140 | #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 |
1141 | static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) |
1142 | { |
1143 | return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; |
1144 | } |
1145 | |
1146 | #define REG_A3XX_RB_MODE_CONTROL 0x000020c0 |
1147 | #define A3XX_RB_MODE_CONTROL_GMEM_BYPASS 0x00000080 |
1148 | #define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK 0x00000700 |
1149 | #define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT 8 |
1150 | static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val) |
1151 | { |
1152 | return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK; |
1153 | } |
1154 | #define A3XX_RB_MODE_CONTROL_MRT__MASK 0x00003000 |
1155 | #define A3XX_RB_MODE_CONTROL_MRT__SHIFT 12 |
1156 | static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val) |
1157 | { |
1158 | return ((val) << A3XX_RB_MODE_CONTROL_MRT__SHIFT) & A3XX_RB_MODE_CONTROL_MRT__MASK; |
1159 | } |
1160 | #define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE 0x00008000 |
1161 | #define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000 |
1162 | |
1163 | #define REG_A3XX_RB_RENDER_CONTROL 0x000020c1 |
1164 | #define A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE 0x00000001 |
1165 | #define A3XX_RB_RENDER_CONTROL_YUV_IN_ENABLE 0x00000002 |
1166 | #define A3XX_RB_RENDER_CONTROL_COV_VALUE_INPUT_ENABLE 0x00000004 |
1167 | #define A3XX_RB_RENDER_CONTROL_FACENESS 0x00000008 |
1168 | #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0 |
1169 | #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4 |
1170 | static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) |
1171 | { |
1172 | assert(!(val & 0x1f)); |
1173 | return (((val >> 5)) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK; |
1174 | } |
1175 | #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000 |
1176 | #define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000 |
1177 | #define A3XX_RB_RENDER_CONTROL_COORD_MASK__MASK 0x0003c000 |
1178 | #define A3XX_RB_RENDER_CONTROL_COORD_MASK__SHIFT 14 |
1179 | static inline uint32_t A3XX_RB_RENDER_CONTROL_COORD_MASK(uint32_t val) |
1180 | { |
1181 | return ((val) << A3XX_RB_RENDER_CONTROL_COORD_MASK__SHIFT) & A3XX_RB_RENDER_CONTROL_COORD_MASK__MASK; |
1182 | } |
1183 | #define A3XX_RB_RENDER_CONTROL_I_CLAMP_ENABLE 0x00080000 |
1184 | #define A3XX_RB_RENDER_CONTROL_COV_VALUE_OUTPUT_ENABLE 0x00100000 |
1185 | #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000 |
1186 | #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000 |
1187 | #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24 |
1188 | static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) |
1189 | { |
1190 | return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK; |
1191 | } |
1192 | #define A3XX_RB_RENDER_CONTROL_ALPHA_TO_COVERAGE 0x40000000 |
1193 | #define A3XX_RB_RENDER_CONTROL_ALPHA_TO_ONE 0x80000000 |
1194 | |
1195 | #define REG_A3XX_RB_MSAA_CONTROL 0x000020c2 |
1196 | #define A3XX_RB_MSAA_CONTROL_DISABLE 0x00000400 |
1197 | #define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000f000 |
1198 | #define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 12 |
1199 | static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val) |
1200 | { |
1201 | return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK; |
1202 | } |
1203 | #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK 0xffff0000 |
1204 | #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT 16 |
1205 | static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val) |
1206 | { |
1207 | return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK; |
1208 | } |
1209 | |
1210 | #define REG_A3XX_RB_ALPHA_REF 0x000020c3 |
1211 | #define A3XX_RB_ALPHA_REF_UINT__MASK 0x0000ff00 |
1212 | #define A3XX_RB_ALPHA_REF_UINT__SHIFT 8 |
1213 | static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val) |
1214 | { |
1215 | return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK; |
1216 | } |
1217 | #define A3XX_RB_ALPHA_REF_FLOAT__MASK 0xffff0000 |
1218 | #define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16 |
1219 | static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val) |
1220 | { |
1221 | return ((_mesa_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK; |
1222 | } |
1223 | |
1224 | #define REG_A3XX_RB_MRT(i0) (0x000020c4 + 0x4*(i0)) |
1225 | |
1226 | static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } |
1227 | #define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 |
1228 | #define A3XX_RB_MRT_CONTROL_BLEND 0x00000010 |
1229 | #define A3XX_RB_MRT_CONTROL_BLEND2 0x00000020 |
1230 | #define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00 |
1231 | #define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8 |
1232 | static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) |
1233 | { |
1234 | return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK; |
1235 | } |
1236 | #define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK 0x00003000 |
1237 | #define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT 12 |
1238 | static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) |
1239 | { |
1240 | return ((val) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK; |
1241 | } |
1242 | #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000 |
1243 | #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24 |
1244 | static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) |
1245 | { |
1246 | return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; |
1247 | } |
1248 | |
1249 | static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; } |
1250 | #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f |
1251 | #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 |
1252 | static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val) |
1253 | { |
1254 | return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; |
1255 | } |
1256 | #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0 |
1257 | #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6 |
1258 | static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val) |
1259 | { |
1260 | return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; |
1261 | } |
1262 | #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00000c00 |
1263 | #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 10 |
1264 | static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) |
1265 | { |
1266 | return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; |
1267 | } |
1268 | #define A3XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00004000 |
1269 | #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xfffe0000 |
1270 | #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 17 |
1271 | static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) |
1272 | { |
1273 | assert(!(val & 0x1f)); |
1274 | return (((val >> 5)) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; |
1275 | } |
1276 | |
1277 | static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } |
1278 | #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK 0xfffffff0 |
1279 | #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4 |
1280 | static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) |
1281 | { |
1282 | assert(!(val & 0x1f)); |
1283 | return (((val >> 5)) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK; |
1284 | } |
1285 | |
1286 | static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } |
1287 | #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f |
1288 | #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 |
1289 | static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) |
1290 | { |
1291 | return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; |
1292 | } |
1293 | #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 |
1294 | #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 |
1295 | static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) |
1296 | { |
1297 | return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; |
1298 | } |
1299 | #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 |
1300 | #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 |
1301 | static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) |
1302 | { |
1303 | return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; |
1304 | } |
1305 | #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 |
1306 | #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 |
1307 | static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) |
1308 | { |
1309 | return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; |
1310 | } |
1311 | #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 |
1312 | #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 |
1313 | static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) |
1314 | { |
1315 | return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; |
1316 | } |
1317 | #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 |
1318 | #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 |
1319 | static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) |
1320 | { |
1321 | return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; |
1322 | } |
1323 | #define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE 0x20000000 |
1324 | |
1325 | #define REG_A3XX_RB_BLEND_RED 0x000020e4 |
1326 | #define A3XX_RB_BLEND_RED_UINT__MASK 0x000000ff |
1327 | #define A3XX_RB_BLEND_RED_UINT__SHIFT 0 |
1328 | static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val) |
1329 | { |
1330 | return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK; |
1331 | } |
1332 | #define A3XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000 |
1333 | #define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16 |
1334 | static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val) |
1335 | { |
1336 | return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK; |
1337 | } |
1338 | |
1339 | #define REG_A3XX_RB_BLEND_GREEN 0x000020e5 |
1340 | #define A3XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff |
1341 | #define A3XX_RB_BLEND_GREEN_UINT__SHIFT 0 |
1342 | static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val) |
1343 | { |
1344 | return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK; |
1345 | } |
1346 | #define A3XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000 |
1347 | #define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16 |
1348 | static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val) |
1349 | { |
1350 | return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK; |
1351 | } |
1352 | |
1353 | #define REG_A3XX_RB_BLEND_BLUE 0x000020e6 |
1354 | #define A3XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff |
1355 | #define A3XX_RB_BLEND_BLUE_UINT__SHIFT 0 |
1356 | static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val) |
1357 | { |
1358 | return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK; |
1359 | } |
1360 | #define A3XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000 |
1361 | #define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16 |
1362 | static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val) |
1363 | { |
1364 | return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK; |
1365 | } |
1366 | |
1367 | #define REG_A3XX_RB_BLEND_ALPHA 0x000020e7 |
1368 | #define A3XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff |
1369 | #define A3XX_RB_BLEND_ALPHA_UINT__SHIFT 0 |
1370 | static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val) |
1371 | { |
1372 | return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK; |
1373 | } |
1374 | #define A3XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000 |
1375 | #define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16 |
1376 | static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val) |
1377 | { |
1378 | return ((_mesa_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK; |
1379 | } |
1380 | |
1381 | #define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8 |
1382 | |
1383 | #define REG_A3XX_RB_CLEAR_COLOR_DW1 0x000020e9 |
1384 | |
1385 | #define REG_A3XX_RB_CLEAR_COLOR_DW2 0x000020ea |
1386 | |
1387 | #define REG_A3XX_RB_CLEAR_COLOR_DW3 0x000020eb |
1388 | |
1389 | #define REG_A3XX_RB_COPY_CONTROL 0x000020ec |
1390 | #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003 |
1391 | #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0 |
1392 | static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val) |
1393 | { |
1394 | return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; |
1395 | } |
1396 | #define A3XX_RB_COPY_CONTROL_DEPTHCLEAR 0x00000008 |
1397 | #define A3XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 |
1398 | #define A3XX_RB_COPY_CONTROL_MODE__SHIFT 4 |
1399 | static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) |
1400 | { |
1401 | return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK; |
1402 | } |
1403 | #define A3XX_RB_COPY_CONTROL_MSAA_SRGB_DOWNSAMPLE 0x00000080 |
1404 | #define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00 |
1405 | #define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8 |
1406 | static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) |
1407 | { |
1408 | return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK; |
1409 | } |
1410 | #define A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE 0x00001000 |
1411 | #define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000 |
1412 | #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 |
1413 | static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) |
1414 | { |
1415 | assert(!(val & 0x3fff)); |
1416 | return (((val >> 14)) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK; |
1417 | } |
1418 | |
1419 | #define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed |
1420 | #define A3XX_RB_COPY_DEST_BASE_BASE__MASK 0xfffffff0 |
1421 | #define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT 4 |
1422 | static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) |
1423 | { |
1424 | assert(!(val & 0x1f)); |
1425 | return (((val >> 5)) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK; |
1426 | } |
1427 | |
1428 | #define REG_A3XX_RB_COPY_DEST_PITCH 0x000020ee |
1429 | #define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff |
1430 | #define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 |
1431 | static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) |
1432 | { |
1433 | assert(!(val & 0x1f)); |
1434 | return (((val >> 5)) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK; |
1435 | } |
1436 | |
1437 | #define REG_A3XX_RB_COPY_DEST_INFO 0x000020ef |
1438 | #define A3XX_RB_COPY_DEST_INFO_TILE__MASK 0x00000003 |
1439 | #define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT 0 |
1440 | static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val) |
1441 | { |
1442 | return ((val) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A3XX_RB_COPY_DEST_INFO_TILE__MASK; |
1443 | } |
1444 | #define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc |
1445 | #define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2 |
1446 | static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val) |
1447 | { |
1448 | return ((val) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK; |
1449 | } |
1450 | #define A3XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 |
1451 | #define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 |
1452 | static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val) |
1453 | { |
1454 | return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK; |
1455 | } |
1456 | #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 |
1457 | #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 |
1458 | static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) |
1459 | { |
1460 | return ((val) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; |
1461 | } |
1462 | #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 |
1463 | #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 |
1464 | static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) |
1465 | { |
1466 | return ((val) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK; |
1467 | } |
1468 | #define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000 |
1469 | #define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18 |
1470 | static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val) |
1471 | { |
1472 | return ((val) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK; |
1473 | } |
1474 | |
1475 | #define REG_A3XX_RB_DEPTH_CONTROL 0x00002100 |
1476 | #define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001 |
1477 | #define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x00000002 |
1478 | #define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 |
1479 | #define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008 |
1480 | #define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070 |
1481 | #define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4 |
1482 | static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val) |
1483 | { |
1484 | return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK; |
1485 | } |
1486 | #define A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080 |
1487 | #define A3XX_RB_DEPTH_CONTROL_Z_READ_ENABLE 0x80000000 |
1488 | |
1489 | #define REG_A3XX_RB_DEPTH_CLEAR 0x00002101 |
1490 | |
1491 | #define REG_A3XX_RB_DEPTH_INFO 0x00002102 |
1492 | #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003 |
1493 | #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 |
1494 | static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) |
1495 | { |
1496 | return ((val) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; |
1497 | } |
1498 | #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff800 |
1499 | #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11 |
1500 | static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) |
1501 | { |
1502 | assert(!(val & 0xfff)); |
1503 | return (((val >> 12)) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; |
1504 | } |
1505 | |
1506 | #define REG_A3XX_RB_DEPTH_PITCH 0x00002103 |
1507 | #define A3XX_RB_DEPTH_PITCH__MASK 0xffffffff |
1508 | #define A3XX_RB_DEPTH_PITCH__SHIFT 0 |
1509 | static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val) |
1510 | { |
1511 | assert(!(val & 0x7)); |
1512 | return (((val >> 3)) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK; |
1513 | } |
1514 | |
1515 | #define REG_A3XX_RB_STENCIL_CONTROL 0x00002104 |
1516 | #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 |
1517 | #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 |
1518 | #define A3XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 |
1519 | #define A3XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 |
1520 | #define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 |
1521 | static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) |
1522 | { |
1523 | return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK; |
1524 | } |
1525 | #define A3XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 |
1526 | #define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 |
1527 | static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) |
1528 | { |
1529 | return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK; |
1530 | } |
1531 | #define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 |
1532 | #define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 |
1533 | static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) |
1534 | { |
1535 | return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK; |
1536 | } |
1537 | #define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 |
1538 | #define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 |
1539 | static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) |
1540 | { |
1541 | return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK; |
1542 | } |
1543 | #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 |
1544 | #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 |
1545 | static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) |
1546 | { |
1547 | return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; |
1548 | } |
1549 | #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 |
1550 | #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 |
1551 | static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) |
1552 | { |
1553 | return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; |
1554 | } |
1555 | #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 |
1556 | #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 |
1557 | static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) |
1558 | { |
1559 | return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; |
1560 | } |
1561 | #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 |
1562 | #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 |
1563 | static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) |
1564 | { |
1565 | return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; |
1566 | } |
1567 | |
1568 | #define REG_A3XX_RB_STENCIL_CLEAR 0x00002105 |
1569 | |
1570 | #define REG_A3XX_RB_STENCIL_INFO 0x00002106 |
1571 | #define A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff800 |
1572 | #define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 11 |
1573 | static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) |
1574 | { |
1575 | assert(!(val & 0xfff)); |
1576 | return (((val >> 12)) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; |
1577 | } |
1578 | |
1579 | #define REG_A3XX_RB_STENCIL_PITCH 0x00002107 |
1580 | #define A3XX_RB_STENCIL_PITCH__MASK 0xffffffff |
1581 | #define A3XX_RB_STENCIL_PITCH__SHIFT 0 |
1582 | static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val) |
1583 | { |
1584 | assert(!(val & 0x7)); |
1585 | return (((val >> 3)) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK; |
1586 | } |
1587 | |
1588 | #define REG_A3XX_RB_STENCILREFMASK 0x00002108 |
1589 | #define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff |
1590 | #define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 |
1591 | static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) |
1592 | { |
1593 | return ((val) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK; |
1594 | } |
1595 | #define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 |
1596 | #define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 |
1597 | static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) |
1598 | { |
1599 | return ((val) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK; |
1600 | } |
1601 | #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 |
1602 | #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 |
1603 | static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) |
1604 | { |
1605 | return ((val) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; |
1606 | } |
1607 | |
1608 | #define REG_A3XX_RB_STENCILREFMASK_BF 0x00002109 |
1609 | #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff |
1610 | #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 |
1611 | static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) |
1612 | { |
1613 | return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; |
1614 | } |
1615 | #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 |
1616 | #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 |
1617 | static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) |
1618 | { |
1619 | return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; |
1620 | } |
1621 | #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 |
1622 | #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 |
1623 | static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) |
1624 | { |
1625 | return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; |
1626 | } |
1627 | |
1628 | #define REG_A3XX_RB_LRZ_VSC_CONTROL 0x0000210c |
1629 | #define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE 0x00000002 |
1630 | |
1631 | #define REG_A3XX_RB_WINDOW_OFFSET 0x0000210e |
1632 | #define A3XX_RB_WINDOW_OFFSET_X__MASK 0x0000ffff |
1633 | #define A3XX_RB_WINDOW_OFFSET_X__SHIFT 0 |
1634 | static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val) |
1635 | { |
1636 | return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK; |
1637 | } |
1638 | #define A3XX_RB_WINDOW_OFFSET_Y__MASK 0xffff0000 |
1639 | #define A3XX_RB_WINDOW_OFFSET_Y__SHIFT 16 |
1640 | static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val) |
1641 | { |
1642 | return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK; |
1643 | } |
1644 | |
1645 | #define REG_A3XX_RB_SAMPLE_COUNT_CONTROL 0x00002110 |
1646 | #define A3XX_RB_SAMPLE_COUNT_CONTROL_RESET 0x00000001 |
1647 | #define A3XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 |
1648 | |
1649 | #define REG_A3XX_RB_SAMPLE_COUNT_ADDR 0x00002111 |
1650 | |
1651 | #define REG_A3XX_RB_Z_CLAMP_MIN 0x00002114 |
1652 | |
1653 | #define REG_A3XX_RB_Z_CLAMP_MAX 0x00002115 |
1654 | |
1655 | #define REG_A3XX_VGT_BIN_BASE 0x000021e1 |
1656 | |
1657 | #define REG_A3XX_VGT_BIN_SIZE 0x000021e2 |
1658 | |
1659 | #define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4 |
1660 | #define A3XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000 |
1661 | #define A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16 |
1662 | static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val) |
1663 | { |
1664 | return ((val) << A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A3XX_PC_VSTREAM_CONTROL_SIZE__MASK; |
1665 | } |
1666 | #define A3XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000 |
1667 | #define A3XX_PC_VSTREAM_CONTROL_N__SHIFT 22 |
1668 | static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val) |
1669 | { |
1670 | return ((val) << A3XX_PC_VSTREAM_CONTROL_N__SHIFT) & A3XX_PC_VSTREAM_CONTROL_N__MASK; |
1671 | } |
1672 | |
1673 | #define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea |
1674 | |
1675 | #define REG_A3XX_PC_PRIM_VTX_CNTL 0x000021ec |
1676 | #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK 0x0000001f |
1677 | #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT 0 |
1678 | static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val) |
1679 | { |
1680 | return ((val) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK; |
1681 | } |
1682 | #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x000000e0 |
1683 | #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 5 |
1684 | static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) |
1685 | { |
1686 | return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK; |
1687 | } |
1688 | #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000700 |
1689 | #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT 8 |
1690 | static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val) |
1691 | { |
1692 | return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK; |
1693 | } |
1694 | #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE 0x00001000 |
1695 | #define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000 |
1696 | #define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 |
1697 | #define A3XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000 |
1698 | |
1699 | #define REG_A3XX_PC_RESTART_INDEX 0x000021ed |
1700 | |
1701 | #define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200 |
1702 | #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000030 |
1703 | #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4 |
1704 | static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val) |
1705 | { |
1706 | return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK; |
1707 | } |
1708 | #define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040 |
1709 | #define A3XX_HLSQ_CONTROL_0_REG_COMPUTEMODE 0x00000100 |
1710 | #define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200 |
1711 | #define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400 |
1712 | #define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK 0x00fff000 |
1713 | #define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT 12 |
1714 | static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC(uint32_t val) |
1715 | { |
1716 | return ((val) << A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK; |
1717 | } |
1718 | #define A3XX_HLSQ_CONTROL_0_REG_FSONLYTEX 0x02000000 |
1719 | #define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000 |
1720 | #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000 |
1721 | #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27 |
1722 | static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val) |
1723 | { |
1724 | return ((val) << A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK; |
1725 | } |
1726 | #define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000 |
1727 | #define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000 |
1728 | #define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000 |
1729 | #define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000 |
1730 | |
1731 | #define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201 |
1732 | #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x000000c0 |
1733 | #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6 |
1734 | static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val) |
1735 | { |
1736 | return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK; |
1737 | } |
1738 | #define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 |
1739 | #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK 0x00ff0000 |
1740 | #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT 16 |
1741 | static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(uint32_t val) |
1742 | { |
1743 | return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK; |
1744 | } |
1745 | #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK 0xff000000 |
1746 | #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT 24 |
1747 | static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(uint32_t val) |
1748 | { |
1749 | return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK; |
1750 | } |
1751 | |
1752 | #define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202 |
1753 | #define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK 0x000003fc |
1754 | #define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT 2 |
1755 | static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(uint32_t val) |
1756 | { |
1757 | return ((val) << A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK; |
1758 | } |
1759 | #define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK 0x03fc0000 |
1760 | #define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT 18 |
1761 | static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID(uint32_t val) |
1762 | { |
1763 | return ((val) << A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK; |
1764 | } |
1765 | #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 |
1766 | #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26 |
1767 | static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val) |
1768 | { |
1769 | return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK; |
1770 | } |
1771 | |
1772 | #define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203 |
1773 | #define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__MASK 0x000000ff |
1774 | #define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__SHIFT 0 |
1775 | static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID(uint32_t val) |
1776 | { |
1777 | return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTERREGID__MASK; |
1778 | } |
1779 | #define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__MASK 0x0000ff00 |
1780 | #define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__SHIFT 8 |
1781 | static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID(uint32_t val) |
1782 | { |
1783 | return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTERREGID__MASK; |
1784 | } |
1785 | #define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__MASK 0x00ff0000 |
1786 | #define A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__SHIFT 16 |
1787 | static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID(uint32_t val) |
1788 | { |
1789 | return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJPERSPCENTROIDREGID__MASK; |
1790 | } |
1791 | #define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__MASK 0xff000000 |
1792 | #define A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__SHIFT 24 |
1793 | static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID(uint32_t val) |
1794 | { |
1795 | return ((val) << A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_IJNONPERSPCENTROIDREGID__MASK; |
1796 | } |
1797 | |
1798 | #define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204 |
1799 | #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000003ff |
1800 | #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0 |
1801 | static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val) |
1802 | { |
1803 | return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK; |
1804 | } |
1805 | #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x001ff000 |
1806 | #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 |
1807 | static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) |
1808 | { |
1809 | return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK; |
1810 | } |
1811 | #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 |
1812 | #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24 |
1813 | static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val) |
1814 | { |
1815 | return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK; |
1816 | } |
1817 | |
1818 | #define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205 |
1819 | #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000003ff |
1820 | #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0 |
1821 | static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val) |
1822 | { |
1823 | return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK; |
1824 | } |
1825 | #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x001ff000 |
1826 | #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12 |
1827 | static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val) |
1828 | { |
1829 | return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK; |
1830 | } |
1831 | #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000 |
1832 | #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24 |
1833 | static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val) |
1834 | { |
1835 | return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK; |
1836 | } |
1837 | |
1838 | #define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206 |
1839 | #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x000001ff |
1840 | #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 |
1841 | static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val) |
1842 | { |
1843 | return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK; |
1844 | } |
1845 | #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0x01ff0000 |
1846 | #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 |
1847 | static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val) |
1848 | { |
1849 | return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK; |
1850 | } |
1851 | |
1852 | #define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207 |
1853 | #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x000001ff |
1854 | #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0 |
1855 | static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val) |
1856 | { |
1857 | return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK; |
1858 | } |
1859 | #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0x01ff0000 |
1860 | #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16 |
1861 | static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val) |
1862 | { |
1863 | return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK; |
1864 | } |
1865 | |
1866 | #define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a |
1867 | #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK 0x00000003 |
1868 | #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT 0 |
1869 | static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val) |
1870 | { |
1871 | return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK; |
1872 | } |
1873 | #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK 0x00000ffc |
1874 | #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT 2 |
1875 | static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val) |
1876 | { |
1877 | return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK; |
1878 | } |
1879 | #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK 0x003ff000 |
1880 | #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT 12 |
1881 | static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val) |
1882 | { |
1883 | return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK; |
1884 | } |
1885 | #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK 0xffc00000 |
1886 | #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT 22 |
1887 | static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val) |
1888 | { |
1889 | return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK; |
1890 | } |
1891 | |
1892 | #define REG_A3XX_HLSQ_CL_GLOBAL_WORK(i0) (0x0000220b + 0x2*(i0)) |
1893 | |
1894 | static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; } |
1895 | |
1896 | static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; } |
1897 | |
1898 | #define REG_A3XX_HLSQ_CL_CONTROL_0_REG 0x00002211 |
1899 | |
1900 | #define REG_A3XX_HLSQ_CL_CONTROL_1_REG 0x00002212 |
1901 | |
1902 | #define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214 |
1903 | |
1904 | #define REG_A3XX_HLSQ_CL_KERNEL_GROUP(i0) (0x00002215 + 0x1*(i0)) |
1905 | |
1906 | static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; } |
1907 | |
1908 | #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG 0x00002216 |
1909 | |
1910 | #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x00002217 |
1911 | |
1912 | #define REG_A3XX_HLSQ_CL_WG_OFFSET_REG 0x0000221a |
1913 | |
1914 | #define REG_A3XX_VFD_CONTROL_0 0x00002240 |
1915 | #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x0003ffff |
1916 | #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0 |
1917 | static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val) |
1918 | { |
1919 | return ((val) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK; |
1920 | } |
1921 | #define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK 0x003c0000 |
1922 | #define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT 18 |
1923 | static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val) |
1924 | { |
1925 | return ((val) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK; |
1926 | } |
1927 | #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x07c00000 |
1928 | #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 22 |
1929 | static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val) |
1930 | { |
1931 | return ((val) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK; |
1932 | } |
1933 | #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xf8000000 |
1934 | #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 27 |
1935 | static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val) |
1936 | { |
1937 | return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK; |
1938 | } |
1939 | |
1940 | #define REG_A3XX_VFD_CONTROL_1 0x00002241 |
1941 | #define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000000f |
1942 | #define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0 |
1943 | static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val) |
1944 | { |
1945 | return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK; |
1946 | } |
1947 | #define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK 0x000000f0 |
1948 | #define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT 4 |
1949 | static inline uint32_t A3XX_VFD_CONTROL_1_MAXTHRESHOLD(uint32_t val) |
1950 | { |
1951 | return ((val) << A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK; |
1952 | } |
1953 | #define A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK 0x00000f00 |
1954 | #define A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT 8 |
1955 | static inline uint32_t A3XX_VFD_CONTROL_1_MINTHRESHOLD(uint32_t val) |
1956 | { |
1957 | return ((val) << A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK; |
1958 | } |
1959 | #define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000 |
1960 | #define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16 |
1961 | static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) |
1962 | { |
1963 | return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK; |
1964 | } |
1965 | #define A3XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000 |
1966 | #define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT 24 |
1967 | static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val) |
1968 | { |
1969 | return ((val) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A3XX_VFD_CONTROL_1_REGID4INST__MASK; |
1970 | } |
1971 | |
1972 | #define REG_A3XX_VFD_INDEX_MIN 0x00002242 |
1973 | |
1974 | #define REG_A3XX_VFD_INDEX_MAX 0x00002243 |
1975 | |
1976 | #define REG_A3XX_VFD_INSTANCEID_OFFSET 0x00002244 |
1977 | |
1978 | #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245 |
1979 | |
1980 | #define REG_A3XX_VFD_FETCH(i0) (0x00002246 + 0x2*(i0)) |
1981 | |
1982 | static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; } |
1983 | #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f |
1984 | #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0 |
1985 | static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val) |
1986 | { |
1987 | return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK; |
1988 | } |
1989 | #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0000ff80 |
1990 | #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7 |
1991 | static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val) |
1992 | { |
1993 | return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK; |
1994 | } |
1995 | #define A3XX_VFD_FETCH_INSTR_0_INSTANCED 0x00010000 |
1996 | #define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00020000 |
1997 | #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK 0x00fc0000 |
1998 | #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT 18 |
1999 | static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val) |
2000 | { |
2001 | return ((val) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK; |
2002 | } |
2003 | #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK 0xff000000 |
2004 | #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT 24 |
2005 | static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) |
2006 | { |
2007 | return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK; |
2008 | } |
2009 | |
2010 | static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; } |
2011 | |
2012 | #define REG_A3XX_VFD_DECODE(i0) (0x00002266 + 0x1*(i0)) |
2013 | |
2014 | static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; } |
2015 | #define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f |
2016 | #define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0 |
2017 | static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val) |
2018 | { |
2019 | return ((val) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK; |
2020 | } |
2021 | #define A3XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010 |
2022 | #define A3XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0 |
2023 | #define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6 |
2024 | static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val) |
2025 | { |
2026 | return ((val) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK; |
2027 | } |
2028 | #define A3XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000 |
2029 | #define A3XX_VFD_DECODE_INSTR_REGID__SHIFT 12 |
2030 | static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val) |
2031 | { |
2032 | return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK; |
2033 | } |
2034 | #define A3XX_VFD_DECODE_INSTR_INT 0x00100000 |
2035 | #define A3XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000 |
2036 | #define A3XX_VFD_DECODE_INSTR_SWAP__SHIFT 22 |
2037 | static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) |
2038 | { |
2039 | return ((val) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A3XX_VFD_DECODE_INSTR_SWAP__MASK; |
2040 | } |
2041 | #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 |
2042 | #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 |
2043 | static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) |
2044 | { |
2045 | return ((val) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK; |
2046 | } |
2047 | #define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000 |
2048 | #define A3XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000 |
2049 | |
2050 | #define REG_A3XX_VFD_VS_THREADING_THRESHOLD 0x0000227e |
2051 | #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK 0x0000000f |
2052 | #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT 0 |
2053 | static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val) |
2054 | { |
2055 | return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK; |
2056 | } |
2057 | #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK 0x0000ff00 |
2058 | #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT 8 |
2059 | static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val) |
2060 | { |
2061 | return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK; |
2062 | } |
2063 | |
2064 | #define REG_A3XX_VPC_ATTR 0x00002280 |
2065 | #define A3XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff |
2066 | #define A3XX_VPC_ATTR_TOTALATTR__SHIFT 0 |
2067 | static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val) |
2068 | { |
2069 | return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK; |
2070 | } |
2071 | #define A3XX_VPC_ATTR_PSIZE 0x00000200 |
2072 | #define A3XX_VPC_ATTR_THRDASSIGN__MASK 0x0ffff000 |
2073 | #define A3XX_VPC_ATTR_THRDASSIGN__SHIFT 12 |
2074 | static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val) |
2075 | { |
2076 | return ((val) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT) & A3XX_VPC_ATTR_THRDASSIGN__MASK; |
2077 | } |
2078 | #define A3XX_VPC_ATTR_LMSIZE__MASK 0xf0000000 |
2079 | #define A3XX_VPC_ATTR_LMSIZE__SHIFT 28 |
2080 | static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val) |
2081 | { |
2082 | return ((val) << A3XX_VPC_ATTR_LMSIZE__SHIFT) & A3XX_VPC_ATTR_LMSIZE__MASK; |
2083 | } |
2084 | |
2085 | #define REG_A3XX_VPC_PACK 0x00002281 |
2086 | #define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00 |
2087 | #define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8 |
2088 | static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val) |
2089 | { |
2090 | return ((val) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK; |
2091 | } |
2092 | #define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000 |
2093 | #define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16 |
2094 | static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) |
2095 | { |
2096 | return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK; |
2097 | } |
2098 | |
2099 | #define REG_A3XX_VPC_VARYING_INTERP(i0) (0x00002282 + 0x1*(i0)) |
2100 | |
2101 | static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; } |
2102 | #define A3XX_VPC_VARYING_INTERP_MODE_C0__MASK 0x00000003 |
2103 | #define A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT 0 |
2104 | static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val) |
2105 | { |
2106 | return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C0__MASK; |
2107 | } |
2108 | #define A3XX_VPC_VARYING_INTERP_MODE_C1__MASK 0x0000000c |
2109 | #define A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT 2 |
2110 | static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val) |
2111 | { |
2112 | return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C1__MASK; |
2113 | } |
2114 | #define A3XX_VPC_VARYING_INTERP_MODE_C2__MASK 0x00000030 |
2115 | #define A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT 4 |
2116 | static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val) |
2117 | { |
2118 | return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C2__MASK; |
2119 | } |
2120 | #define A3XX_VPC_VARYING_INTERP_MODE_C3__MASK 0x000000c0 |
2121 | #define A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT 6 |
2122 | static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val) |
2123 | { |
2124 | return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C3__MASK; |
2125 | } |
2126 | #define A3XX_VPC_VARYING_INTERP_MODE_C4__MASK 0x00000300 |
2127 | #define A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT 8 |
2128 | static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val) |
2129 | { |
2130 | return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C4__MASK; |
2131 | } |
2132 | #define A3XX_VPC_VARYING_INTERP_MODE_C5__MASK 0x00000c00 |
2133 | #define A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT 10 |
2134 | static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val) |
2135 | { |
2136 | return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C5__MASK; |
2137 | } |
2138 | #define A3XX_VPC_VARYING_INTERP_MODE_C6__MASK 0x00003000 |
2139 | #define A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT 12 |
2140 | static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val) |
2141 | { |
2142 | return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C6__MASK; |
2143 | } |
2144 | #define A3XX_VPC_VARYING_INTERP_MODE_C7__MASK 0x0000c000 |
2145 | #define A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT 14 |
2146 | static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val) |
2147 | { |
2148 | return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C7__MASK; |
2149 | } |
2150 | #define A3XX_VPC_VARYING_INTERP_MODE_C8__MASK 0x00030000 |
2151 | #define A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT 16 |
2152 | static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val) |
2153 | { |
2154 | return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C8__MASK; |
2155 | } |
2156 | #define A3XX_VPC_VARYING_INTERP_MODE_C9__MASK 0x000c0000 |
2157 | #define A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT 18 |
2158 | static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val) |
2159 | { |
2160 | return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C9__MASK; |
2161 | } |
2162 | #define A3XX_VPC_VARYING_INTERP_MODE_CA__MASK 0x00300000 |
2163 | #define A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT 20 |
2164 | static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val) |
2165 | { |
2166 | return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CA__MASK; |
2167 | } |
2168 | #define A3XX_VPC_VARYING_INTERP_MODE_CB__MASK 0x00c00000 |
2169 | #define A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT 22 |
2170 | static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val) |
2171 | { |
2172 | return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CB__MASK; |
2173 | } |
2174 | #define A3XX_VPC_VARYING_INTERP_MODE_CC__MASK 0x03000000 |
2175 | #define A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT 24 |
2176 | static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val) |
2177 | { |
2178 | return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CC__MASK; |
2179 | } |
2180 | #define A3XX_VPC_VARYING_INTERP_MODE_CD__MASK 0x0c000000 |
2181 | #define A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT 26 |
2182 | static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val) |
2183 | { |
2184 | return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CD__MASK; |
2185 | } |
2186 | #define A3XX_VPC_VARYING_INTERP_MODE_CE__MASK 0x30000000 |
2187 | #define A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT 28 |
2188 | static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val) |
2189 | { |
2190 | return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CE__MASK; |
2191 | } |
2192 | #define A3XX_VPC_VARYING_INTERP_MODE_CF__MASK 0xc0000000 |
2193 | #define A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT 30 |
2194 | static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val) |
2195 | { |
2196 | return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CF__MASK; |
2197 | } |
2198 | |
2199 | #define REG_A3XX_VPC_VARYING_PS_REPL(i0) (0x00002286 + 0x1*(i0)) |
2200 | |
2201 | static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; } |
2202 | #define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK 0x00000003 |
2203 | #define A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT 0 |
2204 | static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val) |
2205 | { |
2206 | return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK; |
2207 | } |
2208 | #define A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK 0x0000000c |
2209 | #define A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT 2 |
2210 | static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val) |
2211 | { |
2212 | return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK; |
2213 | } |
2214 | #define A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK 0x00000030 |
2215 | #define A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT 4 |
2216 | static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val) |
2217 | { |
2218 | return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK; |
2219 | } |
2220 | #define A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK 0x000000c0 |
2221 | #define A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT 6 |
2222 | static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val) |
2223 | { |
2224 | return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK; |
2225 | } |
2226 | #define A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK 0x00000300 |
2227 | #define A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT 8 |
2228 | static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val) |
2229 | { |
2230 | return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK; |
2231 | } |
2232 | #define A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK 0x00000c00 |
2233 | #define A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT 10 |
2234 | static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val) |
2235 | { |
2236 | return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK; |
2237 | } |
2238 | #define A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK 0x00003000 |
2239 | #define A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT 12 |
2240 | static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val) |
2241 | { |
2242 | return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK; |
2243 | } |
2244 | #define A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK 0x0000c000 |
2245 | #define A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT 14 |
2246 | static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val) |
2247 | { |
2248 | return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK; |
2249 | } |
2250 | #define A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK 0x00030000 |
2251 | #define A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT 16 |
2252 | static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val) |
2253 | { |
2254 | return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK; |
2255 | } |
2256 | #define A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK 0x000c0000 |
2257 | #define A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT 18 |
2258 | static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val) |
2259 | { |
2260 | return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK; |
2261 | } |
2262 | #define A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK 0x00300000 |
2263 | #define A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT 20 |
2264 | static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val) |
2265 | { |
2266 | return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK; |
2267 | } |
2268 | #define A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK 0x00c00000 |
2269 | #define A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT 22 |
2270 | static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val) |
2271 | { |
2272 | return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK; |
2273 | } |
2274 | #define A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK 0x03000000 |
2275 | #define A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT 24 |
2276 | static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val) |
2277 | { |
2278 | return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK; |
2279 | } |
2280 | #define A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK 0x0c000000 |
2281 | #define A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT 26 |
2282 | static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val) |
2283 | { |
2284 | return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK; |
2285 | } |
2286 | #define A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK 0x30000000 |
2287 | #define A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT 28 |
2288 | static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val) |
2289 | { |
2290 | return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK; |
2291 | } |
2292 | #define A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK 0xc0000000 |
2293 | #define A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT 30 |
2294 | static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val) |
2295 | { |
2296 | return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK; |
2297 | } |
2298 | |
2299 | #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a |
2300 | |
2301 | #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1 0x0000228b |
2302 | |
2303 | #define REG_A3XX_SP_SP_CTRL_REG 0x000022c0 |
2304 | #define A3XX_SP_SP_CTRL_REG_RESOLVE 0x00010000 |
2305 | #define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x00040000 |
2306 | #define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT 18 |
2307 | static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val) |
2308 | { |
2309 | return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK; |
2310 | } |
2311 | #define A3XX_SP_SP_CTRL_REG_BINNING 0x00080000 |
2312 | #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK 0x00300000 |
2313 | #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT 20 |
2314 | static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val) |
2315 | { |
2316 | return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK; |
2317 | } |
2318 | #define A3XX_SP_SP_CTRL_REG_L0MODE__MASK 0x00c00000 |
2319 | #define A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT 22 |
2320 | static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val) |
2321 | { |
2322 | return ((val) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK; |
2323 | } |
2324 | |
2325 | #define REG_A3XX_SP_VS_CTRL_REG0 0x000022c4 |
2326 | #define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 |
2327 | #define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 |
2328 | static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) |
2329 | { |
2330 | return ((val) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK; |
2331 | } |
2332 | #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 |
2333 | #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 |
2334 | static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) |
2335 | { |
2336 | return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK; |
2337 | } |
2338 | #define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004 |
2339 | #define A3XX_SP_VS_CTRL_REG0_ALUSCHMODE 0x00000008 |
2340 | #define 0x000003f0 |
2341 | #define 4 |
2342 | static inline uint32_t (uint32_t val) |
2343 | { |
2344 | return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; |
2345 | } |
2346 | #define 0x0000fc00 |
2347 | #define 10 |
2348 | static inline uint32_t (uint32_t val) |
2349 | { |
2350 | return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; |
2351 | } |
2352 | #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000 |
2353 | #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20 |
2354 | static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) |
2355 | { |
2356 | return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK; |
2357 | } |
2358 | #define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 |
2359 | #define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000 |
2360 | #define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24 |
2361 | static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val) |
2362 | { |
2363 | return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK; |
2364 | } |
2365 | |
2366 | #define REG_A3XX_SP_VS_CTRL_REG1 0x000022c5 |
2367 | #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff |
2368 | #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0 |
2369 | static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val) |
2370 | { |
2371 | return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK; |
2372 | } |
2373 | #define 0x000ffc00 |
2374 | #define 10 |
2375 | static inline uint32_t (uint32_t val) |
2376 | { |
2377 | return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK; |
2378 | } |
2379 | #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000 |
2380 | #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24 |
2381 | static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) |
2382 | { |
2383 | return ((val) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK; |
2384 | } |
2385 | |
2386 | #define REG_A3XX_SP_VS_PARAM_REG 0x000022c6 |
2387 | #define A3XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff |
2388 | #define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0 |
2389 | static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val) |
2390 | { |
2391 | return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK; |
2392 | } |
2393 | #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00 |
2394 | #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8 |
2395 | static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val) |
2396 | { |
2397 | return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK; |
2398 | } |
2399 | #define A3XX_SP_VS_PARAM_REG_POS2DMODE 0x00010000 |
2400 | #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0x01f00000 |
2401 | #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20 |
2402 | static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) |
2403 | { |
2404 | return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; |
2405 | } |
2406 | |
2407 | #define REG_A3XX_SP_VS_OUT(i0) (0x000022c7 + 0x1*(i0)) |
2408 | |
2409 | static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } |
2410 | #define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff |
2411 | #define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 |
2412 | static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val) |
2413 | { |
2414 | return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK; |
2415 | } |
2416 | #define A3XX_SP_VS_OUT_REG_A_HALF 0x00000100 |
2417 | #define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00 |
2418 | #define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9 |
2419 | static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) |
2420 | { |
2421 | return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK; |
2422 | } |
2423 | #define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 |
2424 | #define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 |
2425 | static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val) |
2426 | { |
2427 | return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK; |
2428 | } |
2429 | #define A3XX_SP_VS_OUT_REG_B_HALF 0x01000000 |
2430 | #define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000 |
2431 | #define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25 |
2432 | static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) |
2433 | { |
2434 | return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK; |
2435 | } |
2436 | |
2437 | #define REG_A3XX_SP_VS_VPC_DST(i0) (0x000022d0 + 0x1*(i0)) |
2438 | |
2439 | static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; } |
2440 | #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x0000007f |
2441 | #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 |
2442 | static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) |
2443 | { |
2444 | return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; |
2445 | } |
2446 | #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x00007f00 |
2447 | #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 |
2448 | static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) |
2449 | { |
2450 | return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; |
2451 | } |
2452 | #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x007f0000 |
2453 | #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 |
2454 | static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) |
2455 | { |
2456 | return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; |
2457 | } |
2458 | #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0x7f000000 |
2459 | #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 |
2460 | static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) |
2461 | { |
2462 | return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; |
2463 | } |
2464 | |
2465 | #define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4 |
2466 | #define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK 0x0000ffff |
2467 | #define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT 0 |
2468 | static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val) |
2469 | { |
2470 | return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK; |
2471 | } |
2472 | #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 |
2473 | #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 |
2474 | static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) |
2475 | { |
2476 | return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; |
2477 | } |
2478 | #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 |
2479 | #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 |
2480 | static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) |
2481 | { |
2482 | return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; |
2483 | } |
2484 | |
2485 | #define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5 |
2486 | |
2487 | #define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6 |
2488 | #define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK 0x000000ff |
2489 | #define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0 |
2490 | static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) |
2491 | { |
2492 | assert(!(val & 0x7f)); |
2493 | return (((val >> 7)) << A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK; |
2494 | } |
2495 | #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00 |
2496 | #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8 |
2497 | static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val) |
2498 | { |
2499 | return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK; |
2500 | } |
2501 | #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000 |
2502 | #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT 24 |
2503 | static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val) |
2504 | { |
2505 | return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK; |
2506 | } |
2507 | |
2508 | #define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7 |
2509 | #define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK 0x0000001f |
2510 | #define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT 0 |
2511 | static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) |
2512 | { |
2513 | return ((val) << A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK; |
2514 | } |
2515 | #define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK 0xffffffe0 |
2516 | #define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5 |
2517 | static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) |
2518 | { |
2519 | assert(!(val & 0x1f)); |
2520 | return (((val >> 5)) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK; |
2521 | } |
2522 | |
2523 | #define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8 |
2524 | |
2525 | #define REG_A3XX_SP_VS_LENGTH_REG 0x000022df |
2526 | #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff |
2527 | #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT 0 |
2528 | static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val) |
2529 | { |
2530 | return ((val) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK; |
2531 | } |
2532 | |
2533 | #define REG_A3XX_SP_FS_CTRL_REG0 0x000022e0 |
2534 | #define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 |
2535 | #define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 |
2536 | static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) |
2537 | { |
2538 | return ((val) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK; |
2539 | } |
2540 | #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002 |
2541 | #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1 |
2542 | static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val) |
2543 | { |
2544 | return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK; |
2545 | } |
2546 | #define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004 |
2547 | #define A3XX_SP_FS_CTRL_REG0_ALUSCHMODE 0x00000008 |
2548 | #define 0x000003f0 |
2549 | #define 4 |
2550 | static inline uint32_t (uint32_t val) |
2551 | { |
2552 | return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; |
2553 | } |
2554 | #define 0x0000fc00 |
2555 | #define 10 |
2556 | static inline uint32_t (uint32_t val) |
2557 | { |
2558 | return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; |
2559 | } |
2560 | #define A3XX_SP_FS_CTRL_REG0_FSBYPASSENABLE 0x00020000 |
2561 | #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP 0x00040000 |
2562 | #define A3XX_SP_FS_CTRL_REG0_OUTORDERED 0x00080000 |
2563 | #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 |
2564 | #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 |
2565 | static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val) |
2566 | { |
2567 | return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; |
2568 | } |
2569 | #define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 |
2570 | #define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 |
2571 | #define A3XX_SP_FS_CTRL_REG0_COMPUTEMODE 0x00800000 |
2572 | #define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK 0xff000000 |
2573 | #define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT 24 |
2574 | static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val) |
2575 | { |
2576 | return ((val) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK; |
2577 | } |
2578 | |
2579 | #define REG_A3XX_SP_FS_CTRL_REG1 0x000022e1 |
2580 | #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff |
2581 | #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0 |
2582 | static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val) |
2583 | { |
2584 | return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK; |
2585 | } |
2586 | #define 0x000ffc00 |
2587 | #define 10 |
2588 | static inline uint32_t (uint32_t val) |
2589 | { |
2590 | return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK; |
2591 | } |
2592 | #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x00f00000 |
2593 | #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 20 |
2594 | static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val) |
2595 | { |
2596 | return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK; |
2597 | } |
2598 | #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x7f000000 |
2599 | #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24 |
2600 | static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val) |
2601 | { |
2602 | return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK; |
2603 | } |
2604 | |
2605 | #define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2 |
2606 | #define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK 0x0000ffff |
2607 | #define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT 0 |
2608 | static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val) |
2609 | { |
2610 | return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK; |
2611 | } |
2612 | #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000 |
2613 | #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16 |
2614 | static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val) |
2615 | { |
2616 | return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK; |
2617 | } |
2618 | #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000 |
2619 | #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25 |
2620 | static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) |
2621 | { |
2622 | return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK; |
2623 | } |
2624 | |
2625 | #define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3 |
2626 | |
2627 | #define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4 |
2628 | #define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK 0x000000ff |
2629 | #define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0 |
2630 | static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) |
2631 | { |
2632 | return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK; |
2633 | } |
2634 | #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00 |
2635 | #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8 |
2636 | static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val) |
2637 | { |
2638 | return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK; |
2639 | } |
2640 | #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000 |
2641 | #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT 24 |
2642 | static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val) |
2643 | { |
2644 | return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK; |
2645 | } |
2646 | |
2647 | #define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5 |
2648 | #define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK 0x0000001f |
2649 | #define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT 0 |
2650 | static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) |
2651 | { |
2652 | return ((val) << A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK; |
2653 | } |
2654 | #define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK 0xffffffe0 |
2655 | #define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5 |
2656 | static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) |
2657 | { |
2658 | assert(!(val & 0x1f)); |
2659 | return (((val >> 5)) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK; |
2660 | } |
2661 | |
2662 | #define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6 |
2663 | |
2664 | #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x000022e8 |
2665 | |
2666 | #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9 |
2667 | |
2668 | #define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec |
2669 | #define A3XX_SP_FS_OUTPUT_REG_MRT__MASK 0x00000003 |
2670 | #define A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0 |
2671 | static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val) |
2672 | { |
2673 | return ((val) << A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A3XX_SP_FS_OUTPUT_REG_MRT__MASK; |
2674 | } |
2675 | #define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080 |
2676 | #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00 |
2677 | #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8 |
2678 | static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) |
2679 | { |
2680 | return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; |
2681 | } |
2682 | |
2683 | #define REG_A3XX_SP_FS_MRT(i0) (0x000022f0 + 0x1*(i0)) |
2684 | |
2685 | static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; } |
2686 | #define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff |
2687 | #define A3XX_SP_FS_MRT_REG_REGID__SHIFT 0 |
2688 | static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val) |
2689 | { |
2690 | return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK; |
2691 | } |
2692 | #define A3XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100 |
2693 | #define A3XX_SP_FS_MRT_REG_SINT 0x00000400 |
2694 | #define A3XX_SP_FS_MRT_REG_UINT 0x00000800 |
2695 | |
2696 | #define REG_A3XX_SP_FS_IMAGE_OUTPUT(i0) (0x000022f4 + 0x1*(i0)) |
2697 | |
2698 | static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; } |
2699 | #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK 0x0000003f |
2700 | #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT 0 |
2701 | static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val) |
2702 | { |
2703 | return ((val) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK; |
2704 | } |
2705 | |
2706 | #define REG_A3XX_SP_FS_LENGTH_REG 0x000022ff |
2707 | #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff |
2708 | #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT 0 |
2709 | static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val) |
2710 | { |
2711 | return ((val) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK; |
2712 | } |
2713 | |
2714 | #define REG_A3XX_PA_SC_AA_CONFIG 0x00002301 |
2715 | |
2716 | #define REG_A3XX_TPL1_TP_VS_TEX_OFFSET 0x00002340 |
2717 | #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff |
2718 | #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 |
2719 | static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) |
2720 | { |
2721 | return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK; |
2722 | } |
2723 | #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 |
2724 | #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 |
2725 | static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) |
2726 | { |
2727 | return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK; |
2728 | } |
2729 | #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 |
2730 | #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 |
2731 | static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val) |
2732 | { |
2733 | return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK; |
2734 | } |
2735 | |
2736 | #define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002341 |
2737 | |
2738 | #define REG_A3XX_TPL1_TP_FS_TEX_OFFSET 0x00002342 |
2739 | #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff |
2740 | #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0 |
2741 | static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val) |
2742 | { |
2743 | return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK; |
2744 | } |
2745 | #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00 |
2746 | #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8 |
2747 | static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val) |
2748 | { |
2749 | return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK; |
2750 | } |
2751 | #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000 |
2752 | #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT 16 |
2753 | static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) |
2754 | { |
2755 | return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK; |
2756 | } |
2757 | |
2758 | #define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x00002343 |
2759 | |
2760 | #define REG_A3XX_VBIF_CLKON 0x00003001 |
2761 | |
2762 | #define REG_A3XX_VBIF_FIXED_SORT_EN 0x0000300c |
2763 | |
2764 | #define REG_A3XX_VBIF_FIXED_SORT_SEL0 0x0000300d |
2765 | |
2766 | #define REG_A3XX_VBIF_FIXED_SORT_SEL1 0x0000300e |
2767 | |
2768 | #define REG_A3XX_VBIF_ABIT_SORT 0x0000301c |
2769 | |
2770 | #define REG_A3XX_VBIF_ABIT_SORT_CONF 0x0000301d |
2771 | |
2772 | #define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a |
2773 | |
2774 | #define REG_A3XX_VBIF_IN_RD_LIM_CONF0 0x0000302c |
2775 | |
2776 | #define REG_A3XX_VBIF_IN_RD_LIM_CONF1 0x0000302d |
2777 | |
2778 | #define REG_A3XX_VBIF_IN_WR_LIM_CONF0 0x00003030 |
2779 | |
2780 | #define REG_A3XX_VBIF_IN_WR_LIM_CONF1 0x00003031 |
2781 | |
2782 | #define REG_A3XX_VBIF_OUT_RD_LIM_CONF0 0x00003034 |
2783 | |
2784 | #define REG_A3XX_VBIF_OUT_WR_LIM_CONF0 0x00003035 |
2785 | |
2786 | #define REG_A3XX_VBIF_DDR_OUT_MAX_BURST 0x00003036 |
2787 | |
2788 | #define REG_A3XX_VBIF_ARB_CTL 0x0000303c |
2789 | |
2790 | #define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049 |
2791 | |
2792 | #define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0 0x00003058 |
2793 | |
2794 | #define REG_A3XX_VBIF_OUT_AXI_AOOO_EN 0x0000305e |
2795 | |
2796 | #define REG_A3XX_VBIF_OUT_AXI_AOOO 0x0000305f |
2797 | |
2798 | #define REG_A3XX_VBIF_PERF_CNT_EN 0x00003070 |
2799 | #define A3XX_VBIF_PERF_CNT_EN_CNT0 0x00000001 |
2800 | #define A3XX_VBIF_PERF_CNT_EN_CNT1 0x00000002 |
2801 | #define A3XX_VBIF_PERF_CNT_EN_PWRCNT0 0x00000004 |
2802 | #define A3XX_VBIF_PERF_CNT_EN_PWRCNT1 0x00000008 |
2803 | #define A3XX_VBIF_PERF_CNT_EN_PWRCNT2 0x00000010 |
2804 | |
2805 | #define REG_A3XX_VBIF_PERF_CNT_CLR 0x00003071 |
2806 | #define A3XX_VBIF_PERF_CNT_CLR_CNT0 0x00000001 |
2807 | #define A3XX_VBIF_PERF_CNT_CLR_CNT1 0x00000002 |
2808 | #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT0 0x00000004 |
2809 | #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT1 0x00000008 |
2810 | #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT2 0x00000010 |
2811 | |
2812 | #define REG_A3XX_VBIF_PERF_CNT_SEL 0x00003072 |
2813 | |
2814 | #define REG_A3XX_VBIF_PERF_CNT0_LO 0x00003073 |
2815 | |
2816 | #define REG_A3XX_VBIF_PERF_CNT0_HI 0x00003074 |
2817 | |
2818 | #define REG_A3XX_VBIF_PERF_CNT1_LO 0x00003075 |
2819 | |
2820 | #define REG_A3XX_VBIF_PERF_CNT1_HI 0x00003076 |
2821 | |
2822 | #define REG_A3XX_VBIF_PERF_PWR_CNT0_LO 0x00003077 |
2823 | |
2824 | #define REG_A3XX_VBIF_PERF_PWR_CNT0_HI 0x00003078 |
2825 | |
2826 | #define REG_A3XX_VBIF_PERF_PWR_CNT1_LO 0x00003079 |
2827 | |
2828 | #define REG_A3XX_VBIF_PERF_PWR_CNT1_HI 0x0000307a |
2829 | |
2830 | #define REG_A3XX_VBIF_PERF_PWR_CNT2_LO 0x0000307b |
2831 | |
2832 | #define REG_A3XX_VBIF_PERF_PWR_CNT2_HI 0x0000307c |
2833 | |
2834 | #define REG_A3XX_VSC_BIN_SIZE 0x00000c01 |
2835 | #define A3XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f |
2836 | #define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 |
2837 | static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val) |
2838 | { |
2839 | assert(!(val & 0x1f)); |
2840 | return (((val >> 5)) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK; |
2841 | } |
2842 | #define A3XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 |
2843 | #define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 |
2844 | static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) |
2845 | { |
2846 | assert(!(val & 0x1f)); |
2847 | return (((val >> 5)) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK; |
2848 | } |
2849 | |
2850 | #define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02 |
2851 | |
2852 | #define REG_A3XX_VSC_PIPE(i0) (0x00000c06 + 0x3*(i0)) |
2853 | |
2854 | static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } |
2855 | #define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff |
2856 | #define A3XX_VSC_PIPE_CONFIG_X__SHIFT 0 |
2857 | static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val) |
2858 | { |
2859 | return ((val) << A3XX_VSC_PIPE_CONFIG_X__SHIFT) & A3XX_VSC_PIPE_CONFIG_X__MASK; |
2860 | } |
2861 | #define A3XX_VSC_PIPE_CONFIG_Y__MASK 0x000ffc00 |
2862 | #define A3XX_VSC_PIPE_CONFIG_Y__SHIFT 10 |
2863 | static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val) |
2864 | { |
2865 | return ((val) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT) & A3XX_VSC_PIPE_CONFIG_Y__MASK; |
2866 | } |
2867 | #define A3XX_VSC_PIPE_CONFIG_W__MASK 0x00f00000 |
2868 | #define A3XX_VSC_PIPE_CONFIG_W__SHIFT 20 |
2869 | static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val) |
2870 | { |
2871 | return ((val) << A3XX_VSC_PIPE_CONFIG_W__SHIFT) & A3XX_VSC_PIPE_CONFIG_W__MASK; |
2872 | } |
2873 | #define A3XX_VSC_PIPE_CONFIG_H__MASK 0x0f000000 |
2874 | #define A3XX_VSC_PIPE_CONFIG_H__SHIFT 24 |
2875 | static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val) |
2876 | { |
2877 | return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK; |
2878 | } |
2879 | |
2880 | static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } |
2881 | |
2882 | static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } |
2883 | |
2884 | #define REG_A3XX_VSC_BIN_CONTROL 0x00000c3c |
2885 | #define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE 0x00000001 |
2886 | |
2887 | #define REG_A3XX_UNKNOWN_0C3D 0x00000c3d |
2888 | |
2889 | #define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48 |
2890 | |
2891 | #define REG_A3XX_PC_PERFCOUNTER1_SELECT 0x00000c49 |
2892 | |
2893 | #define REG_A3XX_PC_PERFCOUNTER2_SELECT 0x00000c4a |
2894 | |
2895 | #define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b |
2896 | |
2897 | #define REG_A3XX_GRAS_TSE_DEBUG_ECO 0x00000c81 |
2898 | |
2899 | #define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88 |
2900 | |
2901 | #define REG_A3XX_GRAS_PERFCOUNTER1_SELECT 0x00000c89 |
2902 | |
2903 | #define REG_A3XX_GRAS_PERFCOUNTER2_SELECT 0x00000c8a |
2904 | |
2905 | #define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b |
2906 | |
2907 | #define REG_A3XX_GRAS_CL_USER_PLANE(i0) (0x00000ca0 + 0x4*(i0)) |
2908 | |
2909 | static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } |
2910 | |
2911 | static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; } |
2912 | |
2913 | static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; } |
2914 | |
2915 | static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; } |
2916 | |
2917 | #define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0 |
2918 | |
2919 | #define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR 0x00000cc1 |
2920 | |
2921 | #define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6 |
2922 | |
2923 | #define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7 |
2924 | |
2925 | #define REG_A3XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0 |
2926 | #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff |
2927 | #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0 |
2928 | static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val) |
2929 | { |
2930 | return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK; |
2931 | } |
2932 | #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x0fffc000 |
2933 | #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 14 |
2934 | static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) |
2935 | { |
2936 | return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK; |
2937 | } |
2938 | |
2939 | #define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00 |
2940 | |
2941 | #define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT 0x00000e01 |
2942 | |
2943 | #define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT 0x00000e02 |
2944 | |
2945 | #define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT 0x00000e03 |
2946 | |
2947 | #define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT 0x00000e04 |
2948 | |
2949 | #define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT 0x00000e05 |
2950 | |
2951 | #define REG_A3XX_UNKNOWN_0E43 0x00000e43 |
2952 | |
2953 | #define REG_A3XX_VFD_PERFCOUNTER0_SELECT 0x00000e44 |
2954 | |
2955 | #define REG_A3XX_VFD_PERFCOUNTER1_SELECT 0x00000e45 |
2956 | |
2957 | #define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL 0x00000e61 |
2958 | |
2959 | #define REG_A3XX_VPC_VPC_DEBUG_RAM_READ 0x00000e62 |
2960 | |
2961 | #define REG_A3XX_VPC_PERFCOUNTER0_SELECT 0x00000e64 |
2962 | |
2963 | #define REG_A3XX_VPC_PERFCOUNTER1_SELECT 0x00000e65 |
2964 | |
2965 | #define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG 0x00000e82 |
2966 | |
2967 | #define REG_A3XX_UCHE_PERFCOUNTER0_SELECT 0x00000e84 |
2968 | |
2969 | #define REG_A3XX_UCHE_PERFCOUNTER1_SELECT 0x00000e85 |
2970 | |
2971 | #define REG_A3XX_UCHE_PERFCOUNTER2_SELECT 0x00000e86 |
2972 | |
2973 | #define REG_A3XX_UCHE_PERFCOUNTER3_SELECT 0x00000e87 |
2974 | |
2975 | #define REG_A3XX_UCHE_PERFCOUNTER4_SELECT 0x00000e88 |
2976 | |
2977 | #define REG_A3XX_UCHE_PERFCOUNTER5_SELECT 0x00000e89 |
2978 | |
2979 | #define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG 0x00000ea0 |
2980 | #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK 0x0fffffff |
2981 | #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT 0 |
2982 | static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val) |
2983 | { |
2984 | return ((val) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK; |
2985 | } |
2986 | |
2987 | #define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG 0x00000ea1 |
2988 | #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK 0x0fffffff |
2989 | #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT 0 |
2990 | static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val) |
2991 | { |
2992 | return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK; |
2993 | } |
2994 | #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK 0x30000000 |
2995 | #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT 28 |
2996 | static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val) |
2997 | { |
2998 | return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK; |
2999 | } |
3000 | #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE 0x80000000 |
3001 | |
3002 | #define REG_A3XX_UNKNOWN_0EA6 0x00000ea6 |
3003 | |
3004 | #define REG_A3XX_SP_PERFCOUNTER0_SELECT 0x00000ec4 |
3005 | |
3006 | #define REG_A3XX_SP_PERFCOUNTER1_SELECT 0x00000ec5 |
3007 | |
3008 | #define REG_A3XX_SP_PERFCOUNTER2_SELECT 0x00000ec6 |
3009 | |
3010 | #define REG_A3XX_SP_PERFCOUNTER3_SELECT 0x00000ec7 |
3011 | |
3012 | #define REG_A3XX_SP_PERFCOUNTER4_SELECT 0x00000ec8 |
3013 | |
3014 | #define REG_A3XX_SP_PERFCOUNTER5_SELECT 0x00000ec9 |
3015 | |
3016 | #define REG_A3XX_SP_PERFCOUNTER6_SELECT 0x00000eca |
3017 | |
3018 | #define REG_A3XX_SP_PERFCOUNTER7_SELECT 0x00000ecb |
3019 | |
3020 | #define REG_A3XX_UNKNOWN_0EE0 0x00000ee0 |
3021 | |
3022 | #define REG_A3XX_UNKNOWN_0F03 0x00000f03 |
3023 | |
3024 | #define REG_A3XX_TP_PERFCOUNTER0_SELECT 0x00000f04 |
3025 | |
3026 | #define REG_A3XX_TP_PERFCOUNTER1_SELECT 0x00000f05 |
3027 | |
3028 | #define REG_A3XX_TP_PERFCOUNTER2_SELECT 0x00000f06 |
3029 | |
3030 | #define REG_A3XX_TP_PERFCOUNTER3_SELECT 0x00000f07 |
3031 | |
3032 | #define REG_A3XX_TP_PERFCOUNTER4_SELECT 0x00000f08 |
3033 | |
3034 | #define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09 |
3035 | |
3036 | #define REG_A3XX_VGT_CL_INITIATOR 0x000021f0 |
3037 | |
3038 | #define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9 |
3039 | |
3040 | #define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc |
3041 | #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f |
3042 | #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 |
3043 | static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) |
3044 | { |
3045 | return ((val) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; |
3046 | } |
3047 | #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 |
3048 | #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 |
3049 | static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) |
3050 | { |
3051 | return ((val) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; |
3052 | } |
3053 | #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 |
3054 | #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 |
3055 | static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) |
3056 | { |
3057 | return ((val) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; |
3058 | } |
3059 | #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 |
3060 | #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 |
3061 | static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) |
3062 | { |
3063 | return ((val) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; |
3064 | } |
3065 | #define A3XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 |
3066 | #define A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 |
3067 | #define A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 |
3068 | #define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 |
3069 | #define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 |
3070 | static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) |
3071 | { |
3072 | return ((val) << A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; |
3073 | } |
3074 | |
3075 | #define REG_A3XX_VGT_IMMED_DATA 0x000021fd |
3076 | |
3077 | #define REG_A3XX_TEX_SAMP_0 0x00000000 |
3078 | #define A3XX_TEX_SAMP_0_CLAMPENABLE 0x00000001 |
3079 | #define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002 |
3080 | #define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c |
3081 | #define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2 |
3082 | static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val) |
3083 | { |
3084 | return ((val) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT) & A3XX_TEX_SAMP_0_XY_MAG__MASK; |
3085 | } |
3086 | #define A3XX_TEX_SAMP_0_XY_MIN__MASK 0x00000030 |
3087 | #define A3XX_TEX_SAMP_0_XY_MIN__SHIFT 4 |
3088 | static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val) |
3089 | { |
3090 | return ((val) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT) & A3XX_TEX_SAMP_0_XY_MIN__MASK; |
3091 | } |
3092 | #define A3XX_TEX_SAMP_0_WRAP_S__MASK 0x000001c0 |
3093 | #define A3XX_TEX_SAMP_0_WRAP_S__SHIFT 6 |
3094 | static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val) |
3095 | { |
3096 | return ((val) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT) & A3XX_TEX_SAMP_0_WRAP_S__MASK; |
3097 | } |
3098 | #define A3XX_TEX_SAMP_0_WRAP_T__MASK 0x00000e00 |
3099 | #define A3XX_TEX_SAMP_0_WRAP_T__SHIFT 9 |
3100 | static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val) |
3101 | { |
3102 | return ((val) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT) & A3XX_TEX_SAMP_0_WRAP_T__MASK; |
3103 | } |
3104 | #define A3XX_TEX_SAMP_0_WRAP_R__MASK 0x00007000 |
3105 | #define A3XX_TEX_SAMP_0_WRAP_R__SHIFT 12 |
3106 | static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val) |
3107 | { |
3108 | return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK; |
3109 | } |
3110 | #define A3XX_TEX_SAMP_0_ANISO__MASK 0x00038000 |
3111 | #define A3XX_TEX_SAMP_0_ANISO__SHIFT 15 |
3112 | static inline uint32_t A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val) |
3113 | { |
3114 | return ((val) << A3XX_TEX_SAMP_0_ANISO__SHIFT) & A3XX_TEX_SAMP_0_ANISO__MASK; |
3115 | } |
3116 | #define A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK 0x00700000 |
3117 | #define A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT 20 |
3118 | static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val) |
3119 | { |
3120 | return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK; |
3121 | } |
3122 | #define A3XX_TEX_SAMP_0_CUBEMAPSEAMLESSFILTOFF 0x01000000 |
3123 | #define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000 |
3124 | |
3125 | #define REG_A3XX_TEX_SAMP_1 0x00000001 |
3126 | #define A3XX_TEX_SAMP_1_LOD_BIAS__MASK 0x000007ff |
3127 | #define A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT 0 |
3128 | static inline uint32_t A3XX_TEX_SAMP_1_LOD_BIAS(float val) |
3129 | { |
3130 | return ((((int32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT) & A3XX_TEX_SAMP_1_LOD_BIAS__MASK; |
3131 | } |
3132 | #define A3XX_TEX_SAMP_1_MAX_LOD__MASK 0x003ff000 |
3133 | #define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT 12 |
3134 | static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val) |
3135 | { |
3136 | return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK; |
3137 | } |
3138 | #define A3XX_TEX_SAMP_1_MIN_LOD__MASK 0xffc00000 |
3139 | #define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT 22 |
3140 | static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val) |
3141 | { |
3142 | return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK; |
3143 | } |
3144 | |
3145 | #define REG_A3XX_TEX_CONST_0 0x00000000 |
3146 | #define A3XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 |
3147 | #define A3XX_TEX_CONST_0_TILE_MODE__SHIFT 0 |
3148 | static inline uint32_t A3XX_TEX_CONST_0_TILE_MODE(enum a3xx_tile_mode val) |
3149 | { |
3150 | return ((val) << A3XX_TEX_CONST_0_TILE_MODE__SHIFT) & A3XX_TEX_CONST_0_TILE_MODE__MASK; |
3151 | } |
3152 | #define A3XX_TEX_CONST_0_SRGB 0x00000004 |
3153 | #define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 |
3154 | #define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4 |
3155 | static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val) |
3156 | { |
3157 | return ((val) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT) & A3XX_TEX_CONST_0_SWIZ_X__MASK; |
3158 | } |
3159 | #define A3XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 |
3160 | #define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 |
3161 | static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val) |
3162 | { |
3163 | return ((val) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Y__MASK; |
3164 | } |
3165 | #define A3XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 |
3166 | #define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 |
3167 | static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val) |
3168 | { |
3169 | return ((val) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Z__MASK; |
3170 | } |
3171 | #define A3XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 |
3172 | #define A3XX_TEX_CONST_0_SWIZ_W__SHIFT 13 |
3173 | static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val) |
3174 | { |
3175 | return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK; |
3176 | } |
3177 | #define A3XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 |
3178 | #define A3XX_TEX_CONST_0_MIPLVLS__SHIFT 16 |
3179 | static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val) |
3180 | { |
3181 | return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK; |
3182 | } |
3183 | #define A3XX_TEX_CONST_0_MSAATEX__MASK 0x00300000 |
3184 | #define A3XX_TEX_CONST_0_MSAATEX__SHIFT 20 |
3185 | static inline uint32_t A3XX_TEX_CONST_0_MSAATEX(enum a3xx_tex_msaa val) |
3186 | { |
3187 | return ((val) << A3XX_TEX_CONST_0_MSAATEX__SHIFT) & A3XX_TEX_CONST_0_MSAATEX__MASK; |
3188 | } |
3189 | #define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000 |
3190 | #define A3XX_TEX_CONST_0_FMT__SHIFT 22 |
3191 | static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val) |
3192 | { |
3193 | return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK; |
3194 | } |
3195 | #define A3XX_TEX_CONST_0_NOCONVERT 0x20000000 |
3196 | #define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000 |
3197 | #define A3XX_TEX_CONST_0_TYPE__SHIFT 30 |
3198 | static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val) |
3199 | { |
3200 | return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK; |
3201 | } |
3202 | |
3203 | #define REG_A3XX_TEX_CONST_1 0x00000001 |
3204 | #define A3XX_TEX_CONST_1_HEIGHT__MASK 0x00003fff |
3205 | #define A3XX_TEX_CONST_1_HEIGHT__SHIFT 0 |
3206 | static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val) |
3207 | { |
3208 | return ((val) << A3XX_TEX_CONST_1_HEIGHT__SHIFT) & A3XX_TEX_CONST_1_HEIGHT__MASK; |
3209 | } |
3210 | #define A3XX_TEX_CONST_1_WIDTH__MASK 0x0fffc000 |
3211 | #define A3XX_TEX_CONST_1_WIDTH__SHIFT 14 |
3212 | static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val) |
3213 | { |
3214 | return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK; |
3215 | } |
3216 | #define A3XX_TEX_CONST_1_PITCHALIGN__MASK 0xf0000000 |
3217 | #define A3XX_TEX_CONST_1_PITCHALIGN__SHIFT 28 |
3218 | static inline uint32_t A3XX_TEX_CONST_1_PITCHALIGN(uint32_t val) |
3219 | { |
3220 | return ((val) << A3XX_TEX_CONST_1_PITCHALIGN__SHIFT) & A3XX_TEX_CONST_1_PITCHALIGN__MASK; |
3221 | } |
3222 | |
3223 | #define REG_A3XX_TEX_CONST_2 0x00000002 |
3224 | #define A3XX_TEX_CONST_2_INDX__MASK 0x000001ff |
3225 | #define A3XX_TEX_CONST_2_INDX__SHIFT 0 |
3226 | static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val) |
3227 | { |
3228 | return ((val) << A3XX_TEX_CONST_2_INDX__SHIFT) & A3XX_TEX_CONST_2_INDX__MASK; |
3229 | } |
3230 | #define A3XX_TEX_CONST_2_PITCH__MASK 0x3ffff000 |
3231 | #define A3XX_TEX_CONST_2_PITCH__SHIFT 12 |
3232 | static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val) |
3233 | { |
3234 | return ((val) << A3XX_TEX_CONST_2_PITCH__SHIFT) & A3XX_TEX_CONST_2_PITCH__MASK; |
3235 | } |
3236 | #define A3XX_TEX_CONST_2_SWAP__MASK 0xc0000000 |
3237 | #define A3XX_TEX_CONST_2_SWAP__SHIFT 30 |
3238 | static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) |
3239 | { |
3240 | return ((val) << A3XX_TEX_CONST_2_SWAP__SHIFT) & A3XX_TEX_CONST_2_SWAP__MASK; |
3241 | } |
3242 | |
3243 | #define REG_A3XX_TEX_CONST_3 0x00000003 |
3244 | #define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x0001ffff |
3245 | #define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT 0 |
3246 | static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val) |
3247 | { |
3248 | assert(!(val & 0xfff)); |
3249 | return (((val >> 12)) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK; |
3250 | } |
3251 | #define A3XX_TEX_CONST_3_DEPTH__MASK 0x0ffe0000 |
3252 | #define A3XX_TEX_CONST_3_DEPTH__SHIFT 17 |
3253 | static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val) |
3254 | { |
3255 | return ((val) << A3XX_TEX_CONST_3_DEPTH__SHIFT) & A3XX_TEX_CONST_3_DEPTH__MASK; |
3256 | } |
3257 | #define A3XX_TEX_CONST_3_LAYERSZ2__MASK 0xf0000000 |
3258 | #define A3XX_TEX_CONST_3_LAYERSZ2__SHIFT 28 |
3259 | static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val) |
3260 | { |
3261 | assert(!(val & 0xfff)); |
3262 | return (((val >> 12)) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK; |
3263 | } |
3264 | |
3265 | #ifdef __cplusplus |
3266 | #endif |
3267 | |
3268 | #endif /* A3XX_XML */ |
3269 | |