1#ifndef A4XX_XML
2#define A4XX_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
7http://gitlab.freedesktop.org/mesa/mesa/
8git clone https://gitlab.freedesktop.org/mesa/mesa.git
9
10The rules-ng-ng source files this header was generated from are:
11
12- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from Fri Jun 2 14:59:26 2023)
13- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023)
14- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
15- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85691 bytes, from Fri Feb 16 09:49:01 2024)
16
17Copyright (C) 2013-2024 by the following authors:
18- Rob Clark <robdclark@gmail.com> Rob Clark
19- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin
20
21Permission is hereby granted, free of charge, to any person obtaining
22a copy of this software and associated documentation files (the
23"Software"), to deal in the Software without restriction, including
24without limitation the rights to use, copy, modify, merge, publish,
25distribute, sublicense, and/or sell copies of the Software, and to
26permit persons to whom the Software is furnished to do so, subject to
27the following conditions:
28
29The above copyright notice and this permission notice (including the
30next paragraph) shall be included in all copies or substantial
31portions of the Software.
32
33THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
35MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
36IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
37LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
38OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
39WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
40
41*/
42
43#ifdef __KERNEL__
44#include <linux/bug.h>
45#define assert(x) BUG_ON(!(x))
46#else
47#include <assert.h>
48#endif
49
50#ifdef __cplusplus
51#define __struct_cast(X)
52#else
53#define __struct_cast(X) (struct X)
54#endif
55
56enum a4xx_color_fmt {
57 RB4_A8_UNORM = 1,
58 RB4_R8_UNORM = 2,
59 RB4_R8_SNORM = 3,
60 RB4_R8_UINT = 4,
61 RB4_R8_SINT = 5,
62 RB4_R4G4B4A4_UNORM = 8,
63 RB4_R5G5B5A1_UNORM = 10,
64 RB4_R5G6B5_UNORM = 14,
65 RB4_R8G8_UNORM = 15,
66 RB4_R8G8_SNORM = 16,
67 RB4_R8G8_UINT = 17,
68 RB4_R8G8_SINT = 18,
69 RB4_R16_UNORM = 19,
70 RB4_R16_SNORM = 20,
71 RB4_R16_FLOAT = 21,
72 RB4_R16_UINT = 22,
73 RB4_R16_SINT = 23,
74 RB4_R8G8B8_UNORM = 25,
75 RB4_R8G8B8A8_UNORM = 26,
76 RB4_R8G8B8A8_SNORM = 28,
77 RB4_R8G8B8A8_UINT = 29,
78 RB4_R8G8B8A8_SINT = 30,
79 RB4_R10G10B10A2_UNORM = 31,
80 RB4_R10G10B10A2_UINT = 34,
81 RB4_R11G11B10_FLOAT = 39,
82 RB4_R16G16_UNORM = 40,
83 RB4_R16G16_SNORM = 41,
84 RB4_R16G16_FLOAT = 42,
85 RB4_R16G16_UINT = 43,
86 RB4_R16G16_SINT = 44,
87 RB4_R32_FLOAT = 45,
88 RB4_R32_UINT = 46,
89 RB4_R32_SINT = 47,
90 RB4_R16G16B16A16_UNORM = 52,
91 RB4_R16G16B16A16_SNORM = 53,
92 RB4_R16G16B16A16_FLOAT = 54,
93 RB4_R16G16B16A16_UINT = 55,
94 RB4_R16G16B16A16_SINT = 56,
95 RB4_R32G32_FLOAT = 57,
96 RB4_R32G32_UINT = 58,
97 RB4_R32G32_SINT = 59,
98 RB4_R32G32B32A32_FLOAT = 60,
99 RB4_R32G32B32A32_UINT = 61,
100 RB4_R32G32B32A32_SINT = 62,
101 RB4_NONE = 255,
102};
103
104enum a4xx_tile_mode {
105 TILE4_LINEAR = 0,
106 TILE4_2 = 2,
107 TILE4_3 = 3,
108};
109
110enum a4xx_vtx_fmt {
111 VFMT4_32_FLOAT = 1,
112 VFMT4_32_32_FLOAT = 2,
113 VFMT4_32_32_32_FLOAT = 3,
114 VFMT4_32_32_32_32_FLOAT = 4,
115 VFMT4_16_FLOAT = 5,
116 VFMT4_16_16_FLOAT = 6,
117 VFMT4_16_16_16_FLOAT = 7,
118 VFMT4_16_16_16_16_FLOAT = 8,
119 VFMT4_32_FIXED = 9,
120 VFMT4_32_32_FIXED = 10,
121 VFMT4_32_32_32_FIXED = 11,
122 VFMT4_32_32_32_32_FIXED = 12,
123 VFMT4_11_11_10_FLOAT = 13,
124 VFMT4_16_SINT = 16,
125 VFMT4_16_16_SINT = 17,
126 VFMT4_16_16_16_SINT = 18,
127 VFMT4_16_16_16_16_SINT = 19,
128 VFMT4_16_UINT = 20,
129 VFMT4_16_16_UINT = 21,
130 VFMT4_16_16_16_UINT = 22,
131 VFMT4_16_16_16_16_UINT = 23,
132 VFMT4_16_SNORM = 24,
133 VFMT4_16_16_SNORM = 25,
134 VFMT4_16_16_16_SNORM = 26,
135 VFMT4_16_16_16_16_SNORM = 27,
136 VFMT4_16_UNORM = 28,
137 VFMT4_16_16_UNORM = 29,
138 VFMT4_16_16_16_UNORM = 30,
139 VFMT4_16_16_16_16_UNORM = 31,
140 VFMT4_32_UINT = 32,
141 VFMT4_32_32_UINT = 33,
142 VFMT4_32_32_32_UINT = 34,
143 VFMT4_32_32_32_32_UINT = 35,
144 VFMT4_32_SINT = 36,
145 VFMT4_32_32_SINT = 37,
146 VFMT4_32_32_32_SINT = 38,
147 VFMT4_32_32_32_32_SINT = 39,
148 VFMT4_8_UINT = 40,
149 VFMT4_8_8_UINT = 41,
150 VFMT4_8_8_8_UINT = 42,
151 VFMT4_8_8_8_8_UINT = 43,
152 VFMT4_8_UNORM = 44,
153 VFMT4_8_8_UNORM = 45,
154 VFMT4_8_8_8_UNORM = 46,
155 VFMT4_8_8_8_8_UNORM = 47,
156 VFMT4_8_SINT = 48,
157 VFMT4_8_8_SINT = 49,
158 VFMT4_8_8_8_SINT = 50,
159 VFMT4_8_8_8_8_SINT = 51,
160 VFMT4_8_SNORM = 52,
161 VFMT4_8_8_SNORM = 53,
162 VFMT4_8_8_8_SNORM = 54,
163 VFMT4_8_8_8_8_SNORM = 55,
164 VFMT4_10_10_10_2_UINT = 56,
165 VFMT4_10_10_10_2_UNORM = 57,
166 VFMT4_10_10_10_2_SINT = 58,
167 VFMT4_10_10_10_2_SNORM = 59,
168 VFMT4_2_10_10_10_UINT = 60,
169 VFMT4_2_10_10_10_UNORM = 61,
170 VFMT4_2_10_10_10_SINT = 62,
171 VFMT4_2_10_10_10_SNORM = 63,
172 VFMT4_NONE = 255,
173};
174
175enum a4xx_tex_fmt {
176 TFMT4_A8_UNORM = 3,
177 TFMT4_8_UNORM = 4,
178 TFMT4_8_SNORM = 5,
179 TFMT4_8_UINT = 6,
180 TFMT4_8_SINT = 7,
181 TFMT4_4_4_4_4_UNORM = 8,
182 TFMT4_5_5_5_1_UNORM = 9,
183 TFMT4_5_6_5_UNORM = 11,
184 TFMT4_L8_A8_UNORM = 13,
185 TFMT4_8_8_UNORM = 14,
186 TFMT4_8_8_SNORM = 15,
187 TFMT4_8_8_UINT = 16,
188 TFMT4_8_8_SINT = 17,
189 TFMT4_16_UNORM = 18,
190 TFMT4_16_SNORM = 19,
191 TFMT4_16_FLOAT = 20,
192 TFMT4_16_UINT = 21,
193 TFMT4_16_SINT = 22,
194 TFMT4_8_8_8_8_UNORM = 28,
195 TFMT4_8_8_8_8_SNORM = 29,
196 TFMT4_8_8_8_8_UINT = 30,
197 TFMT4_8_8_8_8_SINT = 31,
198 TFMT4_9_9_9_E5_FLOAT = 32,
199 TFMT4_10_10_10_2_UNORM = 33,
200 TFMT4_10_10_10_2_UINT = 34,
201 TFMT4_11_11_10_FLOAT = 37,
202 TFMT4_16_16_UNORM = 38,
203 TFMT4_16_16_SNORM = 39,
204 TFMT4_16_16_FLOAT = 40,
205 TFMT4_16_16_UINT = 41,
206 TFMT4_16_16_SINT = 42,
207 TFMT4_32_FLOAT = 43,
208 TFMT4_32_UINT = 44,
209 TFMT4_32_SINT = 45,
210 TFMT4_16_16_16_16_UNORM = 51,
211 TFMT4_16_16_16_16_SNORM = 52,
212 TFMT4_16_16_16_16_FLOAT = 53,
213 TFMT4_16_16_16_16_UINT = 54,
214 TFMT4_16_16_16_16_SINT = 55,
215 TFMT4_32_32_FLOAT = 56,
216 TFMT4_32_32_UINT = 57,
217 TFMT4_32_32_SINT = 58,
218 TFMT4_32_32_32_FLOAT = 59,
219 TFMT4_32_32_32_UINT = 60,
220 TFMT4_32_32_32_SINT = 61,
221 TFMT4_32_32_32_32_FLOAT = 63,
222 TFMT4_32_32_32_32_UINT = 64,
223 TFMT4_32_32_32_32_SINT = 65,
224 TFMT4_X8Z24_UNORM = 71,
225 TFMT4_DXT1 = 86,
226 TFMT4_DXT3 = 87,
227 TFMT4_DXT5 = 88,
228 TFMT4_RGTC1_UNORM = 90,
229 TFMT4_RGTC1_SNORM = 91,
230 TFMT4_RGTC2_UNORM = 94,
231 TFMT4_RGTC2_SNORM = 95,
232 TFMT4_BPTC_UFLOAT = 97,
233 TFMT4_BPTC_FLOAT = 98,
234 TFMT4_BPTC = 99,
235 TFMT4_ATC_RGB = 100,
236 TFMT4_ATC_RGBA_EXPLICIT = 101,
237 TFMT4_ATC_RGBA_INTERPOLATED = 102,
238 TFMT4_ETC2_RG11_UNORM = 103,
239 TFMT4_ETC2_RG11_SNORM = 104,
240 TFMT4_ETC2_R11_UNORM = 105,
241 TFMT4_ETC2_R11_SNORM = 106,
242 TFMT4_ETC1 = 107,
243 TFMT4_ETC2_RGB8 = 108,
244 TFMT4_ETC2_RGBA8 = 109,
245 TFMT4_ETC2_RGB8A1 = 110,
246 TFMT4_ASTC_4x4 = 111,
247 TFMT4_ASTC_5x4 = 112,
248 TFMT4_ASTC_5x5 = 113,
249 TFMT4_ASTC_6x5 = 114,
250 TFMT4_ASTC_6x6 = 115,
251 TFMT4_ASTC_8x5 = 116,
252 TFMT4_ASTC_8x6 = 117,
253 TFMT4_ASTC_8x8 = 118,
254 TFMT4_ASTC_10x5 = 119,
255 TFMT4_ASTC_10x6 = 120,
256 TFMT4_ASTC_10x8 = 121,
257 TFMT4_ASTC_10x10 = 122,
258 TFMT4_ASTC_12x10 = 123,
259 TFMT4_ASTC_12x12 = 124,
260 TFMT4_NONE = 255,
261};
262
263enum a4xx_depth_format {
264 DEPTH4_NONE = 0,
265 DEPTH4_16 = 1,
266 DEPTH4_24_8 = 2,
267 DEPTH4_32 = 3,
268};
269
270enum a4xx_ccu_perfcounter_select {
271 CCU_BUSY_CYCLES = 0,
272 CCU_RB_DEPTH_RETURN_STALL = 2,
273 CCU_RB_COLOR_RETURN_STALL = 3,
274 CCU_DEPTH_BLOCKS = 6,
275 CCU_COLOR_BLOCKS = 7,
276 CCU_DEPTH_BLOCK_HIT = 8,
277 CCU_COLOR_BLOCK_HIT = 9,
278 CCU_DEPTH_FLAG1_COUNT = 10,
279 CCU_DEPTH_FLAG2_COUNT = 11,
280 CCU_DEPTH_FLAG3_COUNT = 12,
281 CCU_DEPTH_FLAG4_COUNT = 13,
282 CCU_COLOR_FLAG1_COUNT = 14,
283 CCU_COLOR_FLAG2_COUNT = 15,
284 CCU_COLOR_FLAG3_COUNT = 16,
285 CCU_COLOR_FLAG4_COUNT = 17,
286 CCU_PARTIAL_BLOCK_READ = 18,
287};
288
289enum a4xx_cp_perfcounter_select {
290 CP_ALWAYS_COUNT = 0,
291 CP_BUSY = 1,
292 CP_PFP_IDLE = 2,
293 CP_PFP_BUSY_WORKING = 3,
294 CP_PFP_STALL_CYCLES_ANY = 4,
295 CP_PFP_STARVE_CYCLES_ANY = 5,
296 CP_PFP_STARVED_PER_LOAD_ADDR = 6,
297 CP_PFP_STALLED_PER_STORE_ADDR = 7,
298 CP_PFP_PC_PROFILE = 8,
299 CP_PFP_MATCH_PM4_PKT_PROFILE = 9,
300 CP_PFP_COND_INDIRECT_DISCARDED = 10,
301 CP_LONG_RESUMPTIONS = 11,
302 CP_RESUME_CYCLES = 12,
303 CP_RESUME_TO_BOUNDARY_CYCLES = 13,
304 CP_LONG_PREEMPTIONS = 14,
305 CP_PREEMPT_CYCLES = 15,
306 CP_PREEMPT_TO_BOUNDARY_CYCLES = 16,
307 CP_ME_FIFO_EMPTY_PFP_IDLE = 17,
308 CP_ME_FIFO_EMPTY_PFP_BUSY = 18,
309 CP_ME_FIFO_NOT_EMPTY_NOT_FULL = 19,
310 CP_ME_FIFO_FULL_ME_BUSY = 20,
311 CP_ME_FIFO_FULL_ME_NON_WORKING = 21,
312 CP_ME_WAITING_FOR_PACKETS = 22,
313 CP_ME_BUSY_WORKING = 23,
314 CP_ME_STARVE_CYCLES_ANY = 24,
315 CP_ME_STARVE_CYCLES_PER_PROFILE = 25,
316 CP_ME_STALL_CYCLES_PER_PROFILE = 26,
317 CP_ME_PC_PROFILE = 27,
318 CP_RCIU_FIFO_EMPTY = 28,
319 CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL = 29,
320 CP_RCIU_FIFO_FULL = 30,
321 CP_RCIU_FIFO_FULL_NO_CONTEXT = 31,
322 CP_RCIU_FIFO_FULL_AHB_MASTER = 32,
323 CP_RCIU_FIFO_FULL_OTHER = 33,
324 CP_AHB_IDLE = 34,
325 CP_AHB_STALL_ON_GRANT_NO_SPLIT = 35,
326 CP_AHB_STALL_ON_GRANT_SPLIT = 36,
327 CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE = 37,
328 CP_AHB_BUSY_WORKING = 38,
329 CP_AHB_BUSY_STALL_ON_HRDY = 39,
330 CP_AHB_BUSY_STALL_ON_HRDY_PROFILE = 40,
331};
332
333enum a4xx_gras_ras_perfcounter_select {
334 RAS_SUPER_TILES = 0,
335 RAS_8X8_TILES = 1,
336 RAS_4X4_TILES = 2,
337 RAS_BUSY_CYCLES = 3,
338 RAS_STALL_CYCLES_BY_RB = 4,
339 RAS_STALL_CYCLES_BY_VSC = 5,
340 RAS_STARVE_CYCLES_BY_TSE = 6,
341 RAS_SUPERTILE_CYCLES = 7,
342 RAS_TILE_CYCLES = 8,
343 RAS_FULLY_COVERED_SUPER_TILES = 9,
344 RAS_FULLY_COVERED_8X8_TILES = 10,
345 RAS_4X4_PRIM = 11,
346 RAS_8X4_4X8_PRIM = 12,
347 RAS_8X8_PRIM = 13,
348};
349
350enum a4xx_gras_tse_perfcounter_select {
351 TSE_INPUT_PRIM = 0,
352 TSE_INPUT_NULL_PRIM = 1,
353 TSE_TRIVAL_REJ_PRIM = 2,
354 TSE_CLIPPED_PRIM = 3,
355 TSE_NEW_PRIM = 4,
356 TSE_ZERO_AREA_PRIM = 5,
357 TSE_FACENESS_CULLED_PRIM = 6,
358 TSE_ZERO_PIXEL_PRIM = 7,
359 TSE_OUTPUT_NULL_PRIM = 8,
360 TSE_OUTPUT_VISIBLE_PRIM = 9,
361 TSE_PRE_CLIP_PRIM = 10,
362 TSE_POST_CLIP_PRIM = 11,
363 TSE_BUSY_CYCLES = 12,
364 TSE_PC_STARVE = 13,
365 TSE_RAS_STALL = 14,
366 TSE_STALL_BARYPLANE_FIFO_FULL = 15,
367 TSE_STALL_ZPLANE_FIFO_FULL = 16,
368};
369
370enum a4xx_hlsq_perfcounter_select {
371 HLSQ_SP_VS_STAGE_CONSTANT = 0,
372 HLSQ_SP_VS_STAGE_INSTRUCTIONS = 1,
373 HLSQ_SP_FS_STAGE_CONSTANT = 2,
374 HLSQ_SP_FS_STAGE_INSTRUCTIONS = 3,
375 HLSQ_TP_STATE = 4,
376 HLSQ_QUADS = 5,
377 HLSQ_PIXELS = 6,
378 HLSQ_VERTICES = 7,
379 HLSQ_SP_VS_STAGE_DATA_BYTES = 13,
380 HLSQ_SP_FS_STAGE_DATA_BYTES = 14,
381 HLSQ_BUSY_CYCLES = 15,
382 HLSQ_STALL_CYCLES_SP_STATE = 16,
383 HLSQ_STALL_CYCLES_SP_VS_STAGE = 17,
384 HLSQ_STALL_CYCLES_SP_FS_STAGE = 18,
385 HLSQ_STALL_CYCLES_UCHE = 19,
386 HLSQ_RBBM_LOAD_CYCLES = 20,
387 HLSQ_DI_TO_VS_START_SP = 21,
388 HLSQ_DI_TO_FS_START_SP = 22,
389 HLSQ_VS_STAGE_START_TO_DONE_SP = 23,
390 HLSQ_FS_STAGE_START_TO_DONE_SP = 24,
391 HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE = 25,
392 HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE = 26,
393 HLSQ_UCHE_LATENCY_CYCLES = 27,
394 HLSQ_UCHE_LATENCY_COUNT = 28,
395 HLSQ_STARVE_CYCLES_VFD = 29,
396};
397
398enum a4xx_pc_perfcounter_select {
399 PC_VIS_STREAMS_LOADED = 0,
400 PC_VPC_PRIMITIVES = 2,
401 PC_DEAD_PRIM = 3,
402 PC_LIVE_PRIM = 4,
403 PC_DEAD_DRAWCALLS = 5,
404 PC_LIVE_DRAWCALLS = 6,
405 PC_VERTEX_MISSES = 7,
406 PC_STALL_CYCLES_VFD = 9,
407 PC_STALL_CYCLES_TSE = 10,
408 PC_STALL_CYCLES_UCHE = 11,
409 PC_WORKING_CYCLES = 12,
410 PC_IA_VERTICES = 13,
411 PC_GS_PRIMITIVES = 14,
412 PC_HS_INVOCATIONS = 15,
413 PC_DS_INVOCATIONS = 16,
414 PC_DS_PRIMITIVES = 17,
415 PC_STARVE_CYCLES_FOR_INDEX = 20,
416 PC_STARVE_CYCLES_FOR_TESS_FACTOR = 21,
417 PC_STARVE_CYCLES_FOR_VIZ_STREAM = 22,
418 PC_STALL_CYCLES_TESS = 23,
419 PC_STARVE_CYCLES_FOR_POSITION = 24,
420 PC_MODE0_DRAWCALL = 25,
421 PC_MODE1_DRAWCALL = 26,
422 PC_MODE2_DRAWCALL = 27,
423 PC_MODE3_DRAWCALL = 28,
424 PC_MODE4_DRAWCALL = 29,
425 PC_PREDICATED_DEAD_DRAWCALL = 30,
426 PC_STALL_CYCLES_BY_TSE_ONLY = 31,
427 PC_STALL_CYCLES_BY_VPC_ONLY = 32,
428 PC_VPC_POS_DATA_TRANSACTION = 33,
429 PC_BUSY_CYCLES = 34,
430 PC_STARVE_CYCLES_DI = 35,
431 PC_STALL_CYCLES_VPC = 36,
432 TESS_WORKING_CYCLES = 37,
433 TESS_NUM_CYCLES_SETUP_WORKING = 38,
434 TESS_NUM_CYCLES_PTGEN_WORKING = 39,
435 TESS_NUM_CYCLES_CONNGEN_WORKING = 40,
436 TESS_BUSY_CYCLES = 41,
437 TESS_STARVE_CYCLES_PC = 42,
438 TESS_STALL_CYCLES_PC = 43,
439};
440
441enum a4xx_pwr_perfcounter_select {
442 PWR_CORE_CLOCK_CYCLES = 0,
443 PWR_BUSY_CLOCK_CYCLES = 1,
444};
445
446enum a4xx_rb_perfcounter_select {
447 RB_BUSY_CYCLES = 0,
448 RB_BUSY_CYCLES_BINNING = 1,
449 RB_BUSY_CYCLES_RENDERING = 2,
450 RB_BUSY_CYCLES_RESOLVE = 3,
451 RB_STARVE_CYCLES_BY_SP = 4,
452 RB_STARVE_CYCLES_BY_RAS = 5,
453 RB_STARVE_CYCLES_BY_MARB = 6,
454 RB_STALL_CYCLES_BY_MARB = 7,
455 RB_STALL_CYCLES_BY_HLSQ = 8,
456 RB_RB_RB_MARB_DATA = 9,
457 RB_SP_RB_QUAD = 10,
458 RB_RAS_RB_Z_QUADS = 11,
459 RB_GMEM_CH0_READ = 12,
460 RB_GMEM_CH1_READ = 13,
461 RB_GMEM_CH0_WRITE = 14,
462 RB_GMEM_CH1_WRITE = 15,
463 RB_CP_CONTEXT_DONE = 16,
464 RB_CP_CACHE_FLUSH = 17,
465 RB_CP_ZPASS_DONE = 18,
466 RB_STALL_FIFO0_FULL = 19,
467 RB_STALL_FIFO1_FULL = 20,
468 RB_STALL_FIFO2_FULL = 21,
469 RB_STALL_FIFO3_FULL = 22,
470 RB_RB_HLSQ_TRANSACTIONS = 23,
471 RB_Z_READ = 24,
472 RB_Z_WRITE = 25,
473 RB_C_READ = 26,
474 RB_C_WRITE = 27,
475 RB_C_READ_LATENCY = 28,
476 RB_Z_READ_LATENCY = 29,
477 RB_STALL_BY_UCHE = 30,
478 RB_MARB_UCHE_TRANSACTIONS = 31,
479 RB_CACHE_STALL_MISS = 32,
480 RB_CACHE_STALL_FIFO_FULL = 33,
481 RB_8BIT_BLENDER_UNITS_ACTIVE = 34,
482 RB_16BIT_BLENDER_UNITS_ACTIVE = 35,
483 RB_SAMPLER_UNITS_ACTIVE = 36,
484 RB_TOTAL_PASS = 38,
485 RB_Z_PASS = 39,
486 RB_Z_FAIL = 40,
487 RB_S_FAIL = 41,
488 RB_POWER0 = 42,
489 RB_POWER1 = 43,
490 RB_POWER2 = 44,
491 RB_POWER3 = 45,
492 RB_POWER4 = 46,
493 RB_POWER5 = 47,
494 RB_POWER6 = 48,
495 RB_POWER7 = 49,
496};
497
498enum a4xx_rbbm_perfcounter_select {
499 RBBM_ALWAYS_ON = 0,
500 RBBM_VBIF_BUSY = 1,
501 RBBM_TSE_BUSY = 2,
502 RBBM_RAS_BUSY = 3,
503 RBBM_PC_DCALL_BUSY = 4,
504 RBBM_PC_VSD_BUSY = 5,
505 RBBM_VFD_BUSY = 6,
506 RBBM_VPC_BUSY = 7,
507 RBBM_UCHE_BUSY = 8,
508 RBBM_VSC_BUSY = 9,
509 RBBM_HLSQ_BUSY = 10,
510 RBBM_ANY_RB_BUSY = 11,
511 RBBM_ANY_TPL1_BUSY = 12,
512 RBBM_ANY_SP_BUSY = 13,
513 RBBM_ANY_MARB_BUSY = 14,
514 RBBM_ANY_ARB_BUSY = 15,
515 RBBM_AHB_STATUS_BUSY = 16,
516 RBBM_AHB_STATUS_STALLED = 17,
517 RBBM_AHB_STATUS_TXFR = 18,
518 RBBM_AHB_STATUS_TXFR_SPLIT = 19,
519 RBBM_AHB_STATUS_TXFR_ERROR = 20,
520 RBBM_AHB_STATUS_LONG_STALL = 21,
521 RBBM_STATUS_MASKED = 22,
522 RBBM_CP_BUSY_GFX_CORE_IDLE = 23,
523 RBBM_TESS_BUSY = 24,
524 RBBM_COM_BUSY = 25,
525 RBBM_DCOM_BUSY = 32,
526 RBBM_ANY_CCU_BUSY = 33,
527 RBBM_DPM_BUSY = 34,
528};
529
530enum a4xx_sp_perfcounter_select {
531 SP_LM_LOAD_INSTRUCTIONS = 0,
532 SP_LM_STORE_INSTRUCTIONS = 1,
533 SP_LM_ATOMICS = 2,
534 SP_GM_LOAD_INSTRUCTIONS = 3,
535 SP_GM_STORE_INSTRUCTIONS = 4,
536 SP_GM_ATOMICS = 5,
537 SP_VS_STAGE_TEX_INSTRUCTIONS = 6,
538 SP_VS_STAGE_CFLOW_INSTRUCTIONS = 7,
539 SP_VS_STAGE_EFU_INSTRUCTIONS = 8,
540 SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 9,
541 SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 10,
542 SP_FS_STAGE_TEX_INSTRUCTIONS = 11,
543 SP_FS_STAGE_CFLOW_INSTRUCTIONS = 12,
544 SP_FS_STAGE_EFU_INSTRUCTIONS = 13,
545 SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 14,
546 SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 15,
547 SP_VS_INSTRUCTIONS = 17,
548 SP_FS_INSTRUCTIONS = 18,
549 SP_ADDR_LOCK_COUNT = 19,
550 SP_UCHE_READ_TRANS = 20,
551 SP_UCHE_WRITE_TRANS = 21,
552 SP_EXPORT_VPC_TRANS = 22,
553 SP_EXPORT_RB_TRANS = 23,
554 SP_PIXELS_KILLED = 24,
555 SP_ICL1_REQUESTS = 25,
556 SP_ICL1_MISSES = 26,
557 SP_ICL0_REQUESTS = 27,
558 SP_ICL0_MISSES = 28,
559 SP_ALU_WORKING_CYCLES = 29,
560 SP_EFU_WORKING_CYCLES = 30,
561 SP_STALL_CYCLES_BY_VPC = 31,
562 SP_STALL_CYCLES_BY_TP = 32,
563 SP_STALL_CYCLES_BY_UCHE = 33,
564 SP_STALL_CYCLES_BY_RB = 34,
565 SP_BUSY_CYCLES = 35,
566 SP_HS_INSTRUCTIONS = 36,
567 SP_DS_INSTRUCTIONS = 37,
568 SP_GS_INSTRUCTIONS = 38,
569 SP_CS_INSTRUCTIONS = 39,
570 SP_SCHEDULER_NON_WORKING = 40,
571 SP_WAVE_CONTEXTS = 41,
572 SP_WAVE_CONTEXT_CYCLES = 42,
573 SP_POWER0 = 43,
574 SP_POWER1 = 44,
575 SP_POWER2 = 45,
576 SP_POWER3 = 46,
577 SP_POWER4 = 47,
578 SP_POWER5 = 48,
579 SP_POWER6 = 49,
580 SP_POWER7 = 50,
581 SP_POWER8 = 51,
582 SP_POWER9 = 52,
583 SP_POWER10 = 53,
584 SP_POWER11 = 54,
585 SP_POWER12 = 55,
586 SP_POWER13 = 56,
587 SP_POWER14 = 57,
588 SP_POWER15 = 58,
589};
590
591enum a4xx_tp_perfcounter_select {
592 TP_L1_REQUESTS = 0,
593 TP_L1_MISSES = 1,
594 TP_QUADS_OFFSET = 8,
595 TP_QUAD_SHADOW = 9,
596 TP_QUADS_ARRAY = 10,
597 TP_QUADS_GRADIENT = 11,
598 TP_QUADS_1D2D = 12,
599 TP_QUADS_3DCUBE = 13,
600 TP_BUSY_CYCLES = 16,
601 TP_STALL_CYCLES_BY_ARB = 17,
602 TP_STATE_CACHE_REQUESTS = 20,
603 TP_STATE_CACHE_MISSES = 21,
604 TP_POWER0 = 22,
605 TP_POWER1 = 23,
606 TP_POWER2 = 24,
607 TP_POWER3 = 25,
608 TP_POWER4 = 26,
609 TP_POWER5 = 27,
610 TP_POWER6 = 28,
611 TP_POWER7 = 29,
612};
613
614enum a4xx_uche_perfcounter_select {
615 UCHE_VBIF_READ_BEATS_TP = 0,
616 UCHE_VBIF_READ_BEATS_VFD = 1,
617 UCHE_VBIF_READ_BEATS_HLSQ = 2,
618 UCHE_VBIF_READ_BEATS_MARB = 3,
619 UCHE_VBIF_READ_BEATS_SP = 4,
620 UCHE_READ_REQUESTS_TP = 5,
621 UCHE_READ_REQUESTS_VFD = 6,
622 UCHE_READ_REQUESTS_HLSQ = 7,
623 UCHE_READ_REQUESTS_MARB = 8,
624 UCHE_READ_REQUESTS_SP = 9,
625 UCHE_WRITE_REQUESTS_MARB = 10,
626 UCHE_WRITE_REQUESTS_SP = 11,
627 UCHE_TAG_CHECK_FAILS = 12,
628 UCHE_EVICTS = 13,
629 UCHE_FLUSHES = 14,
630 UCHE_VBIF_LATENCY_CYCLES = 15,
631 UCHE_VBIF_LATENCY_SAMPLES = 16,
632 UCHE_BUSY_CYCLES = 17,
633 UCHE_VBIF_READ_BEATS_PC = 18,
634 UCHE_READ_REQUESTS_PC = 19,
635 UCHE_WRITE_REQUESTS_VPC = 20,
636 UCHE_STALL_BY_VBIF = 21,
637 UCHE_WRITE_REQUESTS_VSC = 22,
638 UCHE_POWER0 = 23,
639 UCHE_POWER1 = 24,
640 UCHE_POWER2 = 25,
641 UCHE_POWER3 = 26,
642 UCHE_POWER4 = 27,
643 UCHE_POWER5 = 28,
644 UCHE_POWER6 = 29,
645 UCHE_POWER7 = 30,
646};
647
648enum a4xx_vbif_perfcounter_select {
649 AXI_READ_REQUESTS_ID_0 = 0,
650 AXI_READ_REQUESTS_ID_1 = 1,
651 AXI_READ_REQUESTS_ID_2 = 2,
652 AXI_READ_REQUESTS_ID_3 = 3,
653 AXI_READ_REQUESTS_ID_4 = 4,
654 AXI_READ_REQUESTS_ID_5 = 5,
655 AXI_READ_REQUESTS_ID_6 = 6,
656 AXI_READ_REQUESTS_ID_7 = 7,
657 AXI_READ_REQUESTS_ID_8 = 8,
658 AXI_READ_REQUESTS_ID_9 = 9,
659 AXI_READ_REQUESTS_ID_10 = 10,
660 AXI_READ_REQUESTS_ID_11 = 11,
661 AXI_READ_REQUESTS_ID_12 = 12,
662 AXI_READ_REQUESTS_ID_13 = 13,
663 AXI_READ_REQUESTS_ID_14 = 14,
664 AXI_READ_REQUESTS_ID_15 = 15,
665 AXI0_READ_REQUESTS_TOTAL = 16,
666 AXI1_READ_REQUESTS_TOTAL = 17,
667 AXI2_READ_REQUESTS_TOTAL = 18,
668 AXI3_READ_REQUESTS_TOTAL = 19,
669 AXI_READ_REQUESTS_TOTAL = 20,
670 AXI_WRITE_REQUESTS_ID_0 = 21,
671 AXI_WRITE_REQUESTS_ID_1 = 22,
672 AXI_WRITE_REQUESTS_ID_2 = 23,
673 AXI_WRITE_REQUESTS_ID_3 = 24,
674 AXI_WRITE_REQUESTS_ID_4 = 25,
675 AXI_WRITE_REQUESTS_ID_5 = 26,
676 AXI_WRITE_REQUESTS_ID_6 = 27,
677 AXI_WRITE_REQUESTS_ID_7 = 28,
678 AXI_WRITE_REQUESTS_ID_8 = 29,
679 AXI_WRITE_REQUESTS_ID_9 = 30,
680 AXI_WRITE_REQUESTS_ID_10 = 31,
681 AXI_WRITE_REQUESTS_ID_11 = 32,
682 AXI_WRITE_REQUESTS_ID_12 = 33,
683 AXI_WRITE_REQUESTS_ID_13 = 34,
684 AXI_WRITE_REQUESTS_ID_14 = 35,
685 AXI_WRITE_REQUESTS_ID_15 = 36,
686 AXI0_WRITE_REQUESTS_TOTAL = 37,
687 AXI1_WRITE_REQUESTS_TOTAL = 38,
688 AXI2_WRITE_REQUESTS_TOTAL = 39,
689 AXI3_WRITE_REQUESTS_TOTAL = 40,
690 AXI_WRITE_REQUESTS_TOTAL = 41,
691 AXI_TOTAL_REQUESTS = 42,
692 AXI_READ_DATA_BEATS_ID_0 = 43,
693 AXI_READ_DATA_BEATS_ID_1 = 44,
694 AXI_READ_DATA_BEATS_ID_2 = 45,
695 AXI_READ_DATA_BEATS_ID_3 = 46,
696 AXI_READ_DATA_BEATS_ID_4 = 47,
697 AXI_READ_DATA_BEATS_ID_5 = 48,
698 AXI_READ_DATA_BEATS_ID_6 = 49,
699 AXI_READ_DATA_BEATS_ID_7 = 50,
700 AXI_READ_DATA_BEATS_ID_8 = 51,
701 AXI_READ_DATA_BEATS_ID_9 = 52,
702 AXI_READ_DATA_BEATS_ID_10 = 53,
703 AXI_READ_DATA_BEATS_ID_11 = 54,
704 AXI_READ_DATA_BEATS_ID_12 = 55,
705 AXI_READ_DATA_BEATS_ID_13 = 56,
706 AXI_READ_DATA_BEATS_ID_14 = 57,
707 AXI_READ_DATA_BEATS_ID_15 = 58,
708 AXI0_READ_DATA_BEATS_TOTAL = 59,
709 AXI1_READ_DATA_BEATS_TOTAL = 60,
710 AXI2_READ_DATA_BEATS_TOTAL = 61,
711 AXI3_READ_DATA_BEATS_TOTAL = 62,
712 AXI_READ_DATA_BEATS_TOTAL = 63,
713 AXI_WRITE_DATA_BEATS_ID_0 = 64,
714 AXI_WRITE_DATA_BEATS_ID_1 = 65,
715 AXI_WRITE_DATA_BEATS_ID_2 = 66,
716 AXI_WRITE_DATA_BEATS_ID_3 = 67,
717 AXI_WRITE_DATA_BEATS_ID_4 = 68,
718 AXI_WRITE_DATA_BEATS_ID_5 = 69,
719 AXI_WRITE_DATA_BEATS_ID_6 = 70,
720 AXI_WRITE_DATA_BEATS_ID_7 = 71,
721 AXI_WRITE_DATA_BEATS_ID_8 = 72,
722 AXI_WRITE_DATA_BEATS_ID_9 = 73,
723 AXI_WRITE_DATA_BEATS_ID_10 = 74,
724 AXI_WRITE_DATA_BEATS_ID_11 = 75,
725 AXI_WRITE_DATA_BEATS_ID_12 = 76,
726 AXI_WRITE_DATA_BEATS_ID_13 = 77,
727 AXI_WRITE_DATA_BEATS_ID_14 = 78,
728 AXI_WRITE_DATA_BEATS_ID_15 = 79,
729 AXI0_WRITE_DATA_BEATS_TOTAL = 80,
730 AXI1_WRITE_DATA_BEATS_TOTAL = 81,
731 AXI2_WRITE_DATA_BEATS_TOTAL = 82,
732 AXI3_WRITE_DATA_BEATS_TOTAL = 83,
733 AXI_WRITE_DATA_BEATS_TOTAL = 84,
734 AXI_DATA_BEATS_TOTAL = 85,
735 CYCLES_HELD_OFF_ID_0 = 86,
736 CYCLES_HELD_OFF_ID_1 = 87,
737 CYCLES_HELD_OFF_ID_2 = 88,
738 CYCLES_HELD_OFF_ID_3 = 89,
739 CYCLES_HELD_OFF_ID_4 = 90,
740 CYCLES_HELD_OFF_ID_5 = 91,
741 CYCLES_HELD_OFF_ID_6 = 92,
742 CYCLES_HELD_OFF_ID_7 = 93,
743 CYCLES_HELD_OFF_ID_8 = 94,
744 CYCLES_HELD_OFF_ID_9 = 95,
745 CYCLES_HELD_OFF_ID_10 = 96,
746 CYCLES_HELD_OFF_ID_11 = 97,
747 CYCLES_HELD_OFF_ID_12 = 98,
748 CYCLES_HELD_OFF_ID_13 = 99,
749 CYCLES_HELD_OFF_ID_14 = 100,
750 CYCLES_HELD_OFF_ID_15 = 101,
751 AXI_READ_REQUEST_HELD_OFF = 102,
752 AXI_WRITE_REQUEST_HELD_OFF = 103,
753 AXI_REQUEST_HELD_OFF = 104,
754 AXI_WRITE_DATA_HELD_OFF = 105,
755 OCMEM_AXI_READ_REQUEST_HELD_OFF = 106,
756 OCMEM_AXI_WRITE_REQUEST_HELD_OFF = 107,
757 OCMEM_AXI_REQUEST_HELD_OFF = 108,
758 OCMEM_AXI_WRITE_DATA_HELD_OFF = 109,
759 ELAPSED_CYCLES_DDR = 110,
760 ELAPSED_CYCLES_OCMEM = 111,
761};
762
763enum a4xx_vfd_perfcounter_select {
764 VFD_UCHE_BYTE_FETCHED = 0,
765 VFD_UCHE_TRANS = 1,
766 VFD_FETCH_INSTRUCTIONS = 3,
767 VFD_BUSY_CYCLES = 5,
768 VFD_STALL_CYCLES_UCHE = 6,
769 VFD_STALL_CYCLES_HLSQ = 7,
770 VFD_STALL_CYCLES_VPC_BYPASS = 8,
771 VFD_STALL_CYCLES_VPC_ALLOC = 9,
772 VFD_MODE_0_FIBERS = 13,
773 VFD_MODE_1_FIBERS = 14,
774 VFD_MODE_2_FIBERS = 15,
775 VFD_MODE_3_FIBERS = 16,
776 VFD_MODE_4_FIBERS = 17,
777 VFD_BFIFO_STALL = 18,
778 VFD_NUM_VERTICES_TOTAL = 19,
779 VFD_PACKER_FULL = 20,
780 VFD_UCHE_REQUEST_FIFO_FULL = 21,
781 VFD_STARVE_CYCLES_PC = 22,
782 VFD_STARVE_CYCLES_UCHE = 23,
783};
784
785enum a4xx_vpc_perfcounter_select {
786 VPC_SP_LM_COMPONENTS = 2,
787 VPC_SP0_LM_BYTES = 3,
788 VPC_SP1_LM_BYTES = 4,
789 VPC_SP2_LM_BYTES = 5,
790 VPC_SP3_LM_BYTES = 6,
791 VPC_WORKING_CYCLES = 7,
792 VPC_STALL_CYCLES_LM = 8,
793 VPC_STARVE_CYCLES_RAS = 9,
794 VPC_STREAMOUT_CYCLES = 10,
795 VPC_UCHE_TRANSACTIONS = 12,
796 VPC_STALL_CYCLES_UCHE = 13,
797 VPC_BUSY_CYCLES = 14,
798 VPC_STARVE_CYCLES_SP = 15,
799};
800
801enum a4xx_vsc_perfcounter_select {
802 VSC_BUSY_CYCLES = 0,
803 VSC_WORKING_CYCLES = 1,
804 VSC_STALL_CYCLES_UCHE = 2,
805 VSC_STARVE_CYCLES_RAS = 3,
806 VSC_EOT_NUM = 4,
807};
808
809enum a4xx_tex_filter {
810 A4XX_TEX_NEAREST = 0,
811 A4XX_TEX_LINEAR = 1,
812 A4XX_TEX_ANISO = 2,
813};
814
815enum a4xx_tex_clamp {
816 A4XX_TEX_REPEAT = 0,
817 A4XX_TEX_CLAMP_TO_EDGE = 1,
818 A4XX_TEX_MIRROR_REPEAT = 2,
819 A4XX_TEX_CLAMP_TO_BORDER = 3,
820 A4XX_TEX_MIRROR_CLAMP = 4,
821};
822
823enum a4xx_tex_aniso {
824 A4XX_TEX_ANISO_1 = 0,
825 A4XX_TEX_ANISO_2 = 1,
826 A4XX_TEX_ANISO_4 = 2,
827 A4XX_TEX_ANISO_8 = 3,
828 A4XX_TEX_ANISO_16 = 4,
829};
830
831enum a4xx_tex_swiz {
832 A4XX_TEX_X = 0,
833 A4XX_TEX_Y = 1,
834 A4XX_TEX_Z = 2,
835 A4XX_TEX_W = 3,
836 A4XX_TEX_ZERO = 4,
837 A4XX_TEX_ONE = 5,
838};
839
840enum a4xx_tex_type {
841 A4XX_TEX_1D = 0,
842 A4XX_TEX_2D = 1,
843 A4XX_TEX_CUBE = 2,
844 A4XX_TEX_3D = 3,
845 A4XX_TEX_BUFFER = 4,
846};
847
848#define A4XX_CGC_HLSQ_EARLY_CYC__MASK 0x00700000
849#define A4XX_CGC_HLSQ_EARLY_CYC__SHIFT 20
850static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val)
851{
852 return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK;
853}
854
855#define A4XX_INT0_RBBM_GPU_IDLE 0x00000001
856#define A4XX_INT0_RBBM_AHB_ERROR 0x00000002
857#define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004
858#define A4XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
859#define A4XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
860#define A4XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020
861#define A4XX_INT0_VFD_ERROR 0x00000040
862#define A4XX_INT0_CP_SW_INT 0x00000080
863#define A4XX_INT0_CP_T0_PACKET_IN_IB 0x00000100
864#define A4XX_INT0_CP_OPCODE_ERROR 0x00000200
865#define A4XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400
866#define A4XX_INT0_CP_HW_FAULT 0x00000800
867#define A4XX_INT0_CP_DMA 0x00001000
868#define A4XX_INT0_CP_IB2_INT 0x00002000
869#define A4XX_INT0_CP_IB1_INT 0x00004000
870#define A4XX_INT0_CP_RB_INT 0x00008000
871#define A4XX_INT0_CP_REG_PROTECT_FAULT 0x00010000
872#define A4XX_INT0_CP_RB_DONE_TS 0x00020000
873#define A4XX_INT0_CP_VS_DONE_TS 0x00040000
874#define A4XX_INT0_CP_PS_DONE_TS 0x00080000
875#define A4XX_INT0_CACHE_FLUSH_TS 0x00100000
876#define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000
877#define A4XX_INT0_MISC_HANG_DETECT 0x01000000
878#define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000
879
880#define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0
881
882#define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7
883
884#define REG_A4XX_RB_PERFCTR_RB_SEL_1 0x00000cc8
885
886#define REG_A4XX_RB_PERFCTR_RB_SEL_2 0x00000cc9
887
888#define REG_A4XX_RB_PERFCTR_RB_SEL_3 0x00000cca
889
890#define REG_A4XX_RB_PERFCTR_RB_SEL_4 0x00000ccb
891
892#define REG_A4XX_RB_PERFCTR_RB_SEL_5 0x00000ccc
893
894#define REG_A4XX_RB_PERFCTR_RB_SEL_6 0x00000ccd
895
896#define REG_A4XX_RB_PERFCTR_RB_SEL_7 0x00000cce
897
898#define REG_A4XX_RB_PERFCTR_CCU_SEL_0 0x00000ccf
899
900#define REG_A4XX_RB_PERFCTR_CCU_SEL_1 0x00000cd0
901
902#define REG_A4XX_RB_PERFCTR_CCU_SEL_2 0x00000cd1
903
904#define REG_A4XX_RB_PERFCTR_CCU_SEL_3 0x00000cd2
905
906#define REG_A4XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
907#define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
908#define A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
909static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
910{
911 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
912}
913#define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x3fff0000
914#define A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 16
915static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
916{
917 return ((val) << A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
918}
919
920#define REG_A4XX_RB_CLEAR_COLOR_DW0 0x000020cc
921
922#define REG_A4XX_RB_CLEAR_COLOR_DW1 0x000020cd
923
924#define REG_A4XX_RB_CLEAR_COLOR_DW2 0x000020ce
925
926#define REG_A4XX_RB_CLEAR_COLOR_DW3 0x000020cf
927
928#define REG_A4XX_RB_MODE_CONTROL 0x000020a0
929#define A4XX_RB_MODE_CONTROL_WIDTH__MASK 0x0000003f
930#define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0
931static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val)
932{
933 assert(!(val & 0x1f));
934 return (((val >> 5)) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK;
935}
936#define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00
937#define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8
938static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val)
939{
940 assert(!(val & 0x1f));
941 return (((val >> 5)) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK;
942}
943#define A4XX_RB_MODE_CONTROL_ENABLE_GMEM 0x00010000
944
945#define REG_A4XX_RB_RENDER_CONTROL 0x000020a1
946#define A4XX_RB_RENDER_CONTROL_BINNING_PASS 0x00000001
947#define A4XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00000020
948
949#define REG_A4XX_RB_MSAA_CONTROL 0x000020a2
950#define A4XX_RB_MSAA_CONTROL_DISABLE 0x00001000
951#define A4XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000e000
952#define A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 13
953static inline uint32_t A4XX_RB_MSAA_CONTROL_SAMPLES(uint32_t val)
954{
955 return ((val) << A4XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A4XX_RB_MSAA_CONTROL_SAMPLES__MASK;
956}
957
958#define REG_A4XX_RB_RENDER_CONTROL2 0x000020a3
959#define A4XX_RB_RENDER_CONTROL2_COORD_MASK__MASK 0x0000000f
960#define A4XX_RB_RENDER_CONTROL2_COORD_MASK__SHIFT 0
961static inline uint32_t A4XX_RB_RENDER_CONTROL2_COORD_MASK(uint32_t val)
962{
963 return ((val) << A4XX_RB_RENDER_CONTROL2_COORD_MASK__SHIFT) & A4XX_RB_RENDER_CONTROL2_COORD_MASK__MASK;
964}
965#define A4XX_RB_RENDER_CONTROL2_SAMPLEMASK 0x00000010
966#define A4XX_RB_RENDER_CONTROL2_FACENESS 0x00000020
967#define A4XX_RB_RENDER_CONTROL2_SAMPLEID 0x00000040
968#define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK 0x00000380
969#define A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT 7
970static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val)
971{
972 return ((val) << A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__SHIFT) & A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES__MASK;
973}
974#define A4XX_RB_RENDER_CONTROL2_SAMPLEID_HR 0x00000800
975#define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_PIXEL 0x00001000
976#define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_CENTROID 0x00002000
977#define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_SAMPLE 0x00004000
978#define A4XX_RB_RENDER_CONTROL2_SIZE 0x00008000
979
980#define REG_A4XX_RB_MRT(i0) (0x000020a4 + 0x5*(i0))
981
982static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; }
983#define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
984#define A4XX_RB_MRT_CONTROL_BLEND 0x00000010
985#define A4XX_RB_MRT_CONTROL_BLEND2 0x00000020
986#define A4XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000040
987#define A4XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00
988#define A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8
989static inline uint32_t A4XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
990{
991 return ((val) << A4XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A4XX_RB_MRT_CONTROL_ROP_CODE__MASK;
992}
993#define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
994#define A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
995static inline uint32_t A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
996{
997 return ((val) << A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A4XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
998}
999
1000static inline uint32_t REG_A4XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020a5 + 0x5*i0; }
1001#define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f
1002#define A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
1003static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a4xx_color_fmt val)
1004{
1005 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
1006}
1007#define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0
1008#define A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6
1009static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a4xx_tile_mode val)
1010{
1011 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
1012}
1013#define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00000600
1014#define A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 9
1015static inline uint32_t A4XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
1016{
1017 return ((val) << A4XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A4XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
1018}
1019#define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00001800
1020#define A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 11
1021static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
1022{
1023 return ((val) << A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
1024}
1025#define A4XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00002000
1026#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xffffc000
1027#define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14
1028static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
1029{
1030 assert(!(val & 0xf));
1031 return (((val >> 4)) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
1032}
1033
1034static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; }
1035
1036static inline uint32_t REG_A4XX_RB_MRT_CONTROL3(uint32_t i0) { return 0x000020a7 + 0x5*i0; }
1037#define A4XX_RB_MRT_CONTROL3_STRIDE__MASK 0x03fffff8
1038#define A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT 3
1039static inline uint32_t A4XX_RB_MRT_CONTROL3_STRIDE(uint32_t val)
1040{
1041 return ((val) << A4XX_RB_MRT_CONTROL3_STRIDE__SHIFT) & A4XX_RB_MRT_CONTROL3_STRIDE__MASK;
1042}
1043
1044static inline uint32_t REG_A4XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020a8 + 0x5*i0; }
1045#define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
1046#define A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
1047static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
1048{
1049 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
1050}
1051#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
1052#define A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
1053static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
1054{
1055 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
1056}
1057#define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
1058#define A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
1059static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
1060{
1061 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
1062}
1063#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
1064#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
1065static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
1066{
1067 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
1068}
1069#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
1070#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
1071static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
1072{
1073 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
1074}
1075#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
1076#define A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
1077static inline uint32_t A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
1078{
1079 return ((val) << A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A4XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
1080}
1081
1082#define REG_A4XX_RB_BLEND_RED 0x000020f0
1083#define A4XX_RB_BLEND_RED_UINT__MASK 0x000000ff
1084#define A4XX_RB_BLEND_RED_UINT__SHIFT 0
1085static inline uint32_t A4XX_RB_BLEND_RED_UINT(uint32_t val)
1086{
1087 return ((val) << A4XX_RB_BLEND_RED_UINT__SHIFT) & A4XX_RB_BLEND_RED_UINT__MASK;
1088}
1089#define A4XX_RB_BLEND_RED_SINT__MASK 0x0000ff00
1090#define A4XX_RB_BLEND_RED_SINT__SHIFT 8
1091static inline uint32_t A4XX_RB_BLEND_RED_SINT(uint32_t val)
1092{
1093 return ((val) << A4XX_RB_BLEND_RED_SINT__SHIFT) & A4XX_RB_BLEND_RED_SINT__MASK;
1094}
1095#define A4XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
1096#define A4XX_RB_BLEND_RED_FLOAT__SHIFT 16
1097static inline uint32_t A4XX_RB_BLEND_RED_FLOAT(float val)
1098{
1099 return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_RED_FLOAT__SHIFT) & A4XX_RB_BLEND_RED_FLOAT__MASK;
1100}
1101
1102#define REG_A4XX_RB_BLEND_RED_F32 0x000020f1
1103#define A4XX_RB_BLEND_RED_F32__MASK 0xffffffff
1104#define A4XX_RB_BLEND_RED_F32__SHIFT 0
1105static inline uint32_t A4XX_RB_BLEND_RED_F32(float val)
1106{
1107 return ((fui(val)) << A4XX_RB_BLEND_RED_F32__SHIFT) & A4XX_RB_BLEND_RED_F32__MASK;
1108}
1109
1110#define REG_A4XX_RB_BLEND_GREEN 0x000020f2
1111#define A4XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
1112#define A4XX_RB_BLEND_GREEN_UINT__SHIFT 0
1113static inline uint32_t A4XX_RB_BLEND_GREEN_UINT(uint32_t val)
1114{
1115 return ((val) << A4XX_RB_BLEND_GREEN_UINT__SHIFT) & A4XX_RB_BLEND_GREEN_UINT__MASK;
1116}
1117#define A4XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00
1118#define A4XX_RB_BLEND_GREEN_SINT__SHIFT 8
1119static inline uint32_t A4XX_RB_BLEND_GREEN_SINT(uint32_t val)
1120{
1121 return ((val) << A4XX_RB_BLEND_GREEN_SINT__SHIFT) & A4XX_RB_BLEND_GREEN_SINT__MASK;
1122}
1123#define A4XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
1124#define A4XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
1125static inline uint32_t A4XX_RB_BLEND_GREEN_FLOAT(float val)
1126{
1127 return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A4XX_RB_BLEND_GREEN_FLOAT__MASK;
1128}
1129
1130#define REG_A4XX_RB_BLEND_GREEN_F32 0x000020f3
1131#define A4XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
1132#define A4XX_RB_BLEND_GREEN_F32__SHIFT 0
1133static inline uint32_t A4XX_RB_BLEND_GREEN_F32(float val)
1134{
1135 return ((fui(val)) << A4XX_RB_BLEND_GREEN_F32__SHIFT) & A4XX_RB_BLEND_GREEN_F32__MASK;
1136}
1137
1138#define REG_A4XX_RB_BLEND_BLUE 0x000020f4
1139#define A4XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
1140#define A4XX_RB_BLEND_BLUE_UINT__SHIFT 0
1141static inline uint32_t A4XX_RB_BLEND_BLUE_UINT(uint32_t val)
1142{
1143 return ((val) << A4XX_RB_BLEND_BLUE_UINT__SHIFT) & A4XX_RB_BLEND_BLUE_UINT__MASK;
1144}
1145#define A4XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00
1146#define A4XX_RB_BLEND_BLUE_SINT__SHIFT 8
1147static inline uint32_t A4XX_RB_BLEND_BLUE_SINT(uint32_t val)
1148{
1149 return ((val) << A4XX_RB_BLEND_BLUE_SINT__SHIFT) & A4XX_RB_BLEND_BLUE_SINT__MASK;
1150}
1151#define A4XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
1152#define A4XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
1153static inline uint32_t A4XX_RB_BLEND_BLUE_FLOAT(float val)
1154{
1155 return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A4XX_RB_BLEND_BLUE_FLOAT__MASK;
1156}
1157
1158#define REG_A4XX_RB_BLEND_BLUE_F32 0x000020f5
1159#define A4XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
1160#define A4XX_RB_BLEND_BLUE_F32__SHIFT 0
1161static inline uint32_t A4XX_RB_BLEND_BLUE_F32(float val)
1162{
1163 return ((fui(val)) << A4XX_RB_BLEND_BLUE_F32__SHIFT) & A4XX_RB_BLEND_BLUE_F32__MASK;
1164}
1165
1166#define REG_A4XX_RB_BLEND_ALPHA 0x000020f6
1167#define A4XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
1168#define A4XX_RB_BLEND_ALPHA_UINT__SHIFT 0
1169static inline uint32_t A4XX_RB_BLEND_ALPHA_UINT(uint32_t val)
1170{
1171 return ((val) << A4XX_RB_BLEND_ALPHA_UINT__SHIFT) & A4XX_RB_BLEND_ALPHA_UINT__MASK;
1172}
1173#define A4XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00
1174#define A4XX_RB_BLEND_ALPHA_SINT__SHIFT 8
1175static inline uint32_t A4XX_RB_BLEND_ALPHA_SINT(uint32_t val)
1176{
1177 return ((val) << A4XX_RB_BLEND_ALPHA_SINT__SHIFT) & A4XX_RB_BLEND_ALPHA_SINT__MASK;
1178}
1179#define A4XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
1180#define A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
1181static inline uint32_t A4XX_RB_BLEND_ALPHA_FLOAT(float val)
1182{
1183 return ((_mesa_float_to_half(val)) << A4XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A4XX_RB_BLEND_ALPHA_FLOAT__MASK;
1184}
1185
1186#define REG_A4XX_RB_BLEND_ALPHA_F32 0x000020f7
1187#define A4XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
1188#define A4XX_RB_BLEND_ALPHA_F32__SHIFT 0
1189static inline uint32_t A4XX_RB_BLEND_ALPHA_F32(float val)
1190{
1191 return ((fui(val)) << A4XX_RB_BLEND_ALPHA_F32__SHIFT) & A4XX_RB_BLEND_ALPHA_F32__MASK;
1192}
1193
1194#define REG_A4XX_RB_ALPHA_CONTROL 0x000020f8
1195#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
1196#define A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
1197static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
1198{
1199 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
1200}
1201#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
1202#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
1203#define A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
1204static inline uint32_t A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
1205{
1206 return ((val) << A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A4XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
1207}
1208
1209#define REG_A4XX_RB_FS_OUTPUT 0x000020f9
1210#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK 0x000000ff
1211#define A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT 0
1212static inline uint32_t A4XX_RB_FS_OUTPUT_ENABLE_BLEND(uint32_t val)
1213{
1214 return ((val) << A4XX_RB_FS_OUTPUT_ENABLE_BLEND__SHIFT) & A4XX_RB_FS_OUTPUT_ENABLE_BLEND__MASK;
1215}
1216#define A4XX_RB_FS_OUTPUT_INDEPENDENT_BLEND 0x00000100
1217#define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK 0xffff0000
1218#define A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT 16
1219static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val)
1220{
1221 return ((val) << A4XX_RB_FS_OUTPUT_SAMPLE_MASK__SHIFT) & A4XX_RB_FS_OUTPUT_SAMPLE_MASK__MASK;
1222}
1223
1224#define REG_A4XX_RB_SAMPLE_COUNT_CONTROL 0x000020fa
1225#define A4XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
1226#define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK 0xfffffffc
1227#define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2
1228static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val)
1229{
1230 assert(!(val & 0x3));
1231 return (((val >> 2)) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK;
1232}
1233
1234#define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb
1235#define A4XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
1236#define A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
1237static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
1238{
1239 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT0__MASK;
1240}
1241#define A4XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
1242#define A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
1243static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
1244{
1245 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT1__MASK;
1246}
1247#define A4XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
1248#define A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
1249static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
1250{
1251 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT2__MASK;
1252}
1253#define A4XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
1254#define A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
1255static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
1256{
1257 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT3__MASK;
1258}
1259#define A4XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
1260#define A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
1261static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
1262{
1263 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT4__MASK;
1264}
1265#define A4XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
1266#define A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
1267static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
1268{
1269 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT5__MASK;
1270}
1271#define A4XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
1272#define A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
1273static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
1274{
1275 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT6__MASK;
1276}
1277#define A4XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
1278#define A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
1279static inline uint32_t A4XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
1280{
1281 return ((val) << A4XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A4XX_RB_RENDER_COMPONENTS_RT7__MASK;
1282}
1283
1284#define REG_A4XX_RB_COPY_CONTROL 0x000020fc
1285#define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
1286#define A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0
1287static inline uint32_t A4XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
1288{
1289 return ((val) << A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A4XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
1290}
1291#define A4XX_RB_COPY_CONTROL_MODE__MASK 0x00000070
1292#define A4XX_RB_COPY_CONTROL_MODE__SHIFT 4
1293static inline uint32_t A4XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
1294{
1295 return ((val) << A4XX_RB_COPY_CONTROL_MODE__SHIFT) & A4XX_RB_COPY_CONTROL_MODE__MASK;
1296}
1297#define A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00
1298#define A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8
1299static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
1300{
1301 return ((val) << A4XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A4XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
1302}
1303#define A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000
1304#define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
1305static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
1306{
1307 assert(!(val & 0x3fff));
1308 return (((val >> 14)) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
1309}
1310
1311#define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd
1312#define A4XX_RB_COPY_DEST_BASE_BASE__MASK 0xffffffe0
1313#define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5
1314static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
1315{
1316 assert(!(val & 0x1f));
1317 return (((val >> 5)) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK;
1318}
1319
1320#define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe
1321#define A4XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff
1322#define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
1323static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
1324{
1325 assert(!(val & 0x1f));
1326 return (((val >> 5)) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK;
1327}
1328
1329#define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff
1330#define A4XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc
1331#define A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2
1332static inline uint32_t A4XX_RB_COPY_DEST_INFO_FORMAT(enum a4xx_color_fmt val)
1333{
1334 return ((val) << A4XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A4XX_RB_COPY_DEST_INFO_FORMAT__MASK;
1335}
1336#define A4XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
1337#define A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
1338static inline uint32_t A4XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
1339{
1340 return ((val) << A4XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A4XX_RB_COPY_DEST_INFO_SWAP__MASK;
1341}
1342#define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
1343#define A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10
1344static inline uint32_t A4XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
1345{
1346 return ((val) << A4XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A4XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
1347}
1348#define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
1349#define A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14
1350static inline uint32_t A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
1351{
1352 return ((val) << A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A4XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
1353}
1354#define A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000
1355#define A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18
1356static inline uint32_t A4XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
1357{
1358 return ((val) << A4XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A4XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
1359}
1360#define A4XX_RB_COPY_DEST_INFO_TILE__MASK 0x03000000
1361#define A4XX_RB_COPY_DEST_INFO_TILE__SHIFT 24
1362static inline uint32_t A4XX_RB_COPY_DEST_INFO_TILE(enum a4xx_tile_mode val)
1363{
1364 return ((val) << A4XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A4XX_RB_COPY_DEST_INFO_TILE__MASK;
1365}
1366
1367#define REG_A4XX_RB_FS_OUTPUT_REG 0x00002100
1368#define A4XX_RB_FS_OUTPUT_REG_MRT__MASK 0x0000000f
1369#define A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT 0
1370static inline uint32_t A4XX_RB_FS_OUTPUT_REG_MRT(uint32_t val)
1371{
1372 return ((val) << A4XX_RB_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_RB_FS_OUTPUT_REG_MRT__MASK;
1373}
1374#define A4XX_RB_FS_OUTPUT_REG_FRAG_WRITES_Z 0x00000020
1375
1376#define REG_A4XX_RB_DEPTH_CONTROL 0x00002101
1377#define A4XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
1378#define A4XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x00000002
1379#define A4XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
1380#define A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
1381#define A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
1382static inline uint32_t A4XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
1383{
1384 return ((val) << A4XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A4XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
1385}
1386#define A4XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080
1387#define A4XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00010000
1388#define A4XX_RB_DEPTH_CONTROL_FORCE_FRAGZ_TO_FS 0x00020000
1389#define A4XX_RB_DEPTH_CONTROL_Z_READ_ENABLE 0x80000000
1390
1391#define REG_A4XX_RB_DEPTH_CLEAR 0x00002102
1392
1393#define REG_A4XX_RB_DEPTH_INFO 0x00002103
1394#define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003
1395#define A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
1396static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format val)
1397{
1398 return ((val) << A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
1399}
1400#define A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000
1401#define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12
1402static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
1403{
1404 assert(!(val & 0xfff));
1405 return (((val >> 12)) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
1406}
1407
1408#define REG_A4XX_RB_DEPTH_PITCH 0x00002104
1409#define A4XX_RB_DEPTH_PITCH__MASK 0xffffffff
1410#define A4XX_RB_DEPTH_PITCH__SHIFT 0
1411static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val)
1412{
1413 assert(!(val & 0x1f));
1414 return (((val >> 5)) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK;
1415}
1416
1417#define REG_A4XX_RB_DEPTH_PITCH2 0x00002105
1418#define A4XX_RB_DEPTH_PITCH2__MASK 0xffffffff
1419#define A4XX_RB_DEPTH_PITCH2__SHIFT 0
1420static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val)
1421{
1422 assert(!(val & 0x1f));
1423 return (((val >> 5)) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK;
1424}
1425
1426#define REG_A4XX_RB_STENCIL_CONTROL 0x00002106
1427#define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
1428#define A4XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
1429#define A4XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
1430#define A4XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
1431#define A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
1432static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
1433{
1434 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC__MASK;
1435}
1436#define A4XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
1437#define A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
1438static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
1439{
1440 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL__MASK;
1441}
1442#define A4XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
1443#define A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
1444static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
1445{
1446 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS__MASK;
1447}
1448#define A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
1449#define A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
1450static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
1451{
1452 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
1453}
1454#define A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
1455#define A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
1456static inline uint32_t A4XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
1457{
1458 return ((val) << A4XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
1459}
1460#define A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
1461#define A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
1462static inline uint32_t A4XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
1463{
1464 return ((val) << A4XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
1465}
1466#define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
1467#define A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
1468static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
1469{
1470 return ((val) << A4XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
1471}
1472#define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
1473#define A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
1474static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
1475{
1476 return ((val) << A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A4XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
1477}
1478
1479#define REG_A4XX_RB_STENCIL_CONTROL2 0x00002107
1480#define A4XX_RB_STENCIL_CONTROL2_STENCIL_BUFFER 0x00000001
1481
1482#define REG_A4XX_RB_STENCIL_INFO 0x00002108
1483#define A4XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
1484#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff000
1485#define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12
1486static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
1487{
1488 assert(!(val & 0xfff));
1489 return (((val >> 12)) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
1490}
1491
1492#define REG_A4XX_RB_STENCIL_PITCH 0x00002109
1493#define A4XX_RB_STENCIL_PITCH__MASK 0xffffffff
1494#define A4XX_RB_STENCIL_PITCH__SHIFT 0
1495static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val)
1496{
1497 assert(!(val & 0x1f));
1498 return (((val >> 5)) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK;
1499}
1500
1501#define REG_A4XX_RB_STENCILREFMASK 0x0000210b
1502#define A4XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
1503#define A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
1504static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
1505{
1506 return ((val) << A4XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILREF__MASK;
1507}
1508#define A4XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
1509#define A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
1510static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
1511{
1512 return ((val) << A4XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILMASK__MASK;
1513}
1514#define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
1515#define A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
1516static inline uint32_t A4XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
1517{
1518 return ((val) << A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
1519}
1520
1521#define REG_A4XX_RB_STENCILREFMASK_BF 0x0000210c
1522#define A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
1523#define A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
1524static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
1525{
1526 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
1527}
1528#define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
1529#define A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
1530static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
1531{
1532 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
1533}
1534#define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
1535#define A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
1536static inline uint32_t A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
1537{
1538 return ((val) << A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A4XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
1539}
1540
1541#define REG_A4XX_RB_BIN_OFFSET 0x0000210d
1542#define A4XX_RB_BIN_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
1543#define A4XX_RB_BIN_OFFSET_X__MASK 0x00007fff
1544#define A4XX_RB_BIN_OFFSET_X__SHIFT 0
1545static inline uint32_t A4XX_RB_BIN_OFFSET_X(uint32_t val)
1546{
1547 return ((val) << A4XX_RB_BIN_OFFSET_X__SHIFT) & A4XX_RB_BIN_OFFSET_X__MASK;
1548}
1549#define A4XX_RB_BIN_OFFSET_Y__MASK 0x7fff0000
1550#define A4XX_RB_BIN_OFFSET_Y__SHIFT 16
1551static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val)
1552{
1553 return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK;
1554}
1555
1556#define REG_A4XX_RB_VPORT_Z_CLAMP(i0) (0x00002120 + 0x2*(i0))
1557
1558static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; }
1559
1560static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x00002121 + 0x2*i0; }
1561
1562#define REG_A4XX_RBBM_HW_VERSION 0x00000000
1563
1564#define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002
1565
1566#define REG_A4XX_RBBM_CLOCK_CTL_TP(i0) (0x00000004 + 0x1*(i0))
1567
1568static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; }
1569
1570#define REG_A4XX_RBBM_CLOCK_CTL2_TP(i0) (0x00000008 + 0x1*(i0))
1571
1572static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; }
1573
1574#define REG_A4XX_RBBM_CLOCK_HYST_TP(i0) (0x0000000c + 0x1*(i0))
1575
1576static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; }
1577
1578#define REG_A4XX_RBBM_CLOCK_DELAY_TP(i0) (0x00000010 + 0x1*(i0))
1579
1580static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; }
1581
1582#define REG_A4XX_RBBM_CLOCK_CTL_UCHE 0x00000014
1583
1584#define REG_A4XX_RBBM_CLOCK_CTL2_UCHE 0x00000015
1585
1586#define REG_A4XX_RBBM_CLOCK_CTL3_UCHE 0x00000016
1587
1588#define REG_A4XX_RBBM_CLOCK_CTL4_UCHE 0x00000017
1589
1590#define REG_A4XX_RBBM_CLOCK_HYST_UCHE 0x00000018
1591
1592#define REG_A4XX_RBBM_CLOCK_DELAY_UCHE 0x00000019
1593
1594#define REG_A4XX_RBBM_CLOCK_MODE_GPC 0x0000001a
1595
1596#define REG_A4XX_RBBM_CLOCK_DELAY_GPC 0x0000001b
1597
1598#define REG_A4XX_RBBM_CLOCK_HYST_GPC 0x0000001c
1599
1600#define REG_A4XX_RBBM_CLOCK_CTL_TSE_RAS_RBBM 0x0000001d
1601
1602#define REG_A4XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000001e
1603
1604#define REG_A4XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x0000001f
1605
1606#define REG_A4XX_RBBM_CLOCK_CTL 0x00000020
1607
1608#define REG_A4XX_RBBM_SP_HYST_CNT 0x00000021
1609
1610#define REG_A4XX_RBBM_SW_RESET_CMD 0x00000022
1611
1612#define REG_A4XX_RBBM_AHB_CTL0 0x00000023
1613
1614#define REG_A4XX_RBBM_AHB_CTL1 0x00000024
1615
1616#define REG_A4XX_RBBM_AHB_CMD 0x00000025
1617
1618#define REG_A4XX_RBBM_RB_SUB_BLOCK_SEL_CTL 0x00000026
1619
1620#define REG_A4XX_RBBM_RAM_ACC_63_32 0x00000028
1621
1622#define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x0000002b
1623
1624#define REG_A4XX_RBBM_INTERFACE_HANG_INT_CTL 0x0000002f
1625
1626#define REG_A4XX_RBBM_INTERFACE_HANG_MASK_CTL4 0x00000034
1627
1628#define REG_A4XX_RBBM_INT_CLEAR_CMD 0x00000036
1629
1630#define REG_A4XX_RBBM_INT_0_MASK 0x00000037
1631
1632#define REG_A4XX_RBBM_RBBM_CTL 0x0000003e
1633
1634#define REG_A4XX_RBBM_AHB_DEBUG_CTL 0x0000003f
1635
1636#define REG_A4XX_RBBM_VBIF_DEBUG_CTL 0x00000041
1637
1638#define REG_A4XX_RBBM_CLOCK_CTL2 0x00000042
1639
1640#define REG_A4XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
1641
1642#define REG_A4XX_RBBM_RESET_CYCLES 0x00000047
1643
1644#define REG_A4XX_RBBM_EXT_TRACE_BUS_CTL 0x00000049
1645
1646#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_A 0x0000004a
1647
1648#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_B 0x0000004b
1649
1650#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_C 0x0000004c
1651
1652#define REG_A4XX_RBBM_CFG_DEBBUS_SEL_D 0x0000004d
1653
1654#define REG_A4XX_RBBM_POWER_CNTL_IP 0x00000098
1655#define A4XX_RBBM_POWER_CNTL_IP_SW_COLLAPSE 0x00000001
1656#define A4XX_RBBM_POWER_CNTL_IP_SP_TP_PWR_ON 0x00100000
1657
1658#define REG_A4XX_RBBM_PERFCTR_CP_0_LO 0x0000009c
1659
1660#define REG_A4XX_RBBM_PERFCTR_CP_0_HI 0x0000009d
1661
1662#define REG_A4XX_RBBM_PERFCTR_CP_1_LO 0x0000009e
1663
1664#define REG_A4XX_RBBM_PERFCTR_CP_1_HI 0x0000009f
1665
1666#define REG_A4XX_RBBM_PERFCTR_CP_2_LO 0x000000a0
1667
1668#define REG_A4XX_RBBM_PERFCTR_CP_2_HI 0x000000a1
1669
1670#define REG_A4XX_RBBM_PERFCTR_CP_3_LO 0x000000a2
1671
1672#define REG_A4XX_RBBM_PERFCTR_CP_3_HI 0x000000a3
1673
1674#define REG_A4XX_RBBM_PERFCTR_CP_4_LO 0x000000a4
1675
1676#define REG_A4XX_RBBM_PERFCTR_CP_4_HI 0x000000a5
1677
1678#define REG_A4XX_RBBM_PERFCTR_CP_5_LO 0x000000a6
1679
1680#define REG_A4XX_RBBM_PERFCTR_CP_5_HI 0x000000a7
1681
1682#define REG_A4XX_RBBM_PERFCTR_CP_6_LO 0x000000a8
1683
1684#define REG_A4XX_RBBM_PERFCTR_CP_6_HI 0x000000a9
1685
1686#define REG_A4XX_RBBM_PERFCTR_CP_7_LO 0x000000aa
1687
1688#define REG_A4XX_RBBM_PERFCTR_CP_7_HI 0x000000ab
1689
1690#define REG_A4XX_RBBM_PERFCTR_RBBM_0_LO 0x000000ac
1691
1692#define REG_A4XX_RBBM_PERFCTR_RBBM_0_HI 0x000000ad
1693
1694#define REG_A4XX_RBBM_PERFCTR_RBBM_1_LO 0x000000ae
1695
1696#define REG_A4XX_RBBM_PERFCTR_RBBM_1_HI 0x000000af
1697
1698#define REG_A4XX_RBBM_PERFCTR_RBBM_2_LO 0x000000b0
1699
1700#define REG_A4XX_RBBM_PERFCTR_RBBM_2_HI 0x000000b1
1701
1702#define REG_A4XX_RBBM_PERFCTR_RBBM_3_LO 0x000000b2
1703
1704#define REG_A4XX_RBBM_PERFCTR_RBBM_3_HI 0x000000b3
1705
1706#define REG_A4XX_RBBM_PERFCTR_PC_0_LO 0x000000b4
1707
1708#define REG_A4XX_RBBM_PERFCTR_PC_0_HI 0x000000b5
1709
1710#define REG_A4XX_RBBM_PERFCTR_PC_1_LO 0x000000b6
1711
1712#define REG_A4XX_RBBM_PERFCTR_PC_1_HI 0x000000b7
1713
1714#define REG_A4XX_RBBM_PERFCTR_PC_2_LO 0x000000b8
1715
1716#define REG_A4XX_RBBM_PERFCTR_PC_2_HI 0x000000b9
1717
1718#define REG_A4XX_RBBM_PERFCTR_PC_3_LO 0x000000ba
1719
1720#define REG_A4XX_RBBM_PERFCTR_PC_3_HI 0x000000bb
1721
1722#define REG_A4XX_RBBM_PERFCTR_PC_4_LO 0x000000bc
1723
1724#define REG_A4XX_RBBM_PERFCTR_PC_4_HI 0x000000bd
1725
1726#define REG_A4XX_RBBM_PERFCTR_PC_5_LO 0x000000be
1727
1728#define REG_A4XX_RBBM_PERFCTR_PC_5_HI 0x000000bf
1729
1730#define REG_A4XX_RBBM_PERFCTR_PC_6_LO 0x000000c0
1731
1732#define REG_A4XX_RBBM_PERFCTR_PC_6_HI 0x000000c1
1733
1734#define REG_A4XX_RBBM_PERFCTR_PC_7_LO 0x000000c2
1735
1736#define REG_A4XX_RBBM_PERFCTR_PC_7_HI 0x000000c3
1737
1738#define REG_A4XX_RBBM_PERFCTR_VFD_0_LO 0x000000c4
1739
1740#define REG_A4XX_RBBM_PERFCTR_VFD_0_HI 0x000000c5
1741
1742#define REG_A4XX_RBBM_PERFCTR_VFD_1_LO 0x000000c6
1743
1744#define REG_A4XX_RBBM_PERFCTR_VFD_1_HI 0x000000c7
1745
1746#define REG_A4XX_RBBM_PERFCTR_VFD_2_LO 0x000000c8
1747
1748#define REG_A4XX_RBBM_PERFCTR_VFD_2_HI 0x000000c9
1749
1750#define REG_A4XX_RBBM_PERFCTR_VFD_3_LO 0x000000ca
1751
1752#define REG_A4XX_RBBM_PERFCTR_VFD_3_HI 0x000000cb
1753
1754#define REG_A4XX_RBBM_PERFCTR_VFD_4_LO 0x000000cc
1755
1756#define REG_A4XX_RBBM_PERFCTR_VFD_4_HI 0x000000cd
1757
1758#define REG_A4XX_RBBM_PERFCTR_VFD_5_LO 0x000000ce
1759
1760#define REG_A4XX_RBBM_PERFCTR_VFD_5_HI 0x000000cf
1761
1762#define REG_A4XX_RBBM_PERFCTR_VFD_6_LO 0x000000d0
1763
1764#define REG_A4XX_RBBM_PERFCTR_VFD_6_HI 0x000000d1
1765
1766#define REG_A4XX_RBBM_PERFCTR_VFD_7_LO 0x000000d2
1767
1768#define REG_A4XX_RBBM_PERFCTR_VFD_7_HI 0x000000d3
1769
1770#define REG_A4XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000d4
1771
1772#define REG_A4XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000d5
1773
1774#define REG_A4XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000d6
1775
1776#define REG_A4XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000d7
1777
1778#define REG_A4XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000d8
1779
1780#define REG_A4XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000d9
1781
1782#define REG_A4XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000da
1783
1784#define REG_A4XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000db
1785
1786#define REG_A4XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000dc
1787
1788#define REG_A4XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000dd
1789
1790#define REG_A4XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000de
1791
1792#define REG_A4XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000df
1793
1794#define REG_A4XX_RBBM_PERFCTR_HLSQ_6_LO 0x000000e0
1795
1796#define REG_A4XX_RBBM_PERFCTR_HLSQ_6_HI 0x000000e1
1797
1798#define REG_A4XX_RBBM_PERFCTR_HLSQ_7_LO 0x000000e2
1799
1800#define REG_A4XX_RBBM_PERFCTR_HLSQ_7_HI 0x000000e3
1801
1802#define REG_A4XX_RBBM_PERFCTR_VPC_0_LO 0x000000e4
1803
1804#define REG_A4XX_RBBM_PERFCTR_VPC_0_HI 0x000000e5
1805
1806#define REG_A4XX_RBBM_PERFCTR_VPC_1_LO 0x000000e6
1807
1808#define REG_A4XX_RBBM_PERFCTR_VPC_1_HI 0x000000e7
1809
1810#define REG_A4XX_RBBM_PERFCTR_VPC_2_LO 0x000000e8
1811
1812#define REG_A4XX_RBBM_PERFCTR_VPC_2_HI 0x000000e9
1813
1814#define REG_A4XX_RBBM_PERFCTR_VPC_3_LO 0x000000ea
1815
1816#define REG_A4XX_RBBM_PERFCTR_VPC_3_HI 0x000000eb
1817
1818#define REG_A4XX_RBBM_PERFCTR_CCU_0_LO 0x000000ec
1819
1820#define REG_A4XX_RBBM_PERFCTR_CCU_0_HI 0x000000ed
1821
1822#define REG_A4XX_RBBM_PERFCTR_CCU_1_LO 0x000000ee
1823
1824#define REG_A4XX_RBBM_PERFCTR_CCU_1_HI 0x000000ef
1825
1826#define REG_A4XX_RBBM_PERFCTR_CCU_2_LO 0x000000f0
1827
1828#define REG_A4XX_RBBM_PERFCTR_CCU_2_HI 0x000000f1
1829
1830#define REG_A4XX_RBBM_PERFCTR_CCU_3_LO 0x000000f2
1831
1832#define REG_A4XX_RBBM_PERFCTR_CCU_3_HI 0x000000f3
1833
1834#define REG_A4XX_RBBM_PERFCTR_TSE_0_LO 0x000000f4
1835
1836#define REG_A4XX_RBBM_PERFCTR_TSE_0_HI 0x000000f5
1837
1838#define REG_A4XX_RBBM_PERFCTR_TSE_1_LO 0x000000f6
1839
1840#define REG_A4XX_RBBM_PERFCTR_TSE_1_HI 0x000000f7
1841
1842#define REG_A4XX_RBBM_PERFCTR_TSE_2_LO 0x000000f8
1843
1844#define REG_A4XX_RBBM_PERFCTR_TSE_2_HI 0x000000f9
1845
1846#define REG_A4XX_RBBM_PERFCTR_TSE_3_LO 0x000000fa
1847
1848#define REG_A4XX_RBBM_PERFCTR_TSE_3_HI 0x000000fb
1849
1850#define REG_A4XX_RBBM_PERFCTR_RAS_0_LO 0x000000fc
1851
1852#define REG_A4XX_RBBM_PERFCTR_RAS_0_HI 0x000000fd
1853
1854#define REG_A4XX_RBBM_PERFCTR_RAS_1_LO 0x000000fe
1855
1856#define REG_A4XX_RBBM_PERFCTR_RAS_1_HI 0x000000ff
1857
1858#define REG_A4XX_RBBM_PERFCTR_RAS_2_LO 0x00000100
1859
1860#define REG_A4XX_RBBM_PERFCTR_RAS_2_HI 0x00000101
1861
1862#define REG_A4XX_RBBM_PERFCTR_RAS_3_LO 0x00000102
1863
1864#define REG_A4XX_RBBM_PERFCTR_RAS_3_HI 0x00000103
1865
1866#define REG_A4XX_RBBM_PERFCTR_UCHE_0_LO 0x00000104
1867
1868#define REG_A4XX_RBBM_PERFCTR_UCHE_0_HI 0x00000105
1869
1870#define REG_A4XX_RBBM_PERFCTR_UCHE_1_LO 0x00000106
1871
1872#define REG_A4XX_RBBM_PERFCTR_UCHE_1_HI 0x00000107
1873
1874#define REG_A4XX_RBBM_PERFCTR_UCHE_2_LO 0x00000108
1875
1876#define REG_A4XX_RBBM_PERFCTR_UCHE_2_HI 0x00000109
1877
1878#define REG_A4XX_RBBM_PERFCTR_UCHE_3_LO 0x0000010a
1879
1880#define REG_A4XX_RBBM_PERFCTR_UCHE_3_HI 0x0000010b
1881
1882#define REG_A4XX_RBBM_PERFCTR_UCHE_4_LO 0x0000010c
1883
1884#define REG_A4XX_RBBM_PERFCTR_UCHE_4_HI 0x0000010d
1885
1886#define REG_A4XX_RBBM_PERFCTR_UCHE_5_LO 0x0000010e
1887
1888#define REG_A4XX_RBBM_PERFCTR_UCHE_5_HI 0x0000010f
1889
1890#define REG_A4XX_RBBM_PERFCTR_UCHE_6_LO 0x00000110
1891
1892#define REG_A4XX_RBBM_PERFCTR_UCHE_6_HI 0x00000111
1893
1894#define REG_A4XX_RBBM_PERFCTR_UCHE_7_LO 0x00000112
1895
1896#define REG_A4XX_RBBM_PERFCTR_UCHE_7_HI 0x00000113
1897
1898#define REG_A4XX_RBBM_PERFCTR_TP_0_LO 0x00000114
1899
1900#define REG_A4XX_RBBM_PERFCTR_TP_0_HI 0x00000115
1901
1902#define REG_A4XX_RBBM_PERFCTR_TP_1_LO 0x00000116
1903
1904#define REG_A4XX_RBBM_PERFCTR_TP_1_HI 0x00000117
1905
1906#define REG_A4XX_RBBM_PERFCTR_TP_2_LO 0x00000118
1907
1908#define REG_A4XX_RBBM_PERFCTR_TP_2_HI 0x00000119
1909
1910#define REG_A4XX_RBBM_PERFCTR_TP_3_LO 0x0000011a
1911
1912#define REG_A4XX_RBBM_PERFCTR_TP_3_HI 0x0000011b
1913
1914#define REG_A4XX_RBBM_PERFCTR_TP_4_LO 0x0000011c
1915
1916#define REG_A4XX_RBBM_PERFCTR_TP_4_HI 0x0000011d
1917
1918#define REG_A4XX_RBBM_PERFCTR_TP_5_LO 0x0000011e
1919
1920#define REG_A4XX_RBBM_PERFCTR_TP_5_HI 0x0000011f
1921
1922#define REG_A4XX_RBBM_PERFCTR_TP_6_LO 0x00000120
1923
1924#define REG_A4XX_RBBM_PERFCTR_TP_6_HI 0x00000121
1925
1926#define REG_A4XX_RBBM_PERFCTR_TP_7_LO 0x00000122
1927
1928#define REG_A4XX_RBBM_PERFCTR_TP_7_HI 0x00000123
1929
1930#define REG_A4XX_RBBM_PERFCTR_SP_0_LO 0x00000124
1931
1932#define REG_A4XX_RBBM_PERFCTR_SP_0_HI 0x00000125
1933
1934#define REG_A4XX_RBBM_PERFCTR_SP_1_LO 0x00000126
1935
1936#define REG_A4XX_RBBM_PERFCTR_SP_1_HI 0x00000127
1937
1938#define REG_A4XX_RBBM_PERFCTR_SP_2_LO 0x00000128
1939
1940#define REG_A4XX_RBBM_PERFCTR_SP_2_HI 0x00000129
1941
1942#define REG_A4XX_RBBM_PERFCTR_SP_3_LO 0x0000012a
1943
1944#define REG_A4XX_RBBM_PERFCTR_SP_3_HI 0x0000012b
1945
1946#define REG_A4XX_RBBM_PERFCTR_SP_4_LO 0x0000012c
1947
1948#define REG_A4XX_RBBM_PERFCTR_SP_4_HI 0x0000012d
1949
1950#define REG_A4XX_RBBM_PERFCTR_SP_5_LO 0x0000012e
1951
1952#define REG_A4XX_RBBM_PERFCTR_SP_5_HI 0x0000012f
1953
1954#define REG_A4XX_RBBM_PERFCTR_SP_6_LO 0x00000130
1955
1956#define REG_A4XX_RBBM_PERFCTR_SP_6_HI 0x00000131
1957
1958#define REG_A4XX_RBBM_PERFCTR_SP_7_LO 0x00000132
1959
1960#define REG_A4XX_RBBM_PERFCTR_SP_7_HI 0x00000133
1961
1962#define REG_A4XX_RBBM_PERFCTR_SP_8_LO 0x00000134
1963
1964#define REG_A4XX_RBBM_PERFCTR_SP_8_HI 0x00000135
1965
1966#define REG_A4XX_RBBM_PERFCTR_SP_9_LO 0x00000136
1967
1968#define REG_A4XX_RBBM_PERFCTR_SP_9_HI 0x00000137
1969
1970#define REG_A4XX_RBBM_PERFCTR_SP_10_LO 0x00000138
1971
1972#define REG_A4XX_RBBM_PERFCTR_SP_10_HI 0x00000139
1973
1974#define REG_A4XX_RBBM_PERFCTR_SP_11_LO 0x0000013a
1975
1976#define REG_A4XX_RBBM_PERFCTR_SP_11_HI 0x0000013b
1977
1978#define REG_A4XX_RBBM_PERFCTR_RB_0_LO 0x0000013c
1979
1980#define REG_A4XX_RBBM_PERFCTR_RB_0_HI 0x0000013d
1981
1982#define REG_A4XX_RBBM_PERFCTR_RB_1_LO 0x0000013e
1983
1984#define REG_A4XX_RBBM_PERFCTR_RB_1_HI 0x0000013f
1985
1986#define REG_A4XX_RBBM_PERFCTR_RB_2_LO 0x00000140
1987
1988#define REG_A4XX_RBBM_PERFCTR_RB_2_HI 0x00000141
1989
1990#define REG_A4XX_RBBM_PERFCTR_RB_3_LO 0x00000142
1991
1992#define REG_A4XX_RBBM_PERFCTR_RB_3_HI 0x00000143
1993
1994#define REG_A4XX_RBBM_PERFCTR_RB_4_LO 0x00000144
1995
1996#define REG_A4XX_RBBM_PERFCTR_RB_4_HI 0x00000145
1997
1998#define REG_A4XX_RBBM_PERFCTR_RB_5_LO 0x00000146
1999
2000#define REG_A4XX_RBBM_PERFCTR_RB_5_HI 0x00000147
2001
2002#define REG_A4XX_RBBM_PERFCTR_RB_6_LO 0x00000148
2003
2004#define REG_A4XX_RBBM_PERFCTR_RB_6_HI 0x00000149
2005
2006#define REG_A4XX_RBBM_PERFCTR_RB_7_LO 0x0000014a
2007
2008#define REG_A4XX_RBBM_PERFCTR_RB_7_HI 0x0000014b
2009
2010#define REG_A4XX_RBBM_PERFCTR_VSC_0_LO 0x0000014c
2011
2012#define REG_A4XX_RBBM_PERFCTR_VSC_0_HI 0x0000014d
2013
2014#define REG_A4XX_RBBM_PERFCTR_VSC_1_LO 0x0000014e
2015
2016#define REG_A4XX_RBBM_PERFCTR_VSC_1_HI 0x0000014f
2017
2018#define REG_A4XX_RBBM_PERFCTR_PWR_0_LO 0x00000166
2019
2020#define REG_A4XX_RBBM_PERFCTR_PWR_0_HI 0x00000167
2021
2022#define REG_A4XX_RBBM_PERFCTR_PWR_1_LO 0x00000168
2023
2024#define REG_A4XX_RBBM_PERFCTR_PWR_1_HI 0x00000169
2025
2026#define REG_A4XX_RBBM_ALWAYSON_COUNTER_LO 0x0000016e
2027
2028#define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI 0x0000016f
2029
2030#define REG_A4XX_RBBM_CLOCK_CTL_SP(i0) (0x00000068 + 0x1*(i0))
2031
2032static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; }
2033
2034#define REG_A4XX_RBBM_CLOCK_CTL2_SP(i0) (0x0000006c + 0x1*(i0))
2035
2036static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; }
2037
2038#define REG_A4XX_RBBM_CLOCK_HYST_SP(i0) (0x00000070 + 0x1*(i0))
2039
2040static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; }
2041
2042#define REG_A4XX_RBBM_CLOCK_DELAY_SP(i0) (0x00000074 + 0x1*(i0))
2043
2044static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; }
2045
2046#define REG_A4XX_RBBM_CLOCK_CTL_RB(i0) (0x00000078 + 0x1*(i0))
2047
2048static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; }
2049
2050#define REG_A4XX_RBBM_CLOCK_CTL2_RB(i0) (0x0000007c + 0x1*(i0))
2051
2052static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; }
2053
2054#define REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(i0) (0x00000082 + 0x1*(i0))
2055
2056static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; }
2057
2058#define REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(i0) (0x00000086 + 0x1*(i0))
2059
2060static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; }
2061
2062#define REG_A4XX_RBBM_CLOCK_HYST_COM_DCOM 0x00000080
2063
2064#define REG_A4XX_RBBM_CLOCK_CTL_COM_DCOM 0x00000081
2065
2066#define REG_A4XX_RBBM_CLOCK_CTL_HLSQ 0x0000008a
2067
2068#define REG_A4XX_RBBM_CLOCK_HYST_HLSQ 0x0000008b
2069
2070#define REG_A4XX_RBBM_CLOCK_DELAY_HLSQ 0x0000008c
2071
2072#define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d
2073
2074#define REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(i0) (0x0000008e + 0x1*(i0))
2075
2076static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; }
2077
2078#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_0 0x00000099
2079
2080#define REG_A4XX_RBBM_SP_REGFILE_SLEEP_CNTL_1 0x0000009a
2081
2082#define REG_A4XX_RBBM_PERFCTR_CTL 0x00000170
2083
2084#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD0 0x00000171
2085
2086#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD1 0x00000172
2087
2088#define REG_A4XX_RBBM_PERFCTR_LOAD_CMD2 0x00000173
2089
2090#define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000174
2091
2092#define REG_A4XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000175
2093
2094#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_0 0x00000176
2095
2096#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_1 0x00000177
2097
2098#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_2 0x00000178
2099
2100#define REG_A4XX_RBBM_PERFCTR_RBBM_SEL_3 0x00000179
2101
2102#define REG_A4XX_RBBM_GPU_BUSY_MASKED 0x0000017a
2103
2104#define REG_A4XX_RBBM_INT_0_STATUS 0x0000017d
2105
2106#define REG_A4XX_RBBM_CLOCK_STATUS 0x00000182
2107
2108#define REG_A4XX_RBBM_AHB_STATUS 0x00000189
2109
2110#define REG_A4XX_RBBM_AHB_ME_SPLIT_STATUS 0x0000018c
2111
2112#define REG_A4XX_RBBM_AHB_PFP_SPLIT_STATUS 0x0000018d
2113
2114#define REG_A4XX_RBBM_AHB_ERROR_STATUS 0x0000018f
2115
2116#define REG_A4XX_RBBM_STATUS 0x00000191
2117#define A4XX_RBBM_STATUS_HI_BUSY 0x00000001
2118#define A4XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
2119#define A4XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
2120#define A4XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000
2121#define A4XX_RBBM_STATUS_VBIF_BUSY 0x00008000
2122#define A4XX_RBBM_STATUS_TSE_BUSY 0x00010000
2123#define A4XX_RBBM_STATUS_RAS_BUSY 0x00020000
2124#define A4XX_RBBM_STATUS_RB_BUSY 0x00040000
2125#define A4XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
2126#define A4XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
2127#define A4XX_RBBM_STATUS_VFD_BUSY 0x00200000
2128#define A4XX_RBBM_STATUS_VPC_BUSY 0x00400000
2129#define A4XX_RBBM_STATUS_UCHE_BUSY 0x00800000
2130#define A4XX_RBBM_STATUS_SP_BUSY 0x01000000
2131#define A4XX_RBBM_STATUS_TPL1_BUSY 0x02000000
2132#define A4XX_RBBM_STATUS_MARB_BUSY 0x04000000
2133#define A4XX_RBBM_STATUS_VSC_BUSY 0x08000000
2134#define A4XX_RBBM_STATUS_ARB_BUSY 0x10000000
2135#define A4XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
2136#define A4XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
2137#define A4XX_RBBM_STATUS_GPU_BUSY 0x80000000
2138
2139#define REG_A4XX_RBBM_INTERFACE_RRDY_STATUS5 0x0000019f
2140
2141#define REG_A4XX_RBBM_POWER_STATUS 0x000001b0
2142#define A4XX_RBBM_POWER_STATUS_SP_TP_PWR_ON 0x00100000
2143
2144#define REG_A4XX_RBBM_WAIT_IDLE_CLOCKS_CTL2 0x000001b8
2145
2146#define REG_A4XX_CP_SCRATCH_UMASK 0x00000228
2147
2148#define REG_A4XX_CP_SCRATCH_ADDR 0x00000229
2149
2150#define REG_A4XX_CP_RB_BASE 0x00000200
2151
2152#define REG_A4XX_CP_RB_CNTL 0x00000201
2153
2154#define REG_A4XX_CP_RB_WPTR 0x00000205
2155
2156#define REG_A4XX_CP_RB_RPTR_ADDR 0x00000203
2157
2158#define REG_A4XX_CP_RB_RPTR 0x00000204
2159
2160#define REG_A4XX_CP_IB1_BASE 0x00000206
2161
2162#define REG_A4XX_CP_IB1_BUFSZ 0x00000207
2163
2164#define REG_A4XX_CP_IB2_BASE 0x00000208
2165
2166#define REG_A4XX_CP_IB2_BUFSZ 0x00000209
2167
2168#define REG_A4XX_CP_ME_NRT_ADDR 0x0000020c
2169
2170#define REG_A4XX_CP_ME_NRT_DATA 0x0000020d
2171
2172#define REG_A4XX_CP_ME_RB_DONE_DATA 0x00000217
2173
2174#define REG_A4XX_CP_QUEUE_THRESH2 0x00000219
2175
2176#define REG_A4XX_CP_MERCIU_SIZE 0x0000021b
2177
2178#define REG_A4XX_CP_ROQ_ADDR 0x0000021c
2179
2180#define REG_A4XX_CP_ROQ_DATA 0x0000021d
2181
2182#define REG_A4XX_CP_MEQ_ADDR 0x0000021e
2183
2184#define REG_A4XX_CP_MEQ_DATA 0x0000021f
2185
2186#define REG_A4XX_CP_MERCIU_ADDR 0x00000220
2187
2188#define REG_A4XX_CP_MERCIU_DATA 0x00000221
2189
2190#define REG_A4XX_CP_MERCIU_DATA2 0x00000222
2191
2192#define REG_A4XX_CP_PFP_UCODE_ADDR 0x00000223
2193
2194#define REG_A4XX_CP_PFP_UCODE_DATA 0x00000224
2195
2196#define REG_A4XX_CP_ME_RAM_WADDR 0x00000225
2197
2198#define REG_A4XX_CP_ME_RAM_RADDR 0x00000226
2199
2200#define REG_A4XX_CP_ME_RAM_DATA 0x00000227
2201
2202#define REG_A4XX_CP_PREEMPT 0x0000022a
2203
2204#define REG_A4XX_CP_CNTL 0x0000022c
2205
2206#define REG_A4XX_CP_ME_CNTL 0x0000022d
2207
2208#define REG_A4XX_CP_DEBUG 0x0000022e
2209
2210#define REG_A4XX_CP_DEBUG_ECO_CONTROL 0x00000231
2211
2212#define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232
2213
2214#define REG_A4XX_CP_PROTECT(i0) (0x00000240 + 0x1*(i0))
2215
2216static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; }
2217#define A4XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff
2218#define A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
2219static inline uint32_t A4XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
2220{
2221 return ((val) << A4XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A4XX_CP_PROTECT_REG_BASE_ADDR__MASK;
2222}
2223#define A4XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000
2224#define A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24
2225static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
2226{
2227 return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK;
2228}
2229#define A4XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000
2230#define A4XX_CP_PROTECT_REG_TRAP_READ 0x40000000
2231
2232#define REG_A4XX_CP_PROTECT_CTRL 0x00000250
2233
2234#define REG_A4XX_CP_ST_BASE 0x000004c0
2235
2236#define REG_A4XX_CP_STQ_AVAIL 0x000004ce
2237
2238#define REG_A4XX_CP_MERCIU_STAT 0x000004d0
2239
2240#define REG_A4XX_CP_WFI_PEND_CTR 0x000004d2
2241
2242#define REG_A4XX_CP_HW_FAULT 0x000004d8
2243
2244#define REG_A4XX_CP_PROTECT_STATUS 0x000004da
2245
2246#define REG_A4XX_CP_EVENTS_IN_FLIGHT 0x000004dd
2247
2248#define REG_A4XX_CP_PERFCTR_CP_SEL_0 0x00000500
2249
2250#define REG_A4XX_CP_PERFCTR_CP_SEL_1 0x00000501
2251
2252#define REG_A4XX_CP_PERFCTR_CP_SEL_2 0x00000502
2253
2254#define REG_A4XX_CP_PERFCTR_CP_SEL_3 0x00000503
2255
2256#define REG_A4XX_CP_PERFCTR_CP_SEL_4 0x00000504
2257
2258#define REG_A4XX_CP_PERFCTR_CP_SEL_5 0x00000505
2259
2260#define REG_A4XX_CP_PERFCTR_CP_SEL_6 0x00000506
2261
2262#define REG_A4XX_CP_PERFCTR_CP_SEL_7 0x00000507
2263
2264#define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b
2265
2266#define REG_A4XX_CP_SCRATCH(i0) (0x00000578 + 0x1*(i0))
2267
2268static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; }
2269
2270#define REG_A4XX_SP_VS_STATUS 0x00000ec0
2271
2272#define REG_A4XX_SP_MODE_CONTROL 0x00000ec3
2273
2274#define REG_A4XX_SP_PERFCTR_SP_SEL_0 0x00000ec4
2275
2276#define REG_A4XX_SP_PERFCTR_SP_SEL_1 0x00000ec5
2277
2278#define REG_A4XX_SP_PERFCTR_SP_SEL_2 0x00000ec6
2279
2280#define REG_A4XX_SP_PERFCTR_SP_SEL_3 0x00000ec7
2281
2282#define REG_A4XX_SP_PERFCTR_SP_SEL_4 0x00000ec8
2283
2284#define REG_A4XX_SP_PERFCTR_SP_SEL_5 0x00000ec9
2285
2286#define REG_A4XX_SP_PERFCTR_SP_SEL_6 0x00000eca
2287
2288#define REG_A4XX_SP_PERFCTR_SP_SEL_7 0x00000ecb
2289
2290#define REG_A4XX_SP_PERFCTR_SP_SEL_8 0x00000ecc
2291
2292#define REG_A4XX_SP_PERFCTR_SP_SEL_9 0x00000ecd
2293
2294#define REG_A4XX_SP_PERFCTR_SP_SEL_10 0x00000ece
2295
2296#define REG_A4XX_SP_PERFCTR_SP_SEL_11 0x00000ecf
2297
2298#define REG_A4XX_SP_SP_CTRL_REG 0x000022c0
2299#define A4XX_SP_SP_CTRL_REG_BINNING_PASS 0x00080000
2300
2301#define REG_A4XX_SP_INSTR_CACHE_CTRL 0x000022c1
2302#define A4XX_SP_INSTR_CACHE_CTRL_VS_BUFFER 0x00000080
2303#define A4XX_SP_INSTR_CACHE_CTRL_FS_BUFFER 0x00000100
2304#define A4XX_SP_INSTR_CACHE_CTRL_INSTR_BUFFER 0x00000400
2305
2306#define REG_A4XX_SP_VS_CTRL_REG0 0x000022c4
2307#define A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
2308#define A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
2309static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
2310{
2311 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
2312}
2313#define A4XX_SP_VS_CTRL_REG0_VARYING 0x00000002
2314#define A4XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
2315#define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
2316#define A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
2317static inline uint32_t A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2318{
2319 return ((val) << A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2320}
2321#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
2322#define A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
2323static inline uint32_t A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2324{
2325 return ((val) << A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2326}
2327#define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
2328#define A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
2329static inline uint32_t A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
2330{
2331 return ((val) << A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_VS_CTRL_REG0_INOUTREGOVERLAP__MASK;
2332}
2333#define A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
2334#define A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
2335static inline uint32_t A4XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2336{
2337 return ((val) << A4XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
2338}
2339#define A4XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
2340#define A4XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
2341
2342#define REG_A4XX_SP_VS_CTRL_REG1 0x000022c5
2343#define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
2344#define A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0
2345static inline uint32_t A4XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
2346{
2347 return ((val) << A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
2348}
2349#define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000
2350#define A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24
2351static inline uint32_t A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
2352{
2353 return ((val) << A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A4XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
2354}
2355
2356#define REG_A4XX_SP_VS_PARAM_REG 0x000022c6
2357#define A4XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff
2358#define A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0
2359static inline uint32_t A4XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
2360{
2361 return ((val) << A4XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_POSREGID__MASK;
2362}
2363#define A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
2364#define A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8
2365static inline uint32_t A4XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
2366{
2367 return ((val) << A4XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A4XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
2368}
2369#define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0xfff00000
2370#define A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
2371static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
2372{
2373 return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
2374}
2375
2376#define REG_A4XX_SP_VS_OUT(i0) (0x000022c7 + 0x1*(i0))
2377
2378static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2379#define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff
2380#define A4XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
2381static inline uint32_t A4XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
2382{
2383 return ((val) << A4XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_A_REGID__MASK;
2384}
2385#define A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
2386#define A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
2387static inline uint32_t A4XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
2388{
2389 return ((val) << A4XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
2390}
2391#define A4XX_SP_VS_OUT_REG_B_REGID__MASK 0x01ff0000
2392#define A4XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
2393static inline uint32_t A4XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
2394{
2395 return ((val) << A4XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_VS_OUT_REG_B_REGID__MASK;
2396}
2397#define A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
2398#define A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
2399static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
2400{
2401 return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
2402}
2403
2404#define REG_A4XX_SP_VS_VPC_DST(i0) (0x000022d8 + 0x1*(i0))
2405
2406static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; }
2407#define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
2408#define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
2409static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
2410{
2411 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
2412}
2413#define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
2414#define A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
2415static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
2416{
2417 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
2418}
2419#define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
2420#define A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
2421static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
2422{
2423 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
2424}
2425#define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
2426#define A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
2427static inline uint32_t A4XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
2428{
2429 return ((val) << A4XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
2430}
2431
2432#define REG_A4XX_SP_VS_OBJ_OFFSET_REG 0x000022e0
2433#define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2434#define A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2435static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2436{
2437 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2438}
2439#define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2440#define A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2441static inline uint32_t A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2442{
2443 return ((val) << A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2444}
2445
2446#define REG_A4XX_SP_VS_OBJ_START 0x000022e1
2447
2448#define REG_A4XX_SP_VS_PVT_MEM_PARAM 0x000022e2
2449
2450#define REG_A4XX_SP_VS_PVT_MEM_ADDR 0x000022e3
2451
2452#define REG_A4XX_SP_VS_LENGTH_REG 0x000022e5
2453
2454#define REG_A4XX_SP_FS_CTRL_REG0 0x000022e8
2455#define A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
2456#define A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
2457static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
2458{
2459 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
2460}
2461#define A4XX_SP_FS_CTRL_REG0_VARYING 0x00000002
2462#define A4XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
2463#define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
2464#define A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
2465static inline uint32_t A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2466{
2467 return ((val) << A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2468}
2469#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
2470#define A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
2471static inline uint32_t A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2472{
2473 return ((val) << A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2474}
2475#define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
2476#define A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
2477static inline uint32_t A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
2478{
2479 return ((val) << A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP__MASK;
2480}
2481#define A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
2482#define A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
2483static inline uint32_t A4XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2484{
2485 return ((val) << A4XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
2486}
2487#define A4XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
2488#define A4XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
2489
2490#define REG_A4XX_SP_FS_CTRL_REG1 0x000022e9
2491#define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000000ff
2492#define A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0
2493static inline uint32_t A4XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
2494{
2495 return ((val) << A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A4XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
2496}
2497#define A4XX_SP_FS_CTRL_REG1_FACENESS 0x00080000
2498#define A4XX_SP_FS_CTRL_REG1_VARYING 0x00100000
2499#define A4XX_SP_FS_CTRL_REG1_FRAGCOORD 0x00200000
2500
2501#define REG_A4XX_SP_FS_OBJ_OFFSET_REG 0x000022ea
2502#define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2503#define A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2504static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2505{
2506 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2507}
2508#define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2509#define A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2510static inline uint32_t A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2511{
2512 return ((val) << A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2513}
2514
2515#define REG_A4XX_SP_FS_OBJ_START 0x000022eb
2516
2517#define REG_A4XX_SP_FS_PVT_MEM_PARAM 0x000022ec
2518
2519#define REG_A4XX_SP_FS_PVT_MEM_ADDR 0x000022ed
2520
2521#define REG_A4XX_SP_FS_LENGTH_REG 0x000022ef
2522
2523#define REG_A4XX_SP_FS_OUTPUT_REG 0x000022f0
2524#define A4XX_SP_FS_OUTPUT_REG_MRT__MASK 0x0000000f
2525#define A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0
2526static inline uint32_t A4XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
2527{
2528 return ((val) << A4XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A4XX_SP_FS_OUTPUT_REG_MRT__MASK;
2529}
2530#define A4XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080
2531#define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00
2532#define A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8
2533static inline uint32_t A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
2534{
2535 return ((val) << A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
2536}
2537#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK 0xff000000
2538#define A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT 24
2539static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val)
2540{
2541 return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK;
2542}
2543
2544#define REG_A4XX_SP_FS_MRT(i0) (0x000022f1 + 0x1*(i0))
2545
2546static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; }
2547#define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
2548#define A4XX_SP_FS_MRT_REG_REGID__SHIFT 0
2549static inline uint32_t A4XX_SP_FS_MRT_REG_REGID(uint32_t val)
2550{
2551 return ((val) << A4XX_SP_FS_MRT_REG_REGID__SHIFT) & A4XX_SP_FS_MRT_REG_REGID__MASK;
2552}
2553#define A4XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
2554#define A4XX_SP_FS_MRT_REG_COLOR_SINT 0x00000400
2555#define A4XX_SP_FS_MRT_REG_COLOR_UINT 0x00000800
2556#define A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK 0x0003f000
2557#define A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT 12
2558static inline uint32_t A4XX_SP_FS_MRT_REG_MRTFORMAT(enum a4xx_color_fmt val)
2559{
2560 return ((val) << A4XX_SP_FS_MRT_REG_MRTFORMAT__SHIFT) & A4XX_SP_FS_MRT_REG_MRTFORMAT__MASK;
2561}
2562#define A4XX_SP_FS_MRT_REG_COLOR_SRGB 0x00040000
2563
2564#define REG_A4XX_SP_CS_CTRL_REG0 0x00002300
2565#define A4XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001
2566#define A4XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0
2567static inline uint32_t A4XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
2568{
2569 return ((val) << A4XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A4XX_SP_CS_CTRL_REG0_THREADMODE__MASK;
2570}
2571#define A4XX_SP_CS_CTRL_REG0_VARYING 0x00000002
2572#define A4XX_SP_CS_CTRL_REG0_CACHEINVALID 0x00000004
2573#define A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
2574#define A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
2575static inline uint32_t A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2576{
2577 return ((val) << A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A4XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2578}
2579#define A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
2580#define A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
2581static inline uint32_t A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2582{
2583 return ((val) << A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A4XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2584}
2585#define A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__MASK 0x000c0000
2586#define A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__SHIFT 18
2587static inline uint32_t A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP(uint32_t val)
2588{
2589 return ((val) << A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__SHIFT) & A4XX_SP_CS_CTRL_REG0_INOUTREGOVERLAP__MASK;
2590}
2591#define A4XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000
2592#define A4XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20
2593static inline uint32_t A4XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2594{
2595 return ((val) << A4XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A4XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
2596}
2597#define A4XX_SP_CS_CTRL_REG0_SUPERTHREADMODE 0x00200000
2598#define A4XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x00400000
2599
2600#define REG_A4XX_SP_CS_OBJ_OFFSET_REG 0x00002301
2601
2602#define REG_A4XX_SP_CS_OBJ_START 0x00002302
2603
2604#define REG_A4XX_SP_CS_PVT_MEM_PARAM 0x00002303
2605
2606#define REG_A4XX_SP_CS_PVT_MEM_ADDR 0x00002304
2607
2608#define REG_A4XX_SP_CS_PVT_MEM_SIZE 0x00002305
2609
2610#define REG_A4XX_SP_CS_LENGTH_REG 0x00002306
2611
2612#define REG_A4XX_SP_HS_OBJ_OFFSET_REG 0x0000230d
2613#define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2614#define A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2615static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2616{
2617 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2618}
2619#define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2620#define A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2621static inline uint32_t A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2622{
2623 return ((val) << A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_HS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2624}
2625
2626#define REG_A4XX_SP_HS_OBJ_START 0x0000230e
2627
2628#define REG_A4XX_SP_HS_PVT_MEM_PARAM 0x0000230f
2629
2630#define REG_A4XX_SP_HS_PVT_MEM_ADDR 0x00002310
2631
2632#define REG_A4XX_SP_HS_LENGTH_REG 0x00002312
2633
2634#define REG_A4XX_SP_DS_PARAM_REG 0x0000231a
2635#define A4XX_SP_DS_PARAM_REG_POSREGID__MASK 0x000000ff
2636#define A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT 0
2637static inline uint32_t A4XX_SP_DS_PARAM_REG_POSREGID(uint32_t val)
2638{
2639 return ((val) << A4XX_SP_DS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_DS_PARAM_REG_POSREGID__MASK;
2640}
2641#define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
2642#define A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
2643static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
2644{
2645 return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK;
2646}
2647
2648#define REG_A4XX_SP_DS_OUT(i0) (0x0000231b + 0x1*(i0))
2649
2650static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; }
2651#define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff
2652#define A4XX_SP_DS_OUT_REG_A_REGID__SHIFT 0
2653static inline uint32_t A4XX_SP_DS_OUT_REG_A_REGID(uint32_t val)
2654{
2655 return ((val) << A4XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_A_REGID__MASK;
2656}
2657#define A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00001e00
2658#define A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 9
2659static inline uint32_t A4XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val)
2660{
2661 return ((val) << A4XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_A_COMPMASK__MASK;
2662}
2663#define A4XX_SP_DS_OUT_REG_B_REGID__MASK 0x01ff0000
2664#define A4XX_SP_DS_OUT_REG_B_REGID__SHIFT 16
2665static inline uint32_t A4XX_SP_DS_OUT_REG_B_REGID(uint32_t val)
2666{
2667 return ((val) << A4XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_DS_OUT_REG_B_REGID__MASK;
2668}
2669#define A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x1e000000
2670#define A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 25
2671static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val)
2672{
2673 return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK;
2674}
2675
2676#define REG_A4XX_SP_DS_VPC_DST(i0) (0x0000232c + 0x1*(i0))
2677
2678static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; }
2679#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
2680#define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0
2681static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val)
2682{
2683 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK;
2684}
2685#define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
2686#define A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8
2687static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val)
2688{
2689 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK;
2690}
2691#define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
2692#define A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16
2693static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val)
2694{
2695 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK;
2696}
2697#define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
2698#define A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24
2699static inline uint32_t A4XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val)
2700{
2701 return ((val) << A4XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK;
2702}
2703
2704#define REG_A4XX_SP_DS_OBJ_OFFSET_REG 0x00002334
2705#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2706#define A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2707static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2708{
2709 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2710}
2711#define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2712#define A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2713static inline uint32_t A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2714{
2715 return ((val) << A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_DS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2716}
2717
2718#define REG_A4XX_SP_DS_OBJ_START 0x00002335
2719
2720#define REG_A4XX_SP_DS_PVT_MEM_PARAM 0x00002336
2721
2722#define REG_A4XX_SP_DS_PVT_MEM_ADDR 0x00002337
2723
2724#define REG_A4XX_SP_DS_LENGTH_REG 0x00002339
2725
2726#define REG_A4XX_SP_GS_PARAM_REG 0x00002341
2727#define A4XX_SP_GS_PARAM_REG_POSREGID__MASK 0x000000ff
2728#define A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT 0
2729static inline uint32_t A4XX_SP_GS_PARAM_REG_POSREGID(uint32_t val)
2730{
2731 return ((val) << A4XX_SP_GS_PARAM_REG_POSREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_POSREGID__MASK;
2732}
2733#define A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK 0x0000ff00
2734#define A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT 8
2735static inline uint32_t A4XX_SP_GS_PARAM_REG_PRIMREGID(uint32_t val)
2736{
2737 return ((val) << A4XX_SP_GS_PARAM_REG_PRIMREGID__SHIFT) & A4XX_SP_GS_PARAM_REG_PRIMREGID__MASK;
2738}
2739#define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK 0xfff00000
2740#define A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT 20
2741static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val)
2742{
2743 return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK;
2744}
2745
2746#define REG_A4XX_SP_GS_OUT(i0) (0x00002342 + 0x1*(i0))
2747
2748static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; }
2749#define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff
2750#define A4XX_SP_GS_OUT_REG_A_REGID__SHIFT 0
2751static inline uint32_t A4XX_SP_GS_OUT_REG_A_REGID(uint32_t val)
2752{
2753 return ((val) << A4XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_A_REGID__MASK;
2754}
2755#define A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00001e00
2756#define A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 9
2757static inline uint32_t A4XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val)
2758{
2759 return ((val) << A4XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_A_COMPMASK__MASK;
2760}
2761#define A4XX_SP_GS_OUT_REG_B_REGID__MASK 0x01ff0000
2762#define A4XX_SP_GS_OUT_REG_B_REGID__SHIFT 16
2763static inline uint32_t A4XX_SP_GS_OUT_REG_B_REGID(uint32_t val)
2764{
2765 return ((val) << A4XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A4XX_SP_GS_OUT_REG_B_REGID__MASK;
2766}
2767#define A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x1e000000
2768#define A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 25
2769static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val)
2770{
2771 return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK;
2772}
2773
2774#define REG_A4XX_SP_GS_VPC_DST(i0) (0x00002353 + 0x1*(i0))
2775
2776static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; }
2777#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
2778#define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0
2779static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val)
2780{
2781 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK;
2782}
2783#define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
2784#define A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8
2785static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val)
2786{
2787 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK;
2788}
2789#define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
2790#define A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16
2791static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val)
2792{
2793 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK;
2794}
2795#define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
2796#define A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24
2797static inline uint32_t A4XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val)
2798{
2799 return ((val) << A4XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A4XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK;
2800}
2801
2802#define REG_A4XX_SP_GS_OBJ_OFFSET_REG 0x0000235b
2803#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2804#define A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2805static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2806{
2807 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2808}
2809#define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2810#define A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2811static inline uint32_t A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2812{
2813 return ((val) << A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A4XX_SP_GS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2814}
2815
2816#define REG_A4XX_SP_GS_OBJ_START 0x0000235c
2817
2818#define REG_A4XX_SP_GS_PVT_MEM_PARAM 0x0000235d
2819
2820#define REG_A4XX_SP_GS_PVT_MEM_ADDR 0x0000235e
2821
2822#define REG_A4XX_SP_GS_LENGTH_REG 0x00002360
2823
2824#define REG_A4XX_VPC_DEBUG_RAM_SEL 0x00000e60
2825
2826#define REG_A4XX_VPC_DEBUG_RAM_READ 0x00000e61
2827
2828#define REG_A4XX_VPC_DEBUG_ECO_CONTROL 0x00000e64
2829
2830#define REG_A4XX_VPC_PERFCTR_VPC_SEL_0 0x00000e65
2831
2832#define REG_A4XX_VPC_PERFCTR_VPC_SEL_1 0x00000e66
2833
2834#define REG_A4XX_VPC_PERFCTR_VPC_SEL_2 0x00000e67
2835
2836#define REG_A4XX_VPC_PERFCTR_VPC_SEL_3 0x00000e68
2837
2838#define REG_A4XX_VPC_ATTR 0x00002140
2839#define A4XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff
2840#define A4XX_VPC_ATTR_TOTALATTR__SHIFT 0
2841static inline uint32_t A4XX_VPC_ATTR_TOTALATTR(uint32_t val)
2842{
2843 return ((val) << A4XX_VPC_ATTR_TOTALATTR__SHIFT) & A4XX_VPC_ATTR_TOTALATTR__MASK;
2844}
2845#define A4XX_VPC_ATTR_PSIZE 0x00000200
2846#define A4XX_VPC_ATTR_THRDASSIGN__MASK 0x00003000
2847#define A4XX_VPC_ATTR_THRDASSIGN__SHIFT 12
2848static inline uint32_t A4XX_VPC_ATTR_THRDASSIGN(uint32_t val)
2849{
2850 return ((val) << A4XX_VPC_ATTR_THRDASSIGN__SHIFT) & A4XX_VPC_ATTR_THRDASSIGN__MASK;
2851}
2852#define A4XX_VPC_ATTR_ENABLE 0x02000000
2853
2854#define REG_A4XX_VPC_PACK 0x00002141
2855#define A4XX_VPC_PACK_NUMBYPASSVAR__MASK 0x000000ff
2856#define A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT 0
2857static inline uint32_t A4XX_VPC_PACK_NUMBYPASSVAR(uint32_t val)
2858{
2859 return ((val) << A4XX_VPC_PACK_NUMBYPASSVAR__SHIFT) & A4XX_VPC_PACK_NUMBYPASSVAR__MASK;
2860}
2861#define A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00
2862#define A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8
2863static inline uint32_t A4XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
2864{
2865 return ((val) << A4XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A4XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
2866}
2867#define A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000
2868#define A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16
2869static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
2870{
2871 return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
2872}
2873
2874#define REG_A4XX_VPC_VARYING_INTERP(i0) (0x00002142 + 0x1*(i0))
2875
2876static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; }
2877
2878#define REG_A4XX_VPC_VARYING_PS_REPL(i0) (0x0000214a + 0x1*(i0))
2879
2880static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; }
2881
2882#define REG_A4XX_VPC_SO_FLUSH_WADDR_3 0x0000216e
2883
2884#define REG_A4XX_VSC_BIN_SIZE 0x00000c00
2885#define A4XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
2886#define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
2887static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2888{
2889 assert(!(val & 0x1f));
2890 return (((val >> 5)) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK;
2891}
2892#define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
2893#define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5
2894static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2895{
2896 assert(!(val & 0x1f));
2897 return (((val >> 5)) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK;
2898}
2899
2900#define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01
2901
2902#define REG_A4XX_VSC_SIZE_ADDRESS2 0x00000c02
2903
2904#define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03
2905
2906#define REG_A4XX_VSC_PIPE_CONFIG(i0) (0x00000c08 + 0x1*(i0))
2907
2908static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; }
2909#define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
2910#define A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
2911static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
2912{
2913 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_X__MASK;
2914}
2915#define A4XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
2916#define A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
2917static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
2918{
2919 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_Y__MASK;
2920}
2921#define A4XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
2922#define A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
2923static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
2924{
2925 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_W__MASK;
2926}
2927#define A4XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
2928#define A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
2929static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
2930{
2931 return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK;
2932}
2933
2934#define REG_A4XX_VSC_PIPE_DATA_ADDRESS(i0) (0x00000c10 + 0x1*(i0))
2935
2936static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; }
2937
2938#define REG_A4XX_VSC_PIPE_DATA_LENGTH(i0) (0x00000c18 + 0x1*(i0))
2939
2940static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; }
2941
2942#define REG_A4XX_VSC_PIPE_PARTIAL_POSN_1 0x00000c41
2943
2944#define REG_A4XX_VSC_PERFCTR_VSC_SEL_0 0x00000c50
2945
2946#define REG_A4XX_VSC_PERFCTR_VSC_SEL_1 0x00000c51
2947
2948#define REG_A4XX_VFD_DEBUG_CONTROL 0x00000e40
2949
2950#define REG_A4XX_VFD_PERFCTR_VFD_SEL_0 0x00000e43
2951
2952#define REG_A4XX_VFD_PERFCTR_VFD_SEL_1 0x00000e44
2953
2954#define REG_A4XX_VFD_PERFCTR_VFD_SEL_2 0x00000e45
2955
2956#define REG_A4XX_VFD_PERFCTR_VFD_SEL_3 0x00000e46
2957
2958#define REG_A4XX_VFD_PERFCTR_VFD_SEL_4 0x00000e47
2959
2960#define REG_A4XX_VFD_PERFCTR_VFD_SEL_5 0x00000e48
2961
2962#define REG_A4XX_VFD_PERFCTR_VFD_SEL_6 0x00000e49
2963
2964#define REG_A4XX_VFD_PERFCTR_VFD_SEL_7 0x00000e4a
2965
2966#define REG_A4XX_VGT_CL_INITIATOR 0x000021d0
2967
2968#define REG_A4XX_VGT_EVENT_INITIATOR 0x000021d9
2969
2970#define REG_A4XX_VFD_CONTROL_0 0x00002200
2971#define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x000000ff
2972#define A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0
2973static inline uint32_t A4XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
2974{
2975 return ((val) << A4XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A4XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
2976}
2977#define A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK 0x0001fe00
2978#define A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT 9
2979static inline uint32_t A4XX_VFD_CONTROL_0_BYPASSATTROVS(uint32_t val)
2980{
2981 return ((val) << A4XX_VFD_CONTROL_0_BYPASSATTROVS__SHIFT) & A4XX_VFD_CONTROL_0_BYPASSATTROVS__MASK;
2982}
2983#define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x03f00000
2984#define A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 20
2985static inline uint32_t A4XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
2986{
2987 return ((val) << A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
2988}
2989#define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xfc000000
2990#define A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 26
2991static inline uint32_t A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
2992{
2993 return ((val) << A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A4XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
2994}
2995
2996#define REG_A4XX_VFD_CONTROL_1 0x00002201
2997#define A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000ffff
2998#define A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
2999static inline uint32_t A4XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
3000{
3001 return ((val) << A4XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A4XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
3002}
3003#define A4XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
3004#define A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
3005static inline uint32_t A4XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
3006{
3007 return ((val) << A4XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A4XX_VFD_CONTROL_1_REGID4VTX__MASK;
3008}
3009#define A4XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
3010#define A4XX_VFD_CONTROL_1_REGID4INST__SHIFT 24
3011static inline uint32_t A4XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
3012{
3013 return ((val) << A4XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A4XX_VFD_CONTROL_1_REGID4INST__MASK;
3014}
3015
3016#define REG_A4XX_VFD_CONTROL_2 0x00002202
3017
3018#define REG_A4XX_VFD_CONTROL_3 0x00002203
3019#define A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK 0x0000ff00
3020#define A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT 8
3021static inline uint32_t A4XX_VFD_CONTROL_3_REGID_VTXCNT(uint32_t val)
3022{
3023 return ((val) << A4XX_VFD_CONTROL_3_REGID_VTXCNT__SHIFT) & A4XX_VFD_CONTROL_3_REGID_VTXCNT__MASK;
3024}
3025#define A4XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
3026#define A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
3027static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
3028{
3029 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSX__MASK;
3030}
3031#define A4XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
3032#define A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
3033static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
3034{
3035 return ((val) << A4XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A4XX_VFD_CONTROL_3_REGID_TESSY__MASK;
3036}
3037
3038#define REG_A4XX_VFD_CONTROL_4 0x00002204
3039
3040#define REG_A4XX_VFD_INDEX_OFFSET 0x00002208
3041
3042#define REG_A4XX_VFD_FETCH(i0) (0x0000220a + 0x4*(i0))
3043
3044static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; }
3045#define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
3046#define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0
3047static inline uint32_t A4XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
3048{
3049 return ((val) << A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
3050}
3051#define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0001ff80
3052#define A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7
3053static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
3054{
3055 return ((val) << A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
3056}
3057#define A4XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00080000
3058#define A4XX_VFD_FETCH_INSTR_0_INSTANCED 0x00100000
3059
3060static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }
3061
3062static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }
3063#define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xffffffff
3064#define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 0
3065static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
3066{
3067 return ((val) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
3068}
3069
3070static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }
3071#define A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK 0x000001ff
3072#define A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT 0
3073static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val)
3074{
3075 return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK;
3076}
3077
3078#define REG_A4XX_VFD_DECODE(i0) (0x0000228a + 0x1*(i0))
3079
3080static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; }
3081#define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
3082#define A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0
3083static inline uint32_t A4XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
3084{
3085 return ((val) << A4XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
3086}
3087#define A4XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010
3088#define A4XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0
3089#define A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6
3090static inline uint32_t A4XX_VFD_DECODE_INSTR_FORMAT(enum a4xx_vtx_fmt val)
3091{
3092 return ((val) << A4XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A4XX_VFD_DECODE_INSTR_FORMAT__MASK;
3093}
3094#define A4XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000
3095#define A4XX_VFD_DECODE_INSTR_REGID__SHIFT 12
3096static inline uint32_t A4XX_VFD_DECODE_INSTR_REGID(uint32_t val)
3097{
3098 return ((val) << A4XX_VFD_DECODE_INSTR_REGID__SHIFT) & A4XX_VFD_DECODE_INSTR_REGID__MASK;
3099}
3100#define A4XX_VFD_DECODE_INSTR_INT 0x00100000
3101#define A4XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000
3102#define A4XX_VFD_DECODE_INSTR_SWAP__SHIFT 22
3103static inline uint32_t A4XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
3104{
3105 return ((val) << A4XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A4XX_VFD_DECODE_INSTR_SWAP__MASK;
3106}
3107#define A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000
3108#define A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24
3109static inline uint32_t A4XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
3110{
3111 return ((val) << A4XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A4XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
3112}
3113#define A4XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
3114#define A4XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
3115
3116#define REG_A4XX_TPL1_DEBUG_ECO_CONTROL 0x00000f00
3117
3118#define REG_A4XX_TPL1_TP_MODE_CONTROL 0x00000f03
3119
3120#define REG_A4XX_TPL1_PERFCTR_TP_SEL_0 0x00000f04
3121
3122#define REG_A4XX_TPL1_PERFCTR_TP_SEL_1 0x00000f05
3123
3124#define REG_A4XX_TPL1_PERFCTR_TP_SEL_2 0x00000f06
3125
3126#define REG_A4XX_TPL1_PERFCTR_TP_SEL_3 0x00000f07
3127
3128#define REG_A4XX_TPL1_PERFCTR_TP_SEL_4 0x00000f08
3129
3130#define REG_A4XX_TPL1_PERFCTR_TP_SEL_5 0x00000f09
3131
3132#define REG_A4XX_TPL1_PERFCTR_TP_SEL_6 0x00000f0a
3133
3134#define REG_A4XX_TPL1_PERFCTR_TP_SEL_7 0x00000f0b
3135
3136#define REG_A4XX_TPL1_TP_TEX_OFFSET 0x00002380
3137
3138#define REG_A4XX_TPL1_TP_TEX_COUNT 0x00002381
3139#define A4XX_TPL1_TP_TEX_COUNT_VS__MASK 0x000000ff
3140#define A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT 0
3141static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_VS(uint32_t val)
3142{
3143 return ((val) << A4XX_TPL1_TP_TEX_COUNT_VS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_VS__MASK;
3144}
3145#define A4XX_TPL1_TP_TEX_COUNT_HS__MASK 0x0000ff00
3146#define A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT 8
3147static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_HS(uint32_t val)
3148{
3149 return ((val) << A4XX_TPL1_TP_TEX_COUNT_HS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_HS__MASK;
3150}
3151#define A4XX_TPL1_TP_TEX_COUNT_DS__MASK 0x00ff0000
3152#define A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT 16
3153static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_DS(uint32_t val)
3154{
3155 return ((val) << A4XX_TPL1_TP_TEX_COUNT_DS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_DS__MASK;
3156}
3157#define A4XX_TPL1_TP_TEX_COUNT_GS__MASK 0xff000000
3158#define A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT 24
3159static inline uint32_t A4XX_TPL1_TP_TEX_COUNT_GS(uint32_t val)
3160{
3161 return ((val) << A4XX_TPL1_TP_TEX_COUNT_GS__SHIFT) & A4XX_TPL1_TP_TEX_COUNT_GS__MASK;
3162}
3163
3164#define REG_A4XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002384
3165
3166#define REG_A4XX_TPL1_TP_HS_BORDER_COLOR_BASE_ADDR 0x00002387
3167
3168#define REG_A4XX_TPL1_TP_DS_BORDER_COLOR_BASE_ADDR 0x0000238a
3169
3170#define REG_A4XX_TPL1_TP_GS_BORDER_COLOR_BASE_ADDR 0x0000238d
3171
3172#define REG_A4XX_TPL1_TP_FS_TEX_COUNT 0x000023a0
3173#define A4XX_TPL1_TP_FS_TEX_COUNT_FS__MASK 0x000000ff
3174#define A4XX_TPL1_TP_FS_TEX_COUNT_FS__SHIFT 0
3175static inline uint32_t A4XX_TPL1_TP_FS_TEX_COUNT_FS(uint32_t val)
3176{
3177 return ((val) << A4XX_TPL1_TP_FS_TEX_COUNT_FS__SHIFT) & A4XX_TPL1_TP_FS_TEX_COUNT_FS__MASK;
3178}
3179#define A4XX_TPL1_TP_FS_TEX_COUNT_CS__MASK 0x0000ff00
3180#define A4XX_TPL1_TP_FS_TEX_COUNT_CS__SHIFT 8
3181static inline uint32_t A4XX_TPL1_TP_FS_TEX_COUNT_CS(uint32_t val)
3182{
3183 return ((val) << A4XX_TPL1_TP_FS_TEX_COUNT_CS__SHIFT) & A4XX_TPL1_TP_FS_TEX_COUNT_CS__MASK;
3184}
3185
3186#define REG_A4XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x000023a1
3187
3188#define REG_A4XX_TPL1_TP_CS_BORDER_COLOR_BASE_ADDR 0x000023a4
3189
3190#define REG_A4XX_TPL1_TP_CS_SAMPLER_BASE_ADDR 0x000023a5
3191
3192#define REG_A4XX_TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR 0x000023a6
3193
3194#define REG_A4XX_GRAS_TSE_STATUS 0x00000c80
3195
3196#define REG_A4XX_GRAS_DEBUG_ECO_CONTROL 0x00000c81
3197
3198#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c88
3199
3200#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c89
3201
3202#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c8a
3203
3204#define REG_A4XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c8b
3205
3206#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c8c
3207
3208#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c8d
3209
3210#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c8e
3211
3212#define REG_A4XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c8f
3213
3214#define REG_A4XX_GRAS_CL_CLIP_CNTL 0x00002000
3215#define A4XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00008000
3216#define A4XX_GRAS_CL_CLIP_CNTL_ZNEAR_CLIP_DISABLE 0x00010000
3217#define A4XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000
3218#define A4XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000
3219
3220#define REG_A4XX_GRAS_CNTL 0x00002003
3221#define A4XX_GRAS_CNTL_IJ_PERSP 0x00000001
3222#define A4XX_GRAS_CNTL_IJ_LINEAR 0x00000002
3223
3224#define REG_A4XX_GRAS_CL_GB_CLIP_ADJ 0x00002004
3225#define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
3226#define A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
3227static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
3228{
3229 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
3230}
3231#define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00
3232#define A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10
3233static inline uint32_t A4XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
3234{
3235 return ((val) << A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A4XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
3236}
3237
3238#define REG_A4XX_GRAS_CL_VPORT_XOFFSET_0 0x00002008
3239#define A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
3240#define A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
3241static inline uint32_t A4XX_GRAS_CL_VPORT_XOFFSET_0(float val)
3242{
3243 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
3244}
3245
3246#define REG_A4XX_GRAS_CL_VPORT_XSCALE_0 0x00002009
3247#define A4XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
3248#define A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
3249static inline uint32_t A4XX_GRAS_CL_VPORT_XSCALE_0(float val)
3250{
3251 return ((fui(val)) << A4XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_XSCALE_0__MASK;
3252}
3253
3254#define REG_A4XX_GRAS_CL_VPORT_YOFFSET_0 0x0000200a
3255#define A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
3256#define A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
3257static inline uint32_t A4XX_GRAS_CL_VPORT_YOFFSET_0(float val)
3258{
3259 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
3260}
3261
3262#define REG_A4XX_GRAS_CL_VPORT_YSCALE_0 0x0000200b
3263#define A4XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
3264#define A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
3265static inline uint32_t A4XX_GRAS_CL_VPORT_YSCALE_0(float val)
3266{
3267 return ((fui(val)) << A4XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_YSCALE_0__MASK;
3268}
3269
3270#define REG_A4XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000200c
3271#define A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
3272#define A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
3273static inline uint32_t A4XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
3274{
3275 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
3276}
3277
3278#define REG_A4XX_GRAS_CL_VPORT_ZSCALE_0 0x0000200d
3279#define A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
3280#define A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
3281static inline uint32_t A4XX_GRAS_CL_VPORT_ZSCALE_0(float val)
3282{
3283 return ((fui(val)) << A4XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A4XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
3284}
3285
3286#define REG_A4XX_GRAS_SU_POINT_MINMAX 0x00002070
3287#define A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
3288#define A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
3289static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MIN(float val)
3290{
3291 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
3292}
3293#define A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
3294#define A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
3295static inline uint32_t A4XX_GRAS_SU_POINT_MINMAX_MAX(float val)
3296{
3297 return ((((uint32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A4XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
3298}
3299
3300#define REG_A4XX_GRAS_SU_POINT_SIZE 0x00002071
3301#define A4XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
3302#define A4XX_GRAS_SU_POINT_SIZE__SHIFT 0
3303static inline uint32_t A4XX_GRAS_SU_POINT_SIZE(float val)
3304{
3305 return ((((int32_t)(val * 16.0))) << A4XX_GRAS_SU_POINT_SIZE__SHIFT) & A4XX_GRAS_SU_POINT_SIZE__MASK;
3306}
3307
3308#define REG_A4XX_GRAS_ALPHA_CONTROL 0x00002073
3309#define A4XX_GRAS_ALPHA_CONTROL_ALPHA_TEST_ENABLE 0x00000004
3310#define A4XX_GRAS_ALPHA_CONTROL_FORCE_FRAGZ_TO_FS 0x00000008
3311
3312#define REG_A4XX_GRAS_SU_POLY_OFFSET_SCALE 0x00002074
3313#define A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
3314#define A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
3315static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
3316{
3317 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
3318}
3319
3320#define REG_A4XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00002075
3321#define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
3322#define A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
3323static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
3324{
3325 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
3326}
3327
3328#define REG_A4XX_GRAS_SU_POLY_OFFSET_CLAMP 0x00002076
3329#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK 0xffffffff
3330#define A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT 0
3331static inline uint32_t A4XX_GRAS_SU_POLY_OFFSET_CLAMP(float val)
3332{
3333 return ((fui(val)) << A4XX_GRAS_SU_POLY_OFFSET_CLAMP__SHIFT) & A4XX_GRAS_SU_POLY_OFFSET_CLAMP__MASK;
3334}
3335
3336#define REG_A4XX_GRAS_DEPTH_CONTROL 0x00002077
3337#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK 0x00000003
3338#define A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT 0
3339static inline uint32_t A4XX_GRAS_DEPTH_CONTROL_FORMAT(enum a4xx_depth_format val)
3340{
3341 return ((val) << A4XX_GRAS_DEPTH_CONTROL_FORMAT__SHIFT) & A4XX_GRAS_DEPTH_CONTROL_FORMAT__MASK;
3342}
3343
3344#define REG_A4XX_GRAS_SU_MODE_CONTROL 0x00002078
3345#define A4XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
3346#define A4XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
3347#define A4XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
3348#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
3349#define A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3
3350static inline uint32_t A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
3351{
3352 return ((((int32_t)(val * 4.0))) << A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A4XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
3353}
3354#define A4XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
3355#define A4XX_GRAS_SU_MODE_CONTROL_MSAA_ENABLE 0x00002000
3356#define A4XX_GRAS_SU_MODE_CONTROL_RENDERING_PASS 0x00100000
3357
3358#define REG_A4XX_GRAS_SC_CONTROL 0x0000207b
3359#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x0000000c
3360#define A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 2
3361static inline uint32_t A4XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
3362{
3363 return ((val) << A4XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
3364}
3365#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000380
3366#define A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 7
3367static inline uint32_t A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES(uint32_t val)
3368{
3369 return ((val) << A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A4XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
3370}
3371#define A4XX_GRAS_SC_CONTROL_MSAA_DISABLE 0x00000800
3372#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000
3373#define A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12
3374static inline uint32_t A4XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
3375{
3376 return ((val) << A4XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A4XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
3377}
3378
3379#define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_TL 0x0000207c
3380#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
3381#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
3382#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
3383static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
3384{
3385 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
3386}
3387#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
3388#define A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
3389static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
3390{
3391 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
3392}
3393
3394#define REG_A4XX_GRAS_SC_SCREEN_SCISSOR_BR 0x0000207d
3395#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
3396#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
3397#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
3398static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
3399{
3400 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
3401}
3402#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
3403#define A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
3404static inline uint32_t A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
3405{
3406 return ((val) << A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
3407}
3408
3409#define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000209c
3410#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
3411#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
3412#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
3413static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
3414{
3415 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
3416}
3417#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
3418#define A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
3419static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
3420{
3421 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
3422}
3423
3424#define REG_A4XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000209d
3425#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
3426#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
3427#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
3428static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
3429{
3430 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
3431}
3432#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
3433#define A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
3434static inline uint32_t A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
3435{
3436 return ((val) << A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A4XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
3437}
3438
3439#define REG_A4XX_GRAS_SC_EXTENT_WINDOW_BR 0x0000209e
3440#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_WINDOW_OFFSET_DISABLE 0x80000000
3441#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK 0x00007fff
3442#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT 0
3443static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_X(uint32_t val)
3444{
3445 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_X__MASK;
3446}
3447#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK 0x7fff0000
3448#define A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT 16
3449static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y(uint32_t val)
3450{
3451 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_BR_Y__MASK;
3452}
3453
3454#define REG_A4XX_GRAS_SC_EXTENT_WINDOW_TL 0x0000209f
3455#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_WINDOW_OFFSET_DISABLE 0x80000000
3456#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK 0x00007fff
3457#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT 0
3458static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_X(uint32_t val)
3459{
3460 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_X__MASK;
3461}
3462#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK 0x7fff0000
3463#define A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT 16
3464static inline uint32_t A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y(uint32_t val)
3465{
3466 return ((val) << A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__SHIFT) & A4XX_GRAS_SC_EXTENT_WINDOW_TL_Y__MASK;
3467}
3468
3469#define REG_A4XX_UCHE_CACHE_MODE_CONTROL 0x00000e80
3470
3471#define REG_A4XX_UCHE_TRAP_BASE_LO 0x00000e83
3472
3473#define REG_A4XX_UCHE_TRAP_BASE_HI 0x00000e84
3474
3475#define REG_A4XX_UCHE_CACHE_STATUS 0x00000e88
3476
3477#define REG_A4XX_UCHE_INVALIDATE0 0x00000e8a
3478
3479#define REG_A4XX_UCHE_INVALIDATE1 0x00000e8b
3480
3481#define REG_A4XX_UCHE_CACHE_WAYS_VFD 0x00000e8c
3482
3483#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000e8e
3484
3485#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000e8f
3486
3487#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000e90
3488
3489#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000e91
3490
3491#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000e92
3492
3493#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000e93
3494
3495#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000e94
3496
3497#define REG_A4XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000e95
3498
3499#define REG_A4XX_HLSQ_TIMEOUT_THRESHOLD 0x00000e00
3500
3501#define REG_A4XX_HLSQ_DEBUG_ECO_CONTROL 0x00000e04
3502
3503#define REG_A4XX_HLSQ_MODE_CONTROL 0x00000e05
3504
3505#define REG_A4XX_HLSQ_PERF_PIPE_MASK 0x00000e0e
3506
3507#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e06
3508
3509#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e07
3510
3511#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e08
3512
3513#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e09
3514
3515#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e0a
3516
3517#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e0b
3518
3519#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e0c
3520
3521#define REG_A4XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e0d
3522
3523#define REG_A4XX_HLSQ_CONTROL_0_REG 0x000023c0
3524#define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000010
3525#define A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
3526static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
3527{
3528 return ((val) << A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
3529}
3530#define A4XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
3531#define A4XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
3532#define A4XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
3533#define A4XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
3534#define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000
3535#define A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27
3536static inline uint32_t A4XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
3537{
3538 return ((val) << A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A4XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
3539}
3540#define A4XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
3541#define A4XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
3542#define A4XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
3543#define A4XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
3544
3545#define REG_A4XX_HLSQ_CONTROL_1_REG 0x000023c1
3546#define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x00000040
3547#define A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
3548static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
3549{
3550 return ((val) << A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
3551}
3552#define A4XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
3553#define A4XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
3554#define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK 0x00ff0000
3555#define A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT 16
3556static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_COORDREGID(uint32_t val)
3557{
3558 return ((val) << A4XX_HLSQ_CONTROL_1_REG_COORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_COORDREGID__MASK;
3559}
3560#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK 0xff000000
3561#define A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT 24
3562static inline uint32_t A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID(uint32_t val)
3563{
3564 return ((val) << A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__SHIFT) & A4XX_HLSQ_CONTROL_1_REG_ZWCOORDREGID__MASK;
3565}
3566
3567#define REG_A4XX_HLSQ_CONTROL_2_REG 0x000023c2
3568#define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
3569#define A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
3570static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
3571{
3572 return ((val) << A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
3573}
3574#define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000003fc
3575#define A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 2
3576static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
3577{
3578 return ((val) << A4XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
3579}
3580#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK 0x0003fc00
3581#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT 10
3582static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID(uint32_t val)
3583{
3584 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEID_REGID__MASK;
3585}
3586#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK 0x03fc0000
3587#define A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT 18
3588static inline uint32_t A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID(uint32_t val)
3589{
3590 return ((val) << A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_HLSQ_CONTROL_2_REG_SAMPLEMASK_REGID__MASK;
3591}
3592
3593#define REG_A4XX_HLSQ_CONTROL_3_REG 0x000023c3
3594#define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
3595#define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
3596static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
3597{
3598 return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
3599}
3600#define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
3601#define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
3602static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
3603{
3604 return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
3605}
3606#define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
3607#define A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
3608static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
3609{
3610 return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
3611}
3612#define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
3613#define A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
3614static inline uint32_t A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
3615{
3616 return ((val) << A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A4XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
3617}
3618
3619#define REG_A4XX_HLSQ_CONTROL_4_REG 0x000023c4
3620#define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
3621#define A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
3622static inline uint32_t A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
3623{
3624 return ((val) << A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A4XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
3625}
3626#define A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
3627#define A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8
3628static inline uint32_t A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
3629{
3630 return ((val) << A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A4XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
3631}
3632
3633#define REG_A4XX_HLSQ_VS_CONTROL_REG 0x000023c5
3634#define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3635#define A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3636static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3637{
3638 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
3639}
3640#define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3641#define A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
3642static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3643{
3644 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3645}
3646#define A4XX_HLSQ_VS_CONTROL_REG_SSBO_ENABLE 0x00008000
3647#define A4XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00010000
3648#define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3649#define A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
3650static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3651{
3652 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3653}
3654#define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3655#define A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24
3656static inline uint32_t A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3657{
3658 return ((val) << A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
3659}
3660
3661#define REG_A4XX_HLSQ_FS_CONTROL_REG 0x000023c6
3662#define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3663#define A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3664static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3665{
3666 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
3667}
3668#define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3669#define A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
3670static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3671{
3672 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3673}
3674#define A4XX_HLSQ_FS_CONTROL_REG_SSBO_ENABLE 0x00008000
3675#define A4XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00010000
3676#define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3677#define A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
3678static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3679{
3680 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3681}
3682#define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3683#define A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24
3684static inline uint32_t A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3685{
3686 return ((val) << A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
3687}
3688
3689#define REG_A4XX_HLSQ_HS_CONTROL_REG 0x000023c7
3690#define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3691#define A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3692static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3693{
3694 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTLENGTH__MASK;
3695}
3696#define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3697#define A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
3698static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3699{
3700 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3701}
3702#define A4XX_HLSQ_HS_CONTROL_REG_SSBO_ENABLE 0x00008000
3703#define A4XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00010000
3704#define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3705#define A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
3706static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3707{
3708 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3709}
3710#define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3711#define A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT 24
3712static inline uint32_t A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3713{
3714 return ((val) << A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_HS_CONTROL_REG_INSTRLENGTH__MASK;
3715}
3716
3717#define REG_A4XX_HLSQ_DS_CONTROL_REG 0x000023c8
3718#define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3719#define A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3720static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3721{
3722 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTLENGTH__MASK;
3723}
3724#define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3725#define A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
3726static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3727{
3728 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3729}
3730#define A4XX_HLSQ_DS_CONTROL_REG_SSBO_ENABLE 0x00008000
3731#define A4XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00010000
3732#define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3733#define A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
3734static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3735{
3736 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3737}
3738#define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3739#define A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT 24
3740static inline uint32_t A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3741{
3742 return ((val) << A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_DS_CONTROL_REG_INSTRLENGTH__MASK;
3743}
3744
3745#define REG_A4XX_HLSQ_GS_CONTROL_REG 0x000023c9
3746#define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3747#define A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3748static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3749{
3750 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTLENGTH__MASK;
3751}
3752#define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3753#define A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
3754static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3755{
3756 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3757}
3758#define A4XX_HLSQ_GS_CONTROL_REG_SSBO_ENABLE 0x00008000
3759#define A4XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00010000
3760#define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3761#define A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
3762static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3763{
3764 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3765}
3766#define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3767#define A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT 24
3768static inline uint32_t A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3769{
3770 return ((val) << A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_GS_CONTROL_REG_INSTRLENGTH__MASK;
3771}
3772
3773#define REG_A4XX_HLSQ_CS_CONTROL_REG 0x000023ca
3774#define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK 0x000000ff
3775#define A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT 0
3776static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH(uint32_t val)
3777{
3778 return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTLENGTH__MASK;
3779}
3780#define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x00007f00
3781#define A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 8
3782static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
3783{
3784 return ((val) << A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
3785}
3786#define A4XX_HLSQ_CS_CONTROL_REG_SSBO_ENABLE 0x00008000
3787#define A4XX_HLSQ_CS_CONTROL_REG_ENABLED 0x00010000
3788#define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00fe0000
3789#define A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 17
3790static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
3791{
3792 return ((val) << A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_SHADEROBJOFFSET__MASK;
3793}
3794#define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
3795#define A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT 24
3796static inline uint32_t A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH(uint32_t val)
3797{
3798 return ((val) << A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__SHIFT) & A4XX_HLSQ_CS_CONTROL_REG_INSTRLENGTH__MASK;
3799}
3800
3801#define REG_A4XX_HLSQ_CL_NDRANGE_0 0x000023cd
3802#define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK 0x00000003
3803#define A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT 0
3804static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM(uint32_t val)
3805{
3806 return ((val) << A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_KERNELDIM__MASK;
3807}
3808#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
3809#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT 2
3810static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX(uint32_t val)
3811{
3812 return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEX__MASK;
3813}
3814#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
3815#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT 12
3816static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY(uint32_t val)
3817{
3818 return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEY__MASK;
3819}
3820#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
3821#define A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT 22
3822static inline uint32_t A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ(uint32_t val)
3823{
3824 return ((val) << A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__SHIFT) & A4XX_HLSQ_CL_NDRANGE_0_LOCALSIZEZ__MASK;
3825}
3826
3827#define REG_A4XX_HLSQ_CL_NDRANGE_1 0x000023ce
3828#define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK 0xffffffff
3829#define A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT 0
3830static inline uint32_t A4XX_HLSQ_CL_NDRANGE_1_SIZE_X(uint32_t val)
3831{
3832 return ((val) << A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__SHIFT) & A4XX_HLSQ_CL_NDRANGE_1_SIZE_X__MASK;
3833}
3834
3835#define REG_A4XX_HLSQ_CL_NDRANGE_2 0x000023cf
3836
3837#define REG_A4XX_HLSQ_CL_NDRANGE_3 0x000023d0
3838#define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK 0xffffffff
3839#define A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT 0
3840static inline uint32_t A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y(uint32_t val)
3841{
3842 return ((val) << A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__SHIFT) & A4XX_HLSQ_CL_NDRANGE_3_SIZE_Y__MASK;
3843}
3844
3845#define REG_A4XX_HLSQ_CL_NDRANGE_4 0x000023d1
3846
3847#define REG_A4XX_HLSQ_CL_NDRANGE_5 0x000023d2
3848#define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK 0xffffffff
3849#define A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT 0
3850static inline uint32_t A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z(uint32_t val)
3851{
3852 return ((val) << A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__SHIFT) & A4XX_HLSQ_CL_NDRANGE_5_SIZE_Z__MASK;
3853}
3854
3855#define REG_A4XX_HLSQ_CL_NDRANGE_6 0x000023d3
3856
3857#define REG_A4XX_HLSQ_CL_CONTROL_0 0x000023d4
3858#define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK 0x00000fff
3859#define A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT 0
3860static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID(uint32_t val)
3861{
3862 return ((val) << A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_WGIDCONSTID__MASK;
3863}
3864#define A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__MASK 0x00fff000
3865#define A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__SHIFT 12
3866static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID(uint32_t val)
3867{
3868 return ((val) << A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_KERNELDIMCONSTID__MASK;
3869}
3870#define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK 0xff000000
3871#define A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT 24
3872static inline uint32_t A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID(uint32_t val)
3873{
3874 return ((val) << A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__SHIFT) & A4XX_HLSQ_CL_CONTROL_0_LOCALIDREGID__MASK;
3875}
3876
3877#define REG_A4XX_HLSQ_CL_CONTROL_1 0x000023d5
3878#define A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__MASK 0x00000fff
3879#define A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__SHIFT 0
3880static inline uint32_t A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID(uint32_t val)
3881{
3882 return ((val) << A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_1_UNK0CONSTID__MASK;
3883}
3884#define A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__MASK 0x00fff000
3885#define A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__SHIFT 12
3886static inline uint32_t A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID(uint32_t val)
3887{
3888 return ((val) << A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__SHIFT) & A4XX_HLSQ_CL_CONTROL_1_WORKGROUPSIZECONSTID__MASK;
3889}
3890
3891#define REG_A4XX_HLSQ_CL_KERNEL_CONST 0x000023d6
3892#define A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__MASK 0x00000fff
3893#define A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__SHIFT 0
3894static inline uint32_t A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID(uint32_t val)
3895{
3896 return ((val) << A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__SHIFT) & A4XX_HLSQ_CL_KERNEL_CONST_UNK0CONSTID__MASK;
3897}
3898#define A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__MASK 0x00fff000
3899#define A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__SHIFT 12
3900static inline uint32_t A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID(uint32_t val)
3901{
3902 return ((val) << A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__SHIFT) & A4XX_HLSQ_CL_KERNEL_CONST_NUMWGCONSTID__MASK;
3903}
3904
3905#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_X 0x000023d7
3906
3907#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Y 0x000023d8
3908
3909#define REG_A4XX_HLSQ_CL_KERNEL_GROUP_Z 0x000023d9
3910
3911#define REG_A4XX_HLSQ_CL_WG_OFFSET 0x000023da
3912#define A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__MASK 0x00000fff
3913#define A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__SHIFT 0
3914static inline uint32_t A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID(uint32_t val)
3915{
3916 return ((val) << A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__SHIFT) & A4XX_HLSQ_CL_WG_OFFSET_UNK0CONSTID__MASK;
3917}
3918
3919#define REG_A4XX_HLSQ_UPDATE_CONTROL 0x000023db
3920
3921#define REG_A4XX_PC_BINNING_COMMAND 0x00000d00
3922#define A4XX_PC_BINNING_COMMAND_BINNING_ENABLE 0x00000001
3923
3924#define REG_A4XX_PC_TESSFACTOR_ADDR 0x00000d08
3925
3926#define REG_A4XX_PC_DRAWCALL_SETUP_OVERRIDE 0x00000d0c
3927
3928#define REG_A4XX_PC_PERFCTR_PC_SEL_0 0x00000d10
3929
3930#define REG_A4XX_PC_PERFCTR_PC_SEL_1 0x00000d11
3931
3932#define REG_A4XX_PC_PERFCTR_PC_SEL_2 0x00000d12
3933
3934#define REG_A4XX_PC_PERFCTR_PC_SEL_3 0x00000d13
3935
3936#define REG_A4XX_PC_PERFCTR_PC_SEL_4 0x00000d14
3937
3938#define REG_A4XX_PC_PERFCTR_PC_SEL_5 0x00000d15
3939
3940#define REG_A4XX_PC_PERFCTR_PC_SEL_6 0x00000d16
3941
3942#define REG_A4XX_PC_PERFCTR_PC_SEL_7 0x00000d17
3943
3944#define REG_A4XX_PC_BIN_BASE 0x000021c0
3945
3946#define REG_A4XX_PC_VSTREAM_CONTROL 0x000021c2
3947#define A4XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000
3948#define A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16
3949static inline uint32_t A4XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val)
3950{
3951 return ((val) << A4XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A4XX_PC_VSTREAM_CONTROL_SIZE__MASK;
3952}
3953#define A4XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000
3954#define A4XX_PC_VSTREAM_CONTROL_N__SHIFT 22
3955static inline uint32_t A4XX_PC_VSTREAM_CONTROL_N(uint32_t val)
3956{
3957 return ((val) << A4XX_PC_VSTREAM_CONTROL_N__SHIFT) & A4XX_PC_VSTREAM_CONTROL_N__MASK;
3958}
3959
3960#define REG_A4XX_PC_PRIM_VTX_CNTL 0x000021c4
3961#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK 0x0000000f
3962#define A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT 0
3963static inline uint32_t A4XX_PC_PRIM_VTX_CNTL_VAROUT(uint32_t val)
3964{
3965 return ((val) << A4XX_PC_PRIM_VTX_CNTL_VAROUT__SHIFT) & A4XX_PC_PRIM_VTX_CNTL_VAROUT__MASK;
3966}
3967#define A4XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
3968#define A4XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
3969#define A4XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
3970
3971#define REG_A4XX_PC_PRIM_VTX_CNTL2 0x000021c5
3972#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK 0x00000007
3973#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT 0
3974static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
3975{
3976 return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_FRONT_PTYPE__MASK;
3977}
3978#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK 0x00000038
3979#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT 3
3980static inline uint32_t A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
3981{
3982 return ((val) << A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__SHIFT) & A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_BACK_PTYPE__MASK;
3983}
3984#define A4XX_PC_PRIM_VTX_CNTL2_POLYMODE_ENABLE 0x00000040
3985
3986#define REG_A4XX_PC_RESTART_INDEX 0x000021c6
3987
3988#define REG_A4XX_PC_GS_PARAM 0x000021e5
3989#define A4XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
3990#define A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
3991static inline uint32_t A4XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
3992{
3993 return ((val) << A4XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A4XX_PC_GS_PARAM_MAX_VERTICES__MASK;
3994}
3995#define A4XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800
3996#define A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11
3997static inline uint32_t A4XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
3998{
3999 return ((val) << A4XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A4XX_PC_GS_PARAM_INVOCATIONS__MASK;
4000}
4001#define A4XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000
4002#define A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23
4003static inline uint32_t A4XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
4004{
4005 return ((val) << A4XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A4XX_PC_GS_PARAM_PRIMTYPE__MASK;
4006}
4007#define A4XX_PC_GS_PARAM_LAYER 0x80000000
4008
4009#define REG_A4XX_PC_HS_PARAM 0x000021e7
4010#define A4XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f
4011#define A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0
4012static inline uint32_t A4XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
4013{
4014 return ((val) << A4XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A4XX_PC_HS_PARAM_VERTICES_OUT__MASK;
4015}
4016#define A4XX_PC_HS_PARAM_SPACING__MASK 0x00600000
4017#define A4XX_PC_HS_PARAM_SPACING__SHIFT 21
4018static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
4019{
4020 return ((val) << A4XX_PC_HS_PARAM_SPACING__SHIFT) & A4XX_PC_HS_PARAM_SPACING__MASK;
4021}
4022#define A4XX_PC_HS_PARAM_CW 0x00800000
4023#define A4XX_PC_HS_PARAM_CONNECTED 0x01000000
4024
4025#define REG_A4XX_VBIF_VERSION 0x00003000
4026
4027#define REG_A4XX_VBIF_CLKON 0x00003001
4028#define A4XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000001
4029
4030#define REG_A4XX_VBIF_ABIT_SORT 0x0000301c
4031
4032#define REG_A4XX_VBIF_ABIT_SORT_CONF 0x0000301d
4033
4034#define REG_A4XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
4035
4036#define REG_A4XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
4037
4038#define REG_A4XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
4039
4040#define REG_A4XX_VBIF_IN_WR_LIM_CONF0 0x00003030
4041
4042#define REG_A4XX_VBIF_IN_WR_LIM_CONF1 0x00003031
4043
4044#define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
4045
4046#define REG_A4XX_VBIF_PERF_CNT_EN0 0x000030c0
4047
4048#define REG_A4XX_VBIF_PERF_CNT_EN1 0x000030c1
4049
4050#define REG_A4XX_VBIF_PERF_CNT_EN2 0x000030c2
4051
4052#define REG_A4XX_VBIF_PERF_CNT_EN3 0x000030c3
4053
4054#define REG_A4XX_VBIF_PERF_CNT_SEL0 0x000030d0
4055
4056#define REG_A4XX_VBIF_PERF_CNT_SEL1 0x000030d1
4057
4058#define REG_A4XX_VBIF_PERF_CNT_SEL2 0x000030d2
4059
4060#define REG_A4XX_VBIF_PERF_CNT_SEL3 0x000030d3
4061
4062#define REG_A4XX_VBIF_PERF_CNT_LOW0 0x000030d8
4063
4064#define REG_A4XX_VBIF_PERF_CNT_LOW1 0x000030d9
4065
4066#define REG_A4XX_VBIF_PERF_CNT_LOW2 0x000030da
4067
4068#define REG_A4XX_VBIF_PERF_CNT_LOW3 0x000030db
4069
4070#define REG_A4XX_VBIF_PERF_CNT_HIGH0 0x000030e0
4071
4072#define REG_A4XX_VBIF_PERF_CNT_HIGH1 0x000030e1
4073
4074#define REG_A4XX_VBIF_PERF_CNT_HIGH2 0x000030e2
4075
4076#define REG_A4XX_VBIF_PERF_CNT_HIGH3 0x000030e3
4077
4078#define REG_A4XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
4079
4080#define REG_A4XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
4081
4082#define REG_A4XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
4083
4084#define REG_A4XX_UNKNOWN_0CC5 0x00000cc5
4085
4086#define REG_A4XX_UNKNOWN_0CC6 0x00000cc6
4087
4088#define REG_A4XX_UNKNOWN_0D01 0x00000d01
4089
4090#define REG_A4XX_UNKNOWN_0E42 0x00000e42
4091
4092#define REG_A4XX_UNKNOWN_0EC2 0x00000ec2
4093
4094#define REG_A4XX_UNKNOWN_2001 0x00002001
4095
4096#define REG_A4XX_UNKNOWN_209B 0x0000209b
4097
4098#define REG_A4XX_UNKNOWN_20EF 0x000020ef
4099
4100#define REG_A4XX_UNKNOWN_2152 0x00002152
4101
4102#define REG_A4XX_UNKNOWN_2153 0x00002153
4103
4104#define REG_A4XX_UNKNOWN_2154 0x00002154
4105
4106#define REG_A4XX_UNKNOWN_2155 0x00002155
4107
4108#define REG_A4XX_UNKNOWN_2156 0x00002156
4109
4110#define REG_A4XX_UNKNOWN_2157 0x00002157
4111
4112#define REG_A4XX_UNKNOWN_21C3 0x000021c3
4113
4114#define REG_A4XX_UNKNOWN_21E6 0x000021e6
4115
4116#define REG_A4XX_UNKNOWN_2209 0x00002209
4117
4118#define REG_A4XX_UNKNOWN_22D7 0x000022d7
4119
4120#define REG_A4XX_UNKNOWN_2352 0x00002352
4121
4122#define REG_A4XX_TEX_SAMP_0 0x00000000
4123#define A4XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
4124#define A4XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
4125#define A4XX_TEX_SAMP_0_XY_MAG__SHIFT 1
4126static inline uint32_t A4XX_TEX_SAMP_0_XY_MAG(enum a4xx_tex_filter val)
4127{
4128 return ((val) << A4XX_TEX_SAMP_0_XY_MAG__SHIFT) & A4XX_TEX_SAMP_0_XY_MAG__MASK;
4129}
4130#define A4XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
4131#define A4XX_TEX_SAMP_0_XY_MIN__SHIFT 3
4132static inline uint32_t A4XX_TEX_SAMP_0_XY_MIN(enum a4xx_tex_filter val)
4133{
4134 return ((val) << A4XX_TEX_SAMP_0_XY_MIN__SHIFT) & A4XX_TEX_SAMP_0_XY_MIN__MASK;
4135}
4136#define A4XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
4137#define A4XX_TEX_SAMP_0_WRAP_S__SHIFT 5
4138static inline uint32_t A4XX_TEX_SAMP_0_WRAP_S(enum a4xx_tex_clamp val)
4139{
4140 return ((val) << A4XX_TEX_SAMP_0_WRAP_S__SHIFT) & A4XX_TEX_SAMP_0_WRAP_S__MASK;
4141}
4142#define A4XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
4143#define A4XX_TEX_SAMP_0_WRAP_T__SHIFT 8
4144static inline uint32_t A4XX_TEX_SAMP_0_WRAP_T(enum a4xx_tex_clamp val)
4145{
4146 return ((val) << A4XX_TEX_SAMP_0_WRAP_T__SHIFT) & A4XX_TEX_SAMP_0_WRAP_T__MASK;
4147}
4148#define A4XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
4149#define A4XX_TEX_SAMP_0_WRAP_R__SHIFT 11
4150static inline uint32_t A4XX_TEX_SAMP_0_WRAP_R(enum a4xx_tex_clamp val)
4151{
4152 return ((val) << A4XX_TEX_SAMP_0_WRAP_R__SHIFT) & A4XX_TEX_SAMP_0_WRAP_R__MASK;
4153}
4154#define A4XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
4155#define A4XX_TEX_SAMP_0_ANISO__SHIFT 14
4156static inline uint32_t A4XX_TEX_SAMP_0_ANISO(enum a4xx_tex_aniso val)
4157{
4158 return ((val) << A4XX_TEX_SAMP_0_ANISO__SHIFT) & A4XX_TEX_SAMP_0_ANISO__MASK;
4159}
4160#define A4XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
4161#define A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
4162static inline uint32_t A4XX_TEX_SAMP_0_LOD_BIAS(float val)
4163{
4164 return ((((int32_t)(val * 256.0))) << A4XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A4XX_TEX_SAMP_0_LOD_BIAS__MASK;
4165}
4166
4167#define REG_A4XX_TEX_SAMP_1 0x00000001
4168#define A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
4169#define A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
4170static inline uint32_t A4XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
4171{
4172 return ((val) << A4XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A4XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
4173}
4174#define A4XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
4175#define A4XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
4176#define A4XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
4177#define A4XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
4178#define A4XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
4179static inline uint32_t A4XX_TEX_SAMP_1_MAX_LOD(float val)
4180{
4181 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A4XX_TEX_SAMP_1_MAX_LOD__MASK;
4182}
4183#define A4XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
4184#define A4XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
4185static inline uint32_t A4XX_TEX_SAMP_1_MIN_LOD(float val)
4186{
4187 return ((((uint32_t)(val * 256.0))) << A4XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A4XX_TEX_SAMP_1_MIN_LOD__MASK;
4188}
4189
4190#define REG_A4XX_TEX_CONST_0 0x00000000
4191#define A4XX_TEX_CONST_0_TILED 0x00000001
4192#define A4XX_TEX_CONST_0_SRGB 0x00000004
4193#define A4XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
4194#define A4XX_TEX_CONST_0_SWIZ_X__SHIFT 4
4195static inline uint32_t A4XX_TEX_CONST_0_SWIZ_X(enum a4xx_tex_swiz val)
4196{
4197 return ((val) << A4XX_TEX_CONST_0_SWIZ_X__SHIFT) & A4XX_TEX_CONST_0_SWIZ_X__MASK;
4198}
4199#define A4XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
4200#define A4XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
4201static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Y(enum a4xx_tex_swiz val)
4202{
4203 return ((val) << A4XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Y__MASK;
4204}
4205#define A4XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
4206#define A4XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
4207static inline uint32_t A4XX_TEX_CONST_0_SWIZ_Z(enum a4xx_tex_swiz val)
4208{
4209 return ((val) << A4XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A4XX_TEX_CONST_0_SWIZ_Z__MASK;
4210}
4211#define A4XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
4212#define A4XX_TEX_CONST_0_SWIZ_W__SHIFT 13
4213static inline uint32_t A4XX_TEX_CONST_0_SWIZ_W(enum a4xx_tex_swiz val)
4214{
4215 return ((val) << A4XX_TEX_CONST_0_SWIZ_W__SHIFT) & A4XX_TEX_CONST_0_SWIZ_W__MASK;
4216}
4217#define A4XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
4218#define A4XX_TEX_CONST_0_MIPLVLS__SHIFT 16
4219static inline uint32_t A4XX_TEX_CONST_0_MIPLVLS(uint32_t val)
4220{
4221 return ((val) << A4XX_TEX_CONST_0_MIPLVLS__SHIFT) & A4XX_TEX_CONST_0_MIPLVLS__MASK;
4222}
4223#define A4XX_TEX_CONST_0_FMT__MASK 0x1fc00000
4224#define A4XX_TEX_CONST_0_FMT__SHIFT 22
4225static inline uint32_t A4XX_TEX_CONST_0_FMT(enum a4xx_tex_fmt val)
4226{
4227 return ((val) << A4XX_TEX_CONST_0_FMT__SHIFT) & A4XX_TEX_CONST_0_FMT__MASK;
4228}
4229#define A4XX_TEX_CONST_0_TYPE__MASK 0xe0000000
4230#define A4XX_TEX_CONST_0_TYPE__SHIFT 29
4231static inline uint32_t A4XX_TEX_CONST_0_TYPE(enum a4xx_tex_type val)
4232{
4233 return ((val) << A4XX_TEX_CONST_0_TYPE__SHIFT) & A4XX_TEX_CONST_0_TYPE__MASK;
4234}
4235
4236#define REG_A4XX_TEX_CONST_1 0x00000001
4237#define A4XX_TEX_CONST_1_HEIGHT__MASK 0x00007fff
4238#define A4XX_TEX_CONST_1_HEIGHT__SHIFT 0
4239static inline uint32_t A4XX_TEX_CONST_1_HEIGHT(uint32_t val)
4240{
4241 return ((val) << A4XX_TEX_CONST_1_HEIGHT__SHIFT) & A4XX_TEX_CONST_1_HEIGHT__MASK;
4242}
4243#define A4XX_TEX_CONST_1_WIDTH__MASK 0x3fff8000
4244#define A4XX_TEX_CONST_1_WIDTH__SHIFT 15
4245static inline uint32_t A4XX_TEX_CONST_1_WIDTH(uint32_t val)
4246{
4247 return ((val) << A4XX_TEX_CONST_1_WIDTH__SHIFT) & A4XX_TEX_CONST_1_WIDTH__MASK;
4248}
4249
4250#define REG_A4XX_TEX_CONST_2 0x00000002
4251#define A4XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
4252#define A4XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
4253static inline uint32_t A4XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
4254{
4255 return ((val) << A4XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A4XX_TEX_CONST_2_PITCHALIGN__MASK;
4256}
4257#define A4XX_TEX_CONST_2_BUFFER 0x00000040
4258#define A4XX_TEX_CONST_2_PITCH__MASK 0x3ffffe00
4259#define A4XX_TEX_CONST_2_PITCH__SHIFT 9
4260static inline uint32_t A4XX_TEX_CONST_2_PITCH(uint32_t val)
4261{
4262 return ((val) << A4XX_TEX_CONST_2_PITCH__SHIFT) & A4XX_TEX_CONST_2_PITCH__MASK;
4263}
4264#define A4XX_TEX_CONST_2_SWAP__MASK 0xc0000000
4265#define A4XX_TEX_CONST_2_SWAP__SHIFT 30
4266static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
4267{
4268 return ((val) << A4XX_TEX_CONST_2_SWAP__SHIFT) & A4XX_TEX_CONST_2_SWAP__MASK;
4269}
4270
4271#define REG_A4XX_TEX_CONST_3 0x00000003
4272#define A4XX_TEX_CONST_3_LAYERSZ__MASK 0x00003fff
4273#define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0
4274static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val)
4275{
4276 assert(!(val & 0xfff));
4277 return (((val >> 12)) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK;
4278}
4279#define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000
4280#define A4XX_TEX_CONST_3_DEPTH__SHIFT 18
4281static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val)
4282{
4283 return ((val) << A4XX_TEX_CONST_3_DEPTH__SHIFT) & A4XX_TEX_CONST_3_DEPTH__MASK;
4284}
4285
4286#define REG_A4XX_TEX_CONST_4 0x00000004
4287#define A4XX_TEX_CONST_4_LAYERSZ__MASK 0x0000000f
4288#define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0
4289static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val)
4290{
4291 assert(!(val & 0xfff));
4292 return (((val >> 12)) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK;
4293}
4294#define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0
4295#define A4XX_TEX_CONST_4_BASE__SHIFT 5
4296static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val)
4297{
4298 assert(!(val & 0x1f));
4299 return (((val >> 5)) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK;
4300}
4301
4302#define REG_A4XX_TEX_CONST_5 0x00000005
4303
4304#define REG_A4XX_TEX_CONST_6 0x00000006
4305
4306#define REG_A4XX_TEX_CONST_7 0x00000007
4307
4308#define REG_A4XX_SSBO_0_0 0x00000000
4309#define A4XX_SSBO_0_0_BASE__MASK 0xffffffe0
4310#define A4XX_SSBO_0_0_BASE__SHIFT 5
4311static inline uint32_t A4XX_SSBO_0_0_BASE(uint32_t val)
4312{
4313 assert(!(val & 0x1f));
4314 return (((val >> 5)) << A4XX_SSBO_0_0_BASE__SHIFT) & A4XX_SSBO_0_0_BASE__MASK;
4315}
4316
4317#define REG_A4XX_SSBO_0_1 0x00000001
4318#define A4XX_SSBO_0_1_PITCH__MASK 0x003fffff
4319#define A4XX_SSBO_0_1_PITCH__SHIFT 0
4320static inline uint32_t A4XX_SSBO_0_1_PITCH(uint32_t val)
4321{
4322 return ((val) << A4XX_SSBO_0_1_PITCH__SHIFT) & A4XX_SSBO_0_1_PITCH__MASK;
4323}
4324
4325#define REG_A4XX_SSBO_0_2 0x00000002
4326#define A4XX_SSBO_0_2_ARRAY_PITCH__MASK 0x03fff000
4327#define A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12
4328static inline uint32_t A4XX_SSBO_0_2_ARRAY_PITCH(uint32_t val)
4329{
4330 assert(!(val & 0xfff));
4331 return (((val >> 12)) << A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A4XX_SSBO_0_2_ARRAY_PITCH__MASK;
4332}
4333
4334#define REG_A4XX_SSBO_0_3 0x00000003
4335#define A4XX_SSBO_0_3_CPP__MASK 0x0000003f
4336#define A4XX_SSBO_0_3_CPP__SHIFT 0
4337static inline uint32_t A4XX_SSBO_0_3_CPP(uint32_t val)
4338{
4339 return ((val) << A4XX_SSBO_0_3_CPP__SHIFT) & A4XX_SSBO_0_3_CPP__MASK;
4340}
4341
4342#define REG_A4XX_SSBO_1_0 0x00000000
4343#define A4XX_SSBO_1_0_CPP__MASK 0x0000001f
4344#define A4XX_SSBO_1_0_CPP__SHIFT 0
4345static inline uint32_t A4XX_SSBO_1_0_CPP(uint32_t val)
4346{
4347 return ((val) << A4XX_SSBO_1_0_CPP__SHIFT) & A4XX_SSBO_1_0_CPP__MASK;
4348}
4349#define A4XX_SSBO_1_0_FMT__MASK 0x0000ff00
4350#define A4XX_SSBO_1_0_FMT__SHIFT 8
4351static inline uint32_t A4XX_SSBO_1_0_FMT(enum a4xx_color_fmt val)
4352{
4353 return ((val) << A4XX_SSBO_1_0_FMT__SHIFT) & A4XX_SSBO_1_0_FMT__MASK;
4354}
4355#define A4XX_SSBO_1_0_WIDTH__MASK 0xffff0000
4356#define A4XX_SSBO_1_0_WIDTH__SHIFT 16
4357static inline uint32_t A4XX_SSBO_1_0_WIDTH(uint32_t val)
4358{
4359 return ((val) << A4XX_SSBO_1_0_WIDTH__SHIFT) & A4XX_SSBO_1_0_WIDTH__MASK;
4360}
4361
4362#define REG_A4XX_SSBO_1_1 0x00000001
4363#define A4XX_SSBO_1_1_HEIGHT__MASK 0x0000ffff
4364#define A4XX_SSBO_1_1_HEIGHT__SHIFT 0
4365static inline uint32_t A4XX_SSBO_1_1_HEIGHT(uint32_t val)
4366{
4367 return ((val) << A4XX_SSBO_1_1_HEIGHT__SHIFT) & A4XX_SSBO_1_1_HEIGHT__MASK;
4368}
4369#define A4XX_SSBO_1_1_DEPTH__MASK 0xffff0000
4370#define A4XX_SSBO_1_1_DEPTH__SHIFT 16
4371static inline uint32_t A4XX_SSBO_1_1_DEPTH(uint32_t val)
4372{
4373 return ((val) << A4XX_SSBO_1_1_DEPTH__SHIFT) & A4XX_SSBO_1_1_DEPTH__MASK;
4374}
4375
4376#ifdef __cplusplus
4377#endif
4378
4379#endif /* A4XX_XML */
4380

source code of linux/drivers/gpu/drm/msm/adreno/a4xx.xml.h