1	#ifndef A5XX_XML
2	#define A5XX_XML
3
4	/* Autogenerated file, DO NOT EDIT manually!
5
6	This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
7	http://gitlab.freedesktop.org/mesa/mesa/
8	git clone https://gitlab.freedesktop.org/mesa/mesa.git
9
10	The rules-ng-ng source files this header was generated from are:
11
12	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 151693 bytes, from Wed Aug 23 10:39:39 2023)
13	- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023)
14	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023)
15	- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85691 bytes, from Fri Feb 16 09:49:01 2024)
16
17	Copyright (C) 2013-2024 by the following authors:
18	- Rob Clark <robdclark@gmail.com> Rob Clark
19	- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin
20
21	Permission is hereby granted, free of charge, to any person obtaining
22	a copy of this software and associated documentation files (the
23	"Software"), to deal in the Software without restriction, including
24	without limitation the rights to use, copy, modify, merge, publish,
25	distribute, sublicense, and/or sell copies of the Software, and to
26	permit persons to whom the Software is furnished to do so, subject to
27	the following conditions:
28
29	The above copyright notice and this permission notice (including the
30	next paragraph) shall be included in all copies or substantial
31	portions of the Software.
32
33	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34	EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
35	MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
36	IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
37	LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
38	OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
39	WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
40
41	*/
42
43	#ifdef __KERNEL__
44	#include <linux/bug.h>
45	#define assert(x) BUG_ON(!(x))
46	#else
47	#include <assert.h>
48	#endif
49
50	#ifdef __cplusplus
51	#define __struct_cast(X)
52	#else
53	#define __struct_cast(X) (struct X)
54	#endif
55
56	enum a5xx_color_fmt {
57	RB5_A8_UNORM = 2,
58	RB5_R8_UNORM = 3,
59	RB5_R8_SNORM = 4,
60	RB5_R8_UINT = 5,
61	RB5_R8_SINT = 6,
62	RB5_R4G4B4A4_UNORM = 8,
63	RB5_R5G5B5A1_UNORM = 10,
64	RB5_R5G6B5_UNORM = 14,
65	RB5_R8G8_UNORM = 15,
66	RB5_R8G8_SNORM = 16,
67	RB5_R8G8_UINT = 17,
68	RB5_R8G8_SINT = 18,
69	RB5_R16_UNORM = 21,
70	RB5_R16_SNORM = 22,
71	RB5_R16_FLOAT = 23,
72	RB5_R16_UINT = 24,
73	RB5_R16_SINT = 25,
74	RB5_R8G8B8A8_UNORM = 48,
75	RB5_R8G8B8_UNORM = 49,
76	RB5_R8G8B8A8_SNORM = 50,
77	RB5_R8G8B8A8_UINT = 51,
78	RB5_R8G8B8A8_SINT = 52,
79	RB5_R10G10B10A2_UNORM = 55,
80	RB5_R10G10B10A2_UINT = 58,
81	RB5_R11G11B10_FLOAT = 66,
82	RB5_R16G16_UNORM = 67,
83	RB5_R16G16_SNORM = 68,
84	RB5_R16G16_FLOAT = 69,
85	RB5_R16G16_UINT = 70,
86	RB5_R16G16_SINT = 71,
87	RB5_R32_FLOAT = 74,
88	RB5_R32_UINT = 75,
89	RB5_R32_SINT = 76,
90	RB5_R16G16B16A16_UNORM = 96,
91	RB5_R16G16B16A16_SNORM = 97,
92	RB5_R16G16B16A16_FLOAT = 98,
93	RB5_R16G16B16A16_UINT = 99,
94	RB5_R16G16B16A16_SINT = 100,
95	RB5_R32G32_FLOAT = 103,
96	RB5_R32G32_UINT = 104,
97	RB5_R32G32_SINT = 105,
98	RB5_R32G32B32A32_FLOAT = 130,
99	RB5_R32G32B32A32_UINT = 131,
100	RB5_R32G32B32A32_SINT = 132,
101	RB5_NONE = 255,
102	};
103
104	enum a5xx_tile_mode {
105	TILE5_LINEAR = 0,
106	TILE5_2 = 2,
107	TILE5_3 = 3,
108	};
109
110	enum a5xx_vtx_fmt {
111	VFMT5_8_UNORM = 3,
112	VFMT5_8_SNORM = 4,
113	VFMT5_8_UINT = 5,
114	VFMT5_8_SINT = 6,
115	VFMT5_8_8_UNORM = 15,
116	VFMT5_8_8_SNORM = 16,
117	VFMT5_8_8_UINT = 17,
118	VFMT5_8_8_SINT = 18,
119	VFMT5_16_UNORM = 21,
120	VFMT5_16_SNORM = 22,
121	VFMT5_16_FLOAT = 23,
122	VFMT5_16_UINT = 24,
123	VFMT5_16_SINT = 25,
124	VFMT5_8_8_8_UNORM = 33,
125	VFMT5_8_8_8_SNORM = 34,
126	VFMT5_8_8_8_UINT = 35,
127	VFMT5_8_8_8_SINT = 36,
128	VFMT5_8_8_8_8_UNORM = 48,
129	VFMT5_8_8_8_8_SNORM = 50,
130	VFMT5_8_8_8_8_UINT = 51,
131	VFMT5_8_8_8_8_SINT = 52,
132	VFMT5_10_10_10_2_UNORM = 54,
133	VFMT5_10_10_10_2_SNORM = 57,
134	VFMT5_10_10_10_2_UINT = 58,
135	VFMT5_10_10_10_2_SINT = 59,
136	VFMT5_11_11_10_FLOAT = 66,
137	VFMT5_16_16_UNORM = 67,
138	VFMT5_16_16_SNORM = 68,
139	VFMT5_16_16_FLOAT = 69,
140	VFMT5_16_16_UINT = 70,
141	VFMT5_16_16_SINT = 71,
142	VFMT5_32_UNORM = 72,
143	VFMT5_32_SNORM = 73,
144	VFMT5_32_FLOAT = 74,
145	VFMT5_32_UINT = 75,
146	VFMT5_32_SINT = 76,
147	VFMT5_32_FIXED = 77,
148	VFMT5_16_16_16_UNORM = 88,
149	VFMT5_16_16_16_SNORM = 89,
150	VFMT5_16_16_16_FLOAT = 90,
151	VFMT5_16_16_16_UINT = 91,
152	VFMT5_16_16_16_SINT = 92,
153	VFMT5_16_16_16_16_UNORM = 96,
154	VFMT5_16_16_16_16_SNORM = 97,
155	VFMT5_16_16_16_16_FLOAT = 98,
156	VFMT5_16_16_16_16_UINT = 99,
157	VFMT5_16_16_16_16_SINT = 100,
158	VFMT5_32_32_UNORM = 101,
159	VFMT5_32_32_SNORM = 102,
160	VFMT5_32_32_FLOAT = 103,
161	VFMT5_32_32_UINT = 104,
162	VFMT5_32_32_SINT = 105,
163	VFMT5_32_32_FIXED = 106,
164	VFMT5_32_32_32_UNORM = 112,
165	VFMT5_32_32_32_SNORM = 113,
166	VFMT5_32_32_32_UINT = 114,
167	VFMT5_32_32_32_SINT = 115,
168	VFMT5_32_32_32_FLOAT = 116,
169	VFMT5_32_32_32_FIXED = 117,
170	VFMT5_32_32_32_32_UNORM = 128,
171	VFMT5_32_32_32_32_SNORM = 129,
172	VFMT5_32_32_32_32_FLOAT = 130,
173	VFMT5_32_32_32_32_UINT = 131,
174	VFMT5_32_32_32_32_SINT = 132,
175	VFMT5_32_32_32_32_FIXED = 133,
176	VFMT5_NONE = 255,
177	};
178
179	enum a5xx_tex_fmt {
180	TFMT5_A8_UNORM = 2,
181	TFMT5_8_UNORM = 3,
182	TFMT5_8_SNORM = 4,
183	TFMT5_8_UINT = 5,
184	TFMT5_8_SINT = 6,
185	TFMT5_4_4_4_4_UNORM = 8,
186	TFMT5_5_5_5_1_UNORM = 10,
187	TFMT5_5_6_5_UNORM = 14,
188	TFMT5_8_8_UNORM = 15,
189	TFMT5_8_8_SNORM = 16,
190	TFMT5_8_8_UINT = 17,
191	TFMT5_8_8_SINT = 18,
192	TFMT5_L8_A8_UNORM = 19,
193	TFMT5_16_UNORM = 21,
194	TFMT5_16_SNORM = 22,
195	TFMT5_16_FLOAT = 23,
196	TFMT5_16_UINT = 24,
197	TFMT5_16_SINT = 25,
198	TFMT5_8_8_8_8_UNORM = 48,
199	TFMT5_8_8_8_UNORM = 49,
200	TFMT5_8_8_8_8_SNORM = 50,
201	TFMT5_8_8_8_8_UINT = 51,
202	TFMT5_8_8_8_8_SINT = 52,
203	TFMT5_9_9_9_E5_FLOAT = 53,
204	TFMT5_10_10_10_2_UNORM = 54,
205	TFMT5_10_10_10_2_UINT = 58,
206	TFMT5_11_11_10_FLOAT = 66,
207	TFMT5_16_16_UNORM = 67,
208	TFMT5_16_16_SNORM = 68,
209	TFMT5_16_16_FLOAT = 69,
210	TFMT5_16_16_UINT = 70,
211	TFMT5_16_16_SINT = 71,
212	TFMT5_32_FLOAT = 74,
213	TFMT5_32_UINT = 75,
214	TFMT5_32_SINT = 76,
215	TFMT5_16_16_16_16_UNORM = 96,
216	TFMT5_16_16_16_16_SNORM = 97,
217	TFMT5_16_16_16_16_FLOAT = 98,
218	TFMT5_16_16_16_16_UINT = 99,
219	TFMT5_16_16_16_16_SINT = 100,
220	TFMT5_32_32_FLOAT = 103,
221	TFMT5_32_32_UINT = 104,
222	TFMT5_32_32_SINT = 105,
223	TFMT5_32_32_32_UINT = 114,
224	TFMT5_32_32_32_SINT = 115,
225	TFMT5_32_32_32_FLOAT = 116,
226	TFMT5_32_32_32_32_FLOAT = 130,
227	TFMT5_32_32_32_32_UINT = 131,
228	TFMT5_32_32_32_32_SINT = 132,
229	TFMT5_X8Z24_UNORM = 160,
230	TFMT5_ETC2_RG11_UNORM = 171,
231	TFMT5_ETC2_RG11_SNORM = 172,
232	TFMT5_ETC2_R11_UNORM = 173,
233	TFMT5_ETC2_R11_SNORM = 174,
234	TFMT5_ETC1 = 175,
235	TFMT5_ETC2_RGB8 = 176,
236	TFMT5_ETC2_RGBA8 = 177,
237	TFMT5_ETC2_RGB8A1 = 178,
238	TFMT5_DXT1 = 179,
239	TFMT5_DXT3 = 180,
240	TFMT5_DXT5 = 181,
241	TFMT5_RGTC1_UNORM = 183,
242	TFMT5_RGTC1_SNORM = 184,
243	TFMT5_RGTC2_UNORM = 187,
244	TFMT5_RGTC2_SNORM = 188,
245	TFMT5_BPTC_UFLOAT = 190,
246	TFMT5_BPTC_FLOAT = 191,
247	TFMT5_BPTC = 192,
248	TFMT5_ASTC_4x4 = 193,
249	TFMT5_ASTC_5x4 = 194,
250	TFMT5_ASTC_5x5 = 195,
251	TFMT5_ASTC_6x5 = 196,
252	TFMT5_ASTC_6x6 = 197,
253	TFMT5_ASTC_8x5 = 198,
254	TFMT5_ASTC_8x6 = 199,
255	TFMT5_ASTC_8x8 = 200,
256	TFMT5_ASTC_10x5 = 201,
257	TFMT5_ASTC_10x6 = 202,
258	TFMT5_ASTC_10x8 = 203,
259	TFMT5_ASTC_10x10 = 204,
260	TFMT5_ASTC_12x10 = 205,
261	TFMT5_ASTC_12x12 = 206,
262	TFMT5_NONE = 255,
263	};
264
265	enum a5xx_depth_format {
266	DEPTH5_NONE = 0,
267	DEPTH5_16 = 1,
268	DEPTH5_24_8 = 2,
269	DEPTH5_32 = 4,
270	};
271
272	enum a5xx_blit_buf {
273	BLIT_MRT0 = 0,
274	BLIT_MRT1 = 1,
275	BLIT_MRT2 = 2,
276	BLIT_MRT3 = 3,
277	BLIT_MRT4 = 4,
278	BLIT_MRT5 = 5,
279	BLIT_MRT6 = 6,
280	BLIT_MRT7 = 7,
281	BLIT_ZS = 8,
282	BLIT_S = 9,
283	};
284
285	enum a5xx_cp_perfcounter_select {
286	PERF_CP_ALWAYS_COUNT = 0,
287	PERF_CP_BUSY_GFX_CORE_IDLE = 1,
288	PERF_CP_BUSY_CYCLES = 2,
289	PERF_CP_PFP_IDLE = 3,
290	PERF_CP_PFP_BUSY_WORKING = 4,
291	PERF_CP_PFP_STALL_CYCLES_ANY = 5,
292	PERF_CP_PFP_STARVE_CYCLES_ANY = 6,
293	PERF_CP_PFP_ICACHE_MISS = 7,
294	PERF_CP_PFP_ICACHE_HIT = 8,
295	PERF_CP_PFP_MATCH_PM4_PKT_PROFILE = 9,
296	PERF_CP_ME_BUSY_WORKING = 10,
297	PERF_CP_ME_IDLE = 11,
298	PERF_CP_ME_STARVE_CYCLES_ANY = 12,
299	PERF_CP_ME_FIFO_EMPTY_PFP_IDLE = 13,
300	PERF_CP_ME_FIFO_EMPTY_PFP_BUSY = 14,
301	PERF_CP_ME_FIFO_FULL_ME_BUSY = 15,
302	PERF_CP_ME_FIFO_FULL_ME_NON_WORKING = 16,
303	PERF_CP_ME_STALL_CYCLES_ANY = 17,
304	PERF_CP_ME_ICACHE_MISS = 18,
305	PERF_CP_ME_ICACHE_HIT = 19,
306	PERF_CP_NUM_PREEMPTIONS = 20,
307	PERF_CP_PREEMPTION_REACTION_DELAY = 21,
308	PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 22,
309	PERF_CP_PREEMPTION_SWITCH_IN_TIME = 23,
310	PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 24,
311	PERF_CP_PREDICATED_DRAWS_KILLED = 25,
312	PERF_CP_MODE_SWITCH = 26,
313	PERF_CP_ZPASS_DONE = 27,
314	PERF_CP_CONTEXT_DONE = 28,
315	PERF_CP_CACHE_FLUSH = 29,
316	PERF_CP_LONG_PREEMPTIONS = 30,
317	};
318
319	enum a5xx_rbbm_perfcounter_select {
320	PERF_RBBM_ALWAYS_COUNT = 0,
321	PERF_RBBM_ALWAYS_ON = 1,
322	PERF_RBBM_TSE_BUSY = 2,
323	PERF_RBBM_RAS_BUSY = 3,
324	PERF_RBBM_PC_DCALL_BUSY = 4,
325	PERF_RBBM_PC_VSD_BUSY = 5,
326	PERF_RBBM_STATUS_MASKED = 6,
327	PERF_RBBM_COM_BUSY = 7,
328	PERF_RBBM_DCOM_BUSY = 8,
329	PERF_RBBM_VBIF_BUSY = 9,
330	PERF_RBBM_VSC_BUSY = 10,
331	PERF_RBBM_TESS_BUSY = 11,
332	PERF_RBBM_UCHE_BUSY = 12,
333	PERF_RBBM_HLSQ_BUSY = 13,
334	};
335
336	enum a5xx_pc_perfcounter_select {
337	PERF_PC_BUSY_CYCLES = 0,
338	PERF_PC_WORKING_CYCLES = 1,
339	PERF_PC_STALL_CYCLES_VFD = 2,
340	PERF_PC_STALL_CYCLES_TSE = 3,
341	PERF_PC_STALL_CYCLES_VPC = 4,
342	PERF_PC_STALL_CYCLES_UCHE = 5,
343	PERF_PC_STALL_CYCLES_TESS = 6,
344	PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
345	PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
346	PERF_PC_PASS1_TF_STALL_CYCLES = 9,
347	PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
348	PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
349	PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
350	PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
351	PERF_PC_STARVE_CYCLES_DI = 14,
352	PERF_PC_VIS_STREAMS_LOADED = 15,
353	PERF_PC_INSTANCES = 16,
354	PERF_PC_VPC_PRIMITIVES = 17,
355	PERF_PC_DEAD_PRIM = 18,
356	PERF_PC_LIVE_PRIM = 19,
357	PERF_PC_VERTEX_HITS = 20,
358	PERF_PC_IA_VERTICES = 21,
359	PERF_PC_IA_PRIMITIVES = 22,
360	PERF_PC_GS_PRIMITIVES = 23,
361	PERF_PC_HS_INVOCATIONS = 24,
362	PERF_PC_DS_INVOCATIONS = 25,
363	PERF_PC_VS_INVOCATIONS = 26,
364	PERF_PC_GS_INVOCATIONS = 27,
365	PERF_PC_DS_PRIMITIVES = 28,
366	PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
367	PERF_PC_3D_DRAWCALLS = 30,
368	PERF_PC_2D_DRAWCALLS = 31,
369	PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
370	PERF_TESS_BUSY_CYCLES = 33,
371	PERF_TESS_WORKING_CYCLES = 34,
372	PERF_TESS_STALL_CYCLES_PC = 35,
373	PERF_TESS_STARVE_CYCLES_PC = 36,
374	};
375
376	enum a5xx_vfd_perfcounter_select {
377	PERF_VFD_BUSY_CYCLES = 0,
378	PERF_VFD_STALL_CYCLES_UCHE = 1,
379	PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
380	PERF_VFD_STALL_CYCLES_MISS_VB = 3,
381	PERF_VFD_STALL_CYCLES_MISS_Q = 4,
382	PERF_VFD_STALL_CYCLES_SP_INFO = 5,
383	PERF_VFD_STALL_CYCLES_SP_ATTR = 6,
384	PERF_VFD_STALL_CYCLES_VFDP_VB = 7,
385	PERF_VFD_STALL_CYCLES_VFDP_Q = 8,
386	PERF_VFD_DECODER_PACKER_STALL = 9,
387	PERF_VFD_STARVE_CYCLES_UCHE = 10,
388	PERF_VFD_RBUFFER_FULL = 11,
389	PERF_VFD_ATTR_INFO_FIFO_FULL = 12,
390	PERF_VFD_DECODED_ATTRIBUTE_BYTES = 13,
391	PERF_VFD_NUM_ATTRIBUTES = 14,
392	PERF_VFD_INSTRUCTIONS = 15,
393	PERF_VFD_UPPER_SHADER_FIBERS = 16,
394	PERF_VFD_LOWER_SHADER_FIBERS = 17,
395	PERF_VFD_MODE_0_FIBERS = 18,
396	PERF_VFD_MODE_1_FIBERS = 19,
397	PERF_VFD_MODE_2_FIBERS = 20,
398	PERF_VFD_MODE_3_FIBERS = 21,
399	PERF_VFD_MODE_4_FIBERS = 22,
400	PERF_VFD_TOTAL_VERTICES = 23,
401	PERF_VFD_NUM_ATTR_MISS = 24,
402	PERF_VFD_1_BURST_REQ = 25,
403	PERF_VFDP_STALL_CYCLES_VFD = 26,
404	PERF_VFDP_STALL_CYCLES_VFD_INDEX = 27,
405	PERF_VFDP_STALL_CYCLES_VFD_PROG = 28,
406	PERF_VFDP_STARVE_CYCLES_PC = 29,
407	PERF_VFDP_VS_STAGE_32_WAVES = 30,
408	};
409
410	enum a5xx_hlsq_perfcounter_select {
411	PERF_HLSQ_BUSY_CYCLES = 0,
412	PERF_HLSQ_STALL_CYCLES_UCHE = 1,
413	PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
414	PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
415	PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
416	PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
417	PERF_HLSQ_FS_STAGE_32_WAVES = 6,
418	PERF_HLSQ_FS_STAGE_64_WAVES = 7,
419	PERF_HLSQ_QUADS = 8,
420	PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE = 9,
421	PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE = 10,
422	PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE = 11,
423	PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE = 12,
424	PERF_HLSQ_CS_INVOCATIONS = 13,
425	PERF_HLSQ_COMPUTE_DRAWCALLS = 14,
426	};
427
428	enum a5xx_vpc_perfcounter_select {
429	PERF_VPC_BUSY_CYCLES = 0,
430	PERF_VPC_WORKING_CYCLES = 1,
431	PERF_VPC_STALL_CYCLES_UCHE = 2,
432	PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
433	PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
434	PERF_VPC_STALL_CYCLES_PC = 5,
435	PERF_VPC_STALL_CYCLES_SP_LM = 6,
436	PERF_VPC_POS_EXPORT_STALL_CYCLES = 7,
437	PERF_VPC_STARVE_CYCLES_SP = 8,
438	PERF_VPC_STARVE_CYCLES_LRZ = 9,
439	PERF_VPC_PC_PRIMITIVES = 10,
440	PERF_VPC_SP_COMPONENTS = 11,
441	PERF_VPC_SP_LM_PRIMITIVES = 12,
442	PERF_VPC_SP_LM_COMPONENTS = 13,
443	PERF_VPC_SP_LM_DWORDS = 14,
444	PERF_VPC_STREAMOUT_COMPONENTS = 15,
445	PERF_VPC_GRANT_PHASES = 16,
446	};
447
448	enum a5xx_tse_perfcounter_select {
449	PERF_TSE_BUSY_CYCLES = 0,
450	PERF_TSE_CLIPPING_CYCLES = 1,
451	PERF_TSE_STALL_CYCLES_RAS = 2,
452	PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
453	PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
454	PERF_TSE_STARVE_CYCLES_PC = 5,
455	PERF_TSE_INPUT_PRIM = 6,
456	PERF_TSE_INPUT_NULL_PRIM = 7,
457	PERF_TSE_TRIVAL_REJ_PRIM = 8,
458	PERF_TSE_CLIPPED_PRIM = 9,
459	PERF_TSE_ZERO_AREA_PRIM = 10,
460	PERF_TSE_FACENESS_CULLED_PRIM = 11,
461	PERF_TSE_ZERO_PIXEL_PRIM = 12,
462	PERF_TSE_OUTPUT_NULL_PRIM = 13,
463	PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
464	PERF_TSE_CINVOCATION = 15,
465	PERF_TSE_CPRIMITIVES = 16,
466	PERF_TSE_2D_INPUT_PRIM = 17,
467	PERF_TSE_2D_ALIVE_CLCLES = 18,
468	};
469
470	enum a5xx_ras_perfcounter_select {
471	PERF_RAS_BUSY_CYCLES = 0,
472	PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
473	PERF_RAS_STALL_CYCLES_LRZ = 2,
474	PERF_RAS_STARVE_CYCLES_TSE = 3,
475	PERF_RAS_SUPER_TILES = 4,
476	PERF_RAS_8X4_TILES = 5,
477	PERF_RAS_MASKGEN_ACTIVE = 6,
478	PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
479	PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
480	PERF_RAS_PRIM_KILLED_INVISILBE = 9,
481	};
482
483	enum a5xx_lrz_perfcounter_select {
484	PERF_LRZ_BUSY_CYCLES = 0,
485	PERF_LRZ_STARVE_CYCLES_RAS = 1,
486	PERF_LRZ_STALL_CYCLES_RB = 2,
487	PERF_LRZ_STALL_CYCLES_VSC = 3,
488	PERF_LRZ_STALL_CYCLES_VPC = 4,
489	PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
490	PERF_LRZ_STALL_CYCLES_UCHE = 6,
491	PERF_LRZ_LRZ_READ = 7,
492	PERF_LRZ_LRZ_WRITE = 8,
493	PERF_LRZ_READ_LATENCY = 9,
494	PERF_LRZ_MERGE_CACHE_UPDATING = 10,
495	PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
496	PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
497	PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
498	PERF_LRZ_FULL_8X8_TILES = 14,
499	PERF_LRZ_PARTIAL_8X8_TILES = 15,
500	PERF_LRZ_TILE_KILLED = 16,
501	PERF_LRZ_TOTAL_PIXEL = 17,
502	PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
503	};
504
505	enum a5xx_uche_perfcounter_select {
506	PERF_UCHE_BUSY_CYCLES = 0,
507	PERF_UCHE_STALL_CYCLES_VBIF = 1,
508	PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
509	PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
510	PERF_UCHE_VBIF_READ_BEATS_TP = 4,
511	PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
512	PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
513	PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
514	PERF_UCHE_VBIF_READ_BEATS_SP = 8,
515	PERF_UCHE_READ_REQUESTS_TP = 9,
516	PERF_UCHE_READ_REQUESTS_VFD = 10,
517	PERF_UCHE_READ_REQUESTS_HLSQ = 11,
518	PERF_UCHE_READ_REQUESTS_LRZ = 12,
519	PERF_UCHE_READ_REQUESTS_SP = 13,
520	PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
521	PERF_UCHE_WRITE_REQUESTS_SP = 15,
522	PERF_UCHE_WRITE_REQUESTS_VPC = 16,
523	PERF_UCHE_WRITE_REQUESTS_VSC = 17,
524	PERF_UCHE_EVICTS = 18,
525	PERF_UCHE_BANK_REQ0 = 19,
526	PERF_UCHE_BANK_REQ1 = 20,
527	PERF_UCHE_BANK_REQ2 = 21,
528	PERF_UCHE_BANK_REQ3 = 22,
529	PERF_UCHE_BANK_REQ4 = 23,
530	PERF_UCHE_BANK_REQ5 = 24,
531	PERF_UCHE_BANK_REQ6 = 25,
532	PERF_UCHE_BANK_REQ7 = 26,
533	PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
534	PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
535	PERF_UCHE_GMEM_READ_BEATS = 29,
536	PERF_UCHE_FLAG_COUNT = 30,
537	};
538
539	enum a5xx_tp_perfcounter_select {
540	PERF_TP_BUSY_CYCLES = 0,
541	PERF_TP_STALL_CYCLES_UCHE = 1,
542	PERF_TP_LATENCY_CYCLES = 2,
543	PERF_TP_LATENCY_TRANS = 3,
544	PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
545	PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
546	PERF_TP_L1_CACHELINE_REQUESTS = 6,
547	PERF_TP_L1_CACHELINE_MISSES = 7,
548	PERF_TP_SP_TP_TRANS = 8,
549	PERF_TP_TP_SP_TRANS = 9,
550	PERF_TP_OUTPUT_PIXELS = 10,
551	PERF_TP_FILTER_WORKLOAD_16BIT = 11,
552	PERF_TP_FILTER_WORKLOAD_32BIT = 12,
553	PERF_TP_QUADS_RECEIVED = 13,
554	PERF_TP_QUADS_OFFSET = 14,
555	PERF_TP_QUADS_SHADOW = 15,
556	PERF_TP_QUADS_ARRAY = 16,
557	PERF_TP_QUADS_GRADIENT = 17,
558	PERF_TP_QUADS_1D = 18,
559	PERF_TP_QUADS_2D = 19,
560	PERF_TP_QUADS_BUFFER = 20,
561	PERF_TP_QUADS_3D = 21,
562	PERF_TP_QUADS_CUBE = 22,
563	PERF_TP_STATE_CACHE_REQUESTS = 23,
564	PERF_TP_STATE_CACHE_MISSES = 24,
565	PERF_TP_DIVERGENT_QUADS_RECEIVED = 25,
566	PERF_TP_BINDLESS_STATE_CACHE_REQUESTS = 26,
567	PERF_TP_BINDLESS_STATE_CACHE_MISSES = 27,
568	PERF_TP_PRT_NON_RESIDENT_EVENTS = 28,
569	PERF_TP_OUTPUT_PIXELS_POINT = 29,
570	PERF_TP_OUTPUT_PIXELS_BILINEAR = 30,
571	PERF_TP_OUTPUT_PIXELS_MIP = 31,
572	PERF_TP_OUTPUT_PIXELS_ANISO = 32,
573	PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 33,
574	PERF_TP_FLAG_CACHE_REQUESTS = 34,
575	PERF_TP_FLAG_CACHE_MISSES = 35,
576	PERF_TP_L1_5_L2_REQUESTS = 36,
577	PERF_TP_2D_OUTPUT_PIXELS = 37,
578	PERF_TP_2D_OUTPUT_PIXELS_POINT = 38,
579	PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 39,
580	PERF_TP_2D_FILTER_WORKLOAD_16BIT = 40,
581	PERF_TP_2D_FILTER_WORKLOAD_32BIT = 41,
582	};
583
584	enum a5xx_sp_perfcounter_select {
585	PERF_SP_BUSY_CYCLES = 0,
586	PERF_SP_ALU_WORKING_CYCLES = 1,
587	PERF_SP_EFU_WORKING_CYCLES = 2,
588	PERF_SP_STALL_CYCLES_VPC = 3,
589	PERF_SP_STALL_CYCLES_TP = 4,
590	PERF_SP_STALL_CYCLES_UCHE = 5,
591	PERF_SP_STALL_CYCLES_RB = 6,
592	PERF_SP_SCHEDULER_NON_WORKING = 7,
593	PERF_SP_WAVE_CONTEXTS = 8,
594	PERF_SP_WAVE_CONTEXT_CYCLES = 9,
595	PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
596	PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
597	PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
598	PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
599	PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
600	PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
601	PERF_SP_WAVE_CTRL_CYCLES = 16,
602	PERF_SP_WAVE_LOAD_CYCLES = 17,
603	PERF_SP_WAVE_EMIT_CYCLES = 18,
604	PERF_SP_WAVE_NOP_CYCLES = 19,
605	PERF_SP_WAVE_WAIT_CYCLES = 20,
606	PERF_SP_WAVE_FETCH_CYCLES = 21,
607	PERF_SP_WAVE_IDLE_CYCLES = 22,
608	PERF_SP_WAVE_END_CYCLES = 23,
609	PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
610	PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
611	PERF_SP_WAVE_JOIN_CYCLES = 26,
612	PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
613	PERF_SP_LM_STORE_INSTRUCTIONS = 28,
614	PERF_SP_LM_ATOMICS = 29,
615	PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
616	PERF_SP_GM_STORE_INSTRUCTIONS = 31,
617	PERF_SP_GM_ATOMICS = 32,
618	PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
619	PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS = 34,
620	PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 35,
621	PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 36,
622	PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 37,
623	PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 38,
624	PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 39,
625	PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 40,
626	PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 41,
627	PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 42,
628	PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 43,
629	PERF_SP_VS_INSTRUCTIONS = 44,
630	PERF_SP_FS_INSTRUCTIONS = 45,
631	PERF_SP_ADDR_LOCK_COUNT = 46,
632	PERF_SP_UCHE_READ_TRANS = 47,
633	PERF_SP_UCHE_WRITE_TRANS = 48,
634	PERF_SP_EXPORT_VPC_TRANS = 49,
635	PERF_SP_EXPORT_RB_TRANS = 50,
636	PERF_SP_PIXELS_KILLED = 51,
637	PERF_SP_ICL1_REQUESTS = 52,
638	PERF_SP_ICL1_MISSES = 53,
639	PERF_SP_ICL0_REQUESTS = 54,
640	PERF_SP_ICL0_MISSES = 55,
641	PERF_SP_HS_INSTRUCTIONS = 56,
642	PERF_SP_DS_INSTRUCTIONS = 57,
643	PERF_SP_GS_INSTRUCTIONS = 58,
644	PERF_SP_CS_INSTRUCTIONS = 59,
645	PERF_SP_GPR_READ = 60,
646	PERF_SP_GPR_WRITE = 61,
647	PERF_SP_LM_CH0_REQUESTS = 62,
648	PERF_SP_LM_CH1_REQUESTS = 63,
649	PERF_SP_LM_BANK_CONFLICTS = 64,
650	};
651
652	enum a5xx_rb_perfcounter_select {
653	PERF_RB_BUSY_CYCLES = 0,
654	PERF_RB_STALL_CYCLES_CCU = 1,
655	PERF_RB_STALL_CYCLES_HLSQ = 2,
656	PERF_RB_STALL_CYCLES_FIFO0_FULL = 3,
657	PERF_RB_STALL_CYCLES_FIFO1_FULL = 4,
658	PERF_RB_STALL_CYCLES_FIFO2_FULL = 5,
659	PERF_RB_STARVE_CYCLES_SP = 6,
660	PERF_RB_STARVE_CYCLES_LRZ_TILE = 7,
661	PERF_RB_STARVE_CYCLES_CCU = 8,
662	PERF_RB_STARVE_CYCLES_Z_PLANE = 9,
663	PERF_RB_STARVE_CYCLES_BARY_PLANE = 10,
664	PERF_RB_Z_WORKLOAD = 11,
665	PERF_RB_HLSQ_ACTIVE = 12,
666	PERF_RB_Z_READ = 13,
667	PERF_RB_Z_WRITE = 14,
668	PERF_RB_C_READ = 15,
669	PERF_RB_C_WRITE = 16,
670	PERF_RB_TOTAL_PASS = 17,
671	PERF_RB_Z_PASS = 18,
672	PERF_RB_Z_FAIL = 19,
673	PERF_RB_S_FAIL = 20,
674	PERF_RB_BLENDED_FXP_COMPONENTS = 21,
675	PERF_RB_BLENDED_FP16_COMPONENTS = 22,
676	RB_RESERVED = 23,
677	PERF_RB_2D_ALIVE_CYCLES = 24,
678	PERF_RB_2D_STALL_CYCLES_A2D = 25,
679	PERF_RB_2D_STARVE_CYCLES_SRC = 26,
680	PERF_RB_2D_STARVE_CYCLES_SP = 27,
681	PERF_RB_2D_STARVE_CYCLES_DST = 28,
682	PERF_RB_2D_VALID_PIXELS = 29,
683	};
684
685	enum a5xx_rb_samples_perfcounter_select {
686	TOTAL_SAMPLES = 0,
687	ZPASS_SAMPLES = 1,
688	ZFAIL_SAMPLES = 2,
689	SFAIL_SAMPLES = 3,
690	};
691
692	enum a5xx_vsc_perfcounter_select {
693	PERF_VSC_BUSY_CYCLES = 0,
694	PERF_VSC_WORKING_CYCLES = 1,
695	PERF_VSC_STALL_CYCLES_UCHE = 2,
696	PERF_VSC_EOT_NUM = 3,
697	};
698
699	enum a5xx_ccu_perfcounter_select {
700	PERF_CCU_BUSY_CYCLES = 0,
701	PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
702	PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
703	PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
704	PERF_CCU_DEPTH_BLOCKS = 4,
705	PERF_CCU_COLOR_BLOCKS = 5,
706	PERF_CCU_DEPTH_BLOCK_HIT = 6,
707	PERF_CCU_COLOR_BLOCK_HIT = 7,
708	PERF_CCU_PARTIAL_BLOCK_READ = 8,
709	PERF_CCU_GMEM_READ = 9,
710	PERF_CCU_GMEM_WRITE = 10,
711	PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
712	PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
713	PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
714	PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
715	PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
716	PERF_CCU_COLOR_READ_FLAG0_COUNT = 16,
717	PERF_CCU_COLOR_READ_FLAG1_COUNT = 17,
718	PERF_CCU_COLOR_READ_FLAG2_COUNT = 18,
719	PERF_CCU_COLOR_READ_FLAG3_COUNT = 19,
720	PERF_CCU_COLOR_READ_FLAG4_COUNT = 20,
721	PERF_CCU_2D_BUSY_CYCLES = 21,
722	PERF_CCU_2D_RD_REQ = 22,
723	PERF_CCU_2D_WR_REQ = 23,
724	PERF_CCU_2D_REORDER_STARVE_CYCLES = 24,
725	PERF_CCU_2D_PIXELS = 25,
726	};
727
728	enum a5xx_cmp_perfcounter_select {
729	PERF_CMPDECMP_STALL_CYCLES_VBIF = 0,
730	PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
731	PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
732	PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
733	PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
734	PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
735	PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
736	PERF_CMPDECMP_VBIF_READ_DATA = 7,
737	PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
738	PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
739	PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
740	PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
741	PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
742	PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
743	PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
744	PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 15,
745	PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 16,
746	PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 17,
747	PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 18,
748	PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 19,
749	PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 20,
750	PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 21,
751	PERF_CMPDECMP_2D_RD_DATA = 22,
752	PERF_CMPDECMP_2D_WR_DATA = 23,
753	};
754
755	enum a5xx_vbif_perfcounter_select {
756	AXI_READ_REQUESTS_ID_0 = 0,
757	AXI_READ_REQUESTS_ID_1 = 1,
758	AXI_READ_REQUESTS_ID_2 = 2,
759	AXI_READ_REQUESTS_ID_3 = 3,
760	AXI_READ_REQUESTS_ID_4 = 4,
761	AXI_READ_REQUESTS_ID_5 = 5,
762	AXI_READ_REQUESTS_ID_6 = 6,
763	AXI_READ_REQUESTS_ID_7 = 7,
764	AXI_READ_REQUESTS_ID_8 = 8,
765	AXI_READ_REQUESTS_ID_9 = 9,
766	AXI_READ_REQUESTS_ID_10 = 10,
767	AXI_READ_REQUESTS_ID_11 = 11,
768	AXI_READ_REQUESTS_ID_12 = 12,
769	AXI_READ_REQUESTS_ID_13 = 13,
770	AXI_READ_REQUESTS_ID_14 = 14,
771	AXI_READ_REQUESTS_ID_15 = 15,
772	AXI0_READ_REQUESTS_TOTAL = 16,
773	AXI1_READ_REQUESTS_TOTAL = 17,
774	AXI2_READ_REQUESTS_TOTAL = 18,
775	AXI3_READ_REQUESTS_TOTAL = 19,
776	AXI_READ_REQUESTS_TOTAL = 20,
777	AXI_WRITE_REQUESTS_ID_0 = 21,
778	AXI_WRITE_REQUESTS_ID_1 = 22,
779	AXI_WRITE_REQUESTS_ID_2 = 23,
780	AXI_WRITE_REQUESTS_ID_3 = 24,
781	AXI_WRITE_REQUESTS_ID_4 = 25,
782	AXI_WRITE_REQUESTS_ID_5 = 26,
783	AXI_WRITE_REQUESTS_ID_6 = 27,
784	AXI_WRITE_REQUESTS_ID_7 = 28,
785	AXI_WRITE_REQUESTS_ID_8 = 29,
786	AXI_WRITE_REQUESTS_ID_9 = 30,
787	AXI_WRITE_REQUESTS_ID_10 = 31,
788	AXI_WRITE_REQUESTS_ID_11 = 32,
789	AXI_WRITE_REQUESTS_ID_12 = 33,
790	AXI_WRITE_REQUESTS_ID_13 = 34,
791	AXI_WRITE_REQUESTS_ID_14 = 35,
792	AXI_WRITE_REQUESTS_ID_15 = 36,
793	AXI0_WRITE_REQUESTS_TOTAL = 37,
794	AXI1_WRITE_REQUESTS_TOTAL = 38,
795	AXI2_WRITE_REQUESTS_TOTAL = 39,
796	AXI3_WRITE_REQUESTS_TOTAL = 40,
797	AXI_WRITE_REQUESTS_TOTAL = 41,
798	AXI_TOTAL_REQUESTS = 42,
799	AXI_READ_DATA_BEATS_ID_0 = 43,
800	AXI_READ_DATA_BEATS_ID_1 = 44,
801	AXI_READ_DATA_BEATS_ID_2 = 45,
802	AXI_READ_DATA_BEATS_ID_3 = 46,
803	AXI_READ_DATA_BEATS_ID_4 = 47,
804	AXI_READ_DATA_BEATS_ID_5 = 48,
805	AXI_READ_DATA_BEATS_ID_6 = 49,
806	AXI_READ_DATA_BEATS_ID_7 = 50,
807	AXI_READ_DATA_BEATS_ID_8 = 51,
808	AXI_READ_DATA_BEATS_ID_9 = 52,
809	AXI_READ_DATA_BEATS_ID_10 = 53,
810	AXI_READ_DATA_BEATS_ID_11 = 54,
811	AXI_READ_DATA_BEATS_ID_12 = 55,
812	AXI_READ_DATA_BEATS_ID_13 = 56,
813	AXI_READ_DATA_BEATS_ID_14 = 57,
814	AXI_READ_DATA_BEATS_ID_15 = 58,
815	AXI0_READ_DATA_BEATS_TOTAL = 59,
816	AXI1_READ_DATA_BEATS_TOTAL = 60,
817	AXI2_READ_DATA_BEATS_TOTAL = 61,
818	AXI3_READ_DATA_BEATS_TOTAL = 62,
819	AXI_READ_DATA_BEATS_TOTAL = 63,
820	AXI_WRITE_DATA_BEATS_ID_0 = 64,
821	AXI_WRITE_DATA_BEATS_ID_1 = 65,
822	AXI_WRITE_DATA_BEATS_ID_2 = 66,
823	AXI_WRITE_DATA_BEATS_ID_3 = 67,
824	AXI_WRITE_DATA_BEATS_ID_4 = 68,
825	AXI_WRITE_DATA_BEATS_ID_5 = 69,
826	AXI_WRITE_DATA_BEATS_ID_6 = 70,
827	AXI_WRITE_DATA_BEATS_ID_7 = 71,
828	AXI_WRITE_DATA_BEATS_ID_8 = 72,
829	AXI_WRITE_DATA_BEATS_ID_9 = 73,
830	AXI_WRITE_DATA_BEATS_ID_10 = 74,
831	AXI_WRITE_DATA_BEATS_ID_11 = 75,
832	AXI_WRITE_DATA_BEATS_ID_12 = 76,
833	AXI_WRITE_DATA_BEATS_ID_13 = 77,
834	AXI_WRITE_DATA_BEATS_ID_14 = 78,
835	AXI_WRITE_DATA_BEATS_ID_15 = 79,
836	AXI0_WRITE_DATA_BEATS_TOTAL = 80,
837	AXI1_WRITE_DATA_BEATS_TOTAL = 81,
838	AXI2_WRITE_DATA_BEATS_TOTAL = 82,
839	AXI3_WRITE_DATA_BEATS_TOTAL = 83,
840	AXI_WRITE_DATA_BEATS_TOTAL = 84,
841	AXI_DATA_BEATS_TOTAL = 85,
842	};
843
844	enum a5xx_tex_filter {
845	A5XX_TEX_NEAREST = 0,
846	A5XX_TEX_LINEAR = 1,
847	A5XX_TEX_ANISO = 2,
848	};
849
850	enum a5xx_tex_clamp {
851	A5XX_TEX_REPEAT = 0,
852	A5XX_TEX_CLAMP_TO_EDGE = 1,
853	A5XX_TEX_MIRROR_REPEAT = 2,
854	A5XX_TEX_CLAMP_TO_BORDER = 3,
855	A5XX_TEX_MIRROR_CLAMP = 4,
856	};
857
858	enum a5xx_tex_aniso {
859	A5XX_TEX_ANISO_1 = 0,
860	A5XX_TEX_ANISO_2 = 1,
861	A5XX_TEX_ANISO_4 = 2,
862	A5XX_TEX_ANISO_8 = 3,
863	A5XX_TEX_ANISO_16 = 4,
864	};
865
866	enum a5xx_tex_swiz {
867	A5XX_TEX_X = 0,
868	A5XX_TEX_Y = 1,
869	A5XX_TEX_Z = 2,
870	A5XX_TEX_W = 3,
871	A5XX_TEX_ZERO = 4,
872	A5XX_TEX_ONE = 5,
873	};
874
875	enum a5xx_tex_type {
876	A5XX_TEX_1D = 0,
877	A5XX_TEX_2D = 1,
878	A5XX_TEX_CUBE = 2,
879	A5XX_TEX_3D = 3,
880	A5XX_TEX_BUFFER = 4,
881	};
882
883	#define A5XX_INT0_RBBM_GPU_IDLE 0x00000001
884	#define A5XX_INT0_RBBM_AHB_ERROR 0x00000002
885	#define A5XX_INT0_RBBM_TRANSFER_TIMEOUT 0x00000004
886	#define A5XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
887	#define A5XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
888	#define A5XX_INT0_RBBM_ETS_MS_TIMEOUT 0x00000020
889	#define A5XX_INT0_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
890	#define A5XX_INT0_RBBM_GPC_ERROR 0x00000080
891	#define A5XX_INT0_CP_SW 0x00000100
892	#define A5XX_INT0_CP_HW_ERROR 0x00000200
893	#define A5XX_INT0_CP_CCU_FLUSH_DEPTH_TS 0x00000400
894	#define A5XX_INT0_CP_CCU_FLUSH_COLOR_TS 0x00000800
895	#define A5XX_INT0_CP_CCU_RESOLVE_TS 0x00001000
896	#define A5XX_INT0_CP_IB2 0x00002000
897	#define A5XX_INT0_CP_IB1 0x00004000
898	#define A5XX_INT0_CP_RB 0x00008000
899	#define A5XX_INT0_CP_UNUSED_1 0x00010000
900	#define A5XX_INT0_CP_RB_DONE_TS 0x00020000
901	#define A5XX_INT0_CP_WT_DONE_TS 0x00040000
902	#define A5XX_INT0_UNKNOWN_1 0x00080000
903	#define A5XX_INT0_CP_CACHE_FLUSH_TS 0x00100000
904	#define A5XX_INT0_UNUSED_2 0x00200000
905	#define A5XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00400000
906	#define A5XX_INT0_MISC_HANG_DETECT 0x00800000
907	#define A5XX_INT0_UCHE_OOB_ACCESS 0x01000000
908	#define A5XX_INT0_UCHE_TRAP_INTR 0x02000000
909	#define A5XX_INT0_DEBBUS_INTR_0 0x04000000
910	#define A5XX_INT0_DEBBUS_INTR_1 0x08000000
911	#define A5XX_INT0_GPMU_VOLTAGE_DROOP 0x10000000
912	#define A5XX_INT0_GPMU_FIRMWARE 0x20000000
913	#define A5XX_INT0_ISDB_CPU_IRQ 0x40000000
914	#define A5XX_INT0_ISDB_UNDER_DEBUG 0x80000000
915
916	#define A5XX_CP_INT_CP_OPCODE_ERROR 0x00000001
917	#define A5XX_CP_INT_CP_RESERVED_BIT_ERROR 0x00000002
918	#define A5XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004
919	#define A5XX_CP_INT_CP_DMA_ERROR 0x00000008
920	#define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010
921	#define A5XX_CP_INT_CP_AHB_ERROR 0x00000020
922
923	#define REG_A5XX_CP_RB_BASE 0x00000800
924
925	#define REG_A5XX_CP_RB_BASE_HI 0x00000801
926
927	#define REG_A5XX_CP_RB_CNTL 0x00000802
928
929	#define REG_A5XX_CP_RB_RPTR_ADDR 0x00000804
930
931	#define REG_A5XX_CP_RB_RPTR_ADDR_HI 0x00000805
932
933	#define REG_A5XX_CP_RB_RPTR 0x00000806
934
935	#define REG_A5XX_CP_RB_WPTR 0x00000807
936
937	#define REG_A5XX_CP_PFP_STAT_ADDR 0x00000808
938
939	#define REG_A5XX_CP_PFP_STAT_DATA 0x00000809
940
941	#define REG_A5XX_CP_DRAW_STATE_ADDR 0x0000080b
942
943	#define REG_A5XX_CP_DRAW_STATE_DATA 0x0000080c
944
945	#define REG_A5XX_CP_ME_NRT_ADDR_LO 0x0000080d
946
947	#define REG_A5XX_CP_ME_NRT_ADDR_HI 0x0000080e
948
949	#define REG_A5XX_CP_ME_NRT_DATA 0x00000810
950
951	#define REG_A5XX_CP_CRASH_SCRIPT_BASE_LO 0x00000817
952
953	#define REG_A5XX_CP_CRASH_SCRIPT_BASE_HI 0x00000818
954
955	#define REG_A5XX_CP_CRASH_DUMP_CNTL 0x00000819
956
957	#define REG_A5XX_CP_ME_STAT_ADDR 0x0000081a
958
959	#define REG_A5XX_CP_ROQ_THRESHOLDS_1 0x0000081f
960
961	#define REG_A5XX_CP_ROQ_THRESHOLDS_2 0x00000820
962
963	#define REG_A5XX_CP_ROQ_DBG_ADDR 0x00000821
964
965	#define REG_A5XX_CP_ROQ_DBG_DATA 0x00000822
966
967	#define REG_A5XX_CP_MEQ_DBG_ADDR 0x00000823
968
969	#define REG_A5XX_CP_MEQ_DBG_DATA 0x00000824
970
971	#define REG_A5XX_CP_MEQ_THRESHOLDS 0x00000825
972
973	#define REG_A5XX_CP_MERCIU_SIZE 0x00000826
974
975	#define REG_A5XX_CP_MERCIU_DBG_ADDR 0x00000827
976
977	#define REG_A5XX_CP_MERCIU_DBG_DATA_1 0x00000828
978
979	#define REG_A5XX_CP_MERCIU_DBG_DATA_2 0x00000829
980
981	#define REG_A5XX_CP_PFP_UCODE_DBG_ADDR 0x0000082a
982
983	#define REG_A5XX_CP_PFP_UCODE_DBG_DATA 0x0000082b
984
985	#define REG_A5XX_CP_ME_UCODE_DBG_ADDR 0x0000082f
986
987	#define REG_A5XX_CP_ME_UCODE_DBG_DATA 0x00000830
988
989	#define REG_A5XX_CP_CNTL 0x00000831
990
991	#define REG_A5XX_CP_PFP_ME_CNTL 0x00000832
992
993	#define REG_A5XX_CP_CHICKEN_DBG 0x00000833
994
995	#define REG_A5XX_CP_PFP_INSTR_BASE_LO 0x00000835
996
997	#define REG_A5XX_CP_PFP_INSTR_BASE_HI 0x00000836
998
999	#define REG_A5XX_CP_ME_INSTR_BASE_LO 0x00000838
1000
1001	#define REG_A5XX_CP_ME_INSTR_BASE_HI 0x00000839
1002
1003	#define REG_A5XX_CP_CONTEXT_SWITCH_CNTL 0x0000083b
1004
1005	#define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_LO 0x0000083c
1006
1007	#define REG_A5XX_CP_CONTEXT_SWITCH_RESTORE_ADDR_HI 0x0000083d
1008
1009	#define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_LO 0x0000083e
1010
1011	#define REG_A5XX_CP_CONTEXT_SWITCH_SAVE_ADDR_HI 0x0000083f
1012
1013	#define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO 0x00000840
1014
1015	#define REG_A5XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI 0x00000841
1016
1017	#define REG_A5XX_CP_ADDR_MODE_CNTL 0x00000860
1018
1019	#define REG_A5XX_CP_ME_STAT_DATA 0x00000b14
1020
1021	#define REG_A5XX_CP_WFI_PEND_CTR 0x00000b15
1022
1023	#define REG_A5XX_CP_INTERRUPT_STATUS 0x00000b18
1024
1025	#define REG_A5XX_CP_HW_FAULT 0x00000b1a
1026
1027	#define REG_A5XX_CP_PROTECT_STATUS 0x00000b1c
1028
1029	#define REG_A5XX_CP_IB1_BASE 0x00000b1f
1030
1031	#define REG_A5XX_CP_IB1_BASE_HI 0x00000b20
1032
1033	#define REG_A5XX_CP_IB1_BUFSZ 0x00000b21
1034
1035	#define REG_A5XX_CP_IB2_BASE 0x00000b22
1036
1037	#define REG_A5XX_CP_IB2_BASE_HI 0x00000b23
1038
1039	#define REG_A5XX_CP_IB2_BUFSZ 0x00000b24
1040
1041	#define REG_A5XX_CP_SCRATCH(i0) (0x00000b78 + 0x1*(i0))
1042
1043	static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; }
1044
1045	#define REG_A5XX_CP_PROTECT(i0) (0x00000880 + 0x1*(i0))
1046
1047	static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; }
1048	#define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff
1049	#define A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0
1050	static inline uint32_t A5XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val)
1051	{
1052	return ((val) << A5XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A5XX_CP_PROTECT_REG_BASE_ADDR__MASK;
1053	}
1054	#define A5XX_CP_PROTECT_REG_MASK_LEN__MASK 0x1f000000
1055	#define A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT 24
1056	static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
1057	{
1058	return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK;
1059	}
1060	#define A5XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000
1061	#define A5XX_CP_PROTECT_REG_TRAP_READ 0x40000000
1062
1063	#define REG_A5XX_CP_PROTECT_CNTL 0x000008a0
1064
1065	#define REG_A5XX_CP_AHB_FAULT 0x00000b1b
1066
1067	#define REG_A5XX_CP_PERFCTR_CP_SEL_0 0x00000bb0
1068
1069	#define REG_A5XX_CP_PERFCTR_CP_SEL_1 0x00000bb1
1070
1071	#define REG_A5XX_CP_PERFCTR_CP_SEL_2 0x00000bb2
1072
1073	#define REG_A5XX_CP_PERFCTR_CP_SEL_3 0x00000bb3
1074
1075	#define REG_A5XX_CP_PERFCTR_CP_SEL_4 0x00000bb4
1076
1077	#define REG_A5XX_CP_PERFCTR_CP_SEL_5 0x00000bb5
1078
1079	#define REG_A5XX_CP_PERFCTR_CP_SEL_6 0x00000bb6
1080
1081	#define REG_A5XX_CP_PERFCTR_CP_SEL_7 0x00000bb7
1082
1083	#define REG_A5XX_VSC_ADDR_MODE_CNTL 0x00000bc1
1084
1085	#define REG_A5XX_CP_POWERCTR_CP_SEL_0 0x00000bba
1086
1087	#define REG_A5XX_CP_POWERCTR_CP_SEL_1 0x00000bbb
1088
1089	#define REG_A5XX_CP_POWERCTR_CP_SEL_2 0x00000bbc
1090
1091	#define REG_A5XX_CP_POWERCTR_CP_SEL_3 0x00000bbd
1092
1093	#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_A 0x00000004
1094
1095	#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_B 0x00000005
1096
1097	#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_C 0x00000006
1098
1099	#define REG_A5XX_RBBM_CFG_DBGBUS_SEL_D 0x00000007
1100
1101	#define REG_A5XX_RBBM_CFG_DBGBUS_CNTLT 0x00000008
1102
1103	#define REG_A5XX_RBBM_CFG_DBGBUS_CNTLM 0x00000009
1104
1105	#define REG_A5XX_RBBM_CFG_DEBBUS_CTLTM_ENABLE_SHIFT 0x00000018
1106
1107	#define REG_A5XX_RBBM_CFG_DBGBUS_OPL 0x0000000a
1108
1109	#define REG_A5XX_RBBM_CFG_DBGBUS_OPE 0x0000000b
1110
1111	#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_0 0x0000000c
1112
1113	#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_1 0x0000000d
1114
1115	#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_2 0x0000000e
1116
1117	#define REG_A5XX_RBBM_CFG_DBGBUS_IVTL_3 0x0000000f
1118
1119	#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_0 0x00000010
1120
1121	#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_1 0x00000011
1122
1123	#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_2 0x00000012
1124
1125	#define REG_A5XX_RBBM_CFG_DBGBUS_MASKL_3 0x00000013
1126
1127	#define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_0 0x00000014
1128
1129	#define REG_A5XX_RBBM_CFG_DBGBUS_BYTEL_1 0x00000015
1130
1131	#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_0 0x00000016
1132
1133	#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_1 0x00000017
1134
1135	#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_2 0x00000018
1136
1137	#define REG_A5XX_RBBM_CFG_DBGBUS_IVTE_3 0x00000019
1138
1139	#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_0 0x0000001a
1140
1141	#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_1 0x0000001b
1142
1143	#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_2 0x0000001c
1144
1145	#define REG_A5XX_RBBM_CFG_DBGBUS_MASKE_3 0x0000001d
1146
1147	#define REG_A5XX_RBBM_CFG_DBGBUS_NIBBLEE 0x0000001e
1148
1149	#define REG_A5XX_RBBM_CFG_DBGBUS_PTRC0 0x0000001f
1150
1151	#define REG_A5XX_RBBM_CFG_DBGBUS_PTRC1 0x00000020
1152
1153	#define REG_A5XX_RBBM_CFG_DBGBUS_LOADREG 0x00000021
1154
1155	#define REG_A5XX_RBBM_CFG_DBGBUS_IDX 0x00000022
1156
1157	#define REG_A5XX_RBBM_CFG_DBGBUS_CLRC 0x00000023
1158
1159	#define REG_A5XX_RBBM_CFG_DBGBUS_LOADIVT 0x00000024
1160
1161	#define REG_A5XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000002f
1162
1163	#define REG_A5XX_RBBM_INT_CLEAR_CMD 0x00000037
1164
1165	#define REG_A5XX_RBBM_INT_0_MASK 0x00000038
1166	#define A5XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001
1167	#define A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR 0x00000002
1168	#define A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT 0x00000004
1169	#define A5XX_RBBM_INT_0_MASK_RBBM_ME_MS_TIMEOUT 0x00000008
1170	#define A5XX_RBBM_INT_0_MASK_RBBM_PFP_MS_TIMEOUT 0x00000010
1171	#define A5XX_RBBM_INT_0_MASK_RBBM_ETS_MS_TIMEOUT 0x00000020
1172	#define A5XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNC_OVERFLOW 0x00000040
1173	#define A5XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080
1174	#define A5XX_RBBM_INT_0_MASK_CP_SW 0x00000100
1175	#define A5XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200
1176	#define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400
1177	#define A5XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800
1178	#define A5XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000
1179	#define A5XX_RBBM_INT_0_MASK_CP_IB2 0x00002000
1180	#define A5XX_RBBM_INT_0_MASK_CP_IB1 0x00004000
1181	#define A5XX_RBBM_INT_0_MASK_CP_RB 0x00008000
1182	#define A5XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000
1183	#define A5XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000
1184	#define A5XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000
1185	#define A5XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000
1186	#define A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT 0x00800000
1187	#define A5XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000
1188	#define A5XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000
1189	#define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000
1190	#define A5XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000
1191	#define A5XX_RBBM_INT_0_MASK_GPMU_VOLTAGE_DROOP 0x10000000
1192	#define A5XX_RBBM_INT_0_MASK_GPMU_FIRMWARE 0x20000000
1193	#define A5XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000
1194	#define A5XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000
1195
1196	#define REG_A5XX_RBBM_AHB_DBG_CNTL 0x0000003f
1197
1198	#define REG_A5XX_RBBM_EXT_VBIF_DBG_CNTL 0x00000041
1199
1200	#define REG_A5XX_RBBM_SW_RESET_CMD 0x00000043
1201
1202	#define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045
1203
1204	#define REG_A5XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046
1205
1206	#define REG_A5XX_RBBM_DBG_LO_HI_GPIO 0x00000048
1207
1208	#define REG_A5XX_RBBM_EXT_TRACE_BUS_CNTL 0x00000049
1209
1210	#define REG_A5XX_RBBM_CLOCK_CNTL_TP0 0x0000004a
1211
1212	#define REG_A5XX_RBBM_CLOCK_CNTL_TP1 0x0000004b
1213
1214	#define REG_A5XX_RBBM_CLOCK_CNTL_TP2 0x0000004c
1215
1216	#define REG_A5XX_RBBM_CLOCK_CNTL_TP3 0x0000004d
1217
1218	#define REG_A5XX_RBBM_CLOCK_CNTL2_TP0 0x0000004e
1219
1220	#define REG_A5XX_RBBM_CLOCK_CNTL2_TP1 0x0000004f
1221
1222	#define REG_A5XX_RBBM_CLOCK_CNTL2_TP2 0x00000050
1223
1224	#define REG_A5XX_RBBM_CLOCK_CNTL2_TP3 0x00000051
1225
1226	#define REG_A5XX_RBBM_CLOCK_CNTL3_TP0 0x00000052
1227
1228	#define REG_A5XX_RBBM_CLOCK_CNTL3_TP1 0x00000053
1229
1230	#define REG_A5XX_RBBM_CLOCK_CNTL3_TP2 0x00000054
1231
1232	#define REG_A5XX_RBBM_CLOCK_CNTL3_TP3 0x00000055
1233
1234	#define REG_A5XX_RBBM_READ_AHB_THROUGH_DBG 0x00000059
1235
1236	#define REG_A5XX_RBBM_CLOCK_CNTL_UCHE 0x0000005a
1237
1238	#define REG_A5XX_RBBM_CLOCK_CNTL2_UCHE 0x0000005b
1239
1240	#define REG_A5XX_RBBM_CLOCK_CNTL3_UCHE 0x0000005c
1241
1242	#define REG_A5XX_RBBM_CLOCK_CNTL4_UCHE 0x0000005d
1243
1244	#define REG_A5XX_RBBM_CLOCK_HYST_UCHE 0x0000005e
1245
1246	#define REG_A5XX_RBBM_CLOCK_DELAY_UCHE 0x0000005f
1247
1248	#define REG_A5XX_RBBM_CLOCK_MODE_GPC 0x00000060
1249
1250	#define REG_A5XX_RBBM_CLOCK_DELAY_GPC 0x00000061
1251
1252	#define REG_A5XX_RBBM_CLOCK_HYST_GPC 0x00000062
1253
1254	#define REG_A5XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000063
1255
1256	#define REG_A5XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x00000064
1257
1258	#define REG_A5XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000065
1259
1260	#define REG_A5XX_RBBM_CLOCK_DELAY_HLSQ 0x00000066
1261
1262	#define REG_A5XX_RBBM_CLOCK_CNTL 0x00000067
1263
1264	#define REG_A5XX_RBBM_CLOCK_CNTL_SP0 0x00000068
1265
1266	#define REG_A5XX_RBBM_CLOCK_CNTL_SP1 0x00000069
1267
1268	#define REG_A5XX_RBBM_CLOCK_CNTL_SP2 0x0000006a
1269
1270	#define REG_A5XX_RBBM_CLOCK_CNTL_SP3 0x0000006b
1271
1272	#define REG_A5XX_RBBM_CLOCK_CNTL2_SP0 0x0000006c
1273
1274	#define REG_A5XX_RBBM_CLOCK_CNTL2_SP1 0x0000006d
1275
1276	#define REG_A5XX_RBBM_CLOCK_CNTL2_SP2 0x0000006e
1277
1278	#define REG_A5XX_RBBM_CLOCK_CNTL2_SP3 0x0000006f
1279
1280	#define REG_A5XX_RBBM_CLOCK_HYST_SP0 0x00000070
1281
1282	#define REG_A5XX_RBBM_CLOCK_HYST_SP1 0x00000071
1283
1284	#define REG_A5XX_RBBM_CLOCK_HYST_SP2 0x00000072
1285
1286	#define REG_A5XX_RBBM_CLOCK_HYST_SP3 0x00000073
1287
1288	#define REG_A5XX_RBBM_CLOCK_DELAY_SP0 0x00000074
1289
1290	#define REG_A5XX_RBBM_CLOCK_DELAY_SP1 0x00000075
1291
1292	#define REG_A5XX_RBBM_CLOCK_DELAY_SP2 0x00000076
1293
1294	#define REG_A5XX_RBBM_CLOCK_DELAY_SP3 0x00000077
1295
1296	#define REG_A5XX_RBBM_CLOCK_CNTL_RB0 0x00000078
1297
1298	#define REG_A5XX_RBBM_CLOCK_CNTL_RB1 0x00000079
1299
1300	#define REG_A5XX_RBBM_CLOCK_CNTL_RB2 0x0000007a
1301
1302	#define REG_A5XX_RBBM_CLOCK_CNTL_RB3 0x0000007b
1303
1304	#define REG_A5XX_RBBM_CLOCK_CNTL2_RB0 0x0000007c
1305
1306	#define REG_A5XX_RBBM_CLOCK_CNTL2_RB1 0x0000007d
1307
1308	#define REG_A5XX_RBBM_CLOCK_CNTL2_RB2 0x0000007e
1309
1310	#define REG_A5XX_RBBM_CLOCK_CNTL2_RB3 0x0000007f
1311
1312	#define REG_A5XX_RBBM_CLOCK_HYST_RAC 0x00000080
1313
1314	#define REG_A5XX_RBBM_CLOCK_DELAY_RAC 0x00000081
1315
1316	#define REG_A5XX_RBBM_CLOCK_CNTL_CCU0 0x00000082
1317
1318	#define REG_A5XX_RBBM_CLOCK_CNTL_CCU1 0x00000083
1319
1320	#define REG_A5XX_RBBM_CLOCK_CNTL_CCU2 0x00000084
1321
1322	#define REG_A5XX_RBBM_CLOCK_CNTL_CCU3 0x00000085
1323
1324	#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000086
1325
1326	#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000087
1327
1328	#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000088
1329
1330	#define REG_A5XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000089
1331
1332	#define REG_A5XX_RBBM_CLOCK_CNTL_RAC 0x0000008a
1333
1334	#define REG_A5XX_RBBM_CLOCK_CNTL2_RAC 0x0000008b
1335
1336	#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_0 0x0000008c
1337
1338	#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_1 0x0000008d
1339
1340	#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_2 0x0000008e
1341
1342	#define REG_A5XX_RBBM_CLOCK_DELAY_RB_CCU_L1_3 0x0000008f
1343
1344	#define REG_A5XX_RBBM_CLOCK_HYST_VFD 0x00000090
1345
1346	#define REG_A5XX_RBBM_CLOCK_MODE_VFD 0x00000091
1347
1348	#define REG_A5XX_RBBM_CLOCK_DELAY_VFD 0x00000092
1349
1350	#define REG_A5XX_RBBM_AHB_CNTL0 0x00000093
1351
1352	#define REG_A5XX_RBBM_AHB_CNTL1 0x00000094
1353
1354	#define REG_A5XX_RBBM_AHB_CNTL2 0x00000095
1355
1356	#define REG_A5XX_RBBM_AHB_CMD 0x00000096
1357
1358	#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL11 0x0000009c
1359
1360	#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL12 0x0000009d
1361
1362	#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL13 0x0000009e
1363
1364	#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL14 0x0000009f
1365
1366	#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL15 0x000000a0
1367
1368	#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL16 0x000000a1
1369
1370	#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL17 0x000000a2
1371
1372	#define REG_A5XX_RBBM_INTERFACE_HANG_MASK_CNTL18 0x000000a3
1373
1374	#define REG_A5XX_RBBM_CLOCK_DELAY_TP0 0x000000a4
1375
1376	#define REG_A5XX_RBBM_CLOCK_DELAY_TP1 0x000000a5
1377
1378	#define REG_A5XX_RBBM_CLOCK_DELAY_TP2 0x000000a6
1379
1380	#define REG_A5XX_RBBM_CLOCK_DELAY_TP3 0x000000a7
1381
1382	#define REG_A5XX_RBBM_CLOCK_DELAY2_TP0 0x000000a8
1383
1384	#define REG_A5XX_RBBM_CLOCK_DELAY2_TP1 0x000000a9
1385
1386	#define REG_A5XX_RBBM_CLOCK_DELAY2_TP2 0x000000aa
1387
1388	#define REG_A5XX_RBBM_CLOCK_DELAY2_TP3 0x000000ab
1389
1390	#define REG_A5XX_RBBM_CLOCK_DELAY3_TP0 0x000000ac
1391
1392	#define REG_A5XX_RBBM_CLOCK_DELAY3_TP1 0x000000ad
1393
1394	#define REG_A5XX_RBBM_CLOCK_DELAY3_TP2 0x000000ae
1395
1396	#define REG_A5XX_RBBM_CLOCK_DELAY3_TP3 0x000000af
1397
1398	#define REG_A5XX_RBBM_CLOCK_HYST_TP0 0x000000b0
1399
1400	#define REG_A5XX_RBBM_CLOCK_HYST_TP1 0x000000b1
1401
1402	#define REG_A5XX_RBBM_CLOCK_HYST_TP2 0x000000b2
1403
1404	#define REG_A5XX_RBBM_CLOCK_HYST_TP3 0x000000b3
1405
1406	#define REG_A5XX_RBBM_CLOCK_HYST2_TP0 0x000000b4
1407
1408	#define REG_A5XX_RBBM_CLOCK_HYST2_TP1 0x000000b5
1409
1410	#define REG_A5XX_RBBM_CLOCK_HYST2_TP2 0x000000b6
1411
1412	#define REG_A5XX_RBBM_CLOCK_HYST2_TP3 0x000000b7
1413
1414	#define REG_A5XX_RBBM_CLOCK_HYST3_TP0 0x000000b8
1415
1416	#define REG_A5XX_RBBM_CLOCK_HYST3_TP1 0x000000b9
1417
1418	#define REG_A5XX_RBBM_CLOCK_HYST3_TP2 0x000000ba
1419
1420	#define REG_A5XX_RBBM_CLOCK_HYST3_TP3 0x000000bb
1421
1422	#define REG_A5XX_RBBM_CLOCK_CNTL_GPMU 0x000000c8
1423
1424	#define REG_A5XX_RBBM_CLOCK_DELAY_GPMU 0x000000c9
1425
1426	#define REG_A5XX_RBBM_CLOCK_HYST_GPMU 0x000000ca
1427
1428	#define REG_A5XX_RBBM_PERFCTR_CP_0_LO 0x000003a0
1429
1430	#define REG_A5XX_RBBM_PERFCTR_CP_0_HI 0x000003a1
1431
1432	#define REG_A5XX_RBBM_PERFCTR_CP_1_LO 0x000003a2
1433
1434	#define REG_A5XX_RBBM_PERFCTR_CP_1_HI 0x000003a3
1435
1436	#define REG_A5XX_RBBM_PERFCTR_CP_2_LO 0x000003a4
1437
1438	#define REG_A5XX_RBBM_PERFCTR_CP_2_HI 0x000003a5
1439
1440	#define REG_A5XX_RBBM_PERFCTR_CP_3_LO 0x000003a6
1441
1442	#define REG_A5XX_RBBM_PERFCTR_CP_3_HI 0x000003a7
1443
1444	#define REG_A5XX_RBBM_PERFCTR_CP_4_LO 0x000003a8
1445
1446	#define REG_A5XX_RBBM_PERFCTR_CP_4_HI 0x000003a9
1447
1448	#define REG_A5XX_RBBM_PERFCTR_CP_5_LO 0x000003aa
1449
1450	#define REG_A5XX_RBBM_PERFCTR_CP_5_HI 0x000003ab
1451
1452	#define REG_A5XX_RBBM_PERFCTR_CP_6_LO 0x000003ac
1453
1454	#define REG_A5XX_RBBM_PERFCTR_CP_6_HI 0x000003ad
1455
1456	#define REG_A5XX_RBBM_PERFCTR_CP_7_LO 0x000003ae
1457
1458	#define REG_A5XX_RBBM_PERFCTR_CP_7_HI 0x000003af
1459
1460	#define REG_A5XX_RBBM_PERFCTR_RBBM_0_LO 0x000003b0
1461
1462	#define REG_A5XX_RBBM_PERFCTR_RBBM_0_HI 0x000003b1
1463
1464	#define REG_A5XX_RBBM_PERFCTR_RBBM_1_LO 0x000003b2
1465
1466	#define REG_A5XX_RBBM_PERFCTR_RBBM_1_HI 0x000003b3
1467
1468	#define REG_A5XX_RBBM_PERFCTR_RBBM_2_LO 0x000003b4
1469
1470	#define REG_A5XX_RBBM_PERFCTR_RBBM_2_HI 0x000003b5
1471
1472	#define REG_A5XX_RBBM_PERFCTR_RBBM_3_LO 0x000003b6
1473
1474	#define REG_A5XX_RBBM_PERFCTR_RBBM_3_HI 0x000003b7
1475
1476	#define REG_A5XX_RBBM_PERFCTR_PC_0_LO 0x000003b8
1477
1478	#define REG_A5XX_RBBM_PERFCTR_PC_0_HI 0x000003b9
1479
1480	#define REG_A5XX_RBBM_PERFCTR_PC_1_LO 0x000003ba
1481
1482	#define REG_A5XX_RBBM_PERFCTR_PC_1_HI 0x000003bb
1483
1484	#define REG_A5XX_RBBM_PERFCTR_PC_2_LO 0x000003bc
1485
1486	#define REG_A5XX_RBBM_PERFCTR_PC_2_HI 0x000003bd
1487
1488	#define REG_A5XX_RBBM_PERFCTR_PC_3_LO 0x000003be
1489
1490	#define REG_A5XX_RBBM_PERFCTR_PC_3_HI 0x000003bf
1491
1492	#define REG_A5XX_RBBM_PERFCTR_PC_4_LO 0x000003c0
1493
1494	#define REG_A5XX_RBBM_PERFCTR_PC_4_HI 0x000003c1
1495
1496	#define REG_A5XX_RBBM_PERFCTR_PC_5_LO 0x000003c2
1497
1498	#define REG_A5XX_RBBM_PERFCTR_PC_5_HI 0x000003c3
1499
1500	#define REG_A5XX_RBBM_PERFCTR_PC_6_LO 0x000003c4
1501
1502	#define REG_A5XX_RBBM_PERFCTR_PC_6_HI 0x000003c5
1503
1504	#define REG_A5XX_RBBM_PERFCTR_PC_7_LO 0x000003c6
1505
1506	#define REG_A5XX_RBBM_PERFCTR_PC_7_HI 0x000003c7
1507
1508	#define REG_A5XX_RBBM_PERFCTR_VFD_0_LO 0x000003c8
1509
1510	#define REG_A5XX_RBBM_PERFCTR_VFD_0_HI 0x000003c9
1511
1512	#define REG_A5XX_RBBM_PERFCTR_VFD_1_LO 0x000003ca
1513
1514	#define REG_A5XX_RBBM_PERFCTR_VFD_1_HI 0x000003cb
1515
1516	#define REG_A5XX_RBBM_PERFCTR_VFD_2_LO 0x000003cc
1517
1518	#define REG_A5XX_RBBM_PERFCTR_VFD_2_HI 0x000003cd
1519
1520	#define REG_A5XX_RBBM_PERFCTR_VFD_3_LO 0x000003ce
1521
1522	#define REG_A5XX_RBBM_PERFCTR_VFD_3_HI 0x000003cf
1523
1524	#define REG_A5XX_RBBM_PERFCTR_VFD_4_LO 0x000003d0
1525
1526	#define REG_A5XX_RBBM_PERFCTR_VFD_4_HI 0x000003d1
1527
1528	#define REG_A5XX_RBBM_PERFCTR_VFD_5_LO 0x000003d2
1529
1530	#define REG_A5XX_RBBM_PERFCTR_VFD_5_HI 0x000003d3
1531
1532	#define REG_A5XX_RBBM_PERFCTR_VFD_6_LO 0x000003d4
1533
1534	#define REG_A5XX_RBBM_PERFCTR_VFD_6_HI 0x000003d5
1535
1536	#define REG_A5XX_RBBM_PERFCTR_VFD_7_LO 0x000003d6
1537
1538	#define REG_A5XX_RBBM_PERFCTR_VFD_7_HI 0x000003d7
1539
1540	#define REG_A5XX_RBBM_PERFCTR_HLSQ_0_LO 0x000003d8
1541
1542	#define REG_A5XX_RBBM_PERFCTR_HLSQ_0_HI 0x000003d9
1543
1544	#define REG_A5XX_RBBM_PERFCTR_HLSQ_1_LO 0x000003da
1545
1546	#define REG_A5XX_RBBM_PERFCTR_HLSQ_1_HI 0x000003db
1547
1548	#define REG_A5XX_RBBM_PERFCTR_HLSQ_2_LO 0x000003dc
1549
1550	#define REG_A5XX_RBBM_PERFCTR_HLSQ_2_HI 0x000003dd
1551
1552	#define REG_A5XX_RBBM_PERFCTR_HLSQ_3_LO 0x000003de
1553
1554	#define REG_A5XX_RBBM_PERFCTR_HLSQ_3_HI 0x000003df
1555
1556	#define REG_A5XX_RBBM_PERFCTR_HLSQ_4_LO 0x000003e0
1557
1558	#define REG_A5XX_RBBM_PERFCTR_HLSQ_4_HI 0x000003e1
1559
1560	#define REG_A5XX_RBBM_PERFCTR_HLSQ_5_LO 0x000003e2
1561
1562	#define REG_A5XX_RBBM_PERFCTR_HLSQ_5_HI 0x000003e3
1563
1564	#define REG_A5XX_RBBM_PERFCTR_HLSQ_6_LO 0x000003e4
1565
1566	#define REG_A5XX_RBBM_PERFCTR_HLSQ_6_HI 0x000003e5
1567
1568	#define REG_A5XX_RBBM_PERFCTR_HLSQ_7_LO 0x000003e6
1569
1570	#define REG_A5XX_RBBM_PERFCTR_HLSQ_7_HI 0x000003e7
1571
1572	#define REG_A5XX_RBBM_PERFCTR_VPC_0_LO 0x000003e8
1573
1574	#define REG_A5XX_RBBM_PERFCTR_VPC_0_HI 0x000003e9
1575
1576	#define REG_A5XX_RBBM_PERFCTR_VPC_1_LO 0x000003ea
1577
1578	#define REG_A5XX_RBBM_PERFCTR_VPC_1_HI 0x000003eb
1579
1580	#define REG_A5XX_RBBM_PERFCTR_VPC_2_LO 0x000003ec
1581
1582	#define REG_A5XX_RBBM_PERFCTR_VPC_2_HI 0x000003ed
1583
1584	#define REG_A5XX_RBBM_PERFCTR_VPC_3_LO 0x000003ee
1585
1586	#define REG_A5XX_RBBM_PERFCTR_VPC_3_HI 0x000003ef
1587
1588	#define REG_A5XX_RBBM_PERFCTR_CCU_0_LO 0x000003f0
1589
1590	#define REG_A5XX_RBBM_PERFCTR_CCU_0_HI 0x000003f1
1591
1592	#define REG_A5XX_RBBM_PERFCTR_CCU_1_LO 0x000003f2
1593
1594	#define REG_A5XX_RBBM_PERFCTR_CCU_1_HI 0x000003f3
1595
1596	#define REG_A5XX_RBBM_PERFCTR_CCU_2_LO 0x000003f4
1597
1598	#define REG_A5XX_RBBM_PERFCTR_CCU_2_HI 0x000003f5
1599
1600	#define REG_A5XX_RBBM_PERFCTR_CCU_3_LO 0x000003f6
1601
1602	#define REG_A5XX_RBBM_PERFCTR_CCU_3_HI 0x000003f7
1603
1604	#define REG_A5XX_RBBM_PERFCTR_TSE_0_LO 0x000003f8
1605
1606	#define REG_A5XX_RBBM_PERFCTR_TSE_0_HI 0x000003f9
1607
1608	#define REG_A5XX_RBBM_PERFCTR_TSE_1_LO 0x000003fa
1609
1610	#define REG_A5XX_RBBM_PERFCTR_TSE_1_HI 0x000003fb
1611
1612	#define REG_A5XX_RBBM_PERFCTR_TSE_2_LO 0x000003fc
1613
1614	#define REG_A5XX_RBBM_PERFCTR_TSE_2_HI 0x000003fd
1615
1616	#define REG_A5XX_RBBM_PERFCTR_TSE_3_LO 0x000003fe
1617
1618	#define REG_A5XX_RBBM_PERFCTR_TSE_3_HI 0x000003ff
1619
1620	#define REG_A5XX_RBBM_PERFCTR_RAS_0_LO 0x00000400
1621
1622	#define REG_A5XX_RBBM_PERFCTR_RAS_0_HI 0x00000401
1623
1624	#define REG_A5XX_RBBM_PERFCTR_RAS_1_LO 0x00000402
1625
1626	#define REG_A5XX_RBBM_PERFCTR_RAS_1_HI 0x00000403
1627
1628	#define REG_A5XX_RBBM_PERFCTR_RAS_2_LO 0x00000404
1629
1630	#define REG_A5XX_RBBM_PERFCTR_RAS_2_HI 0x00000405
1631
1632	#define REG_A5XX_RBBM_PERFCTR_RAS_3_LO 0x00000406
1633
1634	#define REG_A5XX_RBBM_PERFCTR_RAS_3_HI 0x00000407
1635
1636	#define REG_A5XX_RBBM_PERFCTR_UCHE_0_LO 0x00000408
1637
1638	#define REG_A5XX_RBBM_PERFCTR_UCHE_0_HI 0x00000409
1639
1640	#define REG_A5XX_RBBM_PERFCTR_UCHE_1_LO 0x0000040a
1641
1642	#define REG_A5XX_RBBM_PERFCTR_UCHE_1_HI 0x0000040b
1643
1644	#define REG_A5XX_RBBM_PERFCTR_UCHE_2_LO 0x0000040c
1645
1646	#define REG_A5XX_RBBM_PERFCTR_UCHE_2_HI 0x0000040d
1647
1648	#define REG_A5XX_RBBM_PERFCTR_UCHE_3_LO 0x0000040e
1649
1650	#define REG_A5XX_RBBM_PERFCTR_UCHE_3_HI 0x0000040f
1651
1652	#define REG_A5XX_RBBM_PERFCTR_UCHE_4_LO 0x00000410
1653
1654	#define REG_A5XX_RBBM_PERFCTR_UCHE_4_HI 0x00000411
1655
1656	#define REG_A5XX_RBBM_PERFCTR_UCHE_5_LO 0x00000412
1657
1658	#define REG_A5XX_RBBM_PERFCTR_UCHE_5_HI 0x00000413
1659
1660	#define REG_A5XX_RBBM_PERFCTR_UCHE_6_LO 0x00000414
1661
1662	#define REG_A5XX_RBBM_PERFCTR_UCHE_6_HI 0x00000415
1663
1664	#define REG_A5XX_RBBM_PERFCTR_UCHE_7_LO 0x00000416
1665
1666	#define REG_A5XX_RBBM_PERFCTR_UCHE_7_HI 0x00000417
1667
1668	#define REG_A5XX_RBBM_PERFCTR_TP_0_LO 0x00000418
1669
1670	#define REG_A5XX_RBBM_PERFCTR_TP_0_HI 0x00000419
1671
1672	#define REG_A5XX_RBBM_PERFCTR_TP_1_LO 0x0000041a
1673
1674	#define REG_A5XX_RBBM_PERFCTR_TP_1_HI 0x0000041b
1675
1676	#define REG_A5XX_RBBM_PERFCTR_TP_2_LO 0x0000041c
1677
1678	#define REG_A5XX_RBBM_PERFCTR_TP_2_HI 0x0000041d
1679
1680	#define REG_A5XX_RBBM_PERFCTR_TP_3_LO 0x0000041e
1681
1682	#define REG_A5XX_RBBM_PERFCTR_TP_3_HI 0x0000041f
1683
1684	#define REG_A5XX_RBBM_PERFCTR_TP_4_LO 0x00000420
1685
1686	#define REG_A5XX_RBBM_PERFCTR_TP_4_HI 0x00000421
1687
1688	#define REG_A5XX_RBBM_PERFCTR_TP_5_LO 0x00000422
1689
1690	#define REG_A5XX_RBBM_PERFCTR_TP_5_HI 0x00000423
1691
1692	#define REG_A5XX_RBBM_PERFCTR_TP_6_LO 0x00000424
1693
1694	#define REG_A5XX_RBBM_PERFCTR_TP_6_HI 0x00000425
1695
1696	#define REG_A5XX_RBBM_PERFCTR_TP_7_LO 0x00000426
1697
1698	#define REG_A5XX_RBBM_PERFCTR_TP_7_HI 0x00000427
1699
1700	#define REG_A5XX_RBBM_PERFCTR_SP_0_LO 0x00000428
1701
1702	#define REG_A5XX_RBBM_PERFCTR_SP_0_HI 0x00000429
1703
1704	#define REG_A5XX_RBBM_PERFCTR_SP_1_LO 0x0000042a
1705
1706	#define REG_A5XX_RBBM_PERFCTR_SP_1_HI 0x0000042b
1707
1708	#define REG_A5XX_RBBM_PERFCTR_SP_2_LO 0x0000042c
1709
1710	#define REG_A5XX_RBBM_PERFCTR_SP_2_HI 0x0000042d
1711
1712	#define REG_A5XX_RBBM_PERFCTR_SP_3_LO 0x0000042e
1713
1714	#define REG_A5XX_RBBM_PERFCTR_SP_3_HI 0x0000042f
1715
1716	#define REG_A5XX_RBBM_PERFCTR_SP_4_LO 0x00000430
1717
1718	#define REG_A5XX_RBBM_PERFCTR_SP_4_HI 0x00000431
1719
1720	#define REG_A5XX_RBBM_PERFCTR_SP_5_LO 0x00000432
1721
1722	#define REG_A5XX_RBBM_PERFCTR_SP_5_HI 0x00000433
1723
1724	#define REG_A5XX_RBBM_PERFCTR_SP_6_LO 0x00000434
1725
1726	#define REG_A5XX_RBBM_PERFCTR_SP_6_HI 0x00000435
1727
1728	#define REG_A5XX_RBBM_PERFCTR_SP_7_LO 0x00000436
1729
1730	#define REG_A5XX_RBBM_PERFCTR_SP_7_HI 0x00000437
1731
1732	#define REG_A5XX_RBBM_PERFCTR_SP_8_LO 0x00000438
1733
1734	#define REG_A5XX_RBBM_PERFCTR_SP_8_HI 0x00000439
1735
1736	#define REG_A5XX_RBBM_PERFCTR_SP_9_LO 0x0000043a
1737
1738	#define REG_A5XX_RBBM_PERFCTR_SP_9_HI 0x0000043b
1739
1740	#define REG_A5XX_RBBM_PERFCTR_SP_10_LO 0x0000043c
1741
1742	#define REG_A5XX_RBBM_PERFCTR_SP_10_HI 0x0000043d
1743
1744	#define REG_A5XX_RBBM_PERFCTR_SP_11_LO 0x0000043e
1745
1746	#define REG_A5XX_RBBM_PERFCTR_SP_11_HI 0x0000043f
1747
1748	#define REG_A5XX_RBBM_PERFCTR_RB_0_LO 0x00000440
1749
1750	#define REG_A5XX_RBBM_PERFCTR_RB_0_HI 0x00000441
1751
1752	#define REG_A5XX_RBBM_PERFCTR_RB_1_LO 0x00000442
1753
1754	#define REG_A5XX_RBBM_PERFCTR_RB_1_HI 0x00000443
1755
1756	#define REG_A5XX_RBBM_PERFCTR_RB_2_LO 0x00000444
1757
1758	#define REG_A5XX_RBBM_PERFCTR_RB_2_HI 0x00000445
1759
1760	#define REG_A5XX_RBBM_PERFCTR_RB_3_LO 0x00000446
1761
1762	#define REG_A5XX_RBBM_PERFCTR_RB_3_HI 0x00000447
1763
1764	#define REG_A5XX_RBBM_PERFCTR_RB_4_LO 0x00000448
1765
1766	#define REG_A5XX_RBBM_PERFCTR_RB_4_HI 0x00000449
1767
1768	#define REG_A5XX_RBBM_PERFCTR_RB_5_LO 0x0000044a
1769
1770	#define REG_A5XX_RBBM_PERFCTR_RB_5_HI 0x0000044b
1771
1772	#define REG_A5XX_RBBM_PERFCTR_RB_6_LO 0x0000044c
1773
1774	#define REG_A5XX_RBBM_PERFCTR_RB_6_HI 0x0000044d
1775
1776	#define REG_A5XX_RBBM_PERFCTR_RB_7_LO 0x0000044e
1777
1778	#define REG_A5XX_RBBM_PERFCTR_RB_7_HI 0x0000044f
1779
1780	#define REG_A5XX_RBBM_PERFCTR_VSC_0_LO 0x00000450
1781
1782	#define REG_A5XX_RBBM_PERFCTR_VSC_0_HI 0x00000451
1783
1784	#define REG_A5XX_RBBM_PERFCTR_VSC_1_LO 0x00000452
1785
1786	#define REG_A5XX_RBBM_PERFCTR_VSC_1_HI 0x00000453
1787
1788	#define REG_A5XX_RBBM_PERFCTR_LRZ_0_LO 0x00000454
1789
1790	#define REG_A5XX_RBBM_PERFCTR_LRZ_0_HI 0x00000455
1791
1792	#define REG_A5XX_RBBM_PERFCTR_LRZ_1_LO 0x00000456
1793
1794	#define REG_A5XX_RBBM_PERFCTR_LRZ_1_HI 0x00000457
1795
1796	#define REG_A5XX_RBBM_PERFCTR_LRZ_2_LO 0x00000458
1797
1798	#define REG_A5XX_RBBM_PERFCTR_LRZ_2_HI 0x00000459
1799
1800	#define REG_A5XX_RBBM_PERFCTR_LRZ_3_LO 0x0000045a
1801
1802	#define REG_A5XX_RBBM_PERFCTR_LRZ_3_HI 0x0000045b
1803
1804	#define REG_A5XX_RBBM_PERFCTR_CMP_0_LO 0x0000045c
1805
1806	#define REG_A5XX_RBBM_PERFCTR_CMP_0_HI 0x0000045d
1807
1808	#define REG_A5XX_RBBM_PERFCTR_CMP_1_LO 0x0000045e
1809
1810	#define REG_A5XX_RBBM_PERFCTR_CMP_1_HI 0x0000045f
1811
1812	#define REG_A5XX_RBBM_PERFCTR_CMP_2_LO 0x00000460
1813
1814	#define REG_A5XX_RBBM_PERFCTR_CMP_2_HI 0x00000461
1815
1816	#define REG_A5XX_RBBM_PERFCTR_CMP_3_LO 0x00000462
1817
1818	#define REG_A5XX_RBBM_PERFCTR_CMP_3_HI 0x00000463
1819
1820	#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_0 0x0000046b
1821
1822	#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_1 0x0000046c
1823
1824	#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_2 0x0000046d
1825
1826	#define REG_A5XX_RBBM_PERFCTR_RBBM_SEL_3 0x0000046e
1827
1828	#define REG_A5XX_RBBM_ALWAYSON_COUNTER_LO 0x000004d2
1829
1830	#define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3
1831
1832	#define REG_A5XX_RBBM_STATUS 0x000004f5
1833	#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x80000000
1834	#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x40000000
1835	#define A5XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
1836	#define A5XX_RBBM_STATUS_VSC_BUSY 0x10000000
1837	#define A5XX_RBBM_STATUS_TPL1_BUSY 0x08000000
1838	#define A5XX_RBBM_STATUS_SP_BUSY 0x04000000
1839	#define A5XX_RBBM_STATUS_UCHE_BUSY 0x02000000
1840	#define A5XX_RBBM_STATUS_VPC_BUSY 0x01000000
1841	#define A5XX_RBBM_STATUS_VFDP_BUSY 0x00800000
1842	#define A5XX_RBBM_STATUS_VFD_BUSY 0x00400000
1843	#define A5XX_RBBM_STATUS_TESS_BUSY 0x00200000
1844	#define A5XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
1845	#define A5XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
1846	#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY 0x00040000
1847	#define A5XX_RBBM_STATUS_DCOM_BUSY 0x00020000
1848	#define A5XX_RBBM_STATUS_COM_BUSY 0x00010000
1849	#define A5XX_RBBM_STATUS_LRZ_BUZY 0x00008000
1850	#define A5XX_RBBM_STATUS_A2D_DSP_BUSY 0x00004000
1851	#define A5XX_RBBM_STATUS_CCUFCHE_BUSY 0x00002000
1852	#define A5XX_RBBM_STATUS_RB_BUSY 0x00001000
1853	#define A5XX_RBBM_STATUS_RAS_BUSY 0x00000800
1854	#define A5XX_RBBM_STATUS_TSE_BUSY 0x00000400
1855	#define A5XX_RBBM_STATUS_VBIF_BUSY 0x00000200
1856	#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST 0x00000100
1857	#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST 0x00000080
1858	#define A5XX_RBBM_STATUS_CP_BUSY 0x00000040
1859	#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY 0x00000020
1860	#define A5XX_RBBM_STATUS_CP_CRASH_BUSY 0x00000010
1861	#define A5XX_RBBM_STATUS_CP_ETS_BUSY 0x00000008
1862	#define A5XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
1863	#define A5XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
1864	#define A5XX_RBBM_STATUS_HI_BUSY 0x00000001
1865
1866	#define REG_A5XX_RBBM_STATUS3 0x00000530
1867	#define A5XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000
1868
1869	#define REG_A5XX_RBBM_INT_0_STATUS 0x000004e1
1870
1871	#define REG_A5XX_RBBM_AHB_ME_SPLIT_STATUS 0x000004f0
1872
1873	#define REG_A5XX_RBBM_AHB_PFP_SPLIT_STATUS 0x000004f1
1874
1875	#define REG_A5XX_RBBM_AHB_ETS_SPLIT_STATUS 0x000004f3
1876
1877	#define REG_A5XX_RBBM_AHB_ERROR_STATUS 0x000004f4
1878
1879	#define REG_A5XX_RBBM_PERFCTR_CNTL 0x00000464
1880
1881	#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD0 0x00000465
1882
1883	#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD1 0x00000466
1884
1885	#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD2 0x00000467
1886
1887	#define REG_A5XX_RBBM_PERFCTR_LOAD_CMD3 0x00000468
1888
1889	#define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000469
1890
1891	#define REG_A5XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x0000046a
1892
1893	#define REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000046f
1894
1895	#define REG_A5XX_RBBM_AHB_ERROR 0x000004ed
1896
1897	#define REG_A5XX_RBBM_CFG_DBGBUS_EVENT_LOGIC 0x00000504
1898
1899	#define REG_A5XX_RBBM_CFG_DBGBUS_OVER 0x00000505
1900
1901	#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT0 0x00000506
1902
1903	#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT1 0x00000507
1904
1905	#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT2 0x00000508
1906
1907	#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT3 0x00000509
1908
1909	#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT4 0x0000050a
1910
1911	#define REG_A5XX_RBBM_CFG_DBGBUS_COUNT5 0x0000050b
1912
1913	#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_ADDR 0x0000050c
1914
1915	#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF0 0x0000050d
1916
1917	#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF1 0x0000050e
1918
1919	#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF2 0x0000050f
1920
1921	#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF3 0x00000510
1922
1923	#define REG_A5XX_RBBM_CFG_DBGBUS_TRACE_BUF4 0x00000511
1924
1925	#define REG_A5XX_RBBM_CFG_DBGBUS_MISR0 0x00000512
1926
1927	#define REG_A5XX_RBBM_CFG_DBGBUS_MISR1 0x00000513
1928
1929	#define REG_A5XX_RBBM_ISDB_CNT 0x00000533
1930
1931	#define REG_A5XX_RBBM_SECVID_TRUST_CONFIG 0x0000f000
1932
1933	#define REG_A5XX_RBBM_SECVID_TRUST_CNTL 0x0000f400
1934
1935	#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO 0x0000f800
1936
1937	#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI 0x0000f801
1938
1939	#define REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802
1940
1941	#define REG_A5XX_RBBM_SECVID_TSB_CNTL 0x0000f803
1942
1943	#define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_LO 0x0000f804
1944
1945	#define REG_A5XX_RBBM_SECVID_TSB_COMP_STATUS_HI 0x0000f805
1946
1947	#define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_LO 0x0000f806
1948
1949	#define REG_A5XX_RBBM_SECVID_TSB_UCHE_STATUS_HI 0x0000f807
1950
1951	#define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
1952
1953	#define REG_A5XX_VSC_BIN_SIZE 0x00000bc2
1954	#define A5XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
1955	#define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
1956	static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
1957	{
1958	assert(!(val & 0x1f));
1959	return (((val >> 5)) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK;
1960	}
1961	#define A5XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001fe00
1962	#define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT 9
1963	static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
1964	{
1965	assert(!(val & 0x1f));
1966	return (((val >> 5)) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK;
1967	}
1968
1969	#define REG_A5XX_VSC_SIZE_ADDRESS_LO 0x00000bc3
1970
1971	#define REG_A5XX_VSC_SIZE_ADDRESS_HI 0x00000bc4
1972
1973	#define REG_A5XX_UNKNOWN_0BC5 0x00000bc5
1974
1975	#define REG_A5XX_UNKNOWN_0BC6 0x00000bc6
1976
1977	#define REG_A5XX_VSC_PIPE_CONFIG(i0) (0x00000bd0 + 0x1*(i0))
1978
1979	static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
1980	#define A5XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
1981	#define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
1982	static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
1983	{
1984	return ((val) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK;
1985	}
1986	#define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
1987	#define A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
1988	static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
1989	{
1990	return ((val) << A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_Y__MASK;
1991	}
1992	#define A5XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
1993	#define A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
1994	static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
1995	{
1996	return ((val) << A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_W__MASK;
1997	}
1998	#define A5XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
1999	#define A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
2000	static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
2001	{
2002	return ((val) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK;
2003	}
2004
2005	#define REG_A5XX_VSC_PIPE_DATA_ADDRESS(i0) (0x00000be0 + 0x2*(i0))
2006
2007	static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
2008
2009	static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; }
2010
2011	#define REG_A5XX_VSC_PIPE_DATA_LENGTH(i0) (0x00000c00 + 0x1*(i0))
2012
2013	static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
2014
2015	#define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 0x00000c60
2016
2017	#define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 0x00000c61
2018
2019	#define REG_A5XX_VSC_RESOLVE_CNTL 0x00000cdd
2020	#define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE 0x80000000
2021	#define A5XX_VSC_RESOLVE_CNTL_X__MASK 0x00007fff
2022	#define A5XX_VSC_RESOLVE_CNTL_X__SHIFT 0
2023	static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val)
2024	{
2025	return ((val) << A5XX_VSC_RESOLVE_CNTL_X__SHIFT) & A5XX_VSC_RESOLVE_CNTL_X__MASK;
2026	}
2027	#define A5XX_VSC_RESOLVE_CNTL_Y__MASK 0x7fff0000
2028	#define A5XX_VSC_RESOLVE_CNTL_Y__SHIFT 16
2029	static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
2030	{
2031	return ((val) << A5XX_VSC_RESOLVE_CNTL_Y__SHIFT) & A5XX_VSC_RESOLVE_CNTL_Y__MASK;
2032	}
2033
2034	#define REG_A5XX_GRAS_ADDR_MODE_CNTL 0x00000c81
2035
2036	#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_0 0x00000c90
2037
2038	#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_1 0x00000c91
2039
2040	#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_2 0x00000c92
2041
2042	#define REG_A5XX_GRAS_PERFCTR_TSE_SEL_3 0x00000c93
2043
2044	#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_0 0x00000c94
2045
2046	#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_1 0x00000c95
2047
2048	#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_2 0x00000c96
2049
2050	#define REG_A5XX_GRAS_PERFCTR_RAS_SEL_3 0x00000c97
2051
2052	#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_0 0x00000c98
2053
2054	#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_1 0x00000c99
2055
2056	#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_2 0x00000c9a
2057
2058	#define REG_A5XX_GRAS_PERFCTR_LRZ_SEL_3 0x00000c9b
2059
2060	#define REG_A5XX_RB_DBG_ECO_CNTL 0x00000cc4
2061
2062	#define REG_A5XX_RB_ADDR_MODE_CNTL 0x00000cc5
2063
2064	#define REG_A5XX_RB_MODE_CNTL 0x00000cc6
2065
2066	#define REG_A5XX_RB_CCU_CNTL 0x00000cc7
2067
2068	#define REG_A5XX_RB_PERFCTR_RB_SEL_0 0x00000cd0
2069
2070	#define REG_A5XX_RB_PERFCTR_RB_SEL_1 0x00000cd1
2071
2072	#define REG_A5XX_RB_PERFCTR_RB_SEL_2 0x00000cd2
2073
2074	#define REG_A5XX_RB_PERFCTR_RB_SEL_3 0x00000cd3
2075
2076	#define REG_A5XX_RB_PERFCTR_RB_SEL_4 0x00000cd4
2077
2078	#define REG_A5XX_RB_PERFCTR_RB_SEL_5 0x00000cd5
2079
2080	#define REG_A5XX_RB_PERFCTR_RB_SEL_6 0x00000cd6
2081
2082	#define REG_A5XX_RB_PERFCTR_RB_SEL_7 0x00000cd7
2083
2084	#define REG_A5XX_RB_PERFCTR_CCU_SEL_0 0x00000cd8
2085
2086	#define REG_A5XX_RB_PERFCTR_CCU_SEL_1 0x00000cd9
2087
2088	#define REG_A5XX_RB_PERFCTR_CCU_SEL_2 0x00000cda
2089
2090	#define REG_A5XX_RB_PERFCTR_CCU_SEL_3 0x00000cdb
2091
2092	#define REG_A5XX_RB_POWERCTR_RB_SEL_0 0x00000ce0
2093
2094	#define REG_A5XX_RB_POWERCTR_RB_SEL_1 0x00000ce1
2095
2096	#define REG_A5XX_RB_POWERCTR_RB_SEL_2 0x00000ce2
2097
2098	#define REG_A5XX_RB_POWERCTR_RB_SEL_3 0x00000ce3
2099
2100	#define REG_A5XX_RB_POWERCTR_CCU_SEL_0 0x00000ce4
2101
2102	#define REG_A5XX_RB_POWERCTR_CCU_SEL_1 0x00000ce5
2103
2104	#define REG_A5XX_RB_PERFCTR_CMP_SEL_0 0x00000cec
2105
2106	#define REG_A5XX_RB_PERFCTR_CMP_SEL_1 0x00000ced
2107
2108	#define REG_A5XX_RB_PERFCTR_CMP_SEL_2 0x00000cee
2109
2110	#define REG_A5XX_RB_PERFCTR_CMP_SEL_3 0x00000cef
2111
2112	#define REG_A5XX_PC_DBG_ECO_CNTL 0x00000d00
2113	#define A5XX_PC_DBG_ECO_CNTL_TWOPASSUSEWFI 0x00000100
2114
2115	#define REG_A5XX_PC_ADDR_MODE_CNTL 0x00000d01
2116
2117	#define REG_A5XX_PC_MODE_CNTL 0x00000d02
2118
2119	#define REG_A5XX_PC_INDEX_BUF_LO 0x00000d04
2120
2121	#define REG_A5XX_PC_INDEX_BUF_HI 0x00000d05
2122
2123	#define REG_A5XX_PC_START_INDEX 0x00000d06
2124
2125	#define REG_A5XX_PC_MAX_INDEX 0x00000d07
2126
2127	#define REG_A5XX_PC_TESSFACTOR_ADDR_LO 0x00000d08
2128
2129	#define REG_A5XX_PC_TESSFACTOR_ADDR_HI 0x00000d09
2130
2131	#define REG_A5XX_PC_PERFCTR_PC_SEL_0 0x00000d10
2132
2133	#define REG_A5XX_PC_PERFCTR_PC_SEL_1 0x00000d11
2134
2135	#define REG_A5XX_PC_PERFCTR_PC_SEL_2 0x00000d12
2136
2137	#define REG_A5XX_PC_PERFCTR_PC_SEL_3 0x00000d13
2138
2139	#define REG_A5XX_PC_PERFCTR_PC_SEL_4 0x00000d14
2140
2141	#define REG_A5XX_PC_PERFCTR_PC_SEL_5 0x00000d15
2142
2143	#define REG_A5XX_PC_PERFCTR_PC_SEL_6 0x00000d16
2144
2145	#define REG_A5XX_PC_PERFCTR_PC_SEL_7 0x00000d17
2146
2147	#define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0 0x00000e00
2148
2149	#define REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_1 0x00000e01
2150
2151	#define REG_A5XX_HLSQ_DBG_ECO_CNTL 0x00000e04
2152
2153	#define REG_A5XX_HLSQ_ADDR_MODE_CNTL 0x00000e05
2154
2155	#define REG_A5XX_HLSQ_MODE_CNTL 0x00000e06
2156
2157	#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_0 0x00000e10
2158
2159	#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_1 0x00000e11
2160
2161	#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_2 0x00000e12
2162
2163	#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_3 0x00000e13
2164
2165	#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_4 0x00000e14
2166
2167	#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_5 0x00000e15
2168
2169	#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_6 0x00000e16
2170
2171	#define REG_A5XX_HLSQ_PERFCTR_HLSQ_SEL_7 0x00000e17
2172
2173	#define REG_A5XX_HLSQ_SPTP_RDSEL 0x00000f08
2174
2175	#define REG_A5XX_HLSQ_DBG_READ_SEL 0x0000bc00
2176
2177	#define REG_A5XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000a000
2178
2179	#define REG_A5XX_VFD_ADDR_MODE_CNTL 0x00000e41
2180
2181	#define REG_A5XX_VFD_MODE_CNTL 0x00000e42
2182
2183	#define REG_A5XX_VFD_PERFCTR_VFD_SEL_0 0x00000e50
2184
2185	#define REG_A5XX_VFD_PERFCTR_VFD_SEL_1 0x00000e51
2186
2187	#define REG_A5XX_VFD_PERFCTR_VFD_SEL_2 0x00000e52
2188
2189	#define REG_A5XX_VFD_PERFCTR_VFD_SEL_3 0x00000e53
2190
2191	#define REG_A5XX_VFD_PERFCTR_VFD_SEL_4 0x00000e54
2192
2193	#define REG_A5XX_VFD_PERFCTR_VFD_SEL_5 0x00000e55
2194
2195	#define REG_A5XX_VFD_PERFCTR_VFD_SEL_6 0x00000e56
2196
2197	#define REG_A5XX_VFD_PERFCTR_VFD_SEL_7 0x00000e57
2198
2199	#define REG_A5XX_VPC_DBG_ECO_CNTL 0x00000e60
2200	#define A5XX_VPC_DBG_ECO_CNTL_ALLFLATOPTDIS 0x00000400
2201
2202	#define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61
2203
2204	#define REG_A5XX_VPC_MODE_CNTL 0x00000e62
2205	#define A5XX_VPC_MODE_CNTL_BINNING_PASS 0x00000001
2206
2207	#define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64
2208
2209	#define REG_A5XX_VPC_PERFCTR_VPC_SEL_1 0x00000e65
2210
2211	#define REG_A5XX_VPC_PERFCTR_VPC_SEL_2 0x00000e66
2212
2213	#define REG_A5XX_VPC_PERFCTR_VPC_SEL_3 0x00000e67
2214
2215	#define REG_A5XX_UCHE_ADDR_MODE_CNTL 0x00000e80
2216
2217	#define REG_A5XX_UCHE_MODE_CNTL 0x00000e81
2218
2219	#define REG_A5XX_UCHE_SVM_CNTL 0x00000e82
2220
2221	#define REG_A5XX_UCHE_WRITE_THRU_BASE_LO 0x00000e87
2222
2223	#define REG_A5XX_UCHE_WRITE_THRU_BASE_HI 0x00000e88
2224
2225	#define REG_A5XX_UCHE_TRAP_BASE_LO 0x00000e89
2226
2227	#define REG_A5XX_UCHE_TRAP_BASE_HI 0x00000e8a
2228
2229	#define REG_A5XX_UCHE_GMEM_RANGE_MIN_LO 0x00000e8b
2230
2231	#define REG_A5XX_UCHE_GMEM_RANGE_MIN_HI 0x00000e8c
2232
2233	#define REG_A5XX_UCHE_GMEM_RANGE_MAX_LO 0x00000e8d
2234
2235	#define REG_A5XX_UCHE_GMEM_RANGE_MAX_HI 0x00000e8e
2236
2237	#define REG_A5XX_UCHE_DBG_ECO_CNTL_2 0x00000e8f
2238
2239	#define REG_A5XX_UCHE_DBG_ECO_CNTL 0x00000e90
2240
2241	#define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_LO 0x00000e91
2242
2243	#define REG_A5XX_UCHE_CACHE_INVALIDATE_MIN_HI 0x00000e92
2244
2245	#define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_LO 0x00000e93
2246
2247	#define REG_A5XX_UCHE_CACHE_INVALIDATE_MAX_HI 0x00000e94
2248
2249	#define REG_A5XX_UCHE_CACHE_INVALIDATE 0x00000e95
2250
2251	#define REG_A5XX_UCHE_CACHE_WAYS 0x00000e96
2252
2253	#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_0 0x00000ea0
2254
2255	#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_1 0x00000ea1
2256
2257	#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_2 0x00000ea2
2258
2259	#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_3 0x00000ea3
2260
2261	#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_4 0x00000ea4
2262
2263	#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_5 0x00000ea5
2264
2265	#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_6 0x00000ea6
2266
2267	#define REG_A5XX_UCHE_PERFCTR_UCHE_SEL_7 0x00000ea7
2268
2269	#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_0 0x00000ea8
2270
2271	#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_1 0x00000ea9
2272
2273	#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_2 0x00000eaa
2274
2275	#define REG_A5XX_UCHE_POWERCTR_UCHE_SEL_3 0x00000eab
2276
2277	#define REG_A5XX_UCHE_TRAP_LOG_LO 0x00000eb1
2278
2279	#define REG_A5XX_UCHE_TRAP_LOG_HI 0x00000eb2
2280
2281	#define REG_A5XX_SP_DBG_ECO_CNTL 0x00000ec0
2282
2283	#define REG_A5XX_SP_ADDR_MODE_CNTL 0x00000ec1
2284
2285	#define REG_A5XX_SP_MODE_CNTL 0x00000ec2
2286
2287	#define REG_A5XX_SP_PERFCTR_SP_SEL_0 0x00000ed0
2288
2289	#define REG_A5XX_SP_PERFCTR_SP_SEL_1 0x00000ed1
2290
2291	#define REG_A5XX_SP_PERFCTR_SP_SEL_2 0x00000ed2
2292
2293	#define REG_A5XX_SP_PERFCTR_SP_SEL_3 0x00000ed3
2294
2295	#define REG_A5XX_SP_PERFCTR_SP_SEL_4 0x00000ed4
2296
2297	#define REG_A5XX_SP_PERFCTR_SP_SEL_5 0x00000ed5
2298
2299	#define REG_A5XX_SP_PERFCTR_SP_SEL_6 0x00000ed6
2300
2301	#define REG_A5XX_SP_PERFCTR_SP_SEL_7 0x00000ed7
2302
2303	#define REG_A5XX_SP_PERFCTR_SP_SEL_8 0x00000ed8
2304
2305	#define REG_A5XX_SP_PERFCTR_SP_SEL_9 0x00000ed9
2306
2307	#define REG_A5XX_SP_PERFCTR_SP_SEL_10 0x00000eda
2308
2309	#define REG_A5XX_SP_PERFCTR_SP_SEL_11 0x00000edb
2310
2311	#define REG_A5XX_SP_POWERCTR_SP_SEL_0 0x00000edc
2312
2313	#define REG_A5XX_SP_POWERCTR_SP_SEL_1 0x00000edd
2314
2315	#define REG_A5XX_SP_POWERCTR_SP_SEL_2 0x00000ede
2316
2317	#define REG_A5XX_SP_POWERCTR_SP_SEL_3 0x00000edf
2318
2319	#define REG_A5XX_TPL1_ADDR_MODE_CNTL 0x00000f01
2320
2321	#define REG_A5XX_TPL1_MODE_CNTL 0x00000f02
2322
2323	#define REG_A5XX_TPL1_PERFCTR_TP_SEL_0 0x00000f10
2324
2325	#define REG_A5XX_TPL1_PERFCTR_TP_SEL_1 0x00000f11
2326
2327	#define REG_A5XX_TPL1_PERFCTR_TP_SEL_2 0x00000f12
2328
2329	#define REG_A5XX_TPL1_PERFCTR_TP_SEL_3 0x00000f13
2330
2331	#define REG_A5XX_TPL1_PERFCTR_TP_SEL_4 0x00000f14
2332
2333	#define REG_A5XX_TPL1_PERFCTR_TP_SEL_5 0x00000f15
2334
2335	#define REG_A5XX_TPL1_PERFCTR_TP_SEL_6 0x00000f16
2336
2337	#define REG_A5XX_TPL1_PERFCTR_TP_SEL_7 0x00000f17
2338
2339	#define REG_A5XX_TPL1_POWERCTR_TP_SEL_0 0x00000f18
2340
2341	#define REG_A5XX_TPL1_POWERCTR_TP_SEL_1 0x00000f19
2342
2343	#define REG_A5XX_TPL1_POWERCTR_TP_SEL_2 0x00000f1a
2344
2345	#define REG_A5XX_TPL1_POWERCTR_TP_SEL_3 0x00000f1b
2346
2347	#define REG_A5XX_VBIF_VERSION 0x00003000
2348
2349	#define REG_A5XX_VBIF_CLKON 0x00003001
2350
2351	#define REG_A5XX_VBIF_ABIT_SORT 0x00003028
2352
2353	#define REG_A5XX_VBIF_ABIT_SORT_CONF 0x00003029
2354
2355	#define REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
2356
2357	#define REG_A5XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
2358
2359	#define REG_A5XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
2360
2361	#define REG_A5XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
2362
2363	#define REG_A5XX_VBIF_XIN_HALT_CTRL0 0x00003080
2364
2365	#define REG_A5XX_VBIF_XIN_HALT_CTRL1 0x00003081
2366
2367	#define REG_A5XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084
2368
2369	#define REG_A5XX_VBIF_TEST_BUS1_CTRL0 0x00003085
2370
2371	#define REG_A5XX_VBIF_TEST_BUS1_CTRL1 0x00003086
2372
2373	#define REG_A5XX_VBIF_TEST_BUS2_CTRL0 0x00003087
2374
2375	#define REG_A5XX_VBIF_TEST_BUS2_CTRL1 0x00003088
2376
2377	#define REG_A5XX_VBIF_TEST_BUS_OUT 0x0000308c
2378
2379	#define REG_A5XX_VBIF_PERF_CNT_EN0 0x000030c0
2380
2381	#define REG_A5XX_VBIF_PERF_CNT_EN1 0x000030c1
2382
2383	#define REG_A5XX_VBIF_PERF_CNT_EN2 0x000030c2
2384
2385	#define REG_A5XX_VBIF_PERF_CNT_EN3 0x000030c3
2386
2387	#define REG_A5XX_VBIF_PERF_CNT_CLR0 0x000030c8
2388
2389	#define REG_A5XX_VBIF_PERF_CNT_CLR1 0x000030c9
2390
2391	#define REG_A5XX_VBIF_PERF_CNT_CLR2 0x000030ca
2392
2393	#define REG_A5XX_VBIF_PERF_CNT_CLR3 0x000030cb
2394
2395	#define REG_A5XX_VBIF_PERF_CNT_SEL0 0x000030d0
2396
2397	#define REG_A5XX_VBIF_PERF_CNT_SEL1 0x000030d1
2398
2399	#define REG_A5XX_VBIF_PERF_CNT_SEL2 0x000030d2
2400
2401	#define REG_A5XX_VBIF_PERF_CNT_SEL3 0x000030d3
2402
2403	#define REG_A5XX_VBIF_PERF_CNT_LOW0 0x000030d8
2404
2405	#define REG_A5XX_VBIF_PERF_CNT_LOW1 0x000030d9
2406
2407	#define REG_A5XX_VBIF_PERF_CNT_LOW2 0x000030da
2408
2409	#define REG_A5XX_VBIF_PERF_CNT_LOW3 0x000030db
2410
2411	#define REG_A5XX_VBIF_PERF_CNT_HIGH0 0x000030e0
2412
2413	#define REG_A5XX_VBIF_PERF_CNT_HIGH1 0x000030e1
2414
2415	#define REG_A5XX_VBIF_PERF_CNT_HIGH2 0x000030e2
2416
2417	#define REG_A5XX_VBIF_PERF_CNT_HIGH3 0x000030e3
2418
2419	#define REG_A5XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
2420
2421	#define REG_A5XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
2422
2423	#define REG_A5XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
2424
2425	#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110
2426
2427	#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111
2428
2429	#define REG_A5XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112
2430
2431	#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118
2432
2433	#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119
2434
2435	#define REG_A5XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a
2436
2437	#define REG_A5XX_GPMU_INST_RAM_BASE 0x00008800
2438
2439	#define REG_A5XX_GPMU_DATA_RAM_BASE 0x00009800
2440
2441	#define REG_A5XX_SP_POWER_COUNTER_0_LO 0x0000a840
2442
2443	#define REG_A5XX_SP_POWER_COUNTER_0_HI 0x0000a841
2444
2445	#define REG_A5XX_SP_POWER_COUNTER_1_LO 0x0000a842
2446
2447	#define REG_A5XX_SP_POWER_COUNTER_1_HI 0x0000a843
2448
2449	#define REG_A5XX_SP_POWER_COUNTER_2_LO 0x0000a844
2450
2451	#define REG_A5XX_SP_POWER_COUNTER_2_HI 0x0000a845
2452
2453	#define REG_A5XX_SP_POWER_COUNTER_3_LO 0x0000a846
2454
2455	#define REG_A5XX_SP_POWER_COUNTER_3_HI 0x0000a847
2456
2457	#define REG_A5XX_TP_POWER_COUNTER_0_LO 0x0000a848
2458
2459	#define REG_A5XX_TP_POWER_COUNTER_0_HI 0x0000a849
2460
2461	#define REG_A5XX_TP_POWER_COUNTER_1_LO 0x0000a84a
2462
2463	#define REG_A5XX_TP_POWER_COUNTER_1_HI 0x0000a84b
2464
2465	#define REG_A5XX_TP_POWER_COUNTER_2_LO 0x0000a84c
2466
2467	#define REG_A5XX_TP_POWER_COUNTER_2_HI 0x0000a84d
2468
2469	#define REG_A5XX_TP_POWER_COUNTER_3_LO 0x0000a84e
2470
2471	#define REG_A5XX_TP_POWER_COUNTER_3_HI 0x0000a84f
2472
2473	#define REG_A5XX_RB_POWER_COUNTER_0_LO 0x0000a850
2474
2475	#define REG_A5XX_RB_POWER_COUNTER_0_HI 0x0000a851
2476
2477	#define REG_A5XX_RB_POWER_COUNTER_1_LO 0x0000a852
2478
2479	#define REG_A5XX_RB_POWER_COUNTER_1_HI 0x0000a853
2480
2481	#define REG_A5XX_RB_POWER_COUNTER_2_LO 0x0000a854
2482
2483	#define REG_A5XX_RB_POWER_COUNTER_2_HI 0x0000a855
2484
2485	#define REG_A5XX_RB_POWER_COUNTER_3_LO 0x0000a856
2486
2487	#define REG_A5XX_RB_POWER_COUNTER_3_HI 0x0000a857
2488
2489	#define REG_A5XX_CCU_POWER_COUNTER_0_LO 0x0000a858
2490
2491	#define REG_A5XX_CCU_POWER_COUNTER_0_HI 0x0000a859
2492
2493	#define REG_A5XX_CCU_POWER_COUNTER_1_LO 0x0000a85a
2494
2495	#define REG_A5XX_CCU_POWER_COUNTER_1_HI 0x0000a85b
2496
2497	#define REG_A5XX_UCHE_POWER_COUNTER_0_LO 0x0000a85c
2498
2499	#define REG_A5XX_UCHE_POWER_COUNTER_0_HI 0x0000a85d
2500
2501	#define REG_A5XX_UCHE_POWER_COUNTER_1_LO 0x0000a85e
2502
2503	#define REG_A5XX_UCHE_POWER_COUNTER_1_HI 0x0000a85f
2504
2505	#define REG_A5XX_UCHE_POWER_COUNTER_2_LO 0x0000a860
2506
2507	#define REG_A5XX_UCHE_POWER_COUNTER_2_HI 0x0000a861
2508
2509	#define REG_A5XX_UCHE_POWER_COUNTER_3_LO 0x0000a862
2510
2511	#define REG_A5XX_UCHE_POWER_COUNTER_3_HI 0x0000a863
2512
2513	#define REG_A5XX_CP_POWER_COUNTER_0_LO 0x0000a864
2514
2515	#define REG_A5XX_CP_POWER_COUNTER_0_HI 0x0000a865
2516
2517	#define REG_A5XX_CP_POWER_COUNTER_1_LO 0x0000a866
2518
2519	#define REG_A5XX_CP_POWER_COUNTER_1_HI 0x0000a867
2520
2521	#define REG_A5XX_CP_POWER_COUNTER_2_LO 0x0000a868
2522
2523	#define REG_A5XX_CP_POWER_COUNTER_2_HI 0x0000a869
2524
2525	#define REG_A5XX_CP_POWER_COUNTER_3_LO 0x0000a86a
2526
2527	#define REG_A5XX_CP_POWER_COUNTER_3_HI 0x0000a86b
2528
2529	#define REG_A5XX_GPMU_POWER_COUNTER_0_LO 0x0000a86c
2530
2531	#define REG_A5XX_GPMU_POWER_COUNTER_0_HI 0x0000a86d
2532
2533	#define REG_A5XX_GPMU_POWER_COUNTER_1_LO 0x0000a86e
2534
2535	#define REG_A5XX_GPMU_POWER_COUNTER_1_HI 0x0000a86f
2536
2537	#define REG_A5XX_GPMU_POWER_COUNTER_2_LO 0x0000a870
2538
2539	#define REG_A5XX_GPMU_POWER_COUNTER_2_HI 0x0000a871
2540
2541	#define REG_A5XX_GPMU_POWER_COUNTER_3_LO 0x0000a872
2542
2543	#define REG_A5XX_GPMU_POWER_COUNTER_3_HI 0x0000a873
2544
2545	#define REG_A5XX_GPMU_POWER_COUNTER_4_LO 0x0000a874
2546
2547	#define REG_A5XX_GPMU_POWER_COUNTER_4_HI 0x0000a875
2548
2549	#define REG_A5XX_GPMU_POWER_COUNTER_5_LO 0x0000a876
2550
2551	#define REG_A5XX_GPMU_POWER_COUNTER_5_HI 0x0000a877
2552
2553	#define REG_A5XX_GPMU_POWER_COUNTER_ENABLE 0x0000a878
2554
2555	#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_LO 0x0000a879
2556
2557	#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_HI 0x0000a87a
2558
2559	#define REG_A5XX_GPMU_ALWAYS_ON_COUNTER_RESET 0x0000a87b
2560
2561	#define REG_A5XX_GPMU_POWER_COUNTER_SELECT_0 0x0000a87c
2562
2563	#define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 0x0000a87d
2564
2565	#define REG_A5XX_GPMU_GPMU_SP_CLOCK_CONTROL 0x0000a880
2566
2567	#define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881
2568
2569	#define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886
2570
2571	#define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887
2572
2573	#define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b
2574	#define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000
2575
2576	#define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d
2577	#define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000
2578
2579	#define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891
2580
2581	#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892
2582
2583	#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893
2584
2585	#define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894
2586
2587	#define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3
2588
2589	#define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL 0x0000a8a8
2590
2591	#define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1
2592
2593	#define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6
2594
2595	#define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8
2596
2597	#define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0
2598
2599	#define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1
2600
2601	#define REG_A5XX_GPMU_TEMP_SENSOR_ID 0x0000ac00
2602
2603	#define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG 0x0000ac01
2604
2605	#define REG_A5XX_GPMU_TEMP_VAL 0x0000ac02
2606
2607	#define REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD 0x0000ac03
2608
2609	#define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_STATUS 0x0000ac05
2610
2611	#define REG_A5XX_GPMU_TEMP_THRESHOLD_INTR_EN_MASK 0x0000ac06
2612
2613	#define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_0_1 0x0000ac40
2614
2615	#define REG_A5XX_GPMU_LEAKAGE_TEMP_COEFF_2_3 0x0000ac41
2616
2617	#define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_0_1 0x0000ac42
2618
2619	#define REG_A5XX_GPMU_LEAKAGE_VTG_COEFF_2_3 0x0000ac43
2620
2621	#define REG_A5XX_GPMU_BASE_LEAKAGE 0x0000ac46
2622
2623	#define REG_A5XX_GPMU_GPMU_VOLTAGE 0x0000ac60
2624
2625	#define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_STATUS 0x0000ac61
2626
2627	#define REG_A5XX_GPMU_GPMU_VOLTAGE_INTR_EN_MASK 0x0000ac62
2628
2629	#define REG_A5XX_GPMU_GPMU_PWR_THRESHOLD 0x0000ac80
2630
2631	#define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_CTRL 0x0000acc4
2632
2633	#define REG_A5XX_GPMU_GPMU_LLM_GLM_SLEEP_STATUS 0x0000acc5
2634
2635	#define REG_A5XX_GDPM_CONFIG1 0x0000b80c
2636
2637	#define REG_A5XX_GDPM_CONFIG2 0x0000b80d
2638
2639	#define REG_A5XX_GDPM_INT_EN 0x0000b80f
2640
2641	#define REG_A5XX_GDPM_INT_MASK 0x0000b811
2642
2643	#define REG_A5XX_GPMU_BEC_ENABLE 0x0000b9a0
2644
2645	#define REG_A5XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000c41a
2646
2647	#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000c41d
2648
2649	#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000c41f
2650
2651	#define REG_A5XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x0000c421
2652
2653	#define REG_A5XX_GPU_CS_ENABLE_REG 0x0000c520
2654
2655	#define REG_A5XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x0000c557
2656
2657	#define REG_A5XX_GRAS_CL_CNTL 0x0000e000
2658	#define A5XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040
2659
2660	#define REG_A5XX_GRAS_VS_CL_CNTL 0x0000e001
2661	#define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff
2662	#define A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0
2663	static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val)
2664	{
2665	return ((val) << A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK;
2666	}
2667	#define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00
2668	#define A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8
2669	static inline uint32_t A5XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val)
2670	{
2671	return ((val) << A5XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A5XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK;
2672	}
2673
2674	#define REG_A5XX_UNKNOWN_E004 0x0000e004
2675
2676	#define REG_A5XX_GRAS_CNTL 0x0000e005
2677	#define A5XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001
2678	#define A5XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002
2679	#define A5XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004
2680	#define A5XX_GRAS_CNTL_IJ_LINEAR_PIXEL 0x00000008
2681	#define A5XX_GRAS_CNTL_IJ_LINEAR_CENTROID 0x00000010
2682	#define A5XX_GRAS_CNTL_IJ_LINEAR_SAMPLE 0x00000020
2683	#define A5XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0
2684	#define A5XX_GRAS_CNTL_COORD_MASK__SHIFT 6
2685	static inline uint32_t A5XX_GRAS_CNTL_COORD_MASK(uint32_t val)
2686	{
2687	return ((val) << A5XX_GRAS_CNTL_COORD_MASK__SHIFT) & A5XX_GRAS_CNTL_COORD_MASK__MASK;
2688	}
2689
2690	#define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006
2691	#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff
2692	#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0
2693	static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val)
2694	{
2695	return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK;
2696	}
2697	#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x000ffc00
2698	#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10
2699	static inline uint32_t A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val)
2700	{
2701	return ((val) << A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK;
2702	}
2703
2704	#define REG_A5XX_GRAS_CL_VPORT_XOFFSET_0 0x0000e010
2705	#define A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK 0xffffffff
2706	#define A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT 0
2707	static inline uint32_t A5XX_GRAS_CL_VPORT_XOFFSET_0(float val)
2708	{
2709	return ((fui(val)) << A5XX_GRAS_CL_VPORT_XOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_XOFFSET_0__MASK;
2710	}
2711
2712	#define REG_A5XX_GRAS_CL_VPORT_XSCALE_0 0x0000e011
2713	#define A5XX_GRAS_CL_VPORT_XSCALE_0__MASK 0xffffffff
2714	#define A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT 0
2715	static inline uint32_t A5XX_GRAS_CL_VPORT_XSCALE_0(float val)
2716	{
2717	return ((fui(val)) << A5XX_GRAS_CL_VPORT_XSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_XSCALE_0__MASK;
2718	}
2719
2720	#define REG_A5XX_GRAS_CL_VPORT_YOFFSET_0 0x0000e012
2721	#define A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK 0xffffffff
2722	#define A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT 0
2723	static inline uint32_t A5XX_GRAS_CL_VPORT_YOFFSET_0(float val)
2724	{
2725	return ((fui(val)) << A5XX_GRAS_CL_VPORT_YOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_YOFFSET_0__MASK;
2726	}
2727
2728	#define REG_A5XX_GRAS_CL_VPORT_YSCALE_0 0x0000e013
2729	#define A5XX_GRAS_CL_VPORT_YSCALE_0__MASK 0xffffffff
2730	#define A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT 0
2731	static inline uint32_t A5XX_GRAS_CL_VPORT_YSCALE_0(float val)
2732	{
2733	return ((fui(val)) << A5XX_GRAS_CL_VPORT_YSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_YSCALE_0__MASK;
2734	}
2735
2736	#define REG_A5XX_GRAS_CL_VPORT_ZOFFSET_0 0x0000e014
2737	#define A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK 0xffffffff
2738	#define A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT 0
2739	static inline uint32_t A5XX_GRAS_CL_VPORT_ZOFFSET_0(float val)
2740	{
2741	return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZOFFSET_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZOFFSET_0__MASK;
2742	}
2743
2744	#define REG_A5XX_GRAS_CL_VPORT_ZSCALE_0 0x0000e015
2745	#define A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK 0xffffffff
2746	#define A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT 0
2747	static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val)
2748	{
2749	return ((fui(val)) << A5XX_GRAS_CL_VPORT_ZSCALE_0__SHIFT) & A5XX_GRAS_CL_VPORT_ZSCALE_0__MASK;
2750	}
2751
2752	#define REG_A5XX_GRAS_SU_CNTL 0x0000e090
2753	#define A5XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001
2754	#define A5XX_GRAS_SU_CNTL_CULL_BACK 0x00000002
2755	#define A5XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
2756	#define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
2757	#define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
2758	static inline uint32_t A5XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val)
2759	{
2760	return ((((int32_t)(val * 4.0))) << A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK;
2761	}
2762	#define A5XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800
2763	#define A5XX_GRAS_SU_CNTL_LINE_MODE__MASK 0x00002000
2764	#define A5XX_GRAS_SU_CNTL_LINE_MODE__SHIFT 13
2765	static inline uint32_t A5XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val)
2766	{
2767	return ((val) << A5XX_GRAS_SU_CNTL_LINE_MODE__SHIFT) & A5XX_GRAS_SU_CNTL_LINE_MODE__MASK;
2768	}
2769
2770	#define REG_A5XX_GRAS_SU_POINT_MINMAX 0x0000e091
2771	#define A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
2772	#define A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
2773	static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MIN(float val)
2774	{
2775	return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
2776	}
2777	#define A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
2778	#define A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
2779	static inline uint32_t A5XX_GRAS_SU_POINT_MINMAX_MAX(float val)
2780	{
2781	return ((((uint32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A5XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
2782	}
2783
2784	#define REG_A5XX_GRAS_SU_POINT_SIZE 0x0000e092
2785	#define A5XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
2786	#define A5XX_GRAS_SU_POINT_SIZE__SHIFT 0
2787	static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val)
2788	{
2789	return ((((int32_t)(val * 16.0))) << A5XX_GRAS_SU_POINT_SIZE__SHIFT) & A5XX_GRAS_SU_POINT_SIZE__MASK;
2790	}
2791
2792	#define REG_A5XX_GRAS_SU_LAYERED 0x0000e093
2793
2794	#define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094
2795	#define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
2796	#define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1 0x00000002
2797
2798	#define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000e095
2799	#define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
2800	#define A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0
2801	static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_SCALE(float val)
2802	{
2803	return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK;
2804	}
2805
2806	#define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000e096
2807	#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
2808	#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
2809	static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
2810	{
2811	return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
2812	}
2813
2814	#define REG_A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x0000e097
2815	#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff
2816	#define A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0
2817	static inline uint32_t A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val)
2818	{
2819	return ((fui(val)) << A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A5XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK;
2820	}
2821
2822	#define REG_A5XX_GRAS_SU_DEPTH_BUFFER_INFO 0x0000e098
2823	#define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
2824	#define A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
2825	static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
2826	{
2827	return ((val) << A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
2828	}
2829
2830	#define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x0000e099
2831
2832	#define REG_A5XX_GRAS_SC_CNTL 0x0000e0a0
2833	#define A5XX_GRAS_SC_CNTL_BINNING_PASS 0x00000001
2834	#define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED 0x00008000
2835
2836	#define REG_A5XX_GRAS_SC_BIN_CNTL 0x0000e0a1
2837
2838	#define REG_A5XX_GRAS_SC_RAS_MSAA_CNTL 0x0000e0a2
2839	#define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
2840	#define A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
2841	static inline uint32_t A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2842	{
2843	return ((val) << A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES__MASK;
2844	}
2845
2846	#define REG_A5XX_GRAS_SC_DEST_MSAA_CNTL 0x0000e0a3
2847	#define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
2848	#define A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
2849	static inline uint32_t A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
2850	{
2851	return ((val) << A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES__MASK;
2852	}
2853	#define A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
2854
2855	#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL 0x0000e0a4
2856
2857	#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0 0x0000e0aa
2858	#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
2859	#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK 0x00007fff
2860	#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT 0
2861	static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X(uint32_t val)
2862	{
2863	return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_X__MASK;
2864	}
2865	#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK 0x7fff0000
2866	#define A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT 16
2867	static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y(uint32_t val)
2868	{
2869	return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0_Y__MASK;
2870	}
2871
2872	#define REG_A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0 0x0000e0ab
2873	#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
2874	#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK 0x00007fff
2875	#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT 0
2876	static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X(uint32_t val)
2877	{
2878	return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_X__MASK;
2879	}
2880	#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK 0x7fff0000
2881	#define A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT 16
2882	static inline uint32_t A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y(uint32_t val)
2883	{
2884	return ((val) << A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_SCREEN_SCISSOR_BR_0_Y__MASK;
2885	}
2886
2887	#define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0 0x0000e0ca
2888	#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_WINDOW_OFFSET_DISABLE 0x80000000
2889	#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK 0x00007fff
2890	#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT 0
2891	static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X(uint32_t val)
2892	{
2893	return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_X__MASK;
2894	}
2895	#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK 0x7fff0000
2896	#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT 16
2897	static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y(uint32_t val)
2898	{
2899	return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0_Y__MASK;
2900	}
2901
2902	#define REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0 0x0000e0cb
2903	#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_WINDOW_OFFSET_DISABLE 0x80000000
2904	#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK 0x00007fff
2905	#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT 0
2906	static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X(uint32_t val)
2907	{
2908	return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_X__MASK;
2909	}
2910	#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK 0x7fff0000
2911	#define A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT 16
2912	static inline uint32_t A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y(uint32_t val)
2913	{
2914	return ((val) << A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__SHIFT) & A5XX_GRAS_SC_VIEWPORT_SCISSOR_BR_0_Y__MASK;
2915	}
2916
2917	#define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL 0x0000e0ea
2918	#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
2919	#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
2920	#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
2921	static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
2922	{
2923	return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
2924	}
2925	#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
2926	#define A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
2927	static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
2928	{
2929	return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
2930	}
2931
2932	#define REG_A5XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000e0eb
2933	#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
2934	#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
2935	#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
2936	static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
2937	{
2938	return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
2939	}
2940	#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
2941	#define A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
2942	static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
2943	{
2944	return ((val) << A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
2945	}
2946
2947	#define REG_A5XX_GRAS_LRZ_CNTL 0x0000e100
2948	#define A5XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
2949	#define A5XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
2950	#define A5XX_GRAS_LRZ_CNTL_GREATER 0x00000004
2951
2952	#define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO 0x0000e101
2953
2954	#define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI 0x0000e102
2955
2956	#define REG_A5XX_GRAS_LRZ_BUFFER_PITCH 0x0000e103
2957	#define A5XX_GRAS_LRZ_BUFFER_PITCH__MASK 0xffffffff
2958	#define A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT 0
2959	static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val)
2960	{
2961	assert(!(val & 0x1f));
2962	return (((val >> 5)) << A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT) & A5XX_GRAS_LRZ_BUFFER_PITCH__MASK;
2963	}
2964
2965	#define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104
2966
2967	#define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI 0x0000e105
2968
2969	#define REG_A5XX_RB_CNTL 0x0000e140
2970	#define A5XX_RB_CNTL_WIDTH__MASK 0x000000ff
2971	#define A5XX_RB_CNTL_WIDTH__SHIFT 0
2972	static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val)
2973	{
2974	assert(!(val & 0x1f));
2975	return (((val >> 5)) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK;
2976	}
2977	#define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00
2978	#define A5XX_RB_CNTL_HEIGHT__SHIFT 9
2979	static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val)
2980	{
2981	assert(!(val & 0x1f));
2982	return (((val >> 5)) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK;
2983	}
2984	#define A5XX_RB_CNTL_BYPASS 0x00020000
2985
2986	#define REG_A5XX_RB_RENDER_CNTL 0x0000e141
2987	#define A5XX_RB_RENDER_CNTL_BINNING_PASS 0x00000001
2988	#define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED 0x00000040
2989	#define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE 0x00000080
2990	#define A5XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
2991	#define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2 0x00008000
2992	#define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
2993	#define A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16
2994	static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val)
2995	{
2996	return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK;
2997	}
2998	#define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK 0xff000000
2999	#define A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT 24
3000	static inline uint32_t A5XX_RB_RENDER_CNTL_FLAG_MRTS2(uint32_t val)
3001	{
3002	return ((val) << A5XX_RB_RENDER_CNTL_FLAG_MRTS2__SHIFT) & A5XX_RB_RENDER_CNTL_FLAG_MRTS2__MASK;
3003	}
3004
3005	#define REG_A5XX_RB_RAS_MSAA_CNTL 0x0000e142
3006	#define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
3007	#define A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
3008	static inline uint32_t A5XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3009	{
3010	return ((val) << A5XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK;
3011	}
3012
3013	#define REG_A5XX_RB_DEST_MSAA_CNTL 0x0000e143
3014	#define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
3015	#define A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
3016	static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
3017	{
3018	return ((val) << A5XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK;
3019	}
3020	#define A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
3021
3022	#define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144
3023	#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001
3024	#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002
3025	#define A5XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004
3026	#define A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL 0x00000008
3027	#define A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID 0x00000010
3028	#define A5XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE 0x00000020
3029	#define A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0
3030	#define A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6
3031	static inline uint32_t A5XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val)
3032	{
3033	return ((val) << A5XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A5XX_RB_RENDER_CONTROL0_COORD_MASK__MASK;
3034	}
3035
3036	#define REG_A5XX_RB_RENDER_CONTROL1 0x0000e145
3037	#define A5XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001
3038	#define A5XX_RB_RENDER_CONTROL1_FACENESS 0x00000002
3039	#define A5XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000004
3040
3041	#define REG_A5XX_RB_FS_OUTPUT_CNTL 0x0000e146
3042	#define A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
3043	#define A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT 0
3044	static inline uint32_t A5XX_RB_FS_OUTPUT_CNTL_MRT(uint32_t val)
3045	{
3046	return ((val) << A5XX_RB_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_RB_FS_OUTPUT_CNTL_MRT__MASK;
3047	}
3048	#define A5XX_RB_FS_OUTPUT_CNTL_FRAG_WRITES_Z 0x00000020
3049
3050	#define REG_A5XX_RB_RENDER_COMPONENTS 0x0000e147
3051	#define A5XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f
3052	#define A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0
3053	static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT0(uint32_t val)
3054	{
3055	return ((val) << A5XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT0__MASK;
3056	}
3057	#define A5XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0
3058	#define A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4
3059	static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT1(uint32_t val)
3060	{
3061	return ((val) << A5XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT1__MASK;
3062	}
3063	#define A5XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00
3064	#define A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8
3065	static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT2(uint32_t val)
3066	{
3067	return ((val) << A5XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT2__MASK;
3068	}
3069	#define A5XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000
3070	#define A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12
3071	static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT3(uint32_t val)
3072	{
3073	return ((val) << A5XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT3__MASK;
3074	}
3075	#define A5XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000
3076	#define A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16
3077	static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT4(uint32_t val)
3078	{
3079	return ((val) << A5XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT4__MASK;
3080	}
3081	#define A5XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000
3082	#define A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20
3083	static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT5(uint32_t val)
3084	{
3085	return ((val) << A5XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT5__MASK;
3086	}
3087	#define A5XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000
3088	#define A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24
3089	static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT6(uint32_t val)
3090	{
3091	return ((val) << A5XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT6__MASK;
3092	}
3093	#define A5XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000
3094	#define A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28
3095	static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val)
3096	{
3097	return ((val) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK;
3098	}
3099
3100	#define REG_A5XX_RB_MRT(i0) (0x0000e150 + 0x7*(i0))
3101
3102	static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; }
3103	#define A5XX_RB_MRT_CONTROL_BLEND 0x00000001
3104	#define A5XX_RB_MRT_CONTROL_BLEND2 0x00000002
3105	#define A5XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004
3106	#define A5XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078
3107	#define A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3
3108	static inline uint32_t A5XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
3109	{
3110	return ((val) << A5XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A5XX_RB_MRT_CONTROL_ROP_CODE__MASK;
3111	}
3112	#define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780
3113	#define A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7
3114	static inline uint32_t A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
3115	{
3116	return ((val) << A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A5XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
3117	}
3118
3119	static inline uint32_t REG_A5XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x0000e151 + 0x7*i0; }
3120	#define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
3121	#define A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
3122	static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
3123	{
3124	return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
3125	}
3126	#define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
3127	#define A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
3128	static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3129	{
3130	return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
3131	}
3132	#define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
3133	#define A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
3134	static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
3135	{
3136	return ((val) << A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
3137	}
3138	#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
3139	#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
3140	static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
3141	{
3142	return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
3143	}
3144	#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
3145	#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
3146	static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
3147	{
3148	return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
3149	}
3150	#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
3151	#define A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
3152	static inline uint32_t A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
3153	{
3154	return ((val) << A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A5XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
3155	}
3156
3157	static inline uint32_t REG_A5XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x0000e152 + 0x7*i0; }
3158	#define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff
3159	#define A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
3160	static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
3161	{
3162	return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
3163	}
3164	#define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300
3165	#define A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8
3166	static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a5xx_tile_mode val)
3167	{
3168	return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
3169	}
3170	#define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK 0x00001800
3171	#define A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT 11
3172	static inline uint32_t A5XX_RB_MRT_BUF_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
3173	{
3174	return ((val) << A5XX_RB_MRT_BUF_INFO_DITHER_MODE__SHIFT) & A5XX_RB_MRT_BUF_INFO_DITHER_MODE__MASK;
3175	}
3176	#define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000
3177	#define A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13
3178	static inline uint32_t A5XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
3179	{
3180	return ((val) << A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
3181	}
3182	#define A5XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00008000
3183
3184	static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + 0x7*i0; }
3185	#define A5XX_RB_MRT_PITCH__MASK 0xffffffff
3186	#define A5XX_RB_MRT_PITCH__SHIFT 0
3187	static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val)
3188	{
3189	assert(!(val & 0x3f));
3190	return (((val >> 6)) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK;
3191	}
3192
3193	static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; }
3194	#define A5XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff
3195	#define A5XX_RB_MRT_ARRAY_PITCH__SHIFT 0
3196	static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val)
3197	{
3198	assert(!(val & 0x3f));
3199	return (((val >> 6)) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK;
3200	}
3201
3202	static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; }
3203
3204	static inline uint32_t REG_A5XX_RB_MRT_BASE_HI(uint32_t i0) { return 0x0000e156 + 0x7*i0; }
3205
3206	#define REG_A5XX_RB_BLEND_RED 0x0000e1a0
3207	#define A5XX_RB_BLEND_RED_UINT__MASK 0x000000ff
3208	#define A5XX_RB_BLEND_RED_UINT__SHIFT 0
3209	static inline uint32_t A5XX_RB_BLEND_RED_UINT(uint32_t val)
3210	{
3211	return ((val) << A5XX_RB_BLEND_RED_UINT__SHIFT) & A5XX_RB_BLEND_RED_UINT__MASK;
3212	}
3213	#define A5XX_RB_BLEND_RED_SINT__MASK 0x0000ff00
3214	#define A5XX_RB_BLEND_RED_SINT__SHIFT 8
3215	static inline uint32_t A5XX_RB_BLEND_RED_SINT(uint32_t val)
3216	{
3217	return ((val) << A5XX_RB_BLEND_RED_SINT__SHIFT) & A5XX_RB_BLEND_RED_SINT__MASK;
3218	}
3219	#define A5XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
3220	#define A5XX_RB_BLEND_RED_FLOAT__SHIFT 16
3221	static inline uint32_t A5XX_RB_BLEND_RED_FLOAT(float val)
3222	{
3223	return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_RED_FLOAT__SHIFT) & A5XX_RB_BLEND_RED_FLOAT__MASK;
3224	}
3225
3226	#define REG_A5XX_RB_BLEND_RED_F32 0x0000e1a1
3227	#define A5XX_RB_BLEND_RED_F32__MASK 0xffffffff
3228	#define A5XX_RB_BLEND_RED_F32__SHIFT 0
3229	static inline uint32_t A5XX_RB_BLEND_RED_F32(float val)
3230	{
3231	return ((fui(val)) << A5XX_RB_BLEND_RED_F32__SHIFT) & A5XX_RB_BLEND_RED_F32__MASK;
3232	}
3233
3234	#define REG_A5XX_RB_BLEND_GREEN 0x0000e1a2
3235	#define A5XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
3236	#define A5XX_RB_BLEND_GREEN_UINT__SHIFT 0
3237	static inline uint32_t A5XX_RB_BLEND_GREEN_UINT(uint32_t val)
3238	{
3239	return ((val) << A5XX_RB_BLEND_GREEN_UINT__SHIFT) & A5XX_RB_BLEND_GREEN_UINT__MASK;
3240	}
3241	#define A5XX_RB_BLEND_GREEN_SINT__MASK 0x0000ff00
3242	#define A5XX_RB_BLEND_GREEN_SINT__SHIFT 8
3243	static inline uint32_t A5XX_RB_BLEND_GREEN_SINT(uint32_t val)
3244	{
3245	return ((val) << A5XX_RB_BLEND_GREEN_SINT__SHIFT) & A5XX_RB_BLEND_GREEN_SINT__MASK;
3246	}
3247	#define A5XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
3248	#define A5XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
3249	static inline uint32_t A5XX_RB_BLEND_GREEN_FLOAT(float val)
3250	{
3251	return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A5XX_RB_BLEND_GREEN_FLOAT__MASK;
3252	}
3253
3254	#define REG_A5XX_RB_BLEND_GREEN_F32 0x0000e1a3
3255	#define A5XX_RB_BLEND_GREEN_F32__MASK 0xffffffff
3256	#define A5XX_RB_BLEND_GREEN_F32__SHIFT 0
3257	static inline uint32_t A5XX_RB_BLEND_GREEN_F32(float val)
3258	{
3259	return ((fui(val)) << A5XX_RB_BLEND_GREEN_F32__SHIFT) & A5XX_RB_BLEND_GREEN_F32__MASK;
3260	}
3261
3262	#define REG_A5XX_RB_BLEND_BLUE 0x0000e1a4
3263	#define A5XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
3264	#define A5XX_RB_BLEND_BLUE_UINT__SHIFT 0
3265	static inline uint32_t A5XX_RB_BLEND_BLUE_UINT(uint32_t val)
3266	{
3267	return ((val) << A5XX_RB_BLEND_BLUE_UINT__SHIFT) & A5XX_RB_BLEND_BLUE_UINT__MASK;
3268	}
3269	#define A5XX_RB_BLEND_BLUE_SINT__MASK 0x0000ff00
3270	#define A5XX_RB_BLEND_BLUE_SINT__SHIFT 8
3271	static inline uint32_t A5XX_RB_BLEND_BLUE_SINT(uint32_t val)
3272	{
3273	return ((val) << A5XX_RB_BLEND_BLUE_SINT__SHIFT) & A5XX_RB_BLEND_BLUE_SINT__MASK;
3274	}
3275	#define A5XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
3276	#define A5XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
3277	static inline uint32_t A5XX_RB_BLEND_BLUE_FLOAT(float val)
3278	{
3279	return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A5XX_RB_BLEND_BLUE_FLOAT__MASK;
3280	}
3281
3282	#define REG_A5XX_RB_BLEND_BLUE_F32 0x0000e1a5
3283	#define A5XX_RB_BLEND_BLUE_F32__MASK 0xffffffff
3284	#define A5XX_RB_BLEND_BLUE_F32__SHIFT 0
3285	static inline uint32_t A5XX_RB_BLEND_BLUE_F32(float val)
3286	{
3287	return ((fui(val)) << A5XX_RB_BLEND_BLUE_F32__SHIFT) & A5XX_RB_BLEND_BLUE_F32__MASK;
3288	}
3289
3290	#define REG_A5XX_RB_BLEND_ALPHA 0x0000e1a6
3291	#define A5XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
3292	#define A5XX_RB_BLEND_ALPHA_UINT__SHIFT 0
3293	static inline uint32_t A5XX_RB_BLEND_ALPHA_UINT(uint32_t val)
3294	{
3295	return ((val) << A5XX_RB_BLEND_ALPHA_UINT__SHIFT) & A5XX_RB_BLEND_ALPHA_UINT__MASK;
3296	}
3297	#define A5XX_RB_BLEND_ALPHA_SINT__MASK 0x0000ff00
3298	#define A5XX_RB_BLEND_ALPHA_SINT__SHIFT 8
3299	static inline uint32_t A5XX_RB_BLEND_ALPHA_SINT(uint32_t val)
3300	{
3301	return ((val) << A5XX_RB_BLEND_ALPHA_SINT__SHIFT) & A5XX_RB_BLEND_ALPHA_SINT__MASK;
3302	}
3303	#define A5XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
3304	#define A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
3305	static inline uint32_t A5XX_RB_BLEND_ALPHA_FLOAT(float val)
3306	{
3307	return ((_mesa_float_to_half(val)) << A5XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A5XX_RB_BLEND_ALPHA_FLOAT__MASK;
3308	}
3309
3310	#define REG_A5XX_RB_BLEND_ALPHA_F32 0x0000e1a7
3311	#define A5XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff
3312	#define A5XX_RB_BLEND_ALPHA_F32__SHIFT 0
3313	static inline uint32_t A5XX_RB_BLEND_ALPHA_F32(float val)
3314	{
3315	return ((fui(val)) << A5XX_RB_BLEND_ALPHA_F32__SHIFT) & A5XX_RB_BLEND_ALPHA_F32__MASK;
3316	}
3317
3318	#define REG_A5XX_RB_ALPHA_CONTROL 0x0000e1a8
3319	#define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff
3320	#define A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0
3321	static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val)
3322	{
3323	return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK;
3324	}
3325	#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100
3326	#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00
3327	#define A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9
3328	static inline uint32_t A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
3329	{
3330	return ((val) << A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A5XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK;
3331	}
3332
3333	#define REG_A5XX_RB_BLEND_CNTL 0x0000e1a9
3334	#define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
3335	#define A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
3336	static inline uint32_t A5XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
3337	{
3338	return ((val) << A5XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK;
3339	}
3340	#define A5XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100
3341	#define A5XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
3342	#define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000
3343	#define A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16
3344	static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
3345	{
3346	return ((val) << A5XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A5XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK;
3347	}
3348
3349	#define REG_A5XX_RB_DEPTH_PLANE_CNTL 0x0000e1b0
3350	#define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
3351	#define A5XX_RB_DEPTH_PLANE_CNTL_UNK1 0x00000002
3352
3353	#define REG_A5XX_RB_DEPTH_CNTL 0x0000e1b1
3354	#define A5XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000001
3355	#define A5XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002
3356	#define A5XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c
3357	#define A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2
3358	static inline uint32_t A5XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val)
3359	{
3360	return ((val) << A5XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A5XX_RB_DEPTH_CNTL_ZFUNC__MASK;
3361	}
3362	#define A5XX_RB_DEPTH_CNTL_Z_READ_ENABLE 0x00000040
3363
3364	#define REG_A5XX_RB_DEPTH_BUFFER_INFO 0x0000e1b2
3365	#define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007
3366	#define A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0
3367	static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_format val)
3368	{
3369	return ((val) << A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK;
3370	}
3371
3372	#define REG_A5XX_RB_DEPTH_BUFFER_BASE_LO 0x0000e1b3
3373
3374	#define REG_A5XX_RB_DEPTH_BUFFER_BASE_HI 0x0000e1b4
3375
3376	#define REG_A5XX_RB_DEPTH_BUFFER_PITCH 0x0000e1b5
3377	#define A5XX_RB_DEPTH_BUFFER_PITCH__MASK 0xffffffff
3378	#define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
3379	static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
3380	{
3381	assert(!(val & 0x3f));
3382	return (((val >> 6)) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK;
3383	}
3384
3385	#define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6
3386	#define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0xffffffff
3387	#define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
3388	static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
3389	{
3390	assert(!(val & 0x3f));
3391	return (((val >> 6)) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
3392	}
3393
3394	#define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0
3395	#define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
3396	#define A5XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
3397	#define A5XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
3398	#define A5XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
3399	#define A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
3400	static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
3401	{
3402	return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC__MASK;
3403	}
3404	#define A5XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
3405	#define A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
3406	static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
3407	{
3408	return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL__MASK;
3409	}
3410	#define A5XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
3411	#define A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
3412	static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
3413	{
3414	return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS__MASK;
3415	}
3416	#define A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
3417	#define A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
3418	static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
3419	{
3420	return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
3421	}
3422	#define A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
3423	#define A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
3424	static inline uint32_t A5XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
3425	{
3426	return ((val) << A5XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
3427	}
3428	#define A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
3429	#define A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
3430	static inline uint32_t A5XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
3431	{
3432	return ((val) << A5XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
3433	}
3434	#define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
3435	#define A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
3436	static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
3437	{
3438	return ((val) << A5XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
3439	}
3440	#define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
3441	#define A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
3442	static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
3443	{
3444	return ((val) << A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A5XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
3445	}
3446
3447	#define REG_A5XX_RB_STENCIL_INFO 0x0000e1c1
3448	#define A5XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001
3449
3450	#define REG_A5XX_RB_STENCIL_BASE_LO 0x0000e1c2
3451
3452	#define REG_A5XX_RB_STENCIL_BASE_HI 0x0000e1c3
3453
3454	#define REG_A5XX_RB_STENCIL_PITCH 0x0000e1c4
3455	#define A5XX_RB_STENCIL_PITCH__MASK 0xffffffff
3456	#define A5XX_RB_STENCIL_PITCH__SHIFT 0
3457	static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val)
3458	{
3459	assert(!(val & 0x3f));
3460	return (((val >> 6)) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK;
3461	}
3462
3463	#define REG_A5XX_RB_STENCIL_ARRAY_PITCH 0x0000e1c5
3464	#define A5XX_RB_STENCIL_ARRAY_PITCH__MASK 0xffffffff
3465	#define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT 0
3466	static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val)
3467	{
3468	assert(!(val & 0x3f));
3469	return (((val >> 6)) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK;
3470	}
3471
3472	#define REG_A5XX_RB_STENCILREFMASK 0x0000e1c6
3473	#define A5XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
3474	#define A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
3475	static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
3476	{
3477	return ((val) << A5XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILREF__MASK;
3478	}
3479	#define A5XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
3480	#define A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
3481	static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
3482	{
3483	return ((val) << A5XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILMASK__MASK;
3484	}
3485	#define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
3486	#define A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
3487	static inline uint32_t A5XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
3488	{
3489	return ((val) << A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
3490	}
3491
3492	#define REG_A5XX_RB_STENCILREFMASK_BF 0x0000e1c7
3493	#define A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
3494	#define A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
3495	static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
3496	{
3497	return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
3498	}
3499	#define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
3500	#define A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
3501	static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
3502	{
3503	return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
3504	}
3505	#define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
3506	#define A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
3507	static inline uint32_t A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
3508	{
3509	return ((val) << A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A5XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
3510	}
3511
3512	#define REG_A5XX_RB_WINDOW_OFFSET 0x0000e1d0
3513	#define A5XX_RB_WINDOW_OFFSET_WINDOW_OFFSET_DISABLE 0x80000000
3514	#define A5XX_RB_WINDOW_OFFSET_X__MASK 0x00007fff
3515	#define A5XX_RB_WINDOW_OFFSET_X__SHIFT 0
3516	static inline uint32_t A5XX_RB_WINDOW_OFFSET_X(uint32_t val)
3517	{
3518	return ((val) << A5XX_RB_WINDOW_OFFSET_X__SHIFT) & A5XX_RB_WINDOW_OFFSET_X__MASK;
3519	}
3520	#define A5XX_RB_WINDOW_OFFSET_Y__MASK 0x7fff0000
3521	#define A5XX_RB_WINDOW_OFFSET_Y__SHIFT 16
3522	static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val)
3523	{
3524	return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK;
3525	}
3526
3527	#define REG_A5XX_RB_SAMPLE_COUNT_CONTROL 0x0000e1d1
3528	#define A5XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
3529
3530	#define REG_A5XX_RB_BLIT_CNTL 0x0000e210
3531	#define A5XX_RB_BLIT_CNTL_BUF__MASK 0x0000000f
3532	#define A5XX_RB_BLIT_CNTL_BUF__SHIFT 0
3533	static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val)
3534	{
3535	return ((val) << A5XX_RB_BLIT_CNTL_BUF__SHIFT) & A5XX_RB_BLIT_CNTL_BUF__MASK;
3536	}
3537
3538	#define REG_A5XX_RB_RESOLVE_CNTL_1 0x0000e211
3539	#define A5XX_RB_RESOLVE_CNTL_1_WINDOW_OFFSET_DISABLE 0x80000000
3540	#define A5XX_RB_RESOLVE_CNTL_1_X__MASK 0x00007fff
3541	#define A5XX_RB_RESOLVE_CNTL_1_X__SHIFT 0
3542	static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_X(uint32_t val)
3543	{
3544	return ((val) << A5XX_RB_RESOLVE_CNTL_1_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_X__MASK;
3545	}
3546	#define A5XX_RB_RESOLVE_CNTL_1_Y__MASK 0x7fff0000
3547	#define A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT 16
3548	static inline uint32_t A5XX_RB_RESOLVE_CNTL_1_Y(uint32_t val)
3549	{
3550	return ((val) << A5XX_RB_RESOLVE_CNTL_1_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_1_Y__MASK;
3551	}
3552
3553	#define REG_A5XX_RB_RESOLVE_CNTL_2 0x0000e212
3554	#define A5XX_RB_RESOLVE_CNTL_2_WINDOW_OFFSET_DISABLE 0x80000000
3555	#define A5XX_RB_RESOLVE_CNTL_2_X__MASK 0x00007fff
3556	#define A5XX_RB_RESOLVE_CNTL_2_X__SHIFT 0
3557	static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_X(uint32_t val)
3558	{
3559	return ((val) << A5XX_RB_RESOLVE_CNTL_2_X__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_X__MASK;
3560	}
3561	#define A5XX_RB_RESOLVE_CNTL_2_Y__MASK 0x7fff0000
3562	#define A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT 16
3563	static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val)
3564	{
3565	return ((val) << A5XX_RB_RESOLVE_CNTL_2_Y__SHIFT) & A5XX_RB_RESOLVE_CNTL_2_Y__MASK;
3566	}
3567
3568	#define REG_A5XX_RB_RESOLVE_CNTL_3 0x0000e213
3569	#define A5XX_RB_RESOLVE_CNTL_3_TILED 0x00000001
3570
3571	#define REG_A5XX_RB_BLIT_DST_LO 0x0000e214
3572
3573	#define REG_A5XX_RB_BLIT_DST_HI 0x0000e215
3574
3575	#define REG_A5XX_RB_BLIT_DST_PITCH 0x0000e216
3576	#define A5XX_RB_BLIT_DST_PITCH__MASK 0xffffffff
3577	#define A5XX_RB_BLIT_DST_PITCH__SHIFT 0
3578	static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val)
3579	{
3580	assert(!(val & 0x3f));
3581	return (((val >> 6)) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK;
3582	}
3583
3584	#define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH 0x0000e217
3585	#define A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0xffffffff
3586	#define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0
3587	static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val)
3588	{
3589	assert(!(val & 0x3f));
3590	return (((val >> 6)) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK;
3591	}
3592
3593	#define REG_A5XX_RB_CLEAR_COLOR_DW0 0x0000e218
3594
3595	#define REG_A5XX_RB_CLEAR_COLOR_DW1 0x0000e219
3596
3597	#define REG_A5XX_RB_CLEAR_COLOR_DW2 0x0000e21a
3598
3599	#define REG_A5XX_RB_CLEAR_COLOR_DW3 0x0000e21b
3600
3601	#define REG_A5XX_RB_CLEAR_CNTL 0x0000e21c
3602	#define A5XX_RB_CLEAR_CNTL_FAST_CLEAR 0x00000002
3603	#define A5XX_RB_CLEAR_CNTL_MSAA_RESOLVE 0x00000004
3604	#define A5XX_RB_CLEAR_CNTL_MASK__MASK 0x000000f0
3605	#define A5XX_RB_CLEAR_CNTL_MASK__SHIFT 4
3606	static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val)
3607	{
3608	return ((val) << A5XX_RB_CLEAR_CNTL_MASK__SHIFT) & A5XX_RB_CLEAR_CNTL_MASK__MASK;
3609	}
3610
3611	#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_LO 0x0000e240
3612
3613	#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_BASE_HI 0x0000e241
3614
3615	#define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x0000e242
3616
3617	#define REG_A5XX_RB_MRT_FLAG_BUFFER(i0) (0x0000e243 + 0x4*(i0))
3618
3619	static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; }
3620
3621	static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_HI(uint32_t i0) { return 0x0000e244 + 0x4*i0; }
3622
3623	static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x0000e245 + 0x4*i0; }
3624	#define A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK 0xffffffff
3625	#define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT 0
3626	static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val)
3627	{
3628	assert(!(val & 0x3f));
3629	return (((val >> 6)) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK;
3630	}
3631
3632	static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; }
3633	#define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK 0xffffffff
3634	#define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0
3635	static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val)
3636	{
3637	assert(!(val & 0x3f));
3638	return (((val >> 6)) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK;
3639	}
3640
3641	#define REG_A5XX_RB_BLIT_FLAG_DST_LO 0x0000e263
3642
3643	#define REG_A5XX_RB_BLIT_FLAG_DST_HI 0x0000e264
3644
3645	#define REG_A5XX_RB_BLIT_FLAG_DST_PITCH 0x0000e265
3646	#define A5XX_RB_BLIT_FLAG_DST_PITCH__MASK 0xffffffff
3647	#define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT 0
3648	static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val)
3649	{
3650	assert(!(val & 0x3f));
3651	return (((val >> 6)) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK;
3652	}
3653
3654	#define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH 0x0000e266
3655	#define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK 0xffffffff
3656	#define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT 0
3657	static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val)
3658	{
3659	assert(!(val & 0x3f));
3660	return (((val >> 6)) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK;
3661	}
3662
3663	#define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO 0x0000e267
3664
3665	#define REG_A5XX_RB_SAMPLE_COUNT_ADDR_HI 0x0000e268
3666
3667	#define REG_A5XX_VPC_CNTL_0 0x0000e280
3668	#define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK 0x0000007f
3669	#define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT 0
3670	static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val)
3671	{
3672	return ((val) << A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT) & A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK;
3673	}
3674	#define A5XX_VPC_CNTL_0_VARYING 0x00000800
3675
3676	#define REG_A5XX_VPC_VARYING_INTERP(i0) (0x0000e282 + 0x1*(i0))
3677
3678	static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; }
3679
3680	#define REG_A5XX_VPC_VARYING_PS_REPL(i0) (0x0000e28a + 0x1*(i0))
3681
3682	static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; }
3683
3684	#define REG_A5XX_UNKNOWN_E292 0x0000e292
3685
3686	#define REG_A5XX_UNKNOWN_E293 0x0000e293
3687
3688	#define REG_A5XX_VPC_VAR(i0) (0x0000e294 + 0x1*(i0))
3689
3690	static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; }
3691
3692	#define REG_A5XX_VPC_GS_SIV_CNTL 0x0000e298
3693
3694	#define REG_A5XX_VPC_CLIP_CNTL 0x0000e29a
3695	#define A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
3696	#define A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT 0
3697	static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_MASK(uint32_t val)
3698	{
3699	return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_MASK__MASK;
3700	}
3701	#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00
3702	#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8
3703	static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val)
3704	{
3705	return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_03_LOC__MASK;
3706	}
3707	#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000
3708	#define A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16
3709	static inline uint32_t A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val)
3710	{
3711	return ((val) << A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A5XX_VPC_CLIP_CNTL_CLIP_DIST_47_LOC__MASK;
3712	}
3713
3714	#define REG_A5XX_VPC_PACK 0x0000e29d
3715	#define A5XX_VPC_PACK_NUMNONPOSVAR__MASK 0x000000ff
3716	#define A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT 0
3717	static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
3718	{
3719	return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK;
3720	}
3721	#define A5XX_VPC_PACK_PSIZELOC__MASK 0x0000ff00
3722	#define A5XX_VPC_PACK_PSIZELOC__SHIFT 8
3723	static inline uint32_t A5XX_VPC_PACK_PSIZELOC(uint32_t val)
3724	{
3725	return ((val) << A5XX_VPC_PACK_PSIZELOC__SHIFT) & A5XX_VPC_PACK_PSIZELOC__MASK;
3726	}
3727
3728	#define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL 0x0000e2a0
3729
3730	#define REG_A5XX_VPC_SO_BUF_CNTL 0x0000e2a1
3731	#define A5XX_VPC_SO_BUF_CNTL_BUF0 0x00000001
3732	#define A5XX_VPC_SO_BUF_CNTL_BUF1 0x00000008
3733	#define A5XX_VPC_SO_BUF_CNTL_BUF2 0x00000040
3734	#define A5XX_VPC_SO_BUF_CNTL_BUF3 0x00000200
3735	#define A5XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000
3736
3737	#define REG_A5XX_VPC_SO_OVERRIDE 0x0000e2a2
3738	#define A5XX_VPC_SO_OVERRIDE_SO_DISABLE 0x00000001
3739
3740	#define REG_A5XX_VPC_SO_CNTL 0x0000e2a3
3741	#define A5XX_VPC_SO_CNTL_ENABLE 0x00010000
3742
3743	#define REG_A5XX_VPC_SO_PROG 0x0000e2a4
3744	#define A5XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
3745	#define A5XX_VPC_SO_PROG_A_BUF__SHIFT 0
3746	static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val)
3747	{
3748	return ((val) << A5XX_VPC_SO_PROG_A_BUF__SHIFT) & A5XX_VPC_SO_PROG_A_BUF__MASK;
3749	}
3750	#define A5XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc
3751	#define A5XX_VPC_SO_PROG_A_OFF__SHIFT 2
3752	static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val)
3753	{
3754	assert(!(val & 0x3));
3755	return (((val >> 2)) << A5XX_VPC_SO_PROG_A_OFF__SHIFT) & A5XX_VPC_SO_PROG_A_OFF__MASK;
3756	}
3757	#define A5XX_VPC_SO_PROG_A_EN 0x00000800
3758	#define A5XX_VPC_SO_PROG_B_BUF__MASK 0x00003000
3759	#define A5XX_VPC_SO_PROG_B_BUF__SHIFT 12
3760	static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val)
3761	{
3762	return ((val) << A5XX_VPC_SO_PROG_B_BUF__SHIFT) & A5XX_VPC_SO_PROG_B_BUF__MASK;
3763	}
3764	#define A5XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000
3765	#define A5XX_VPC_SO_PROG_B_OFF__SHIFT 14
3766	static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val)
3767	{
3768	assert(!(val & 0x3));
3769	return (((val >> 2)) << A5XX_VPC_SO_PROG_B_OFF__SHIFT) & A5XX_VPC_SO_PROG_B_OFF__MASK;
3770	}
3771	#define A5XX_VPC_SO_PROG_B_EN 0x00800000
3772
3773	#define REG_A5XX_VPC_SO(i0) (0x0000e2a7 + 0x7*(i0))
3774
3775	static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
3776
3777	static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000e2a8 + 0x7*i0; }
3778
3779	static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000e2a9 + 0x7*i0; }
3780
3781	static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000e2aa + 0x7*i0; }
3782
3783	static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000e2ab + 0x7*i0; }
3784
3785	static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000e2ac + 0x7*i0; }
3786
3787	static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x0000e2ad + 0x7*i0; }
3788
3789	#define REG_A5XX_PC_PRIMITIVE_CNTL 0x0000e384
3790	#define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000007f
3791	#define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0
3792	static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val)
3793	{
3794	return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK;
3795	}
3796	#define A5XX_PC_PRIMITIVE_CNTL_PRIMITIVE_RESTART 0x00000100
3797	#define A5XX_PC_PRIMITIVE_CNTL_COUNT_PRIMITIVES 0x00000200
3798	#define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST 0x00000400
3799
3800	#define REG_A5XX_PC_PRIM_VTX_CNTL 0x0000e385
3801	#define A5XX_PC_PRIM_VTX_CNTL_PSIZE 0x00000800
3802
3803	#define REG_A5XX_PC_RASTER_CNTL 0x0000e388
3804	#define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x00000007
3805	#define A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 0
3806	static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
3807	{
3808	return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_FRONT_PTYPE__MASK;
3809	}
3810	#define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000038
3811	#define A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT 3
3812	static inline uint32_t A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
3813	{
3814	return ((val) << A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A5XX_PC_RASTER_CNTL_POLYMODE_BACK_PTYPE__MASK;
3815	}
3816	#define A5XX_PC_RASTER_CNTL_POLYMODE_ENABLE 0x00000040
3817
3818	#define REG_A5XX_PC_CLIP_CNTL 0x0000e389
3819	#define A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff
3820	#define A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT 0
3821	static inline uint32_t A5XX_PC_CLIP_CNTL_CLIP_MASK(uint32_t val)
3822	{
3823	return ((val) << A5XX_PC_CLIP_CNTL_CLIP_MASK__SHIFT) & A5XX_PC_CLIP_CNTL_CLIP_MASK__MASK;
3824	}
3825
3826	#define REG_A5XX_PC_RESTART_INDEX 0x0000e38c
3827
3828	#define REG_A5XX_PC_GS_LAYERED 0x0000e38d
3829
3830	#define REG_A5XX_PC_GS_PARAM 0x0000e38e
3831	#define A5XX_PC_GS_PARAM_MAX_VERTICES__MASK 0x000003ff
3832	#define A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT 0
3833	static inline uint32_t A5XX_PC_GS_PARAM_MAX_VERTICES(uint32_t val)
3834	{
3835	return ((val) << A5XX_PC_GS_PARAM_MAX_VERTICES__SHIFT) & A5XX_PC_GS_PARAM_MAX_VERTICES__MASK;
3836	}
3837	#define A5XX_PC_GS_PARAM_INVOCATIONS__MASK 0x0000f800
3838	#define A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT 11
3839	static inline uint32_t A5XX_PC_GS_PARAM_INVOCATIONS(uint32_t val)
3840	{
3841	return ((val) << A5XX_PC_GS_PARAM_INVOCATIONS__SHIFT) & A5XX_PC_GS_PARAM_INVOCATIONS__MASK;
3842	}
3843	#define A5XX_PC_GS_PARAM_PRIMTYPE__MASK 0x01800000
3844	#define A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT 23
3845	static inline uint32_t A5XX_PC_GS_PARAM_PRIMTYPE(enum adreno_pa_su_sc_draw val)
3846	{
3847	return ((val) << A5XX_PC_GS_PARAM_PRIMTYPE__SHIFT) & A5XX_PC_GS_PARAM_PRIMTYPE__MASK;
3848	}
3849
3850	#define REG_A5XX_PC_HS_PARAM 0x0000e38f
3851	#define A5XX_PC_HS_PARAM_VERTICES_OUT__MASK 0x0000003f
3852	#define A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT 0
3853	static inline uint32_t A5XX_PC_HS_PARAM_VERTICES_OUT(uint32_t val)
3854	{
3855	return ((val) << A5XX_PC_HS_PARAM_VERTICES_OUT__SHIFT) & A5XX_PC_HS_PARAM_VERTICES_OUT__MASK;
3856	}
3857	#define A5XX_PC_HS_PARAM_SPACING__MASK 0x00600000
3858	#define A5XX_PC_HS_PARAM_SPACING__SHIFT 21
3859	static inline uint32_t A5XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
3860	{
3861	return ((val) << A5XX_PC_HS_PARAM_SPACING__SHIFT) & A5XX_PC_HS_PARAM_SPACING__MASK;
3862	}
3863	#define A5XX_PC_HS_PARAM_CW 0x00800000
3864	#define A5XX_PC_HS_PARAM_CONNECTED 0x01000000
3865
3866	#define REG_A5XX_PC_POWER_CNTL 0x0000e3b0
3867
3868	#define REG_A5XX_VFD_CONTROL_0 0x0000e400
3869	#define A5XX_VFD_CONTROL_0_VTXCNT__MASK 0x0000003f
3870	#define A5XX_VFD_CONTROL_0_VTXCNT__SHIFT 0
3871	static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val)
3872	{
3873	return ((val) << A5XX_VFD_CONTROL_0_VTXCNT__SHIFT) & A5XX_VFD_CONTROL_0_VTXCNT__MASK;
3874	}
3875
3876	#define REG_A5XX_VFD_CONTROL_1 0x0000e401
3877	#define A5XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff
3878	#define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0
3879	static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
3880	{
3881	return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK;
3882	}
3883	#define A5XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00
3884	#define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT 8
3885	static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
3886	{
3887	return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK;
3888	}
3889	#define A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000
3890	#define A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16
3891	static inline uint32_t A5XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val)
3892	{
3893	return ((val) << A5XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A5XX_VFD_CONTROL_1_REGID4PRIMID__MASK;
3894	}
3895
3896	#define REG_A5XX_VFD_CONTROL_2 0x0000e402
3897	#define A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK 0x000000ff
3898	#define A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT 0
3899	static inline uint32_t A5XX_VFD_CONTROL_2_REGID_PATCHID(uint32_t val)
3900	{
3901	return ((val) << A5XX_VFD_CONTROL_2_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_2_REGID_PATCHID__MASK;
3902	}
3903
3904	#define REG_A5XX_VFD_CONTROL_3 0x0000e403
3905	#define A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK 0x0000ff00
3906	#define A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT 8
3907	static inline uint32_t A5XX_VFD_CONTROL_3_REGID_PATCHID(uint32_t val)
3908	{
3909	return ((val) << A5XX_VFD_CONTROL_3_REGID_PATCHID__SHIFT) & A5XX_VFD_CONTROL_3_REGID_PATCHID__MASK;
3910	}
3911	#define A5XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000
3912	#define A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16
3913	static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val)
3914	{
3915	return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSX__MASK;
3916	}
3917	#define A5XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000
3918	#define A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24
3919	static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val)
3920	{
3921	return ((val) << A5XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A5XX_VFD_CONTROL_3_REGID_TESSY__MASK;
3922	}
3923
3924	#define REG_A5XX_VFD_CONTROL_4 0x0000e404
3925
3926	#define REG_A5XX_VFD_CONTROL_5 0x0000e405
3927
3928	#define REG_A5XX_VFD_INDEX_OFFSET 0x0000e408
3929
3930	#define REG_A5XX_VFD_INSTANCE_START_OFFSET 0x0000e409
3931
3932	#define REG_A5XX_VFD_FETCH(i0) (0x0000e40a + 0x4*(i0))
3933
3934	static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; }
3935
3936	static inline uint32_t REG_A5XX_VFD_FETCH_BASE_HI(uint32_t i0) { return 0x0000e40b + 0x4*i0; }
3937
3938	static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c + 0x4*i0; }
3939
3940	static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; }
3941
3942	#define REG_A5XX_VFD_DECODE(i0) (0x0000e48a + 0x2*(i0))
3943
3944	static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; }
3945	#define A5XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f
3946	#define A5XX_VFD_DECODE_INSTR_IDX__SHIFT 0
3947	static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val)
3948	{
3949	return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK;
3950	}
3951	#define A5XX_VFD_DECODE_INSTR_INSTANCED 0x00020000
3952	#define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000
3953	#define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
3954	static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val)
3955	{
3956	return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK;
3957	}
3958	#define A5XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000
3959	#define A5XX_VFD_DECODE_INSTR_SWAP__SHIFT 28
3960	static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
3961	{
3962	return ((val) << A5XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A5XX_VFD_DECODE_INSTR_SWAP__MASK;
3963	}
3964	#define A5XX_VFD_DECODE_INSTR_UNK30 0x40000000
3965	#define A5XX_VFD_DECODE_INSTR_FLOAT 0x80000000
3966
3967	static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; }
3968
3969	#define REG_A5XX_VFD_DEST_CNTL(i0) (0x0000e4ca + 0x1*(i0))
3970
3971	static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; }
3972	#define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f
3973	#define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0
3974	static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val)
3975	{
3976	return ((val) << A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK;
3977	}
3978	#define A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0
3979	#define A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4
3980	static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
3981	{
3982	return ((val) << A5XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A5XX_VFD_DEST_CNTL_INSTR_REGID__MASK;
3983	}
3984
3985	#define REG_A5XX_VFD_POWER_CNTL 0x0000e4f0
3986
3987	#define REG_A5XX_SP_SP_CNTL 0x0000e580
3988
3989	#define REG_A5XX_SP_VS_CONFIG 0x0000e584
3990	#define A5XX_SP_VS_CONFIG_ENABLED 0x00000001
3991	#define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
3992	#define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
3993	static inline uint32_t A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
3994	{
3995	return ((val) << A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK;
3996	}
3997	#define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
3998	#define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8
3999	static inline uint32_t A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4000	{
4001	return ((val) << A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK;
4002	}
4003
4004	#define REG_A5XX_SP_FS_CONFIG 0x0000e585
4005	#define A5XX_SP_FS_CONFIG_ENABLED 0x00000001
4006	#define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4007	#define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4008	static inline uint32_t A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4009	{
4010	return ((val) << A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK;
4011	}
4012	#define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4013	#define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4014	static inline uint32_t A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4015	{
4016	return ((val) << A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK;
4017	}
4018
4019	#define REG_A5XX_SP_HS_CONFIG 0x0000e586
4020	#define A5XX_SP_HS_CONFIG_ENABLED 0x00000001
4021	#define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4022	#define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4023	static inline uint32_t A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4024	{
4025	return ((val) << A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK;
4026	}
4027	#define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4028	#define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4029	static inline uint32_t A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4030	{
4031	return ((val) << A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK;
4032	}
4033
4034	#define REG_A5XX_SP_DS_CONFIG 0x0000e587
4035	#define A5XX_SP_DS_CONFIG_ENABLED 0x00000001
4036	#define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4037	#define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4038	static inline uint32_t A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4039	{
4040	return ((val) << A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK;
4041	}
4042	#define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4043	#define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4044	static inline uint32_t A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4045	{
4046	return ((val) << A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK;
4047	}
4048
4049	#define REG_A5XX_SP_GS_CONFIG 0x0000e588
4050	#define A5XX_SP_GS_CONFIG_ENABLED 0x00000001
4051	#define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4052	#define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4053	static inline uint32_t A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4054	{
4055	return ((val) << A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK;
4056	}
4057	#define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4058	#define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4059	static inline uint32_t A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4060	{
4061	return ((val) << A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK;
4062	}
4063
4064	#define REG_A5XX_SP_CS_CONFIG 0x0000e589
4065	#define A5XX_SP_CS_CONFIG_ENABLED 0x00000001
4066	#define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4067	#define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4068	static inline uint32_t A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4069	{
4070	return ((val) << A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK;
4071	}
4072	#define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4073	#define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4074	static inline uint32_t A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4075	{
4076	return ((val) << A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK;
4077	}
4078
4079	#define REG_A5XX_SP_VS_CONFIG_MAX_CONST 0x0000e58a
4080
4081	#define REG_A5XX_SP_FS_CONFIG_MAX_CONST 0x0000e58b
4082
4083	#define REG_A5XX_SP_VS_CTRL_REG0 0x0000e590
4084	#define A5XX_SP_VS_CTRL_REG0_BUFFER 0x00000004
4085	#define A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4086	#define A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 3
4087	static inline uint32_t A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4088	{
4089	return ((val) << A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
4090	}
4091	#define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4092	#define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
4093	static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4094	{
4095	return ((val) << A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4096	}
4097	#define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4098	#define A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
4099	static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4100	{
4101	return ((val) << A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4102	}
4103	#define A5XX_SP_VS_CTRL_REG0_VARYING 0x00010000
4104	#define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00100000
4105	#define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4106	#define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 25
4107	static inline uint32_t A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4108	{
4109	return ((val) << A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
4110	}
4111
4112	#define REG_A5XX_SP_PRIMITIVE_CNTL 0x0000e592
4113	#define A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f
4114	#define A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0
4115	static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val)
4116	{
4117	return ((val) << A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK;
4118	}
4119
4120	#define REG_A5XX_SP_VS_OUT(i0) (0x0000e593 + 0x1*(i0))
4121
4122	static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
4123	#define A5XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
4124	#define A5XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
4125	static inline uint32_t A5XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
4126	{
4127	return ((val) << A5XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_A_REGID__MASK;
4128	}
4129	#define A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00
4130	#define A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8
4131	static inline uint32_t A5XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
4132	{
4133	return ((val) << A5XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
4134	}
4135	#define A5XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
4136	#define A5XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
4137	static inline uint32_t A5XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
4138	{
4139	return ((val) << A5XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A5XX_SP_VS_OUT_REG_B_REGID__MASK;
4140	}
4141	#define A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000
4142	#define A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24
4143	static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
4144	{
4145	return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
4146	}
4147
4148	#define REG_A5XX_SP_VS_VPC_DST(i0) (0x0000e5a3 + 0x1*(i0))
4149
4150	static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; }
4151	#define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff
4152	#define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
4153	static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
4154	{
4155	return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
4156	}
4157	#define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00
4158	#define A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
4159	static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
4160	{
4161	return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
4162	}
4163	#define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000
4164	#define A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
4165	static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
4166	{
4167	return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
4168	}
4169	#define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000
4170	#define A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
4171	static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
4172	{
4173	return ((val) << A5XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A5XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
4174	}
4175
4176	#define REG_A5XX_UNKNOWN_E5AB 0x0000e5ab
4177
4178	#define REG_A5XX_SP_VS_OBJ_START_LO 0x0000e5ac
4179
4180	#define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad
4181
4182	#define REG_A5XX_SP_VS_PVT_MEM_PARAM 0x0000e5ae
4183	#define A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
4184	#define A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
4185	static inline uint32_t A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
4186	{
4187	assert(!(val & 0x1ff));
4188	return (((val >> 9)) << A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
4189	}
4190	#define A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00
4191	#define A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8
4192	static inline uint32_t A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val)
4193	{
4194	assert(!(val & 0x7ff));
4195	return (((val >> 11)) << A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK;
4196	}
4197	#define A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
4198	#define A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
4199	static inline uint32_t A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
4200	{
4201	return ((val) << A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
4202	}
4203
4204	#define REG_A5XX_SP_VS_PVT_MEM_ADDR 0x0000e5af
4205
4206	#define REG_A5XX_SP_VS_PVT_MEM_SIZE 0x0000e5b1
4207	#define A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
4208	#define A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
4209	static inline uint32_t A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
4210	{
4211	assert(!(val & 0xfff));
4212	return (((val >> 12)) << A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
4213	}
4214
4215	#define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0
4216	#define A5XX_SP_FS_CTRL_REG0_BUFFER 0x00000004
4217	#define A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4218	#define A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 3
4219	static inline uint32_t A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4220	{
4221	return ((val) << A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
4222	}
4223	#define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4224	#define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
4225	static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4226	{
4227	return ((val) << A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4228	}
4229	#define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4230	#define A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
4231	static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4232	{
4233	return ((val) << A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4234	}
4235	#define A5XX_SP_FS_CTRL_REG0_VARYING 0x00010000
4236	#define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00100000
4237	#define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4238	#define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 25
4239	static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4240	{
4241	return ((val) << A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
4242	}
4243
4244	#define REG_A5XX_UNKNOWN_E5C2 0x0000e5c2
4245
4246	#define REG_A5XX_SP_FS_OBJ_START_LO 0x0000e5c3
4247
4248	#define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4
4249
4250	#define REG_A5XX_SP_FS_PVT_MEM_PARAM 0x0000e5c5
4251	#define A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
4252	#define A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
4253	static inline uint32_t A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
4254	{
4255	assert(!(val & 0x1ff));
4256	return (((val >> 9)) << A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
4257	}
4258	#define A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00
4259	#define A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8
4260	static inline uint32_t A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val)
4261	{
4262	assert(!(val & 0x7ff));
4263	return (((val >> 11)) << A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK;
4264	}
4265	#define A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
4266	#define A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
4267	static inline uint32_t A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
4268	{
4269	return ((val) << A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
4270	}
4271
4272	#define REG_A5XX_SP_FS_PVT_MEM_ADDR 0x0000e5c6
4273
4274	#define REG_A5XX_SP_FS_PVT_MEM_SIZE 0x0000e5c8
4275	#define A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
4276	#define A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
4277	static inline uint32_t A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
4278	{
4279	assert(!(val & 0xfff));
4280	return (((val >> 12)) << A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
4281	}
4282
4283	#define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9
4284	#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff
4285	#define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0
4286	static inline uint32_t A5XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val)
4287	{
4288	return ((val) << A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK;
4289	}
4290	#define A5XX_SP_BLEND_CNTL_UNK8 0x00000100
4291	#define A5XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400
4292
4293	#define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca
4294	#define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
4295	#define A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT 0
4296	static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_MRT(uint32_t val)
4297	{
4298	return ((val) << A5XX_SP_FS_OUTPUT_CNTL_MRT__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK;
4299	}
4300	#define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK 0x00001fe0
4301	#define A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT 5
4302	static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID(uint32_t val)
4303	{
4304	return ((val) << A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_DEPTH_REGID__MASK;
4305	}
4306	#define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK 0x001fe000
4307	#define A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT 13
4308	static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val)
4309	{
4310	return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK;
4311	}
4312
4313	#define REG_A5XX_SP_FS_OUTPUT(i0) (0x0000e5cb + 0x1*(i0))
4314
4315	static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; }
4316	#define A5XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff
4317	#define A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0
4318	static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val)
4319	{
4320	return ((val) << A5XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_REG_REGID__MASK;
4321	}
4322	#define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100
4323
4324	#define REG_A5XX_SP_FS_MRT(i0) (0x0000e5d3 + 0x1*(i0))
4325
4326	static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; }
4327	#define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff
4328	#define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0
4329	static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val)
4330	{
4331	return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
4332	}
4333	#define A5XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100
4334	#define A5XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200
4335	#define A5XX_SP_FS_MRT_REG_COLOR_SRGB 0x00000400
4336
4337	#define REG_A5XX_UNKNOWN_E5DB 0x0000e5db
4338
4339	#define REG_A5XX_SP_CS_CTRL_REG0 0x0000e5f0
4340	#define A5XX_SP_CS_CTRL_REG0_BUFFER 0x00000004
4341	#define A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4342	#define A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 3
4343	static inline uint32_t A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4344	{
4345	return ((val) << A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
4346	}
4347	#define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4348	#define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
4349	static inline uint32_t A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4350	{
4351	return ((val) << A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4352	}
4353	#define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4354	#define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
4355	static inline uint32_t A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4356	{
4357	return ((val) << A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4358	}
4359	#define A5XX_SP_CS_CTRL_REG0_VARYING 0x00010000
4360	#define A5XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x00100000
4361	#define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4362	#define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 25
4363	static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4364	{
4365	return ((val) << A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
4366	}
4367
4368	#define REG_A5XX_UNKNOWN_E5F2 0x0000e5f2
4369
4370	#define REG_A5XX_SP_CS_OBJ_START_LO 0x0000e5f3
4371
4372	#define REG_A5XX_SP_CS_OBJ_START_HI 0x0000e5f4
4373
4374	#define REG_A5XX_SP_CS_PVT_MEM_PARAM 0x0000e5f5
4375	#define A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
4376	#define A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
4377	static inline uint32_t A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
4378	{
4379	assert(!(val & 0x1ff));
4380	return (((val >> 9)) << A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
4381	}
4382	#define A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00
4383	#define A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8
4384	static inline uint32_t A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val)
4385	{
4386	assert(!(val & 0x7ff));
4387	return (((val >> 11)) << A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK;
4388	}
4389	#define A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
4390	#define A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
4391	static inline uint32_t A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
4392	{
4393	return ((val) << A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
4394	}
4395
4396	#define REG_A5XX_SP_CS_PVT_MEM_ADDR 0x0000e5f6
4397
4398	#define REG_A5XX_SP_CS_PVT_MEM_SIZE 0x0000e5f8
4399	#define A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
4400	#define A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
4401	static inline uint32_t A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
4402	{
4403	assert(!(val & 0xfff));
4404	return (((val >> 12)) << A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
4405	}
4406
4407	#define REG_A5XX_SP_HS_CTRL_REG0 0x0000e600
4408	#define A5XX_SP_HS_CTRL_REG0_BUFFER 0x00000004
4409	#define A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4410	#define A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT 3
4411	static inline uint32_t A5XX_SP_HS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4412	{
4413	return ((val) << A5XX_SP_HS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK;
4414	}
4415	#define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4416	#define A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
4417	static inline uint32_t A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4418	{
4419	return ((val) << A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4420	}
4421	#define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4422	#define A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
4423	static inline uint32_t A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4424	{
4425	return ((val) << A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4426	}
4427	#define A5XX_SP_HS_CTRL_REG0_VARYING 0x00010000
4428	#define A5XX_SP_HS_CTRL_REG0_PIXLODENABLE 0x00100000
4429	#define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4430	#define A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 25
4431	static inline uint32_t A5XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4432	{
4433	return ((val) << A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK;
4434	}
4435
4436	#define REG_A5XX_UNKNOWN_E602 0x0000e602
4437
4438	#define REG_A5XX_SP_HS_OBJ_START_LO 0x0000e603
4439
4440	#define REG_A5XX_SP_HS_OBJ_START_HI 0x0000e604
4441
4442	#define REG_A5XX_SP_HS_PVT_MEM_PARAM 0x0000e605
4443	#define A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
4444	#define A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
4445	static inline uint32_t A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
4446	{
4447	assert(!(val & 0x1ff));
4448	return (((val >> 9)) << A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
4449	}
4450	#define A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00
4451	#define A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8
4452	static inline uint32_t A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val)
4453	{
4454	assert(!(val & 0x7ff));
4455	return (((val >> 11)) << A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK;
4456	}
4457	#define A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
4458	#define A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
4459	static inline uint32_t A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
4460	{
4461	return ((val) << A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
4462	}
4463
4464	#define REG_A5XX_SP_HS_PVT_MEM_ADDR 0x0000e606
4465
4466	#define REG_A5XX_SP_HS_PVT_MEM_SIZE 0x0000e608
4467	#define A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
4468	#define A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
4469	static inline uint32_t A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
4470	{
4471	assert(!(val & 0xfff));
4472	return (((val >> 12)) << A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
4473	}
4474
4475	#define REG_A5XX_SP_DS_CTRL_REG0 0x0000e610
4476	#define A5XX_SP_DS_CTRL_REG0_BUFFER 0x00000004
4477	#define A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4478	#define A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT 3
4479	static inline uint32_t A5XX_SP_DS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4480	{
4481	return ((val) << A5XX_SP_DS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK;
4482	}
4483	#define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4484	#define A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
4485	static inline uint32_t A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4486	{
4487	return ((val) << A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4488	}
4489	#define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4490	#define A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
4491	static inline uint32_t A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4492	{
4493	return ((val) << A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4494	}
4495	#define A5XX_SP_DS_CTRL_REG0_VARYING 0x00010000
4496	#define A5XX_SP_DS_CTRL_REG0_PIXLODENABLE 0x00100000
4497	#define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4498	#define A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 25
4499	static inline uint32_t A5XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4500	{
4501	return ((val) << A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK;
4502	}
4503
4504	#define REG_A5XX_UNKNOWN_E62B 0x0000e62b
4505
4506	#define REG_A5XX_SP_DS_OBJ_START_LO 0x0000e62c
4507
4508	#define REG_A5XX_SP_DS_OBJ_START_HI 0x0000e62d
4509
4510	#define REG_A5XX_SP_DS_PVT_MEM_PARAM 0x0000e62e
4511	#define A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
4512	#define A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
4513	static inline uint32_t A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
4514	{
4515	assert(!(val & 0x1ff));
4516	return (((val >> 9)) << A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
4517	}
4518	#define A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00
4519	#define A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8
4520	static inline uint32_t A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val)
4521	{
4522	assert(!(val & 0x7ff));
4523	return (((val >> 11)) << A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK;
4524	}
4525	#define A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
4526	#define A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
4527	static inline uint32_t A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
4528	{
4529	return ((val) << A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
4530	}
4531
4532	#define REG_A5XX_SP_DS_PVT_MEM_ADDR 0x0000e62f
4533
4534	#define REG_A5XX_SP_DS_PVT_MEM_SIZE 0x0000e631
4535	#define A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
4536	#define A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
4537	static inline uint32_t A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
4538	{
4539	assert(!(val & 0xfff));
4540	return (((val >> 12)) << A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
4541	}
4542
4543	#define REG_A5XX_SP_GS_CTRL_REG0 0x0000e640
4544	#define A5XX_SP_GS_CTRL_REG0_BUFFER 0x00000004
4545	#define A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00000008
4546	#define A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT 3
4547	static inline uint32_t A5XX_SP_GS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
4548	{
4549	return ((val) << A5XX_SP_GS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK;
4550	}
4551	#define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
4552	#define A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
4553	static inline uint32_t A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
4554	{
4555	return ((val) << A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
4556	}
4557	#define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
4558	#define A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
4559	static inline uint32_t A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
4560	{
4561	return ((val) << A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
4562	}
4563	#define A5XX_SP_GS_CTRL_REG0_VARYING 0x00010000
4564	#define A5XX_SP_GS_CTRL_REG0_PIXLODENABLE 0x00100000
4565	#define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
4566	#define A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 25
4567	static inline uint32_t A5XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val)
4568	{
4569	return ((val) << A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK;
4570	}
4571
4572	#define REG_A5XX_UNKNOWN_E65B 0x0000e65b
4573
4574	#define REG_A5XX_SP_GS_OBJ_START_LO 0x0000e65c
4575
4576	#define REG_A5XX_SP_GS_OBJ_START_HI 0x0000e65d
4577
4578	#define REG_A5XX_SP_GS_PVT_MEM_PARAM 0x0000e65e
4579	#define A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff
4580	#define A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0
4581	static inline uint32_t A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val)
4582	{
4583	assert(!(val & 0x1ff));
4584	return (((val >> 9)) << A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK;
4585	}
4586	#define A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00
4587	#define A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8
4588	static inline uint32_t A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val)
4589	{
4590	assert(!(val & 0x7ff));
4591	return (((val >> 11)) << A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK;
4592	}
4593	#define A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000
4594	#define A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24
4595	static inline uint32_t A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val)
4596	{
4597	return ((val) << A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK;
4598	}
4599
4600	#define REG_A5XX_SP_GS_PVT_MEM_ADDR 0x0000e65f
4601
4602	#define REG_A5XX_SP_GS_PVT_MEM_SIZE 0x0000e661
4603	#define A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff
4604	#define A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0
4605	static inline uint32_t A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val)
4606	{
4607	assert(!(val & 0xfff));
4608	return (((val >> 12)) << A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK;
4609	}
4610
4611	#define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704
4612	#define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
4613	#define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
4614	static inline uint32_t A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4615	{
4616	return ((val) << A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK;
4617	}
4618
4619	#define REG_A5XX_TPL1_TP_DEST_MSAA_CNTL 0x0000e705
4620	#define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003
4621	#define A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0
4622	static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val)
4623	{
4624	return ((val) << A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES__MASK;
4625	}
4626	#define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
4627
4628	#define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000e706
4629
4630	#define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000e707
4631
4632	#define REG_A5XX_TPL1_VS_TEX_COUNT 0x0000e700
4633
4634	#define REG_A5XX_TPL1_HS_TEX_COUNT 0x0000e701
4635
4636	#define REG_A5XX_TPL1_DS_TEX_COUNT 0x0000e702
4637
4638	#define REG_A5XX_TPL1_GS_TEX_COUNT 0x0000e703
4639
4640	#define REG_A5XX_TPL1_VS_TEX_SAMP_LO 0x0000e722
4641
4642	#define REG_A5XX_TPL1_VS_TEX_SAMP_HI 0x0000e723
4643
4644	#define REG_A5XX_TPL1_HS_TEX_SAMP_LO 0x0000e724
4645
4646	#define REG_A5XX_TPL1_HS_TEX_SAMP_HI 0x0000e725
4647
4648	#define REG_A5XX_TPL1_DS_TEX_SAMP_LO 0x0000e726
4649
4650	#define REG_A5XX_TPL1_DS_TEX_SAMP_HI 0x0000e727
4651
4652	#define REG_A5XX_TPL1_GS_TEX_SAMP_LO 0x0000e728
4653
4654	#define REG_A5XX_TPL1_GS_TEX_SAMP_HI 0x0000e729
4655
4656	#define REG_A5XX_TPL1_VS_TEX_CONST_LO 0x0000e72a
4657
4658	#define REG_A5XX_TPL1_VS_TEX_CONST_HI 0x0000e72b
4659
4660	#define REG_A5XX_TPL1_HS_TEX_CONST_LO 0x0000e72c
4661
4662	#define REG_A5XX_TPL1_HS_TEX_CONST_HI 0x0000e72d
4663
4664	#define REG_A5XX_TPL1_DS_TEX_CONST_LO 0x0000e72e
4665
4666	#define REG_A5XX_TPL1_DS_TEX_CONST_HI 0x0000e72f
4667
4668	#define REG_A5XX_TPL1_GS_TEX_CONST_LO 0x0000e730
4669
4670	#define REG_A5XX_TPL1_GS_TEX_CONST_HI 0x0000e731
4671
4672	#define REG_A5XX_TPL1_FS_TEX_COUNT 0x0000e750
4673
4674	#define REG_A5XX_TPL1_CS_TEX_COUNT 0x0000e751
4675
4676	#define REG_A5XX_TPL1_FS_TEX_SAMP_LO 0x0000e75a
4677
4678	#define REG_A5XX_TPL1_FS_TEX_SAMP_HI 0x0000e75b
4679
4680	#define REG_A5XX_TPL1_CS_TEX_SAMP_LO 0x0000e75c
4681
4682	#define REG_A5XX_TPL1_CS_TEX_SAMP_HI 0x0000e75d
4683
4684	#define REG_A5XX_TPL1_FS_TEX_CONST_LO 0x0000e75e
4685
4686	#define REG_A5XX_TPL1_FS_TEX_CONST_HI 0x0000e75f
4687
4688	#define REG_A5XX_TPL1_CS_TEX_CONST_LO 0x0000e760
4689
4690	#define REG_A5XX_TPL1_CS_TEX_CONST_HI 0x0000e761
4691
4692	#define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL 0x0000e764
4693
4694	#define REG_A5XX_HLSQ_CONTROL_0_REG 0x0000e784
4695	#define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000001
4696	#define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 0
4697	static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
4698	{
4699	return ((val) << A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
4700	}
4701	#define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK 0x00000004
4702	#define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT 2
4703	static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val)
4704	{
4705	return ((val) << A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK;
4706	}
4707
4708	#define REG_A5XX_HLSQ_CONTROL_1_REG 0x0000e785
4709	#define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x0000003f
4710	#define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0
4711	static inline uint32_t A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val)
4712	{
4713	return ((val) << A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK;
4714	}
4715
4716	#define REG_A5XX_HLSQ_CONTROL_2_REG 0x0000e786
4717	#define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff
4718	#define A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0
4719	static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val)
4720	{
4721	return ((val) << A5XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK;
4722	}
4723	#define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00
4724	#define A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8
4725	static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val)
4726	{
4727	return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK;
4728	}
4729	#define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000
4730	#define A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16
4731	static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val)
4732	{
4733	return ((val) << A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK;
4734	}
4735	#define A5XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK 0xff000000
4736	#define A5XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT 24
4737	static inline uint32_t A5XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val)
4738	{
4739	return ((val) << A5XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A5XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK;
4740	}
4741
4742	#define REG_A5XX_HLSQ_CONTROL_3_REG 0x0000e787
4743	#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff
4744	#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0
4745	static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val)
4746	{
4747	return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK;
4748	}
4749	#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00
4750	#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8
4751	static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val)
4752	{
4753	return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK;
4754	}
4755	#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000
4756	#define A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16
4757	static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val)
4758	{
4759	return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK;
4760	}
4761	#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000
4762	#define A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24
4763	static inline uint32_t A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val)
4764	{
4765	return ((val) << A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A5XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK;
4766	}
4767
4768	#define REG_A5XX_HLSQ_CONTROL_4_REG 0x0000e788
4769	#define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff
4770	#define A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0
4771	static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val)
4772	{
4773	return ((val) << A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK;
4774	}
4775	#define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00
4776	#define A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8
4777	static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val)
4778	{
4779	return ((val) << A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK;
4780	}
4781	#define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000
4782	#define A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16
4783	static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val)
4784	{
4785	return ((val) << A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK;
4786	}
4787	#define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000
4788	#define A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24
4789	static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
4790	{
4791	return ((val) << A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK;
4792	}
4793
4794	#define REG_A5XX_HLSQ_UPDATE_CNTL 0x0000e78a
4795
4796	#define REG_A5XX_HLSQ_VS_CONFIG 0x0000e78b
4797	#define A5XX_HLSQ_VS_CONFIG_ENABLED 0x00000001
4798	#define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4799	#define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4800	static inline uint32_t A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4801	{
4802	return ((val) << A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK;
4803	}
4804	#define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4805	#define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4806	static inline uint32_t A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4807	{
4808	return ((val) << A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK;
4809	}
4810
4811	#define REG_A5XX_HLSQ_FS_CONFIG 0x0000e78c
4812	#define A5XX_HLSQ_FS_CONFIG_ENABLED 0x00000001
4813	#define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4814	#define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4815	static inline uint32_t A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4816	{
4817	return ((val) << A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK;
4818	}
4819	#define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4820	#define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4821	static inline uint32_t A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4822	{
4823	return ((val) << A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK;
4824	}
4825
4826	#define REG_A5XX_HLSQ_HS_CONFIG 0x0000e78d
4827	#define A5XX_HLSQ_HS_CONFIG_ENABLED 0x00000001
4828	#define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4829	#define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4830	static inline uint32_t A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4831	{
4832	return ((val) << A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK;
4833	}
4834	#define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4835	#define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4836	static inline uint32_t A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4837	{
4838	return ((val) << A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK;
4839	}
4840
4841	#define REG_A5XX_HLSQ_DS_CONFIG 0x0000e78e
4842	#define A5XX_HLSQ_DS_CONFIG_ENABLED 0x00000001
4843	#define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4844	#define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4845	static inline uint32_t A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4846	{
4847	return ((val) << A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK;
4848	}
4849	#define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4850	#define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4851	static inline uint32_t A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4852	{
4853	return ((val) << A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK;
4854	}
4855
4856	#define REG_A5XX_HLSQ_GS_CONFIG 0x0000e78f
4857	#define A5XX_HLSQ_GS_CONFIG_ENABLED 0x00000001
4858	#define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4859	#define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4860	static inline uint32_t A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4861	{
4862	return ((val) << A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK;
4863	}
4864	#define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4865	#define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4866	static inline uint32_t A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4867	{
4868	return ((val) << A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK;
4869	}
4870
4871	#define REG_A5XX_HLSQ_CS_CONFIG 0x0000e790
4872	#define A5XX_HLSQ_CS_CONFIG_ENABLED 0x00000001
4873	#define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
4874	#define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
4875	static inline uint32_t A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
4876	{
4877	return ((val) << A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK;
4878	}
4879	#define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
4880	#define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8
4881	static inline uint32_t A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
4882	{
4883	return ((val) << A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK;
4884	}
4885
4886	#define REG_A5XX_HLSQ_VS_CNTL 0x0000e791
4887	#define A5XX_HLSQ_VS_CNTL_SSBO_ENABLE 0x00000001
4888	#define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK 0xfffffffe
4889	#define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT 1
4890	static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val)
4891	{
4892	return ((val) << A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK;
4893	}
4894
4895	#define REG_A5XX_HLSQ_FS_CNTL 0x0000e792
4896	#define A5XX_HLSQ_FS_CNTL_SSBO_ENABLE 0x00000001
4897	#define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK 0xfffffffe
4898	#define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT 1
4899	static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val)
4900	{
4901	return ((val) << A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK;
4902	}
4903
4904	#define REG_A5XX_HLSQ_HS_CNTL 0x0000e793
4905	#define A5XX_HLSQ_HS_CNTL_SSBO_ENABLE 0x00000001
4906	#define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK 0xfffffffe
4907	#define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT 1
4908	static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val)
4909	{
4910	return ((val) << A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK;
4911	}
4912
4913	#define REG_A5XX_HLSQ_DS_CNTL 0x0000e794
4914	#define A5XX_HLSQ_DS_CNTL_SSBO_ENABLE 0x00000001
4915	#define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK 0xfffffffe
4916	#define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT 1
4917	static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val)
4918	{
4919	return ((val) << A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK;
4920	}
4921
4922	#define REG_A5XX_HLSQ_GS_CNTL 0x0000e795
4923	#define A5XX_HLSQ_GS_CNTL_SSBO_ENABLE 0x00000001
4924	#define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK 0xfffffffe
4925	#define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT 1
4926	static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val)
4927	{
4928	return ((val) << A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK;
4929	}
4930
4931	#define REG_A5XX_HLSQ_CS_CNTL 0x0000e796
4932	#define A5XX_HLSQ_CS_CNTL_SSBO_ENABLE 0x00000001
4933	#define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK 0xfffffffe
4934	#define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT 1
4935	static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val)
4936	{
4937	return ((val) << A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT) & A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK;
4938	}
4939
4940	#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_X 0x0000e7b9
4941
4942	#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000e7ba
4943
4944	#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000e7bb
4945
4946	#define REG_A5XX_HLSQ_CS_NDRANGE_0 0x0000e7b0
4947	#define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
4948	#define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0
4949	static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
4950	{
4951	return ((val) << A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
4952	}
4953	#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
4954	#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2
4955	static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
4956	{
4957	return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
4958	}
4959	#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
4960	#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12
4961	static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
4962	{
4963	return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
4964	}
4965	#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
4966	#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22
4967	static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
4968	{
4969	return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
4970	}
4971
4972	#define REG_A5XX_HLSQ_CS_NDRANGE_1 0x0000e7b1
4973	#define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff
4974	#define A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0
4975	static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val)
4976	{
4977	return ((val) << A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK;
4978	}
4979
4980	#define REG_A5XX_HLSQ_CS_NDRANGE_2 0x0000e7b2
4981	#define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff
4982	#define A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0
4983	static inline uint32_t A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val)
4984	{
4985	return ((val) << A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK;
4986	}
4987
4988	#define REG_A5XX_HLSQ_CS_NDRANGE_3 0x0000e7b3
4989	#define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff
4990	#define A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0
4991	static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val)
4992	{
4993	return ((val) << A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK;
4994	}
4995
4996	#define REG_A5XX_HLSQ_CS_NDRANGE_4 0x0000e7b4
4997	#define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff
4998	#define A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0
4999	static inline uint32_t A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val)
5000	{
5001	return ((val) << A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK;
5002	}
5003
5004	#define REG_A5XX_HLSQ_CS_NDRANGE_5 0x0000e7b5
5005	#define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff
5006	#define A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0
5007	static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val)
5008	{
5009	return ((val) << A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK;
5010	}
5011
5012	#define REG_A5XX_HLSQ_CS_NDRANGE_6 0x0000e7b6
5013	#define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff
5014	#define A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0
5015	static inline uint32_t A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val)
5016	{
5017	return ((val) << A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK;
5018	}
5019
5020	#define REG_A5XX_HLSQ_CS_CNTL_0 0x0000e7b7
5021	#define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
5022	#define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0
5023	static inline uint32_t A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
5024	{
5025	return ((val) << A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
5026	}
5027	#define A5XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00
5028	#define A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8
5029	static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
5030	{
5031	return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK0__MASK;
5032	}
5033	#define A5XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000
5034	#define A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16
5035	static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
5036	{
5037	return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK1__MASK;
5038	}
5039	#define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
5040	#define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
5041	static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
5042	{
5043	return ((val) << A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
5044	}
5045
5046	#define REG_A5XX_HLSQ_CS_CNTL_1 0x0000e7b8
5047
5048	#define REG_A5XX_UNKNOWN_E7C0 0x0000e7c0
5049
5050	#define REG_A5XX_HLSQ_VS_CONSTLEN 0x0000e7c3
5051
5052	#define REG_A5XX_HLSQ_VS_INSTRLEN 0x0000e7c4
5053
5054	#define REG_A5XX_UNKNOWN_E7C5 0x0000e7c5
5055
5056	#define REG_A5XX_HLSQ_HS_CONSTLEN 0x0000e7c8
5057
5058	#define REG_A5XX_HLSQ_HS_INSTRLEN 0x0000e7c9
5059
5060	#define REG_A5XX_UNKNOWN_E7CA 0x0000e7ca
5061
5062	#define REG_A5XX_HLSQ_DS_CONSTLEN 0x0000e7cd
5063
5064	#define REG_A5XX_HLSQ_DS_INSTRLEN 0x0000e7ce
5065
5066	#define REG_A5XX_UNKNOWN_E7CF 0x0000e7cf
5067
5068	#define REG_A5XX_HLSQ_GS_CONSTLEN 0x0000e7d2
5069
5070	#define REG_A5XX_HLSQ_GS_INSTRLEN 0x0000e7d3
5071
5072	#define REG_A5XX_UNKNOWN_E7D4 0x0000e7d4
5073
5074	#define REG_A5XX_HLSQ_FS_CONSTLEN 0x0000e7d7
5075
5076	#define REG_A5XX_HLSQ_FS_INSTRLEN 0x0000e7d8
5077
5078	#define REG_A5XX_UNKNOWN_E7D9 0x0000e7d9
5079
5080	#define REG_A5XX_HLSQ_CS_CONSTLEN 0x0000e7dc
5081
5082	#define REG_A5XX_HLSQ_CS_INSTRLEN 0x0000e7dd
5083
5084	#define REG_A5XX_RB_2D_BLIT_CNTL 0x00002100
5085
5086	#define REG_A5XX_RB_2D_SRC_SOLID_DW0 0x00002101
5087
5088	#define REG_A5XX_RB_2D_SRC_SOLID_DW1 0x00002102
5089
5090	#define REG_A5XX_RB_2D_SRC_SOLID_DW2 0x00002103
5091
5092	#define REG_A5XX_RB_2D_SRC_SOLID_DW3 0x00002104
5093
5094	#define REG_A5XX_RB_2D_SRC_INFO 0x00002107
5095	#define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
5096	#define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
5097	static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
5098	{
5099	return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK;
5100	}
5101	#define A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
5102	#define A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT 8
5103	static inline uint32_t A5XX_RB_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val)
5104	{
5105	return ((val) << A5XX_RB_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_SRC_INFO_TILE_MODE__MASK;
5106	}
5107	#define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
5108	#define A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
5109	static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
5110	{
5111	return ((val) << A5XX_RB_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_SRC_INFO_COLOR_SWAP__MASK;
5112	}
5113	#define A5XX_RB_2D_SRC_INFO_FLAGS 0x00001000
5114	#define A5XX_RB_2D_SRC_INFO_SRGB 0x00002000
5115
5116	#define REG_A5XX_RB_2D_SRC_LO 0x00002108
5117
5118	#define REG_A5XX_RB_2D_SRC_HI 0x00002109
5119
5120	#define REG_A5XX_RB_2D_SRC_SIZE 0x0000210a
5121	#define A5XX_RB_2D_SRC_SIZE_PITCH__MASK 0x0000ffff
5122	#define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT 0
5123	static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val)
5124	{
5125	assert(!(val & 0x3f));
5126	return (((val >> 6)) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK;
5127	}
5128	#define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK 0xffff0000
5129	#define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT 16
5130	static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val)
5131	{
5132	assert(!(val & 0x3f));
5133	return (((val >> 6)) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK;
5134	}
5135
5136	#define REG_A5XX_RB_2D_DST_INFO 0x00002110
5137	#define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
5138	#define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
5139	static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
5140	{
5141	return ((val) << A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK;
5142	}
5143	#define A5XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300
5144	#define A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8
5145	static inline uint32_t A5XX_RB_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val)
5146	{
5147	return ((val) << A5XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_RB_2D_DST_INFO_TILE_MODE__MASK;
5148	}
5149	#define A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
5150	#define A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10
5151	static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
5152	{
5153	return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
5154	}
5155	#define A5XX_RB_2D_DST_INFO_FLAGS 0x00001000
5156	#define A5XX_RB_2D_DST_INFO_SRGB 0x00002000
5157
5158	#define REG_A5XX_RB_2D_DST_LO 0x00002111
5159
5160	#define REG_A5XX_RB_2D_DST_HI 0x00002112
5161
5162	#define REG_A5XX_RB_2D_DST_SIZE 0x00002113
5163	#define A5XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff
5164	#define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT 0
5165	static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
5166	{
5167	assert(!(val & 0x3f));
5168	return (((val >> 6)) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_PITCH__MASK;
5169	}
5170	#define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK 0xffff0000
5171	#define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT 16
5172	static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val)
5173	{
5174	assert(!(val & 0x3f));
5175	return (((val >> 6)) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK;
5176	}
5177
5178	#define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140
5179
5180	#define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141
5181
5182	#define REG_A5XX_RB_2D_SRC_FLAGS_PITCH 0x00002142
5183	#define A5XX_RB_2D_SRC_FLAGS_PITCH__MASK 0xffffffff
5184	#define A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT 0
5185	static inline uint32_t A5XX_RB_2D_SRC_FLAGS_PITCH(uint32_t val)
5186	{
5187	assert(!(val & 0x3f));
5188	return (((val >> 6)) << A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_SRC_FLAGS_PITCH__MASK;
5189	}
5190
5191	#define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143
5192
5193	#define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144
5194
5195	#define REG_A5XX_RB_2D_DST_FLAGS_PITCH 0x00002145
5196	#define A5XX_RB_2D_DST_FLAGS_PITCH__MASK 0xffffffff
5197	#define A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0
5198	static inline uint32_t A5XX_RB_2D_DST_FLAGS_PITCH(uint32_t val)
5199	{
5200	assert(!(val & 0x3f));
5201	return (((val >> 6)) << A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_DST_FLAGS_PITCH__MASK;
5202	}
5203
5204	#define REG_A5XX_GRAS_2D_BLIT_CNTL 0x00002180
5205
5206	#define REG_A5XX_GRAS_2D_SRC_INFO 0x00002181
5207	#define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
5208	#define A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0
5209	static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
5210	{
5211	return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_FORMAT__MASK;
5212	}
5213	#define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300
5214	#define A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT 8
5215	static inline uint32_t A5XX_GRAS_2D_SRC_INFO_TILE_MODE(enum a5xx_tile_mode val)
5216	{
5217	return ((val) << A5XX_GRAS_2D_SRC_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_SRC_INFO_TILE_MODE__MASK;
5218	}
5219	#define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00
5220	#define A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10
5221	static inline uint32_t A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
5222	{
5223	return ((val) << A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_SRC_INFO_COLOR_SWAP__MASK;
5224	}
5225	#define A5XX_GRAS_2D_SRC_INFO_FLAGS 0x00001000
5226	#define A5XX_GRAS_2D_SRC_INFO_SRGB 0x00002000
5227
5228	#define REG_A5XX_GRAS_2D_DST_INFO 0x00002182
5229	#define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
5230	#define A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
5231	static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT(enum a5xx_color_fmt val)
5232	{
5233	return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_FORMAT__MASK;
5234	}
5235	#define A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK 0x00000300
5236	#define A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT 8
5237	static inline uint32_t A5XX_GRAS_2D_DST_INFO_TILE_MODE(enum a5xx_tile_mode val)
5238	{
5239	return ((val) << A5XX_GRAS_2D_DST_INFO_TILE_MODE__SHIFT) & A5XX_GRAS_2D_DST_INFO_TILE_MODE__MASK;
5240	}
5241	#define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00
5242	#define A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT 10
5243	static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
5244	{
5245	return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK;
5246	}
5247	#define A5XX_GRAS_2D_DST_INFO_FLAGS 0x00001000
5248	#define A5XX_GRAS_2D_DST_INFO_SRGB 0x00002000
5249
5250	#define REG_A5XX_UNKNOWN_2184 0x00002184
5251
5252	#define REG_A5XX_TEX_SAMP_0 0x00000000
5253	#define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
5254	#define A5XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
5255	#define A5XX_TEX_SAMP_0_XY_MAG__SHIFT 1
5256	static inline uint32_t A5XX_TEX_SAMP_0_XY_MAG(enum a5xx_tex_filter val)
5257	{
5258	return ((val) << A5XX_TEX_SAMP_0_XY_MAG__SHIFT) & A5XX_TEX_SAMP_0_XY_MAG__MASK;
5259	}
5260	#define A5XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018
5261	#define A5XX_TEX_SAMP_0_XY_MIN__SHIFT 3
5262	static inline uint32_t A5XX_TEX_SAMP_0_XY_MIN(enum a5xx_tex_filter val)
5263	{
5264	return ((val) << A5XX_TEX_SAMP_0_XY_MIN__SHIFT) & A5XX_TEX_SAMP_0_XY_MIN__MASK;
5265	}
5266	#define A5XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0
5267	#define A5XX_TEX_SAMP_0_WRAP_S__SHIFT 5
5268	static inline uint32_t A5XX_TEX_SAMP_0_WRAP_S(enum a5xx_tex_clamp val)
5269	{
5270	return ((val) << A5XX_TEX_SAMP_0_WRAP_S__SHIFT) & A5XX_TEX_SAMP_0_WRAP_S__MASK;
5271	}
5272	#define A5XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700
5273	#define A5XX_TEX_SAMP_0_WRAP_T__SHIFT 8
5274	static inline uint32_t A5XX_TEX_SAMP_0_WRAP_T(enum a5xx_tex_clamp val)
5275	{
5276	return ((val) << A5XX_TEX_SAMP_0_WRAP_T__SHIFT) & A5XX_TEX_SAMP_0_WRAP_T__MASK;
5277	}
5278	#define A5XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800
5279	#define A5XX_TEX_SAMP_0_WRAP_R__SHIFT 11
5280	static inline uint32_t A5XX_TEX_SAMP_0_WRAP_R(enum a5xx_tex_clamp val)
5281	{
5282	return ((val) << A5XX_TEX_SAMP_0_WRAP_R__SHIFT) & A5XX_TEX_SAMP_0_WRAP_R__MASK;
5283	}
5284	#define A5XX_TEX_SAMP_0_ANISO__MASK 0x0001c000
5285	#define A5XX_TEX_SAMP_0_ANISO__SHIFT 14
5286	static inline uint32_t A5XX_TEX_SAMP_0_ANISO(enum a5xx_tex_aniso val)
5287	{
5288	return ((val) << A5XX_TEX_SAMP_0_ANISO__SHIFT) & A5XX_TEX_SAMP_0_ANISO__MASK;
5289	}
5290	#define A5XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000
5291	#define A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19
5292	static inline uint32_t A5XX_TEX_SAMP_0_LOD_BIAS(float val)
5293	{
5294	return ((((int32_t)(val * 256.0))) << A5XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A5XX_TEX_SAMP_0_LOD_BIAS__MASK;
5295	}
5296
5297	#define REG_A5XX_TEX_SAMP_1 0x00000001
5298	#define A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e
5299	#define A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1
5300	static inline uint32_t A5XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val)
5301	{
5302	return ((val) << A5XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A5XX_TEX_SAMP_1_COMPARE_FUNC__MASK;
5303	}
5304	#define A5XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010
5305	#define A5XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020
5306	#define A5XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040
5307	#define A5XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00
5308	#define A5XX_TEX_SAMP_1_MAX_LOD__SHIFT 8
5309	static inline uint32_t A5XX_TEX_SAMP_1_MAX_LOD(float val)
5310	{
5311	return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A5XX_TEX_SAMP_1_MAX_LOD__MASK;
5312	}
5313	#define A5XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000
5314	#define A5XX_TEX_SAMP_1_MIN_LOD__SHIFT 20
5315	static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val)
5316	{
5317	return ((((uint32_t)(val * 256.0))) << A5XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A5XX_TEX_SAMP_1_MIN_LOD__MASK;
5318	}
5319
5320	#define REG_A5XX_TEX_SAMP_2 0x00000002
5321	#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xffffff80
5322	#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 7
5323	static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
5324	{
5325	return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
5326	}
5327
5328	#define REG_A5XX_TEX_SAMP_3 0x00000003
5329
5330	#define REG_A5XX_TEX_CONST_0 0x00000000
5331	#define A5XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
5332	#define A5XX_TEX_CONST_0_TILE_MODE__SHIFT 0
5333	static inline uint32_t A5XX_TEX_CONST_0_TILE_MODE(enum a5xx_tile_mode val)
5334	{
5335	return ((val) << A5XX_TEX_CONST_0_TILE_MODE__SHIFT) & A5XX_TEX_CONST_0_TILE_MODE__MASK;
5336	}
5337	#define A5XX_TEX_CONST_0_SRGB 0x00000004
5338	#define A5XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
5339	#define A5XX_TEX_CONST_0_SWIZ_X__SHIFT 4
5340	static inline uint32_t A5XX_TEX_CONST_0_SWIZ_X(enum a5xx_tex_swiz val)
5341	{
5342	return ((val) << A5XX_TEX_CONST_0_SWIZ_X__SHIFT) & A5XX_TEX_CONST_0_SWIZ_X__MASK;
5343	}
5344	#define A5XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
5345	#define A5XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
5346	static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Y(enum a5xx_tex_swiz val)
5347	{
5348	return ((val) << A5XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Y__MASK;
5349	}
5350	#define A5XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
5351	#define A5XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
5352	static inline uint32_t A5XX_TEX_CONST_0_SWIZ_Z(enum a5xx_tex_swiz val)
5353	{
5354	return ((val) << A5XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A5XX_TEX_CONST_0_SWIZ_Z__MASK;
5355	}
5356	#define A5XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
5357	#define A5XX_TEX_CONST_0_SWIZ_W__SHIFT 13
5358	static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val)
5359	{
5360	return ((val) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT) & A5XX_TEX_CONST_0_SWIZ_W__MASK;
5361	}
5362	#define A5XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
5363	#define A5XX_TEX_CONST_0_MIPLVLS__SHIFT 16
5364	static inline uint32_t A5XX_TEX_CONST_0_MIPLVLS(uint32_t val)
5365	{
5366	return ((val) << A5XX_TEX_CONST_0_MIPLVLS__SHIFT) & A5XX_TEX_CONST_0_MIPLVLS__MASK;
5367	}
5368	#define A5XX_TEX_CONST_0_SAMPLES__MASK 0x00300000
5369	#define A5XX_TEX_CONST_0_SAMPLES__SHIFT 20
5370	static inline uint32_t A5XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val)
5371	{
5372	return ((val) << A5XX_TEX_CONST_0_SAMPLES__SHIFT) & A5XX_TEX_CONST_0_SAMPLES__MASK;
5373	}
5374	#define A5XX_TEX_CONST_0_FMT__MASK 0x3fc00000
5375	#define A5XX_TEX_CONST_0_FMT__SHIFT 22
5376	static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val)
5377	{
5378	return ((val) << A5XX_TEX_CONST_0_FMT__SHIFT) & A5XX_TEX_CONST_0_FMT__MASK;
5379	}
5380	#define A5XX_TEX_CONST_0_SWAP__MASK 0xc0000000
5381	#define A5XX_TEX_CONST_0_SWAP__SHIFT 30
5382	static inline uint32_t A5XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val)
5383	{
5384	return ((val) << A5XX_TEX_CONST_0_SWAP__SHIFT) & A5XX_TEX_CONST_0_SWAP__MASK;
5385	}
5386
5387	#define REG_A5XX_TEX_CONST_1 0x00000001
5388	#define A5XX_TEX_CONST_1_WIDTH__MASK 0x00007fff
5389	#define A5XX_TEX_CONST_1_WIDTH__SHIFT 0
5390	static inline uint32_t A5XX_TEX_CONST_1_WIDTH(uint32_t val)
5391	{
5392	return ((val) << A5XX_TEX_CONST_1_WIDTH__SHIFT) & A5XX_TEX_CONST_1_WIDTH__MASK;
5393	}
5394	#define A5XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000
5395	#define A5XX_TEX_CONST_1_HEIGHT__SHIFT 15
5396	static inline uint32_t A5XX_TEX_CONST_1_HEIGHT(uint32_t val)
5397	{
5398	return ((val) << A5XX_TEX_CONST_1_HEIGHT__SHIFT) & A5XX_TEX_CONST_1_HEIGHT__MASK;
5399	}
5400
5401	#define REG_A5XX_TEX_CONST_2 0x00000002
5402	#define A5XX_TEX_CONST_2_BUFFER 0x00000010
5403	#define A5XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f
5404	#define A5XX_TEX_CONST_2_PITCHALIGN__SHIFT 0
5405	static inline uint32_t A5XX_TEX_CONST_2_PITCHALIGN(uint32_t val)
5406	{
5407	return ((val) << A5XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A5XX_TEX_CONST_2_PITCHALIGN__MASK;
5408	}
5409	#define A5XX_TEX_CONST_2_PITCH__MASK 0x1fffff80
5410	#define A5XX_TEX_CONST_2_PITCH__SHIFT 7
5411	static inline uint32_t A5XX_TEX_CONST_2_PITCH(uint32_t val)
5412	{
5413	return ((val) << A5XX_TEX_CONST_2_PITCH__SHIFT) & A5XX_TEX_CONST_2_PITCH__MASK;
5414	}
5415	#define A5XX_TEX_CONST_2_TYPE__MASK 0xe0000000
5416	#define A5XX_TEX_CONST_2_TYPE__SHIFT 29
5417	static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val)
5418	{
5419	return ((val) << A5XX_TEX_CONST_2_TYPE__SHIFT) & A5XX_TEX_CONST_2_TYPE__MASK;
5420	}
5421
5422	#define REG_A5XX_TEX_CONST_3 0x00000003
5423	#define A5XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff
5424	#define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0
5425	static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val)
5426	{
5427	assert(!(val & 0xfff));
5428	return (((val >> 12)) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK;
5429	}
5430	#define A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000
5431	#define A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23
5432	static inline uint32_t A5XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val)
5433	{
5434	assert(!(val & 0xfff));
5435	return (((val >> 12)) << A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK;
5436	}
5437	#define A5XX_TEX_CONST_3_TILE_ALL 0x08000000
5438	#define A5XX_TEX_CONST_3_FLAG 0x10000000
5439
5440	#define REG_A5XX_TEX_CONST_4 0x00000004
5441	#define A5XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0
5442	#define A5XX_TEX_CONST_4_BASE_LO__SHIFT 5
5443	static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val)
5444	{
5445	assert(!(val & 0x1f));
5446	return (((val >> 5)) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK;
5447	}
5448
5449	#define REG_A5XX_TEX_CONST_5 0x00000005
5450	#define A5XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff
5451	#define A5XX_TEX_CONST_5_BASE_HI__SHIFT 0
5452	static inline uint32_t A5XX_TEX_CONST_5_BASE_HI(uint32_t val)
5453	{
5454	return ((val) << A5XX_TEX_CONST_5_BASE_HI__SHIFT) & A5XX_TEX_CONST_5_BASE_HI__MASK;
5455	}
5456	#define A5XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000
5457	#define A5XX_TEX_CONST_5_DEPTH__SHIFT 17
5458	static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val)
5459	{
5460	return ((val) << A5XX_TEX_CONST_5_DEPTH__SHIFT) & A5XX_TEX_CONST_5_DEPTH__MASK;
5461	}
5462
5463	#define REG_A5XX_TEX_CONST_6 0x00000006
5464
5465	#define REG_A5XX_TEX_CONST_7 0x00000007
5466
5467	#define REG_A5XX_TEX_CONST_8 0x00000008
5468
5469	#define REG_A5XX_TEX_CONST_9 0x00000009
5470
5471	#define REG_A5XX_TEX_CONST_10 0x0000000a
5472
5473	#define REG_A5XX_TEX_CONST_11 0x0000000b
5474
5475	#define REG_A5XX_SSBO_0_0 0x00000000
5476	#define A5XX_SSBO_0_0_BASE_LO__MASK 0xffffffe0
5477	#define A5XX_SSBO_0_0_BASE_LO__SHIFT 5
5478	static inline uint32_t A5XX_SSBO_0_0_BASE_LO(uint32_t val)
5479	{
5480	assert(!(val & 0x1f));
5481	return (((val >> 5)) << A5XX_SSBO_0_0_BASE_LO__SHIFT) & A5XX_SSBO_0_0_BASE_LO__MASK;
5482	}
5483
5484	#define REG_A5XX_SSBO_0_1 0x00000001
5485	#define A5XX_SSBO_0_1_PITCH__MASK 0x003fffff
5486	#define A5XX_SSBO_0_1_PITCH__SHIFT 0
5487	static inline uint32_t A5XX_SSBO_0_1_PITCH(uint32_t val)
5488	{
5489	return ((val) << A5XX_SSBO_0_1_PITCH__SHIFT) & A5XX_SSBO_0_1_PITCH__MASK;
5490	}
5491
5492	#define REG_A5XX_SSBO_0_2 0x00000002
5493	#define A5XX_SSBO_0_2_ARRAY_PITCH__MASK 0x03fff000
5494	#define A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12
5495	static inline uint32_t A5XX_SSBO_0_2_ARRAY_PITCH(uint32_t val)
5496	{
5497	assert(!(val & 0xfff));
5498	return (((val >> 12)) << A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A5XX_SSBO_0_2_ARRAY_PITCH__MASK;
5499	}
5500
5501	#define REG_A5XX_SSBO_0_3 0x00000003
5502	#define A5XX_SSBO_0_3_CPP__MASK 0x0000003f
5503	#define A5XX_SSBO_0_3_CPP__SHIFT 0
5504	static inline uint32_t A5XX_SSBO_0_3_CPP(uint32_t val)
5505	{
5506	return ((val) << A5XX_SSBO_0_3_CPP__SHIFT) & A5XX_SSBO_0_3_CPP__MASK;
5507	}
5508
5509	#define REG_A5XX_SSBO_1_0 0x00000000
5510	#define A5XX_SSBO_1_0_FMT__MASK 0x0000ff00
5511	#define A5XX_SSBO_1_0_FMT__SHIFT 8
5512	static inline uint32_t A5XX_SSBO_1_0_FMT(enum a5xx_tex_fmt val)
5513	{
5514	return ((val) << A5XX_SSBO_1_0_FMT__SHIFT) & A5XX_SSBO_1_0_FMT__MASK;
5515	}
5516	#define A5XX_SSBO_1_0_WIDTH__MASK 0xffff0000
5517	#define A5XX_SSBO_1_0_WIDTH__SHIFT 16
5518	static inline uint32_t A5XX_SSBO_1_0_WIDTH(uint32_t val)
5519	{
5520	return ((val) << A5XX_SSBO_1_0_WIDTH__SHIFT) & A5XX_SSBO_1_0_WIDTH__MASK;
5521	}
5522
5523	#define REG_A5XX_SSBO_1_1 0x00000001
5524	#define A5XX_SSBO_1_1_HEIGHT__MASK 0x0000ffff
5525	#define A5XX_SSBO_1_1_HEIGHT__SHIFT 0
5526	static inline uint32_t A5XX_SSBO_1_1_HEIGHT(uint32_t val)
5527	{
5528	return ((val) << A5XX_SSBO_1_1_HEIGHT__SHIFT) & A5XX_SSBO_1_1_HEIGHT__MASK;
5529	}
5530	#define A5XX_SSBO_1_1_DEPTH__MASK 0xffff0000
5531	#define A5XX_SSBO_1_1_DEPTH__SHIFT 16
5532	static inline uint32_t A5XX_SSBO_1_1_DEPTH(uint32_t val)
5533	{
5534	return ((val) << A5XX_SSBO_1_1_DEPTH__SHIFT) & A5XX_SSBO_1_1_DEPTH__MASK;
5535	}
5536
5537	#define REG_A5XX_SSBO_2_0 0x00000000
5538	#define A5XX_SSBO_2_0_BASE_LO__MASK 0xffffffff
5539	#define A5XX_SSBO_2_0_BASE_LO__SHIFT 0
5540	static inline uint32_t A5XX_SSBO_2_0_BASE_LO(uint32_t val)
5541	{
5542	return ((val) << A5XX_SSBO_2_0_BASE_LO__SHIFT) & A5XX_SSBO_2_0_BASE_LO__MASK;
5543	}
5544
5545	#define REG_A5XX_SSBO_2_1 0x00000001
5546	#define A5XX_SSBO_2_1_BASE_HI__MASK 0xffffffff
5547	#define A5XX_SSBO_2_1_BASE_HI__SHIFT 0
5548	static inline uint32_t A5XX_SSBO_2_1_BASE_HI(uint32_t val)
5549	{
5550	return ((val) << A5XX_SSBO_2_1_BASE_HI__SHIFT) & A5XX_SSBO_2_1_BASE_HI__MASK;
5551	}
5552
5553	#define REG_A5XX_UBO_0 0x00000000
5554	#define A5XX_UBO_0_BASE_LO__MASK 0xffffffff
5555	#define A5XX_UBO_0_BASE_LO__SHIFT 0
5556	static inline uint32_t A5XX_UBO_0_BASE_LO(uint32_t val)
5557	{
5558	return ((val) << A5XX_UBO_0_BASE_LO__SHIFT) & A5XX_UBO_0_BASE_LO__MASK;
5559	}
5560
5561	#define REG_A5XX_UBO_1 0x00000001
5562	#define A5XX_UBO_1_BASE_HI__MASK 0x0001ffff
5563	#define A5XX_UBO_1_BASE_HI__SHIFT 0
5564	static inline uint32_t A5XX_UBO_1_BASE_HI(uint32_t val)
5565	{
5566	return ((val) << A5XX_UBO_1_BASE_HI__SHIFT) & A5XX_UBO_1_BASE_HI__MASK;
5567	}
5568
5569	#ifdef __cplusplus
5570	#endif
5571
5572	#endif /* A5XX_XML */
5573