1 | #ifndef A6XX_XML |
2 | #define A6XX_XML |
3 | |
4 | /* Autogenerated file, DO NOT EDIT manually! |
5 | |
6 | This file was generated by the rules-ng-ng gen_header.py tool in this git repository: |
7 | http://gitlab.freedesktop.org/mesa/mesa/ |
8 | git clone https://gitlab.freedesktop.org/mesa/mesa.git |
9 | |
10 | The rules-ng-ng source files this header was generated from are: |
11 | |
12 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 243381 bytes, from Sat Feb 24 09:06:40 2024) |
13 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023) |
14 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023) |
15 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85856 bytes, from Fri Feb 23 13:07:00 2024) |
16 | |
17 | Copyright (C) 2013-2024 by the following authors: |
18 | - Rob Clark <robdclark@gmail.com> Rob Clark |
19 | - Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin |
20 | |
21 | Permission is hereby granted, free of charge, to any person obtaining |
22 | a copy of this software and associated documentation files (the |
23 | "Software"), to deal in the Software without restriction, including |
24 | without limitation the rights to use, copy, modify, merge, publish, |
25 | distribute, sublicense, and/or sell copies of the Software, and to |
26 | permit persons to whom the Software is furnished to do so, subject to |
27 | the following conditions: |
28 | |
29 | The above copyright notice and this permission notice (including the |
30 | next paragraph) shall be included in all copies or substantial |
31 | portions of the Software. |
32 | |
33 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
34 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
35 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
36 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
37 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
38 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
39 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
40 | |
41 | */ |
42 | |
43 | #ifdef __KERNEL__ |
44 | #include <linux/bug.h> |
45 | #define assert(x) BUG_ON(!(x)) |
46 | #else |
47 | #include <assert.h> |
48 | #endif |
49 | |
50 | #ifdef __cplusplus |
51 | #define __struct_cast(X) |
52 | #else |
53 | #define __struct_cast(X) (struct X) |
54 | #endif |
55 | |
56 | enum a6xx_tile_mode { |
57 | TILE6_LINEAR = 0, |
58 | TILE6_2 = 2, |
59 | TILE6_3 = 3, |
60 | }; |
61 | |
62 | enum a6xx_format { |
63 | FMT6_A8_UNORM = 2, |
64 | FMT6_8_UNORM = 3, |
65 | FMT6_8_SNORM = 4, |
66 | FMT6_8_UINT = 5, |
67 | FMT6_8_SINT = 6, |
68 | FMT6_4_4_4_4_UNORM = 8, |
69 | FMT6_5_5_5_1_UNORM = 10, |
70 | FMT6_1_5_5_5_UNORM = 12, |
71 | FMT6_5_6_5_UNORM = 14, |
72 | FMT6_8_8_UNORM = 15, |
73 | FMT6_8_8_SNORM = 16, |
74 | FMT6_8_8_UINT = 17, |
75 | FMT6_8_8_SINT = 18, |
76 | FMT6_L8_A8_UNORM = 19, |
77 | FMT6_16_UNORM = 21, |
78 | FMT6_16_SNORM = 22, |
79 | FMT6_16_FLOAT = 23, |
80 | FMT6_16_UINT = 24, |
81 | FMT6_16_SINT = 25, |
82 | FMT6_8_8_8_UNORM = 33, |
83 | FMT6_8_8_8_SNORM = 34, |
84 | FMT6_8_8_8_UINT = 35, |
85 | FMT6_8_8_8_SINT = 36, |
86 | FMT6_8_8_8_8_UNORM = 48, |
87 | FMT6_8_8_8_X8_UNORM = 49, |
88 | FMT6_8_8_8_8_SNORM = 50, |
89 | FMT6_8_8_8_8_UINT = 51, |
90 | FMT6_8_8_8_8_SINT = 52, |
91 | FMT6_9_9_9_E5_FLOAT = 53, |
92 | FMT6_10_10_10_2_UNORM = 54, |
93 | FMT6_10_10_10_2_UNORM_DEST = 55, |
94 | FMT6_10_10_10_2_SNORM = 57, |
95 | FMT6_10_10_10_2_UINT = 58, |
96 | FMT6_10_10_10_2_SINT = 59, |
97 | FMT6_11_11_10_FLOAT = 66, |
98 | FMT6_16_16_UNORM = 67, |
99 | FMT6_16_16_SNORM = 68, |
100 | FMT6_16_16_FLOAT = 69, |
101 | FMT6_16_16_UINT = 70, |
102 | FMT6_16_16_SINT = 71, |
103 | FMT6_32_UNORM = 72, |
104 | FMT6_32_SNORM = 73, |
105 | FMT6_32_FLOAT = 74, |
106 | FMT6_32_UINT = 75, |
107 | FMT6_32_SINT = 76, |
108 | FMT6_32_FIXED = 77, |
109 | FMT6_16_16_16_UNORM = 88, |
110 | FMT6_16_16_16_SNORM = 89, |
111 | FMT6_16_16_16_FLOAT = 90, |
112 | FMT6_16_16_16_UINT = 91, |
113 | FMT6_16_16_16_SINT = 92, |
114 | FMT6_16_16_16_16_UNORM = 96, |
115 | FMT6_16_16_16_16_SNORM = 97, |
116 | FMT6_16_16_16_16_FLOAT = 98, |
117 | FMT6_16_16_16_16_UINT = 99, |
118 | FMT6_16_16_16_16_SINT = 100, |
119 | FMT6_32_32_UNORM = 101, |
120 | FMT6_32_32_SNORM = 102, |
121 | FMT6_32_32_FLOAT = 103, |
122 | FMT6_32_32_UINT = 104, |
123 | FMT6_32_32_SINT = 105, |
124 | FMT6_32_32_FIXED = 106, |
125 | FMT6_32_32_32_UNORM = 112, |
126 | FMT6_32_32_32_SNORM = 113, |
127 | FMT6_32_32_32_UINT = 114, |
128 | FMT6_32_32_32_SINT = 115, |
129 | FMT6_32_32_32_FLOAT = 116, |
130 | FMT6_32_32_32_FIXED = 117, |
131 | FMT6_32_32_32_32_UNORM = 128, |
132 | FMT6_32_32_32_32_SNORM = 129, |
133 | FMT6_32_32_32_32_FLOAT = 130, |
134 | FMT6_32_32_32_32_UINT = 131, |
135 | FMT6_32_32_32_32_SINT = 132, |
136 | FMT6_32_32_32_32_FIXED = 133, |
137 | FMT6_G8R8B8R8_422_UNORM = 140, |
138 | FMT6_R8G8R8B8_422_UNORM = 141, |
139 | FMT6_R8_G8B8_2PLANE_420_UNORM = 142, |
140 | FMT6_NV21 = 143, |
141 | FMT6_R8_G8_B8_3PLANE_420_UNORM = 144, |
142 | FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8 = 145, |
143 | FMT6_NV12_Y = 148, |
144 | FMT6_NV12_UV = 149, |
145 | FMT6_NV12_VU = 150, |
146 | FMT6_NV12_4R = 151, |
147 | FMT6_NV12_4R_Y = 152, |
148 | FMT6_NV12_4R_UV = 153, |
149 | FMT6_P010 = 154, |
150 | FMT6_P010_Y = 155, |
151 | FMT6_P010_UV = 156, |
152 | FMT6_TP10 = 157, |
153 | FMT6_TP10_Y = 158, |
154 | FMT6_TP10_UV = 159, |
155 | FMT6_Z24_UNORM_S8_UINT = 160, |
156 | FMT6_ETC2_RG11_UNORM = 171, |
157 | FMT6_ETC2_RG11_SNORM = 172, |
158 | FMT6_ETC2_R11_UNORM = 173, |
159 | FMT6_ETC2_R11_SNORM = 174, |
160 | FMT6_ETC1 = 175, |
161 | FMT6_ETC2_RGB8 = 176, |
162 | FMT6_ETC2_RGBA8 = 177, |
163 | FMT6_ETC2_RGB8A1 = 178, |
164 | FMT6_DXT1 = 179, |
165 | FMT6_DXT3 = 180, |
166 | FMT6_DXT5 = 181, |
167 | FMT6_RGTC1_UNORM = 183, |
168 | FMT6_RGTC1_SNORM = 184, |
169 | FMT6_RGTC2_UNORM = 187, |
170 | FMT6_RGTC2_SNORM = 188, |
171 | FMT6_BPTC_UFLOAT = 190, |
172 | FMT6_BPTC_FLOAT = 191, |
173 | FMT6_BPTC = 192, |
174 | FMT6_ASTC_4x4 = 193, |
175 | FMT6_ASTC_5x4 = 194, |
176 | FMT6_ASTC_5x5 = 195, |
177 | FMT6_ASTC_6x5 = 196, |
178 | FMT6_ASTC_6x6 = 197, |
179 | FMT6_ASTC_8x5 = 198, |
180 | FMT6_ASTC_8x6 = 199, |
181 | FMT6_ASTC_8x8 = 200, |
182 | FMT6_ASTC_10x5 = 201, |
183 | FMT6_ASTC_10x6 = 202, |
184 | FMT6_ASTC_10x8 = 203, |
185 | FMT6_ASTC_10x10 = 204, |
186 | FMT6_ASTC_12x10 = 205, |
187 | FMT6_ASTC_12x12 = 206, |
188 | FMT6_Z24_UINT_S8_UINT = 234, |
189 | FMT6_NONE = 255, |
190 | }; |
191 | |
192 | enum a6xx_polygon_mode { |
193 | POLYMODE6_POINTS = 1, |
194 | POLYMODE6_LINES = 2, |
195 | POLYMODE6_TRIANGLES = 3, |
196 | }; |
197 | |
198 | enum a6xx_depth_format { |
199 | DEPTH6_NONE = 0, |
200 | DEPTH6_16 = 1, |
201 | DEPTH6_24_8 = 2, |
202 | DEPTH6_32 = 4, |
203 | }; |
204 | |
205 | enum a6xx_shader_id { |
206 | A6XX_TP0_TMO_DATA = 9, |
207 | A6XX_TP0_SMO_DATA = 10, |
208 | A6XX_TP0_MIPMAP_BASE_DATA = 11, |
209 | A6XX_TP1_TMO_DATA = 25, |
210 | A6XX_TP1_SMO_DATA = 26, |
211 | A6XX_TP1_MIPMAP_BASE_DATA = 27, |
212 | A6XX_SP_INST_DATA = 41, |
213 | A6XX_SP_LB_0_DATA = 42, |
214 | A6XX_SP_LB_1_DATA = 43, |
215 | A6XX_SP_LB_2_DATA = 44, |
216 | A6XX_SP_LB_3_DATA = 45, |
217 | A6XX_SP_LB_4_DATA = 46, |
218 | A6XX_SP_LB_5_DATA = 47, |
219 | A6XX_SP_CB_BINDLESS_DATA = 48, |
220 | A6XX_SP_CB_LEGACY_DATA = 49, |
221 | A6XX_SP_UAV_DATA = 50, |
222 | A6XX_SP_INST_TAG = 51, |
223 | A6XX_SP_CB_BINDLESS_TAG = 52, |
224 | A6XX_SP_TMO_UMO_TAG = 53, |
225 | A6XX_SP_SMO_TAG = 54, |
226 | A6XX_SP_STATE_DATA = 55, |
227 | A6XX_HLSQ_CHUNK_CVS_RAM = 73, |
228 | A6XX_HLSQ_CHUNK_CPS_RAM = 74, |
229 | A6XX_HLSQ_CHUNK_CVS_RAM_TAG = 75, |
230 | A6XX_HLSQ_CHUNK_CPS_RAM_TAG = 76, |
231 | A6XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77, |
232 | A6XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78, |
233 | A6XX_HLSQ_CVS_MISC_RAM = 80, |
234 | A6XX_HLSQ_CPS_MISC_RAM = 81, |
235 | A6XX_HLSQ_INST_RAM = 82, |
236 | A6XX_HLSQ_GFX_CVS_CONST_RAM = 83, |
237 | A6XX_HLSQ_GFX_CPS_CONST_RAM = 84, |
238 | A6XX_HLSQ_CVS_MISC_RAM_TAG = 85, |
239 | A6XX_HLSQ_CPS_MISC_RAM_TAG = 86, |
240 | A6XX_HLSQ_INST_RAM_TAG = 87, |
241 | A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88, |
242 | A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89, |
243 | A6XX_HLSQ_PWR_REST_RAM = 90, |
244 | A6XX_HLSQ_PWR_REST_TAG = 91, |
245 | A6XX_HLSQ_DATAPATH_META = 96, |
246 | A6XX_HLSQ_FRONTEND_META = 97, |
247 | A6XX_HLSQ_INDIRECT_META = 98, |
248 | A6XX_HLSQ_BACKEND_META = 99, |
249 | A6XX_SP_LB_6_DATA = 112, |
250 | A6XX_SP_LB_7_DATA = 113, |
251 | A6XX_HLSQ_INST_RAM_1 = 115, |
252 | }; |
253 | |
254 | enum a7xx_statetype_id { |
255 | A7XX_TP0_NCTX_REG = 0, |
256 | A7XX_TP0_CTX0_3D_CVS_REG = 1, |
257 | A7XX_TP0_CTX0_3D_CPS_REG = 2, |
258 | A7XX_TP0_CTX1_3D_CVS_REG = 3, |
259 | A7XX_TP0_CTX1_3D_CPS_REG = 4, |
260 | A7XX_TP0_CTX2_3D_CPS_REG = 5, |
261 | A7XX_TP0_CTX3_3D_CPS_REG = 6, |
262 | A7XX_TP0_TMO_DATA = 9, |
263 | A7XX_TP0_SMO_DATA = 10, |
264 | A7XX_TP0_MIPMAP_BASE_DATA = 11, |
265 | A7XX_SP_NCTX_REG = 32, |
266 | A7XX_SP_CTX0_3D_CVS_REG = 33, |
267 | A7XX_SP_CTX0_3D_CPS_REG = 34, |
268 | A7XX_SP_CTX1_3D_CVS_REG = 35, |
269 | A7XX_SP_CTX1_3D_CPS_REG = 36, |
270 | A7XX_SP_CTX2_3D_CPS_REG = 37, |
271 | A7XX_SP_CTX3_3D_CPS_REG = 38, |
272 | A7XX_SP_INST_DATA = 39, |
273 | A7XX_SP_INST_DATA_1 = 40, |
274 | A7XX_SP_LB_0_DATA = 41, |
275 | A7XX_SP_LB_1_DATA = 42, |
276 | A7XX_SP_LB_2_DATA = 43, |
277 | A7XX_SP_LB_3_DATA = 44, |
278 | A7XX_SP_LB_4_DATA = 45, |
279 | A7XX_SP_LB_5_DATA = 46, |
280 | A7XX_SP_LB_6_DATA = 47, |
281 | A7XX_SP_LB_7_DATA = 48, |
282 | A7XX_SP_CB_RAM = 49, |
283 | A7XX_SP_LB_13_DATA = 50, |
284 | A7XX_SP_LB_14_DATA = 51, |
285 | A7XX_SP_INST_TAG = 52, |
286 | A7XX_SP_INST_DATA_2 = 53, |
287 | A7XX_SP_TMO_TAG = 54, |
288 | A7XX_SP_SMO_TAG = 55, |
289 | A7XX_SP_STATE_DATA = 56, |
290 | A7XX_SP_HWAVE_RAM = 57, |
291 | A7XX_SP_L0_INST_BUF = 58, |
292 | A7XX_SP_LB_8_DATA = 59, |
293 | A7XX_SP_LB_9_DATA = 60, |
294 | A7XX_SP_LB_10_DATA = 61, |
295 | A7XX_SP_LB_11_DATA = 62, |
296 | A7XX_SP_LB_12_DATA = 63, |
297 | A7XX_HLSQ_DATAPATH_DSTR_META = 64, |
298 | A7XX_HLSQ_L2STC_TAG_RAM = 67, |
299 | A7XX_HLSQ_L2STC_INFO_CMD = 68, |
300 | A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG = 69, |
301 | A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG = 70, |
302 | A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM = 71, |
303 | A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM = 72, |
304 | A7XX_HLSQ_CHUNK_CVS_RAM = 73, |
305 | A7XX_HLSQ_CHUNK_CPS_RAM = 74, |
306 | A7XX_HLSQ_CHUNK_CVS_RAM_TAG = 75, |
307 | A7XX_HLSQ_CHUNK_CPS_RAM_TAG = 76, |
308 | A7XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77, |
309 | A7XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78, |
310 | A7XX_HLSQ_CVS_MISC_RAM = 79, |
311 | A7XX_HLSQ_CPS_MISC_RAM = 80, |
312 | A7XX_HLSQ_CPS_MISC_RAM_1 = 81, |
313 | A7XX_HLSQ_INST_RAM = 82, |
314 | A7XX_HLSQ_GFX_CVS_CONST_RAM = 83, |
315 | A7XX_HLSQ_GFX_CPS_CONST_RAM = 84, |
316 | A7XX_HLSQ_CVS_MISC_RAM_TAG = 85, |
317 | A7XX_HLSQ_CPS_MISC_RAM_TAG = 86, |
318 | A7XX_HLSQ_INST_RAM_TAG = 87, |
319 | A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88, |
320 | A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89, |
321 | A7XX_HLSQ_GFX_LOCAL_MISC_RAM = 90, |
322 | A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG = 91, |
323 | A7XX_HLSQ_INST_RAM_1 = 92, |
324 | A7XX_HLSQ_STPROC_META = 93, |
325 | A7XX_HLSQ_BV_BE_META = 94, |
326 | A7XX_HLSQ_INST_RAM_2 = 95, |
327 | A7XX_HLSQ_DATAPATH_META = 96, |
328 | A7XX_HLSQ_FRONTEND_META = 97, |
329 | A7XX_HLSQ_INDIRECT_META = 98, |
330 | A7XX_HLSQ_BACKEND_META = 99, |
331 | }; |
332 | |
333 | enum a6xx_debugbus_id { |
334 | A6XX_DBGBUS_CP = 1, |
335 | A6XX_DBGBUS_RBBM = 2, |
336 | A6XX_DBGBUS_VBIF = 3, |
337 | A6XX_DBGBUS_HLSQ = 4, |
338 | A6XX_DBGBUS_UCHE = 5, |
339 | A6XX_DBGBUS_DPM = 6, |
340 | A6XX_DBGBUS_TESS = 7, |
341 | A6XX_DBGBUS_PC = 8, |
342 | A6XX_DBGBUS_VFDP = 9, |
343 | A6XX_DBGBUS_VPC = 10, |
344 | A6XX_DBGBUS_TSE = 11, |
345 | A6XX_DBGBUS_RAS = 12, |
346 | A6XX_DBGBUS_VSC = 13, |
347 | A6XX_DBGBUS_COM = 14, |
348 | A6XX_DBGBUS_LRZ = 16, |
349 | A6XX_DBGBUS_A2D = 17, |
350 | A6XX_DBGBUS_CCUFCHE = 18, |
351 | A6XX_DBGBUS_GMU_CX = 19, |
352 | A6XX_DBGBUS_RBP = 20, |
353 | A6XX_DBGBUS_DCS = 21, |
354 | A6XX_DBGBUS_DBGC = 22, |
355 | A6XX_DBGBUS_CX = 23, |
356 | A6XX_DBGBUS_GMU_GX = 24, |
357 | A6XX_DBGBUS_TPFCHE = 25, |
358 | A6XX_DBGBUS_GBIF_GX = 26, |
359 | A6XX_DBGBUS_GPC = 29, |
360 | A6XX_DBGBUS_LARC = 30, |
361 | A6XX_DBGBUS_HLSQ_SPTP = 31, |
362 | A6XX_DBGBUS_RB_0 = 32, |
363 | A6XX_DBGBUS_RB_1 = 33, |
364 | A6XX_DBGBUS_RB_2 = 34, |
365 | A6XX_DBGBUS_UCHE_WRAPPER = 36, |
366 | A6XX_DBGBUS_CCU_0 = 40, |
367 | A6XX_DBGBUS_CCU_1 = 41, |
368 | A6XX_DBGBUS_CCU_2 = 42, |
369 | A6XX_DBGBUS_VFD_0 = 56, |
370 | A6XX_DBGBUS_VFD_1 = 57, |
371 | A6XX_DBGBUS_VFD_2 = 58, |
372 | A6XX_DBGBUS_VFD_3 = 59, |
373 | A6XX_DBGBUS_VFD_4 = 60, |
374 | A6XX_DBGBUS_VFD_5 = 61, |
375 | A6XX_DBGBUS_SP_0 = 64, |
376 | A6XX_DBGBUS_SP_1 = 65, |
377 | A6XX_DBGBUS_SP_2 = 66, |
378 | A6XX_DBGBUS_TPL1_0 = 72, |
379 | A6XX_DBGBUS_TPL1_1 = 73, |
380 | A6XX_DBGBUS_TPL1_2 = 74, |
381 | A6XX_DBGBUS_TPL1_3 = 75, |
382 | A6XX_DBGBUS_TPL1_4 = 76, |
383 | A6XX_DBGBUS_TPL1_5 = 77, |
384 | A6XX_DBGBUS_SPTP_0 = 88, |
385 | A6XX_DBGBUS_SPTP_1 = 89, |
386 | A6XX_DBGBUS_SPTP_2 = 90, |
387 | A6XX_DBGBUS_SPTP_3 = 91, |
388 | A6XX_DBGBUS_SPTP_4 = 92, |
389 | A6XX_DBGBUS_SPTP_5 = 93, |
390 | }; |
391 | |
392 | enum a7xx_state_location { |
393 | A7XX_HLSQ_STATE = 0, |
394 | A7XX_HLSQ_DP = 1, |
395 | A7XX_SP_TOP = 2, |
396 | A7XX_USPTP = 3, |
397 | }; |
398 | |
399 | enum a7xx_pipe { |
400 | A7XX_PIPE_NONE = 0, |
401 | A7XX_PIPE_BR = 1, |
402 | A7XX_PIPE_BV = 2, |
403 | A7XX_PIPE_LPAC = 3, |
404 | }; |
405 | |
406 | enum a7xx_cluster { |
407 | A7XX_CLUSTER_NONE = 0, |
408 | A7XX_CLUSTER_FE = 1, |
409 | A7XX_CLUSTER_SP_VS = 2, |
410 | A7XX_CLUSTER_PC_VS = 3, |
411 | A7XX_CLUSTER_GRAS = 4, |
412 | A7XX_CLUSTER_SP_PS = 5, |
413 | A7XX_CLUSTER_VPC_PS = 6, |
414 | A7XX_CLUSTER_PS = 7, |
415 | }; |
416 | |
417 | enum a7xx_debugbus_id { |
418 | A7XX_DBGBUS_CP_0_0 = 1, |
419 | A7XX_DBGBUS_CP_0_1 = 2, |
420 | A7XX_DBGBUS_RBBM = 3, |
421 | A7XX_DBGBUS_GBIF_GX = 5, |
422 | A7XX_DBGBUS_GBIF_CX = 6, |
423 | A7XX_DBGBUS_HLSQ = 7, |
424 | A7XX_DBGBUS_UCHE_0 = 9, |
425 | A7XX_DBGBUS_UCHE_1 = 10, |
426 | A7XX_DBGBUS_TESS_BR = 13, |
427 | A7XX_DBGBUS_TESS_BV = 14, |
428 | A7XX_DBGBUS_PC_BR = 17, |
429 | A7XX_DBGBUS_PC_BV = 18, |
430 | A7XX_DBGBUS_VFDP_BR = 21, |
431 | A7XX_DBGBUS_VFDP_BV = 22, |
432 | A7XX_DBGBUS_VPC_BR = 25, |
433 | A7XX_DBGBUS_VPC_BV = 26, |
434 | A7XX_DBGBUS_TSE_BR = 29, |
435 | A7XX_DBGBUS_TSE_BV = 30, |
436 | A7XX_DBGBUS_RAS_BR = 33, |
437 | A7XX_DBGBUS_RAS_BV = 34, |
438 | A7XX_DBGBUS_VSC = 37, |
439 | A7XX_DBGBUS_COM_0 = 39, |
440 | A7XX_DBGBUS_LRZ_BR = 43, |
441 | A7XX_DBGBUS_LRZ_BV = 44, |
442 | A7XX_DBGBUS_UFC_0 = 47, |
443 | A7XX_DBGBUS_UFC_1 = 48, |
444 | A7XX_DBGBUS_GMU_GX = 55, |
445 | A7XX_DBGBUS_DBGC = 59, |
446 | A7XX_DBGBUS_CX = 60, |
447 | A7XX_DBGBUS_GMU_CX = 61, |
448 | A7XX_DBGBUS_GPC_BR = 62, |
449 | A7XX_DBGBUS_GPC_BV = 63, |
450 | A7XX_DBGBUS_LARC = 66, |
451 | A7XX_DBGBUS_HLSQ_SPTP = 68, |
452 | A7XX_DBGBUS_RB_0 = 70, |
453 | A7XX_DBGBUS_RB_1 = 71, |
454 | A7XX_DBGBUS_RB_2 = 72, |
455 | A7XX_DBGBUS_RB_3 = 73, |
456 | A7XX_DBGBUS_RB_4 = 74, |
457 | A7XX_DBGBUS_RB_5 = 75, |
458 | A7XX_DBGBUS_UCHE_WRAPPER = 102, |
459 | A7XX_DBGBUS_CCU_0 = 106, |
460 | A7XX_DBGBUS_CCU_1 = 107, |
461 | A7XX_DBGBUS_CCU_2 = 108, |
462 | A7XX_DBGBUS_CCU_3 = 109, |
463 | A7XX_DBGBUS_CCU_4 = 110, |
464 | A7XX_DBGBUS_CCU_5 = 111, |
465 | A7XX_DBGBUS_VFD_BR_0 = 138, |
466 | A7XX_DBGBUS_VFD_BR_1 = 139, |
467 | A7XX_DBGBUS_VFD_BR_2 = 140, |
468 | A7XX_DBGBUS_VFD_BR_3 = 141, |
469 | A7XX_DBGBUS_VFD_BR_4 = 142, |
470 | A7XX_DBGBUS_VFD_BR_5 = 143, |
471 | A7XX_DBGBUS_VFD_BR_6 = 144, |
472 | A7XX_DBGBUS_VFD_BR_7 = 145, |
473 | A7XX_DBGBUS_VFD_BV_0 = 202, |
474 | A7XX_DBGBUS_VFD_BV_1 = 203, |
475 | A7XX_DBGBUS_VFD_BV_2 = 204, |
476 | A7XX_DBGBUS_VFD_BV_3 = 205, |
477 | A7XX_DBGBUS_USP_0 = 234, |
478 | A7XX_DBGBUS_USP_1 = 235, |
479 | A7XX_DBGBUS_USP_2 = 236, |
480 | A7XX_DBGBUS_USP_3 = 237, |
481 | A7XX_DBGBUS_USP_4 = 238, |
482 | A7XX_DBGBUS_USP_5 = 239, |
483 | A7XX_DBGBUS_TP_0 = 266, |
484 | A7XX_DBGBUS_TP_1 = 267, |
485 | A7XX_DBGBUS_TP_2 = 268, |
486 | A7XX_DBGBUS_TP_3 = 269, |
487 | A7XX_DBGBUS_TP_4 = 270, |
488 | A7XX_DBGBUS_TP_5 = 271, |
489 | A7XX_DBGBUS_TP_6 = 272, |
490 | A7XX_DBGBUS_TP_7 = 273, |
491 | A7XX_DBGBUS_TP_8 = 274, |
492 | A7XX_DBGBUS_TP_9 = 275, |
493 | A7XX_DBGBUS_TP_10 = 276, |
494 | A7XX_DBGBUS_TP_11 = 277, |
495 | A7XX_DBGBUS_USPTP_0 = 330, |
496 | A7XX_DBGBUS_USPTP_1 = 331, |
497 | A7XX_DBGBUS_USPTP_2 = 332, |
498 | A7XX_DBGBUS_USPTP_3 = 333, |
499 | A7XX_DBGBUS_USPTP_4 = 334, |
500 | A7XX_DBGBUS_USPTP_5 = 335, |
501 | A7XX_DBGBUS_USPTP_6 = 336, |
502 | A7XX_DBGBUS_USPTP_7 = 337, |
503 | A7XX_DBGBUS_USPTP_8 = 338, |
504 | A7XX_DBGBUS_USPTP_9 = 339, |
505 | A7XX_DBGBUS_USPTP_10 = 340, |
506 | A7XX_DBGBUS_USPTP_11 = 341, |
507 | A7XX_DBGBUS_CCHE_0 = 396, |
508 | A7XX_DBGBUS_CCHE_1 = 397, |
509 | A7XX_DBGBUS_CCHE_2 = 398, |
510 | A7XX_DBGBUS_VPC_DSTR_0 = 408, |
511 | A7XX_DBGBUS_VPC_DSTR_1 = 409, |
512 | A7XX_DBGBUS_VPC_DSTR_2 = 410, |
513 | A7XX_DBGBUS_HLSQ_DP_STR_0 = 411, |
514 | A7XX_DBGBUS_HLSQ_DP_STR_1 = 412, |
515 | A7XX_DBGBUS_HLSQ_DP_STR_2 = 413, |
516 | A7XX_DBGBUS_HLSQ_DP_STR_3 = 414, |
517 | A7XX_DBGBUS_HLSQ_DP_STR_4 = 415, |
518 | A7XX_DBGBUS_HLSQ_DP_STR_5 = 416, |
519 | A7XX_DBGBUS_UFC_DSTR_0 = 443, |
520 | A7XX_DBGBUS_UFC_DSTR_1 = 444, |
521 | A7XX_DBGBUS_UFC_DSTR_2 = 445, |
522 | A7XX_DBGBUS_CGC_SUBCORE = 446, |
523 | A7XX_DBGBUS_CGC_CORE = 447, |
524 | }; |
525 | |
526 | enum a6xx_cp_perfcounter_select { |
527 | PERF_CP_ALWAYS_COUNT = 0, |
528 | PERF_CP_BUSY_GFX_CORE_IDLE = 1, |
529 | PERF_CP_BUSY_CYCLES = 2, |
530 | PERF_CP_NUM_PREEMPTIONS = 3, |
531 | PERF_CP_PREEMPTION_REACTION_DELAY = 4, |
532 | PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 5, |
533 | PERF_CP_PREEMPTION_SWITCH_IN_TIME = 6, |
534 | PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 7, |
535 | PERF_CP_PREDICATED_DRAWS_KILLED = 8, |
536 | PERF_CP_MODE_SWITCH = 9, |
537 | PERF_CP_ZPASS_DONE = 10, |
538 | PERF_CP_CONTEXT_DONE = 11, |
539 | PERF_CP_CACHE_FLUSH = 12, |
540 | PERF_CP_LONG_PREEMPTIONS = 13, |
541 | PERF_CP_SQE_I_CACHE_STARVE = 14, |
542 | PERF_CP_SQE_IDLE = 15, |
543 | PERF_CP_SQE_PM4_STARVE_RB_IB = 16, |
544 | PERF_CP_SQE_PM4_STARVE_SDS = 17, |
545 | PERF_CP_SQE_MRB_STARVE = 18, |
546 | PERF_CP_SQE_RRB_STARVE = 19, |
547 | PERF_CP_SQE_VSD_STARVE = 20, |
548 | PERF_CP_VSD_DECODE_STARVE = 21, |
549 | PERF_CP_SQE_PIPE_OUT_STALL = 22, |
550 | PERF_CP_SQE_SYNC_STALL = 23, |
551 | PERF_CP_SQE_PM4_WFI_STALL = 24, |
552 | PERF_CP_SQE_SYS_WFI_STALL = 25, |
553 | PERF_CP_SQE_T4_EXEC = 26, |
554 | PERF_CP_SQE_LOAD_STATE_EXEC = 27, |
555 | PERF_CP_SQE_SAVE_SDS_STATE = 28, |
556 | PERF_CP_SQE_DRAW_EXEC = 29, |
557 | PERF_CP_SQE_CTXT_REG_BUNCH_EXEC = 30, |
558 | PERF_CP_SQE_EXEC_PROFILED = 31, |
559 | PERF_CP_MEMORY_POOL_EMPTY = 32, |
560 | PERF_CP_MEMORY_POOL_SYNC_STALL = 33, |
561 | PERF_CP_MEMORY_POOL_ABOVE_THRESH = 34, |
562 | PERF_CP_AHB_WR_STALL_PRE_DRAWS = 35, |
563 | PERF_CP_AHB_STALL_SQE_GMU = 36, |
564 | PERF_CP_AHB_STALL_SQE_WR_OTHER = 37, |
565 | PERF_CP_AHB_STALL_SQE_RD_OTHER = 38, |
566 | PERF_CP_CLUSTER0_EMPTY = 39, |
567 | PERF_CP_CLUSTER1_EMPTY = 40, |
568 | PERF_CP_CLUSTER2_EMPTY = 41, |
569 | PERF_CP_CLUSTER3_EMPTY = 42, |
570 | PERF_CP_CLUSTER4_EMPTY = 43, |
571 | PERF_CP_CLUSTER5_EMPTY = 44, |
572 | PERF_CP_PM4_DATA = 45, |
573 | = 46, |
574 | PERF_CP_VBIF_READ_BEATS = 47, |
575 | PERF_CP_VBIF_WRITE_BEATS = 48, |
576 | PERF_CP_SQE_INSTR_COUNTER = 49, |
577 | }; |
578 | |
579 | enum a6xx_rbbm_perfcounter_select { |
580 | PERF_RBBM_ALWAYS_COUNT = 0, |
581 | PERF_RBBM_ALWAYS_ON = 1, |
582 | PERF_RBBM_TSE_BUSY = 2, |
583 | PERF_RBBM_RAS_BUSY = 3, |
584 | PERF_RBBM_PC_DCALL_BUSY = 4, |
585 | PERF_RBBM_PC_VSD_BUSY = 5, |
586 | PERF_RBBM_STATUS_MASKED = 6, |
587 | PERF_RBBM_COM_BUSY = 7, |
588 | PERF_RBBM_DCOM_BUSY = 8, |
589 | PERF_RBBM_VBIF_BUSY = 9, |
590 | PERF_RBBM_VSC_BUSY = 10, |
591 | PERF_RBBM_TESS_BUSY = 11, |
592 | PERF_RBBM_UCHE_BUSY = 12, |
593 | PERF_RBBM_HLSQ_BUSY = 13, |
594 | }; |
595 | |
596 | enum a6xx_pc_perfcounter_select { |
597 | PERF_PC_BUSY_CYCLES = 0, |
598 | PERF_PC_WORKING_CYCLES = 1, |
599 | PERF_PC_STALL_CYCLES_VFD = 2, |
600 | PERF_PC_STALL_CYCLES_TSE = 3, |
601 | PERF_PC_STALL_CYCLES_VPC = 4, |
602 | PERF_PC_STALL_CYCLES_UCHE = 5, |
603 | PERF_PC_STALL_CYCLES_TESS = 6, |
604 | PERF_PC_STALL_CYCLES_TSE_ONLY = 7, |
605 | PERF_PC_STALL_CYCLES_VPC_ONLY = 8, |
606 | PERF_PC_PASS1_TF_STALL_CYCLES = 9, |
607 | PERF_PC_STARVE_CYCLES_FOR_INDEX = 10, |
608 | PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11, |
609 | PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12, |
610 | PERF_PC_STARVE_CYCLES_FOR_POSITION = 13, |
611 | PERF_PC_STARVE_CYCLES_DI = 14, |
612 | PERF_PC_VIS_STREAMS_LOADED = 15, |
613 | PERF_PC_INSTANCES = 16, |
614 | PERF_PC_VPC_PRIMITIVES = 17, |
615 | PERF_PC_DEAD_PRIM = 18, |
616 | PERF_PC_LIVE_PRIM = 19, |
617 | PERF_PC_VERTEX_HITS = 20, |
618 | PERF_PC_IA_VERTICES = 21, |
619 | PERF_PC_IA_PRIMITIVES = 22, |
620 | PERF_PC_GS_PRIMITIVES = 23, |
621 | PERF_PC_HS_INVOCATIONS = 24, |
622 | PERF_PC_DS_INVOCATIONS = 25, |
623 | PERF_PC_VS_INVOCATIONS = 26, |
624 | PERF_PC_GS_INVOCATIONS = 27, |
625 | PERF_PC_DS_PRIMITIVES = 28, |
626 | PERF_PC_VPC_POS_DATA_TRANSACTION = 29, |
627 | PERF_PC_3D_DRAWCALLS = 30, |
628 | PERF_PC_2D_DRAWCALLS = 31, |
629 | PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32, |
630 | PERF_TESS_BUSY_CYCLES = 33, |
631 | PERF_TESS_WORKING_CYCLES = 34, |
632 | PERF_TESS_STALL_CYCLES_PC = 35, |
633 | PERF_TESS_STARVE_CYCLES_PC = 36, |
634 | PERF_PC_TSE_TRANSACTION = 37, |
635 | PERF_PC_TSE_VERTEX = 38, |
636 | PERF_PC_TESS_PC_UV_TRANS = 39, |
637 | PERF_PC_TESS_PC_UV_PATCHES = 40, |
638 | PERF_PC_TESS_FACTOR_TRANS = 41, |
639 | }; |
640 | |
641 | enum a6xx_vfd_perfcounter_select { |
642 | PERF_VFD_BUSY_CYCLES = 0, |
643 | PERF_VFD_STALL_CYCLES_UCHE = 1, |
644 | PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2, |
645 | PERF_VFD_STALL_CYCLES_SP_INFO = 3, |
646 | PERF_VFD_STALL_CYCLES_SP_ATTR = 4, |
647 | PERF_VFD_STARVE_CYCLES_UCHE = 5, |
648 | PERF_VFD_RBUFFER_FULL = 6, |
649 | PERF_VFD_ATTR_INFO_FIFO_FULL = 7, |
650 | PERF_VFD_DECODED_ATTRIBUTE_BYTES = 8, |
651 | PERF_VFD_NUM_ATTRIBUTES = 9, |
652 | PERF_VFD_UPPER_SHADER_FIBERS = 10, |
653 | PERF_VFD_LOWER_SHADER_FIBERS = 11, |
654 | PERF_VFD_MODE_0_FIBERS = 12, |
655 | PERF_VFD_MODE_1_FIBERS = 13, |
656 | PERF_VFD_MODE_2_FIBERS = 14, |
657 | PERF_VFD_MODE_3_FIBERS = 15, |
658 | PERF_VFD_MODE_4_FIBERS = 16, |
659 | PERF_VFD_TOTAL_VERTICES = 17, |
660 | PERF_VFDP_STALL_CYCLES_VFD = 18, |
661 | PERF_VFDP_STALL_CYCLES_VFD_INDEX = 19, |
662 | PERF_VFDP_STALL_CYCLES_VFD_PROG = 20, |
663 | PERF_VFDP_STARVE_CYCLES_PC = 21, |
664 | PERF_VFDP_VS_STAGE_WAVES = 22, |
665 | }; |
666 | |
667 | enum a6xx_hlsq_perfcounter_select { |
668 | PERF_HLSQ_BUSY_CYCLES = 0, |
669 | PERF_HLSQ_STALL_CYCLES_UCHE = 1, |
670 | PERF_HLSQ_STALL_CYCLES_SP_STATE = 2, |
671 | PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3, |
672 | PERF_HLSQ_UCHE_LATENCY_CYCLES = 4, |
673 | PERF_HLSQ_UCHE_LATENCY_COUNT = 5, |
674 | PERF_HLSQ_FS_STAGE_1X_WAVES = 6, |
675 | PERF_HLSQ_FS_STAGE_2X_WAVES = 7, |
676 | PERF_HLSQ_QUADS = 8, |
677 | PERF_HLSQ_CS_INVOCATIONS = 9, |
678 | PERF_HLSQ_COMPUTE_DRAWCALLS = 10, |
679 | PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING = 11, |
680 | PERF_HLSQ_DUAL_FS_PROG_ACTIVE = 12, |
681 | PERF_HLSQ_DUAL_VS_PROG_ACTIVE = 13, |
682 | PERF_HLSQ_FS_BATCH_COUNT_ZERO = 14, |
683 | PERF_HLSQ_VS_BATCH_COUNT_ZERO = 15, |
684 | PERF_HLSQ_WAVE_PENDING_NO_QUAD = 16, |
685 | PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE = 17, |
686 | PERF_HLSQ_STALL_CYCLES_VPC = 18, |
687 | PERF_HLSQ_PIXELS = 19, |
688 | PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC = 20, |
689 | }; |
690 | |
691 | enum a6xx_vpc_perfcounter_select { |
692 | PERF_VPC_BUSY_CYCLES = 0, |
693 | PERF_VPC_WORKING_CYCLES = 1, |
694 | PERF_VPC_STALL_CYCLES_UCHE = 2, |
695 | PERF_VPC_STALL_CYCLES_VFD_WACK = 3, |
696 | PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4, |
697 | PERF_VPC_STALL_CYCLES_PC = 5, |
698 | PERF_VPC_STALL_CYCLES_SP_LM = 6, |
699 | PERF_VPC_STARVE_CYCLES_SP = 7, |
700 | PERF_VPC_STARVE_CYCLES_LRZ = 8, |
701 | PERF_VPC_PC_PRIMITIVES = 9, |
702 | PERF_VPC_SP_COMPONENTS = 10, |
703 | PERF_VPC_STALL_CYCLES_VPCRAM_POS = 11, |
704 | PERF_VPC_LRZ_ASSIGN_PRIMITIVES = 12, |
705 | PERF_VPC_RB_VISIBLE_PRIMITIVES = 13, |
706 | PERF_VPC_LM_TRANSACTION = 14, |
707 | PERF_VPC_STREAMOUT_TRANSACTION = 15, |
708 | PERF_VPC_VS_BUSY_CYCLES = 16, |
709 | PERF_VPC_PS_BUSY_CYCLES = 17, |
710 | PERF_VPC_VS_WORKING_CYCLES = 18, |
711 | PERF_VPC_PS_WORKING_CYCLES = 19, |
712 | PERF_VPC_STARVE_CYCLES_RB = 20, |
713 | PERF_VPC_NUM_VPCRAM_READ_POS = 21, |
714 | PERF_VPC_WIT_FULL_CYCLES = 22, |
715 | PERF_VPC_VPCRAM_FULL_CYCLES = 23, |
716 | PERF_VPC_LM_FULL_WAIT_FOR_INTP_END = 24, |
717 | PERF_VPC_NUM_VPCRAM_WRITE = 25, |
718 | PERF_VPC_NUM_VPCRAM_READ_SO = 26, |
719 | PERF_VPC_NUM_ATTR_REQ_LM = 27, |
720 | }; |
721 | |
722 | enum a6xx_tse_perfcounter_select { |
723 | PERF_TSE_BUSY_CYCLES = 0, |
724 | PERF_TSE_CLIPPING_CYCLES = 1, |
725 | PERF_TSE_STALL_CYCLES_RAS = 2, |
726 | PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3, |
727 | PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4, |
728 | PERF_TSE_STARVE_CYCLES_PC = 5, |
729 | PERF_TSE_INPUT_PRIM = 6, |
730 | PERF_TSE_INPUT_NULL_PRIM = 7, |
731 | PERF_TSE_TRIVAL_REJ_PRIM = 8, |
732 | PERF_TSE_CLIPPED_PRIM = 9, |
733 | PERF_TSE_ZERO_AREA_PRIM = 10, |
734 | PERF_TSE_FACENESS_CULLED_PRIM = 11, |
735 | PERF_TSE_ZERO_PIXEL_PRIM = 12, |
736 | PERF_TSE_OUTPUT_NULL_PRIM = 13, |
737 | PERF_TSE_OUTPUT_VISIBLE_PRIM = 14, |
738 | PERF_TSE_CINVOCATION = 15, |
739 | PERF_TSE_CPRIMITIVES = 16, |
740 | PERF_TSE_2D_INPUT_PRIM = 17, |
741 | PERF_TSE_2D_ALIVE_CYCLES = 18, |
742 | PERF_TSE_CLIP_PLANES = 19, |
743 | }; |
744 | |
745 | enum a6xx_ras_perfcounter_select { |
746 | PERF_RAS_BUSY_CYCLES = 0, |
747 | PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1, |
748 | PERF_RAS_STALL_CYCLES_LRZ = 2, |
749 | PERF_RAS_STARVE_CYCLES_TSE = 3, |
750 | PERF_RAS_SUPER_TILES = 4, |
751 | PERF_RAS_8X4_TILES = 5, |
752 | PERF_RAS_MASKGEN_ACTIVE = 6, |
753 | PERF_RAS_FULLY_COVERED_SUPER_TILES = 7, |
754 | PERF_RAS_FULLY_COVERED_8X4_TILES = 8, |
755 | PERF_RAS_PRIM_KILLED_INVISILBE = 9, |
756 | PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES = 10, |
757 | PERF_RAS_LRZ_INTF_WORKING_CYCLES = 11, |
758 | PERF_RAS_BLOCKS = 12, |
759 | }; |
760 | |
761 | enum a6xx_uche_perfcounter_select { |
762 | PERF_UCHE_BUSY_CYCLES = 0, |
763 | PERF_UCHE_STALL_CYCLES_ARBITER = 1, |
764 | PERF_UCHE_VBIF_LATENCY_CYCLES = 2, |
765 | PERF_UCHE_VBIF_LATENCY_SAMPLES = 3, |
766 | PERF_UCHE_VBIF_READ_BEATS_TP = 4, |
767 | PERF_UCHE_VBIF_READ_BEATS_VFD = 5, |
768 | PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6, |
769 | PERF_UCHE_VBIF_READ_BEATS_LRZ = 7, |
770 | PERF_UCHE_VBIF_READ_BEATS_SP = 8, |
771 | PERF_UCHE_READ_REQUESTS_TP = 9, |
772 | PERF_UCHE_READ_REQUESTS_VFD = 10, |
773 | PERF_UCHE_READ_REQUESTS_HLSQ = 11, |
774 | PERF_UCHE_READ_REQUESTS_LRZ = 12, |
775 | PERF_UCHE_READ_REQUESTS_SP = 13, |
776 | PERF_UCHE_WRITE_REQUESTS_LRZ = 14, |
777 | PERF_UCHE_WRITE_REQUESTS_SP = 15, |
778 | PERF_UCHE_WRITE_REQUESTS_VPC = 16, |
779 | PERF_UCHE_WRITE_REQUESTS_VSC = 17, |
780 | PERF_UCHE_EVICTS = 18, |
781 | PERF_UCHE_BANK_REQ0 = 19, |
782 | PERF_UCHE_BANK_REQ1 = 20, |
783 | PERF_UCHE_BANK_REQ2 = 21, |
784 | PERF_UCHE_BANK_REQ3 = 22, |
785 | PERF_UCHE_BANK_REQ4 = 23, |
786 | PERF_UCHE_BANK_REQ5 = 24, |
787 | PERF_UCHE_BANK_REQ6 = 25, |
788 | PERF_UCHE_BANK_REQ7 = 26, |
789 | PERF_UCHE_VBIF_READ_BEATS_CH0 = 27, |
790 | PERF_UCHE_VBIF_READ_BEATS_CH1 = 28, |
791 | PERF_UCHE_GMEM_READ_BEATS = 29, |
792 | PERF_UCHE_TPH_REF_FULL = 30, |
793 | PERF_UCHE_TPH_VICTIM_FULL = 31, |
794 | PERF_UCHE_TPH_EXT_FULL = 32, |
795 | PERF_UCHE_VBIF_STALL_WRITE_DATA = 33, |
796 | PERF_UCHE_DCMP_LATENCY_SAMPLES = 34, |
797 | PERF_UCHE_DCMP_LATENCY_CYCLES = 35, |
798 | PERF_UCHE_VBIF_READ_BEATS_PC = 36, |
799 | PERF_UCHE_READ_REQUESTS_PC = 37, |
800 | PERF_UCHE_RAM_READ_REQ = 38, |
801 | PERF_UCHE_RAM_WRITE_REQ = 39, |
802 | }; |
803 | |
804 | enum a6xx_tp_perfcounter_select { |
805 | PERF_TP_BUSY_CYCLES = 0, |
806 | PERF_TP_STALL_CYCLES_UCHE = 1, |
807 | PERF_TP_LATENCY_CYCLES = 2, |
808 | PERF_TP_LATENCY_TRANS = 3, |
809 | PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4, |
810 | PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5, |
811 | PERF_TP_L1_CACHELINE_REQUESTS = 6, |
812 | PERF_TP_L1_CACHELINE_MISSES = 7, |
813 | PERF_TP_SP_TP_TRANS = 8, |
814 | PERF_TP_TP_SP_TRANS = 9, |
815 | PERF_TP_OUTPUT_PIXELS = 10, |
816 | PERF_TP_FILTER_WORKLOAD_16BIT = 11, |
817 | PERF_TP_FILTER_WORKLOAD_32BIT = 12, |
818 | PERF_TP_QUADS_RECEIVED = 13, |
819 | PERF_TP_QUADS_OFFSET = 14, |
820 | PERF_TP_QUADS_SHADOW = 15, |
821 | PERF_TP_QUADS_ARRAY = 16, |
822 | PERF_TP_QUADS_GRADIENT = 17, |
823 | PERF_TP_QUADS_1D = 18, |
824 | PERF_TP_QUADS_2D = 19, |
825 | PERF_TP_QUADS_BUFFER = 20, |
826 | PERF_TP_QUADS_3D = 21, |
827 | PERF_TP_QUADS_CUBE = 22, |
828 | PERF_TP_DIVERGENT_QUADS_RECEIVED = 23, |
829 | PERF_TP_PRT_NON_RESIDENT_EVENTS = 24, |
830 | PERF_TP_OUTPUT_PIXELS_POINT = 25, |
831 | PERF_TP_OUTPUT_PIXELS_BILINEAR = 26, |
832 | PERF_TP_OUTPUT_PIXELS_MIP = 27, |
833 | PERF_TP_OUTPUT_PIXELS_ANISO = 28, |
834 | PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 29, |
835 | PERF_TP_FLAG_CACHE_REQUESTS = 30, |
836 | PERF_TP_FLAG_CACHE_MISSES = 31, |
837 | PERF_TP_L1_5_L2_REQUESTS = 32, |
838 | PERF_TP_2D_OUTPUT_PIXELS = 33, |
839 | PERF_TP_2D_OUTPUT_PIXELS_POINT = 34, |
840 | PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 35, |
841 | PERF_TP_2D_FILTER_WORKLOAD_16BIT = 36, |
842 | PERF_TP_2D_FILTER_WORKLOAD_32BIT = 37, |
843 | PERF_TP_TPA2TPC_TRANS = 38, |
844 | PERF_TP_L1_MISSES_ASTC_1TILE = 39, |
845 | PERF_TP_L1_MISSES_ASTC_2TILE = 40, |
846 | PERF_TP_L1_MISSES_ASTC_4TILE = 41, |
847 | PERF_TP_L1_5_L2_COMPRESS_REQS = 42, |
848 | PERF_TP_L1_5_L2_COMPRESS_MISS = 43, |
849 | PERF_TP_L1_BANK_CONFLICT = 44, |
850 | PERF_TP_L1_5_MISS_LATENCY_CYCLES = 45, |
851 | PERF_TP_L1_5_MISS_LATENCY_TRANS = 46, |
852 | PERF_TP_QUADS_CONSTANT_MULTIPLIED = 47, |
853 | PERF_TP_FRONTEND_WORKING_CYCLES = 48, |
854 | PERF_TP_L1_TAG_WORKING_CYCLES = 49, |
855 | PERF_TP_L1_DATA_WRITE_WORKING_CYCLES = 50, |
856 | PERF_TP_PRE_L1_DECOM_WORKING_CYCLES = 51, |
857 | PERF_TP_BACKEND_WORKING_CYCLES = 52, |
858 | PERF_TP_FLAG_CACHE_WORKING_CYCLES = 53, |
859 | PERF_TP_L1_5_CACHE_WORKING_CYCLES = 54, |
860 | PERF_TP_STARVE_CYCLES_SP = 55, |
861 | PERF_TP_STARVE_CYCLES_UCHE = 56, |
862 | }; |
863 | |
864 | enum a6xx_sp_perfcounter_select { |
865 | PERF_SP_BUSY_CYCLES = 0, |
866 | PERF_SP_ALU_WORKING_CYCLES = 1, |
867 | PERF_SP_EFU_WORKING_CYCLES = 2, |
868 | PERF_SP_STALL_CYCLES_VPC = 3, |
869 | PERF_SP_STALL_CYCLES_TP = 4, |
870 | PERF_SP_STALL_CYCLES_UCHE = 5, |
871 | PERF_SP_STALL_CYCLES_RB = 6, |
872 | PERF_SP_NON_EXECUTION_CYCLES = 7, |
873 | PERF_SP_WAVE_CONTEXTS = 8, |
874 | PERF_SP_WAVE_CONTEXT_CYCLES = 9, |
875 | PERF_SP_FS_STAGE_WAVE_CYCLES = 10, |
876 | PERF_SP_FS_STAGE_WAVE_SAMPLES = 11, |
877 | PERF_SP_VS_STAGE_WAVE_CYCLES = 12, |
878 | PERF_SP_VS_STAGE_WAVE_SAMPLES = 13, |
879 | PERF_SP_FS_STAGE_DURATION_CYCLES = 14, |
880 | PERF_SP_VS_STAGE_DURATION_CYCLES = 15, |
881 | PERF_SP_WAVE_CTRL_CYCLES = 16, |
882 | PERF_SP_WAVE_LOAD_CYCLES = 17, |
883 | PERF_SP_WAVE_EMIT_CYCLES = 18, |
884 | PERF_SP_WAVE_NOP_CYCLES = 19, |
885 | PERF_SP_WAVE_WAIT_CYCLES = 20, |
886 | PERF_SP_WAVE_FETCH_CYCLES = 21, |
887 | PERF_SP_WAVE_IDLE_CYCLES = 22, |
888 | PERF_SP_WAVE_END_CYCLES = 23, |
889 | PERF_SP_WAVE_LONG_SYNC_CYCLES = 24, |
890 | PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25, |
891 | PERF_SP_WAVE_JOIN_CYCLES = 26, |
892 | PERF_SP_LM_LOAD_INSTRUCTIONS = 27, |
893 | PERF_SP_LM_STORE_INSTRUCTIONS = 28, |
894 | PERF_SP_LM_ATOMICS = 29, |
895 | PERF_SP_GM_LOAD_INSTRUCTIONS = 30, |
896 | PERF_SP_GM_STORE_INSTRUCTIONS = 31, |
897 | PERF_SP_GM_ATOMICS = 32, |
898 | PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33, |
899 | PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 34, |
900 | PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 35, |
901 | PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 36, |
902 | PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 37, |
903 | PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 38, |
904 | PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 39, |
905 | PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 40, |
906 | PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 41, |
907 | PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 42, |
908 | PERF_SP_VS_INSTRUCTIONS = 43, |
909 | PERF_SP_FS_INSTRUCTIONS = 44, |
910 | PERF_SP_ADDR_LOCK_COUNT = 45, |
911 | PERF_SP_UCHE_READ_TRANS = 46, |
912 | PERF_SP_UCHE_WRITE_TRANS = 47, |
913 | PERF_SP_EXPORT_VPC_TRANS = 48, |
914 | PERF_SP_EXPORT_RB_TRANS = 49, |
915 | PERF_SP_PIXELS_KILLED = 50, |
916 | PERF_SP_ICL1_REQUESTS = 51, |
917 | PERF_SP_ICL1_MISSES = 52, |
918 | PERF_SP_HS_INSTRUCTIONS = 53, |
919 | PERF_SP_DS_INSTRUCTIONS = 54, |
920 | PERF_SP_GS_INSTRUCTIONS = 55, |
921 | PERF_SP_CS_INSTRUCTIONS = 56, |
922 | PERF_SP_GPR_READ = 57, |
923 | PERF_SP_GPR_WRITE = 58, |
924 | PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS = 59, |
925 | PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS = 60, |
926 | PERF_SP_LM_BANK_CONFLICTS = 61, |
927 | PERF_SP_TEX_CONTROL_WORKING_CYCLES = 62, |
928 | PERF_SP_LOAD_CONTROL_WORKING_CYCLES = 63, |
929 | PERF_SP_FLOW_CONTROL_WORKING_CYCLES = 64, |
930 | PERF_SP_LM_WORKING_CYCLES = 65, |
931 | PERF_SP_DISPATCHER_WORKING_CYCLES = 66, |
932 | PERF_SP_SEQUENCER_WORKING_CYCLES = 67, |
933 | PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP = 68, |
934 | PERF_SP_STARVE_CYCLES_HLSQ = 69, |
935 | PERF_SP_NON_EXECUTION_LS_CYCLES = 70, |
936 | PERF_SP_WORKING_EU = 71, |
937 | PERF_SP_ANY_EU_WORKING = 72, |
938 | PERF_SP_WORKING_EU_FS_STAGE = 73, |
939 | PERF_SP_ANY_EU_WORKING_FS_STAGE = 74, |
940 | PERF_SP_WORKING_EU_VS_STAGE = 75, |
941 | PERF_SP_ANY_EU_WORKING_VS_STAGE = 76, |
942 | PERF_SP_WORKING_EU_CS_STAGE = 77, |
943 | PERF_SP_ANY_EU_WORKING_CS_STAGE = 78, |
944 | PERF_SP_GPR_READ_PREFETCH = 79, |
945 | PERF_SP_GPR_READ_CONFLICT = 80, |
946 | PERF_SP_GPR_WRITE_CONFLICT = 81, |
947 | PERF_SP_GM_LOAD_LATENCY_CYCLES = 82, |
948 | PERF_SP_GM_LOAD_LATENCY_SAMPLES = 83, |
949 | PERF_SP_EXECUTABLE_WAVES = 84, |
950 | }; |
951 | |
952 | enum a6xx_rb_perfcounter_select { |
953 | PERF_RB_BUSY_CYCLES = 0, |
954 | PERF_RB_STALL_CYCLES_HLSQ = 1, |
955 | PERF_RB_STALL_CYCLES_FIFO0_FULL = 2, |
956 | PERF_RB_STALL_CYCLES_FIFO1_FULL = 3, |
957 | PERF_RB_STALL_CYCLES_FIFO2_FULL = 4, |
958 | PERF_RB_STARVE_CYCLES_SP = 5, |
959 | PERF_RB_STARVE_CYCLES_LRZ_TILE = 6, |
960 | PERF_RB_STARVE_CYCLES_CCU = 7, |
961 | PERF_RB_STARVE_CYCLES_Z_PLANE = 8, |
962 | PERF_RB_STARVE_CYCLES_BARY_PLANE = 9, |
963 | PERF_RB_Z_WORKLOAD = 10, |
964 | PERF_RB_HLSQ_ACTIVE = 11, |
965 | PERF_RB_Z_READ = 12, |
966 | PERF_RB_Z_WRITE = 13, |
967 | PERF_RB_C_READ = 14, |
968 | PERF_RB_C_WRITE = 15, |
969 | PERF_RB_TOTAL_PASS = 16, |
970 | PERF_RB_Z_PASS = 17, |
971 | PERF_RB_Z_FAIL = 18, |
972 | PERF_RB_S_FAIL = 19, |
973 | PERF_RB_BLENDED_FXP_COMPONENTS = 20, |
974 | PERF_RB_BLENDED_FP16_COMPONENTS = 21, |
975 | PERF_RB_PS_INVOCATIONS = 22, |
976 | PERF_RB_2D_ALIVE_CYCLES = 23, |
977 | PERF_RB_2D_STALL_CYCLES_A2D = 24, |
978 | PERF_RB_2D_STARVE_CYCLES_SRC = 25, |
979 | PERF_RB_2D_STARVE_CYCLES_SP = 26, |
980 | PERF_RB_2D_STARVE_CYCLES_DST = 27, |
981 | PERF_RB_2D_VALID_PIXELS = 28, |
982 | PERF_RB_3D_PIXELS = 29, |
983 | PERF_RB_BLENDER_WORKING_CYCLES = 30, |
984 | PERF_RB_ZPROC_WORKING_CYCLES = 31, |
985 | PERF_RB_CPROC_WORKING_CYCLES = 32, |
986 | PERF_RB_SAMPLER_WORKING_CYCLES = 33, |
987 | PERF_RB_STALL_CYCLES_CCU_COLOR_READ = 34, |
988 | PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE = 35, |
989 | PERF_RB_STALL_CYCLES_CCU_DEPTH_READ = 36, |
990 | PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE = 37, |
991 | PERF_RB_STALL_CYCLES_VPC = 38, |
992 | PERF_RB_2D_INPUT_TRANS = 39, |
993 | PERF_RB_2D_OUTPUT_RB_DST_TRANS = 40, |
994 | PERF_RB_2D_OUTPUT_RB_SRC_TRANS = 41, |
995 | PERF_RB_BLENDED_FP32_COMPONENTS = 42, |
996 | PERF_RB_COLOR_PIX_TILES = 43, |
997 | PERF_RB_STALL_CYCLES_CCU = 44, |
998 | PERF_RB_EARLY_Z_ARB3_GRANT = 45, |
999 | PERF_RB_LATE_Z_ARB3_GRANT = 46, |
1000 | PERF_RB_EARLY_Z_SKIP_GRANT = 47, |
1001 | }; |
1002 | |
1003 | enum a6xx_vsc_perfcounter_select { |
1004 | PERF_VSC_BUSY_CYCLES = 0, |
1005 | PERF_VSC_WORKING_CYCLES = 1, |
1006 | PERF_VSC_STALL_CYCLES_UCHE = 2, |
1007 | PERF_VSC_EOT_NUM = 3, |
1008 | PERF_VSC_INPUT_TILES = 4, |
1009 | }; |
1010 | |
1011 | enum a6xx_ccu_perfcounter_select { |
1012 | PERF_CCU_BUSY_CYCLES = 0, |
1013 | PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1, |
1014 | PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2, |
1015 | PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3, |
1016 | PERF_CCU_DEPTH_BLOCKS = 4, |
1017 | PERF_CCU_COLOR_BLOCKS = 5, |
1018 | PERF_CCU_DEPTH_BLOCK_HIT = 6, |
1019 | PERF_CCU_COLOR_BLOCK_HIT = 7, |
1020 | PERF_CCU_PARTIAL_BLOCK_READ = 8, |
1021 | PERF_CCU_GMEM_READ = 9, |
1022 | PERF_CCU_GMEM_WRITE = 10, |
1023 | PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11, |
1024 | PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12, |
1025 | PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13, |
1026 | PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14, |
1027 | PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15, |
1028 | PERF_CCU_DEPTH_READ_FLAG5_COUNT = 16, |
1029 | PERF_CCU_DEPTH_READ_FLAG6_COUNT = 17, |
1030 | PERF_CCU_DEPTH_READ_FLAG8_COUNT = 18, |
1031 | PERF_CCU_COLOR_READ_FLAG0_COUNT = 19, |
1032 | PERF_CCU_COLOR_READ_FLAG1_COUNT = 20, |
1033 | PERF_CCU_COLOR_READ_FLAG2_COUNT = 21, |
1034 | PERF_CCU_COLOR_READ_FLAG3_COUNT = 22, |
1035 | PERF_CCU_COLOR_READ_FLAG4_COUNT = 23, |
1036 | PERF_CCU_COLOR_READ_FLAG5_COUNT = 24, |
1037 | PERF_CCU_COLOR_READ_FLAG6_COUNT = 25, |
1038 | PERF_CCU_COLOR_READ_FLAG8_COUNT = 26, |
1039 | PERF_CCU_2D_RD_REQ = 27, |
1040 | PERF_CCU_2D_WR_REQ = 28, |
1041 | }; |
1042 | |
1043 | enum a6xx_lrz_perfcounter_select { |
1044 | PERF_LRZ_BUSY_CYCLES = 0, |
1045 | PERF_LRZ_STARVE_CYCLES_RAS = 1, |
1046 | PERF_LRZ_STALL_CYCLES_RB = 2, |
1047 | PERF_LRZ_STALL_CYCLES_VSC = 3, |
1048 | PERF_LRZ_STALL_CYCLES_VPC = 4, |
1049 | PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5, |
1050 | PERF_LRZ_STALL_CYCLES_UCHE = 6, |
1051 | PERF_LRZ_LRZ_READ = 7, |
1052 | PERF_LRZ_LRZ_WRITE = 8, |
1053 | PERF_LRZ_READ_LATENCY = 9, |
1054 | PERF_LRZ_MERGE_CACHE_UPDATING = 10, |
1055 | PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11, |
1056 | PERF_LRZ_PRIM_KILLED_BY_LRZ = 12, |
1057 | PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13, |
1058 | PERF_LRZ_FULL_8X8_TILES = 14, |
1059 | PERF_LRZ_PARTIAL_8X8_TILES = 15, |
1060 | PERF_LRZ_TILE_KILLED = 16, |
1061 | PERF_LRZ_TOTAL_PIXEL = 17, |
1062 | PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18, |
1063 | PERF_LRZ_FULLY_COVERED_TILES = 19, |
1064 | PERF_LRZ_PARTIAL_COVERED_TILES = 20, |
1065 | PERF_LRZ_FEEDBACK_ACCEPT = 21, |
1066 | PERF_LRZ_FEEDBACK_DISCARD = 22, |
1067 | PERF_LRZ_FEEDBACK_STALL = 23, |
1068 | PERF_LRZ_STALL_CYCLES_RB_ZPLANE = 24, |
1069 | PERF_LRZ_STALL_CYCLES_RB_BPLANE = 25, |
1070 | PERF_LRZ_STALL_CYCLES_VC = 26, |
1071 | PERF_LRZ_RAS_MASK_TRANS = 27, |
1072 | }; |
1073 | |
1074 | enum a6xx_cmp_perfcounter_select { |
1075 | PERF_CMPDECMP_STALL_CYCLES_ARB = 0, |
1076 | PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1, |
1077 | PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2, |
1078 | PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3, |
1079 | PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4, |
1080 | PERF_CMPDECMP_VBIF_READ_REQUEST = 5, |
1081 | PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6, |
1082 | PERF_CMPDECMP_VBIF_READ_DATA = 7, |
1083 | PERF_CMPDECMP_VBIF_WRITE_DATA = 8, |
1084 | PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9, |
1085 | PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10, |
1086 | PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11, |
1087 | PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12, |
1088 | PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13, |
1089 | PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14, |
1090 | PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT = 15, |
1091 | PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT = 16, |
1092 | PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT = 17, |
1093 | PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 18, |
1094 | PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 19, |
1095 | PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 20, |
1096 | PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 21, |
1097 | PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT = 22, |
1098 | PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT = 23, |
1099 | PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT = 24, |
1100 | PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 25, |
1101 | PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 26, |
1102 | PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 27, |
1103 | PERF_CMPDECMP_2D_RD_DATA = 28, |
1104 | PERF_CMPDECMP_2D_WR_DATA = 29, |
1105 | PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0 = 30, |
1106 | PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1 = 31, |
1107 | PERF_CMPDECMP_2D_OUTPUT_TRANS = 32, |
1108 | PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE = 33, |
1109 | PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT = 34, |
1110 | PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT = 35, |
1111 | PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT = 36, |
1112 | PERF_CMPDECMP_2D_BUSY_CYCLES = 37, |
1113 | PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES = 38, |
1114 | PERF_CMPDECMP_2D_PIXELS = 39, |
1115 | }; |
1116 | |
1117 | enum a6xx_2d_ifmt { |
1118 | R2D_UNORM8 = 16, |
1119 | R2D_INT32 = 7, |
1120 | R2D_INT16 = 6, |
1121 | R2D_INT8 = 5, |
1122 | R2D_FLOAT32 = 4, |
1123 | R2D_FLOAT16 = 3, |
1124 | R2D_UNORM8_SRGB = 1, |
1125 | R2D_RAW = 0, |
1126 | }; |
1127 | |
1128 | enum a6xx_ztest_mode { |
1129 | A6XX_EARLY_Z = 0, |
1130 | A6XX_LATE_Z = 1, |
1131 | A6XX_EARLY_LRZ_LATE_Z = 2, |
1132 | A6XX_INVALID_ZTEST = 3, |
1133 | }; |
1134 | |
1135 | enum a6xx_tess_spacing { |
1136 | TESS_EQUAL = 0, |
1137 | TESS_FRACTIONAL_ODD = 2, |
1138 | TESS_FRACTIONAL_EVEN = 3, |
1139 | }; |
1140 | |
1141 | enum a6xx_tess_output { |
1142 | TESS_POINTS = 0, |
1143 | TESS_LINES = 1, |
1144 | TESS_CW_TRIS = 2, |
1145 | TESS_CCW_TRIS = 3, |
1146 | }; |
1147 | |
1148 | enum a6xx_sequenced_thread_dist { |
1149 | DIST_SCREEN_COORD = 0, |
1150 | DIST_ALL_TO_RB0 = 1, |
1151 | }; |
1152 | |
1153 | enum a6xx_single_prim_mode { |
1154 | NO_FLUSH = 0, |
1155 | FLUSH_PER_OVERLAP_AND_OVERWRITE = 1, |
1156 | FLUSH_PER_OVERLAP = 3, |
1157 | }; |
1158 | |
1159 | enum a6xx_raster_mode { |
1160 | TYPE_TILED = 0, |
1161 | TYPE_WRITER = 1, |
1162 | }; |
1163 | |
1164 | enum a6xx_raster_direction { |
1165 | LR_TB = 0, |
1166 | RL_TB = 1, |
1167 | LR_BT = 2, |
1168 | RB_BT = 3, |
1169 | }; |
1170 | |
1171 | enum a6xx_render_mode { |
1172 | RENDERING_PASS = 0, |
1173 | BINNING_PASS = 1, |
1174 | }; |
1175 | |
1176 | enum a6xx_buffers_location { |
1177 | BUFFERS_IN_GMEM = 0, |
1178 | BUFFERS_IN_SYSMEM = 3, |
1179 | }; |
1180 | |
1181 | enum a6xx_lrz_dir_status { |
1182 | LRZ_DIR_LE = 1, |
1183 | LRZ_DIR_GE = 2, |
1184 | LRZ_DIR_INVALID = 3, |
1185 | }; |
1186 | |
1187 | enum a6xx_fragcoord_sample_mode { |
1188 | FRAGCOORD_CENTER = 0, |
1189 | FRAGCOORD_SAMPLE = 3, |
1190 | }; |
1191 | |
1192 | enum a6xx_rotation { |
1193 | ROTATE_0 = 0, |
1194 | ROTATE_90 = 1, |
1195 | ROTATE_180 = 2, |
1196 | ROTATE_270 = 3, |
1197 | ROTATE_HFLIP = 4, |
1198 | ROTATE_VFLIP = 5, |
1199 | }; |
1200 | |
1201 | enum a6xx_ccu_cache_size { |
1202 | CCU_CACHE_SIZE_FULL = 0, |
1203 | CCU_CACHE_SIZE_HALF = 1, |
1204 | CCU_CACHE_SIZE_QUARTER = 2, |
1205 | CCU_CACHE_SIZE_EIGHTH = 3, |
1206 | }; |
1207 | |
1208 | enum a6xx_varying_interp_mode { |
1209 | INTERP_SMOOTH = 0, |
1210 | INTERP_FLAT = 1, |
1211 | INTERP_ZERO = 2, |
1212 | INTERP_ONE = 3, |
1213 | }; |
1214 | |
1215 | enum a6xx_varying_ps_repl_mode { |
1216 | PS_REPL_NONE = 0, |
1217 | PS_REPL_S = 1, |
1218 | PS_REPL_T = 2, |
1219 | PS_REPL_ONE_MINUS_T = 3, |
1220 | }; |
1221 | |
1222 | enum a6xx_threadsize { |
1223 | THREAD64 = 0, |
1224 | THREAD128 = 1, |
1225 | }; |
1226 | |
1227 | enum a6xx_bindless_descriptor_size { |
1228 | BINDLESS_DESCRIPTOR_16B = 1, |
1229 | BINDLESS_DESCRIPTOR_64B = 3, |
1230 | }; |
1231 | |
1232 | enum a6xx_isam_mode { |
1233 | ISAMMODE_CL = 1, |
1234 | ISAMMODE_GL = 2, |
1235 | }; |
1236 | |
1237 | enum a7xx_cs_yalign { |
1238 | CS_YALIGN_1 = 8, |
1239 | CS_YALIGN_2 = 4, |
1240 | CS_YALIGN_4 = 2, |
1241 | CS_YALIGN_8 = 1, |
1242 | }; |
1243 | |
1244 | enum a6xx_tex_filter { |
1245 | A6XX_TEX_NEAREST = 0, |
1246 | A6XX_TEX_LINEAR = 1, |
1247 | A6XX_TEX_ANISO = 2, |
1248 | A6XX_TEX_CUBIC = 3, |
1249 | }; |
1250 | |
1251 | enum a6xx_tex_clamp { |
1252 | A6XX_TEX_REPEAT = 0, |
1253 | A6XX_TEX_CLAMP_TO_EDGE = 1, |
1254 | A6XX_TEX_MIRROR_REPEAT = 2, |
1255 | A6XX_TEX_CLAMP_TO_BORDER = 3, |
1256 | A6XX_TEX_MIRROR_CLAMP = 4, |
1257 | }; |
1258 | |
1259 | enum a6xx_tex_aniso { |
1260 | A6XX_TEX_ANISO_1 = 0, |
1261 | A6XX_TEX_ANISO_2 = 1, |
1262 | A6XX_TEX_ANISO_4 = 2, |
1263 | A6XX_TEX_ANISO_8 = 3, |
1264 | A6XX_TEX_ANISO_16 = 4, |
1265 | }; |
1266 | |
1267 | enum a6xx_reduction_mode { |
1268 | A6XX_REDUCTION_MODE_AVERAGE = 0, |
1269 | A6XX_REDUCTION_MODE_MIN = 1, |
1270 | A6XX_REDUCTION_MODE_MAX = 2, |
1271 | }; |
1272 | |
1273 | enum a6xx_tex_swiz { |
1274 | A6XX_TEX_X = 0, |
1275 | A6XX_TEX_Y = 1, |
1276 | A6XX_TEX_Z = 2, |
1277 | A6XX_TEX_W = 3, |
1278 | A6XX_TEX_ZERO = 4, |
1279 | A6XX_TEX_ONE = 5, |
1280 | }; |
1281 | |
1282 | enum a6xx_tex_type { |
1283 | A6XX_TEX_1D = 0, |
1284 | A6XX_TEX_2D = 1, |
1285 | A6XX_TEX_CUBE = 2, |
1286 | A6XX_TEX_3D = 3, |
1287 | A6XX_TEX_BUFFER = 4, |
1288 | }; |
1289 | |
1290 | #define A6XX_RBBM_INT_0_MASK_RBBM_GPU_IDLE 0x00000001 |
1291 | #define A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR 0x00000002 |
1292 | #define A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_0 0x00000010 |
1293 | #define A6XX_RBBM_INT_0_MASK_CP_IPC_INTR_1 0x00000020 |
1294 | #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW 0x00000040 |
1295 | #define A6XX_RBBM_INT_0_MASK_RBBM_GPC_ERROR 0x00000080 |
1296 | #define A6XX_RBBM_INT_0_MASK_CP_SW 0x00000100 |
1297 | #define A6XX_RBBM_INT_0_MASK_CP_HW_ERROR 0x00000200 |
1298 | #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_DEPTH_TS 0x00000400 |
1299 | #define A6XX_RBBM_INT_0_MASK_CP_CCU_FLUSH_COLOR_TS 0x00000800 |
1300 | #define A6XX_RBBM_INT_0_MASK_CP_CCU_RESOLVE_TS 0x00001000 |
1301 | #define A6XX_RBBM_INT_0_MASK_CP_IB2 0x00002000 |
1302 | #define A6XX_RBBM_INT_0_MASK_CP_IB1 0x00004000 |
1303 | #define A6XX_RBBM_INT_0_MASK_CP_RB 0x00008000 |
1304 | #define A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPT 0x00008000 |
1305 | #define A6XX_RBBM_INT_0_MASK_PM4CPINTERRUPTLPAC 0x00010000 |
1306 | #define A6XX_RBBM_INT_0_MASK_CP_RB_DONE_TS 0x00020000 |
1307 | #define A6XX_RBBM_INT_0_MASK_CP_WT_DONE_TS 0x00040000 |
1308 | #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS 0x00100000 |
1309 | #define A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS_LPAC 0x00200000 |
1310 | #define A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW 0x00400000 |
1311 | #define A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT 0x00800000 |
1312 | #define A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS 0x01000000 |
1313 | #define A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR 0x02000000 |
1314 | #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_0 0x04000000 |
1315 | #define A6XX_RBBM_INT_0_MASK_DEBBUS_INTR_1 0x08000000 |
1316 | #define A6XX_RBBM_INT_0_MASK_TSBWRITEERROR 0x10000000 |
1317 | #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 |
1318 | #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 |
1319 | |
1320 | #define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001 |
1321 | #define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002 |
1322 | #define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 |
1323 | #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 |
1324 | #define A6XX_CP_INT_CP_AHB_ERROR 0x00000020 |
1325 | #define A6XX_CP_INT_CP_VSD_PARITY_ERROR 0x00000040 |
1326 | #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR 0x00000080 |
1327 | #define A6XX_CP_INT_CP_OPCODE_ERROR_LPAC 0x00000100 |
1328 | #define A6XX_CP_INT_CP_UCODE_ERROR_LPAC 0x00000200 |
1329 | #define A6XX_CP_INT_CP_HW_FAULT_ERROR_LPAC 0x00000400 |
1330 | #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_LPAC 0x00000800 |
1331 | #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_LPAC 0x00001000 |
1332 | #define A6XX_CP_INT_CP_OPCODE_ERROR_BV 0x00002000 |
1333 | #define A6XX_CP_INT_CP_UCODE_ERROR_BV 0x00004000 |
1334 | #define A6XX_CP_INT_CP_HW_FAULT_ERROR_BV 0x00008000 |
1335 | #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_BV 0x00010000 |
1336 | #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_BV 0x00020000 |
1337 | |
1338 | #define REG_A6XX_CP_RB_BASE 0x00000800 |
1339 | |
1340 | #define REG_A6XX_CP_RB_CNTL 0x00000802 |
1341 | |
1342 | #define REG_A6XX_CP_RB_RPTR_ADDR 0x00000804 |
1343 | |
1344 | #define REG_A6XX_CP_RB_RPTR 0x00000806 |
1345 | |
1346 | #define REG_A6XX_CP_RB_WPTR 0x00000807 |
1347 | |
1348 | #define REG_A6XX_CP_SQE_CNTL 0x00000808 |
1349 | |
1350 | #define REG_A6XX_CP_CP2GMU_STATUS 0x00000812 |
1351 | #define A6XX_CP_CP2GMU_STATUS_IFPC 0x00000001 |
1352 | |
1353 | #define REG_A6XX_CP_HW_FAULT 0x00000821 |
1354 | |
1355 | #define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823 |
1356 | #define REG_A6XX_CP_PROTECT_STATUS 0x00000824 |
1357 | |
1358 | #define REG_A6XX_CP_STATUS_1 0x00000825 |
1359 | |
1360 | #define REG_A6XX_CP_SQE_INSTR_BASE 0x00000830 |
1361 | |
1362 | #define REG_A6XX_CP_MISC_CNTL 0x00000840 |
1363 | |
1364 | #define REG_A6XX_CP_APRIV_CNTL 0x00000844 |
1365 | #define A6XX_CP_APRIV_CNTL_CDWRITE 0x00000040 |
1366 | #define A6XX_CP_APRIV_CNTL_CDREAD 0x00000020 |
1367 | #define A6XX_CP_APRIV_CNTL_RBRPWB 0x00000008 |
1368 | #define A6XX_CP_APRIV_CNTL_RBPRIVLEVEL 0x00000004 |
1369 | #define A6XX_CP_APRIV_CNTL_RBFETCH 0x00000002 |
1370 | #define A6XX_CP_APRIV_CNTL_ICACHE 0x00000001 |
1371 | |
1372 | #define REG_A6XX_CP_PREEMPT_THRESHOLD 0x000008c0 |
1373 | |
1374 | #define REG_A6XX_CP_ROQ_THRESHOLDS_1 0x000008c1 |
1375 | #define A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK 0x000000ff |
1376 | #define A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT 0 |
1377 | static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(uint32_t val) |
1378 | { |
1379 | assert(!(val & 0x3)); |
1380 | return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK; |
1381 | } |
1382 | #define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK 0x0000ff00 |
1383 | #define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT 8 |
1384 | static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(uint32_t val) |
1385 | { |
1386 | assert(!(val & 0x3)); |
1387 | return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK; |
1388 | } |
1389 | #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK 0x00ff0000 |
1390 | #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT 16 |
1391 | static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) |
1392 | { |
1393 | assert(!(val & 0x3)); |
1394 | return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK; |
1395 | } |
1396 | #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK 0xff000000 |
1397 | #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT 24 |
1398 | static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) |
1399 | { |
1400 | assert(!(val & 0x3)); |
1401 | return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK; |
1402 | } |
1403 | |
1404 | #define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2 |
1405 | #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK 0x000001ff |
1406 | #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT 0 |
1407 | static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) |
1408 | { |
1409 | assert(!(val & 0x3)); |
1410 | return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK; |
1411 | } |
1412 | #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK 0xffff0000 |
1413 | #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT 16 |
1414 | static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) |
1415 | { |
1416 | assert(!(val & 0x3)); |
1417 | return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK; |
1418 | } |
1419 | |
1420 | #define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3 |
1421 | |
1422 | #define REG_A6XX_CP_CHICKEN_DBG 0x00000841 |
1423 | |
1424 | #define REG_A6XX_CP_ADDR_MODE_CNTL 0x00000842 |
1425 | |
1426 | #define REG_A6XX_CP_DBG_ECO_CNTL 0x00000843 |
1427 | |
1428 | #define REG_A6XX_CP_PROTECT_CNTL 0x0000084f |
1429 | #define A6XX_CP_PROTECT_CNTL_LAST_SPAN_INF_RANGE 0x00000008 |
1430 | #define A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN 0x00000002 |
1431 | #define A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN 0x00000001 |
1432 | |
1433 | #define REG_A6XX_CP_SCRATCH(i0) (0x00000883 + 0x1*(i0)) |
1434 | |
1435 | static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } |
1436 | |
1437 | #define REG_A6XX_CP_PROTECT(i0) (0x00000850 + 0x1*(i0)) |
1438 | |
1439 | static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } |
1440 | #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff |
1441 | #define A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT 0 |
1442 | static inline uint32_t A6XX_CP_PROTECT_REG_BASE_ADDR(uint32_t val) |
1443 | { |
1444 | return ((val) << A6XX_CP_PROTECT_REG_BASE_ADDR__SHIFT) & A6XX_CP_PROTECT_REG_BASE_ADDR__MASK; |
1445 | } |
1446 | #define A6XX_CP_PROTECT_REG_MASK_LEN__MASK 0x7ffc0000 |
1447 | #define A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT 18 |
1448 | static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) |
1449 | { |
1450 | return ((val) << A6XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A6XX_CP_PROTECT_REG_MASK_LEN__MASK; |
1451 | } |
1452 | #define A6XX_CP_PROTECT_REG_READ 0x80000000 |
1453 | |
1454 | #define REG_A6XX_CP_CONTEXT_SWITCH_CNTL 0x000008a0 |
1455 | |
1456 | #define REG_A6XX_CP_CONTEXT_SWITCH_SMMU_INFO 0x000008a1 |
1457 | |
1458 | #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR 0x000008a3 |
1459 | |
1460 | #define REG_A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR 0x000008a5 |
1461 | |
1462 | #define REG_A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR 0x000008a7 |
1463 | |
1464 | #define REG_A7XX_CP_CONTEXT_SWITCH_LEVEL_STATUS 0x000008ab |
1465 | |
1466 | #define REG_A6XX_CP_PERFCTR_CP_SEL(i0) (0x000008d0 + 0x1*(i0)) |
1467 | |
1468 | #define REG_A7XX_CP_BV_PERFCTR_CP_SEL(i0) (0x000008e0 + 0x1*(i0)) |
1469 | |
1470 | #define REG_A6XX_CP_CRASH_SCRIPT_BASE 0x00000900 |
1471 | |
1472 | #define REG_A6XX_CP_CRASH_DUMP_CNTL 0x00000902 |
1473 | |
1474 | #define REG_A6XX_CP_CRASH_DUMP_STATUS 0x00000903 |
1475 | |
1476 | #define REG_A6XX_CP_SQE_STAT_ADDR 0x00000908 |
1477 | |
1478 | #define REG_A6XX_CP_SQE_STAT_DATA 0x00000909 |
1479 | |
1480 | #define REG_A6XX_CP_DRAW_STATE_ADDR 0x0000090a |
1481 | |
1482 | #define REG_A6XX_CP_DRAW_STATE_DATA 0x0000090b |
1483 | |
1484 | #define REG_A6XX_CP_ROQ_DBG_ADDR 0x0000090c |
1485 | |
1486 | #define REG_A6XX_CP_ROQ_DBG_DATA 0x0000090d |
1487 | |
1488 | #define REG_A6XX_CP_MEM_POOL_DBG_ADDR 0x0000090e |
1489 | |
1490 | #define REG_A6XX_CP_MEM_POOL_DBG_DATA 0x0000090f |
1491 | |
1492 | #define REG_A6XX_CP_SQE_UCODE_DBG_ADDR 0x00000910 |
1493 | |
1494 | #define REG_A6XX_CP_SQE_UCODE_DBG_DATA 0x00000911 |
1495 | |
1496 | #define REG_A6XX_CP_IB1_BASE 0x00000928 |
1497 | |
1498 | #define REG_A6XX_CP_IB1_REM_SIZE 0x0000092a |
1499 | |
1500 | #define REG_A6XX_CP_IB2_BASE 0x0000092b |
1501 | |
1502 | #define REG_A6XX_CP_IB2_REM_SIZE 0x0000092d |
1503 | |
1504 | #define REG_A6XX_CP_SDS_BASE 0x0000092e |
1505 | |
1506 | #define REG_A6XX_CP_SDS_REM_SIZE 0x00000930 |
1507 | |
1508 | #define REG_A6XX_CP_MRB_BASE 0x00000931 |
1509 | |
1510 | #define REG_A6XX_CP_MRB_REM_SIZE 0x00000933 |
1511 | |
1512 | #define REG_A6XX_CP_VSD_BASE 0x00000934 |
1513 | |
1514 | #define REG_A6XX_CP_ROQ_RB_STAT 0x00000939 |
1515 | #define A6XX_CP_ROQ_RB_STAT_RPTR__MASK 0x000003ff |
1516 | #define A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT 0 |
1517 | static inline uint32_t A6XX_CP_ROQ_RB_STAT_RPTR(uint32_t val) |
1518 | { |
1519 | return ((val) << A6XX_CP_ROQ_RB_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_RB_STAT_RPTR__MASK; |
1520 | } |
1521 | #define A6XX_CP_ROQ_RB_STAT_WPTR__MASK 0x03ff0000 |
1522 | #define A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT 16 |
1523 | static inline uint32_t A6XX_CP_ROQ_RB_STAT_WPTR(uint32_t val) |
1524 | { |
1525 | return ((val) << A6XX_CP_ROQ_RB_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_RB_STAT_WPTR__MASK; |
1526 | } |
1527 | |
1528 | #define REG_A6XX_CP_ROQ_IB1_STAT 0x0000093a |
1529 | #define A6XX_CP_ROQ_IB1_STAT_RPTR__MASK 0x000003ff |
1530 | #define A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT 0 |
1531 | static inline uint32_t A6XX_CP_ROQ_IB1_STAT_RPTR(uint32_t val) |
1532 | { |
1533 | return ((val) << A6XX_CP_ROQ_IB1_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_IB1_STAT_RPTR__MASK; |
1534 | } |
1535 | #define A6XX_CP_ROQ_IB1_STAT_WPTR__MASK 0x03ff0000 |
1536 | #define A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT 16 |
1537 | static inline uint32_t A6XX_CP_ROQ_IB1_STAT_WPTR(uint32_t val) |
1538 | { |
1539 | return ((val) << A6XX_CP_ROQ_IB1_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_IB1_STAT_WPTR__MASK; |
1540 | } |
1541 | |
1542 | #define REG_A6XX_CP_ROQ_IB2_STAT 0x0000093b |
1543 | #define A6XX_CP_ROQ_IB2_STAT_RPTR__MASK 0x000003ff |
1544 | #define A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT 0 |
1545 | static inline uint32_t A6XX_CP_ROQ_IB2_STAT_RPTR(uint32_t val) |
1546 | { |
1547 | return ((val) << A6XX_CP_ROQ_IB2_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_IB2_STAT_RPTR__MASK; |
1548 | } |
1549 | #define A6XX_CP_ROQ_IB2_STAT_WPTR__MASK 0x03ff0000 |
1550 | #define A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT 16 |
1551 | static inline uint32_t A6XX_CP_ROQ_IB2_STAT_WPTR(uint32_t val) |
1552 | { |
1553 | return ((val) << A6XX_CP_ROQ_IB2_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_IB2_STAT_WPTR__MASK; |
1554 | } |
1555 | |
1556 | #define REG_A6XX_CP_ROQ_SDS_STAT 0x0000093c |
1557 | #define A6XX_CP_ROQ_SDS_STAT_RPTR__MASK 0x000003ff |
1558 | #define A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT 0 |
1559 | static inline uint32_t A6XX_CP_ROQ_SDS_STAT_RPTR(uint32_t val) |
1560 | { |
1561 | return ((val) << A6XX_CP_ROQ_SDS_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_SDS_STAT_RPTR__MASK; |
1562 | } |
1563 | #define A6XX_CP_ROQ_SDS_STAT_WPTR__MASK 0x03ff0000 |
1564 | #define A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT 16 |
1565 | static inline uint32_t A6XX_CP_ROQ_SDS_STAT_WPTR(uint32_t val) |
1566 | { |
1567 | return ((val) << A6XX_CP_ROQ_SDS_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_SDS_STAT_WPTR__MASK; |
1568 | } |
1569 | |
1570 | #define REG_A6XX_CP_ROQ_MRB_STAT 0x0000093d |
1571 | #define A6XX_CP_ROQ_MRB_STAT_RPTR__MASK 0x000003ff |
1572 | #define A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT 0 |
1573 | static inline uint32_t A6XX_CP_ROQ_MRB_STAT_RPTR(uint32_t val) |
1574 | { |
1575 | return ((val) << A6XX_CP_ROQ_MRB_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_MRB_STAT_RPTR__MASK; |
1576 | } |
1577 | #define A6XX_CP_ROQ_MRB_STAT_WPTR__MASK 0x03ff0000 |
1578 | #define A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT 16 |
1579 | static inline uint32_t A6XX_CP_ROQ_MRB_STAT_WPTR(uint32_t val) |
1580 | { |
1581 | return ((val) << A6XX_CP_ROQ_MRB_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_MRB_STAT_WPTR__MASK; |
1582 | } |
1583 | |
1584 | #define REG_A6XX_CP_ROQ_VSD_STAT 0x0000093e |
1585 | #define A6XX_CP_ROQ_VSD_STAT_RPTR__MASK 0x000003ff |
1586 | #define A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT 0 |
1587 | static inline uint32_t A6XX_CP_ROQ_VSD_STAT_RPTR(uint32_t val) |
1588 | { |
1589 | return ((val) << A6XX_CP_ROQ_VSD_STAT_RPTR__SHIFT) & A6XX_CP_ROQ_VSD_STAT_RPTR__MASK; |
1590 | } |
1591 | #define A6XX_CP_ROQ_VSD_STAT_WPTR__MASK 0x03ff0000 |
1592 | #define A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT 16 |
1593 | static inline uint32_t A6XX_CP_ROQ_VSD_STAT_WPTR(uint32_t val) |
1594 | { |
1595 | return ((val) << A6XX_CP_ROQ_VSD_STAT_WPTR__SHIFT) & A6XX_CP_ROQ_VSD_STAT_WPTR__MASK; |
1596 | } |
1597 | |
1598 | #define REG_A6XX_CP_IB1_DWORDS 0x00000943 |
1599 | |
1600 | #define REG_A6XX_CP_IB2_DWORDS 0x00000944 |
1601 | |
1602 | #define REG_A6XX_CP_SDS_DWORDS 0x00000945 |
1603 | |
1604 | #define REG_A6XX_CP_MRB_DWORDS 0x00000946 |
1605 | |
1606 | #define REG_A6XX_CP_VSD_DWORDS 0x00000947 |
1607 | |
1608 | #define REG_A6XX_CP_ROQ_AVAIL_RB 0x00000948 |
1609 | #define A6XX_CP_ROQ_AVAIL_RB_REM__MASK 0xffff0000 |
1610 | #define A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT 16 |
1611 | static inline uint32_t A6XX_CP_ROQ_AVAIL_RB_REM(uint32_t val) |
1612 | { |
1613 | return ((val) << A6XX_CP_ROQ_AVAIL_RB_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_RB_REM__MASK; |
1614 | } |
1615 | |
1616 | #define REG_A6XX_CP_ROQ_AVAIL_IB1 0x00000949 |
1617 | #define A6XX_CP_ROQ_AVAIL_IB1_REM__MASK 0xffff0000 |
1618 | #define A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT 16 |
1619 | static inline uint32_t A6XX_CP_ROQ_AVAIL_IB1_REM(uint32_t val) |
1620 | { |
1621 | return ((val) << A6XX_CP_ROQ_AVAIL_IB1_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_IB1_REM__MASK; |
1622 | } |
1623 | |
1624 | #define REG_A6XX_CP_ROQ_AVAIL_IB2 0x0000094a |
1625 | #define A6XX_CP_ROQ_AVAIL_IB2_REM__MASK 0xffff0000 |
1626 | #define A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT 16 |
1627 | static inline uint32_t A6XX_CP_ROQ_AVAIL_IB2_REM(uint32_t val) |
1628 | { |
1629 | return ((val) << A6XX_CP_ROQ_AVAIL_IB2_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_IB2_REM__MASK; |
1630 | } |
1631 | |
1632 | #define REG_A6XX_CP_ROQ_AVAIL_SDS 0x0000094b |
1633 | #define A6XX_CP_ROQ_AVAIL_SDS_REM__MASK 0xffff0000 |
1634 | #define A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT 16 |
1635 | static inline uint32_t A6XX_CP_ROQ_AVAIL_SDS_REM(uint32_t val) |
1636 | { |
1637 | return ((val) << A6XX_CP_ROQ_AVAIL_SDS_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_SDS_REM__MASK; |
1638 | } |
1639 | |
1640 | #define REG_A6XX_CP_ROQ_AVAIL_MRB 0x0000094c |
1641 | #define A6XX_CP_ROQ_AVAIL_MRB_REM__MASK 0xffff0000 |
1642 | #define A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT 16 |
1643 | static inline uint32_t A6XX_CP_ROQ_AVAIL_MRB_REM(uint32_t val) |
1644 | { |
1645 | return ((val) << A6XX_CP_ROQ_AVAIL_MRB_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_MRB_REM__MASK; |
1646 | } |
1647 | |
1648 | #define REG_A6XX_CP_ROQ_AVAIL_VSD 0x0000094d |
1649 | #define A6XX_CP_ROQ_AVAIL_VSD_REM__MASK 0xffff0000 |
1650 | #define A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT 16 |
1651 | static inline uint32_t A6XX_CP_ROQ_AVAIL_VSD_REM(uint32_t val) |
1652 | { |
1653 | return ((val) << A6XX_CP_ROQ_AVAIL_VSD_REM__SHIFT) & A6XX_CP_ROQ_AVAIL_VSD_REM__MASK; |
1654 | } |
1655 | |
1656 | #define REG_A6XX_CP_ALWAYS_ON_COUNTER 0x00000980 |
1657 | |
1658 | #define REG_A6XX_CP_AHB_CNTL 0x0000098d |
1659 | |
1660 | #define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00 |
1661 | |
1662 | #define REG_A7XX_CP_APERTURE_CNTL_HOST 0x00000a00 |
1663 | #define A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK 0x00003000 |
1664 | #define A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT 12 |
1665 | static inline uint32_t A7XX_CP_APERTURE_CNTL_HOST_PIPE(enum a7xx_pipe val) |
1666 | { |
1667 | return ((val) << A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK; |
1668 | } |
1669 | #define A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK 0x00000700 |
1670 | #define A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT 8 |
1671 | static inline uint32_t A7XX_CP_APERTURE_CNTL_HOST_CLUSTER(enum a7xx_cluster val) |
1672 | { |
1673 | return ((val) << A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK; |
1674 | } |
1675 | #define A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK 0x00000030 |
1676 | #define A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT 4 |
1677 | static inline uint32_t A7XX_CP_APERTURE_CNTL_HOST_CONTEXT(uint32_t val) |
1678 | { |
1679 | return ((val) << A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK; |
1680 | } |
1681 | |
1682 | #define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03 |
1683 | |
1684 | #define REG_A7XX_CP_APERTURE_CNTL_CD 0x00000a03 |
1685 | #define A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK 0x00003000 |
1686 | #define A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT 12 |
1687 | static inline uint32_t A7XX_CP_APERTURE_CNTL_CD_PIPE(enum a7xx_pipe val) |
1688 | { |
1689 | return ((val) << A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK; |
1690 | } |
1691 | #define A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK 0x00000700 |
1692 | #define A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT 8 |
1693 | static inline uint32_t A7XX_CP_APERTURE_CNTL_CD_CLUSTER(enum a7xx_cluster val) |
1694 | { |
1695 | return ((val) << A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK; |
1696 | } |
1697 | #define A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK 0x00000030 |
1698 | #define A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT 4 |
1699 | static inline uint32_t A7XX_CP_APERTURE_CNTL_CD_CONTEXT(uint32_t val) |
1700 | { |
1701 | return ((val) << A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK; |
1702 | } |
1703 | |
1704 | #define REG_A7XX_CP_BV_PROTECT_STATUS 0x00000a61 |
1705 | |
1706 | #define REG_A7XX_CP_BV_HW_FAULT 0x00000a64 |
1707 | |
1708 | #define REG_A7XX_CP_BV_DRAW_STATE_ADDR 0x00000a81 |
1709 | |
1710 | #define REG_A7XX_CP_BV_DRAW_STATE_DATA 0x00000a82 |
1711 | |
1712 | #define REG_A7XX_CP_BV_ROQ_DBG_ADDR 0x00000a83 |
1713 | |
1714 | #define REG_A7XX_CP_BV_ROQ_DBG_DATA 0x00000a84 |
1715 | |
1716 | #define REG_A7XX_CP_BV_SQE_UCODE_DBG_ADDR 0x00000a85 |
1717 | |
1718 | #define REG_A7XX_CP_BV_SQE_UCODE_DBG_DATA 0x00000a86 |
1719 | |
1720 | #define REG_A7XX_CP_BV_SQE_STAT_ADDR 0x00000a87 |
1721 | |
1722 | #define REG_A7XX_CP_BV_SQE_STAT_DATA 0x00000a88 |
1723 | |
1724 | #define REG_A7XX_CP_BV_MEM_POOL_DBG_ADDR 0x00000a96 |
1725 | |
1726 | #define REG_A7XX_CP_BV_MEM_POOL_DBG_DATA 0x00000a97 |
1727 | |
1728 | #define REG_A7XX_CP_BV_RB_RPTR_ADDR 0x00000a98 |
1729 | |
1730 | #define REG_A7XX_CP_RESOURCE_TBL_DBG_ADDR 0x00000a9a |
1731 | |
1732 | #define REG_A7XX_CP_RESOURCE_TBL_DBG_DATA 0x00000a9b |
1733 | |
1734 | #define REG_A7XX_CP_BV_APRIV_CNTL 0x00000ad0 |
1735 | |
1736 | #define REG_A7XX_CP_BV_CHICKEN_DBG 0x00000ada |
1737 | |
1738 | #define REG_A7XX_CP_LPAC_DRAW_STATE_ADDR 0x00000b0a |
1739 | |
1740 | #define REG_A7XX_CP_LPAC_DRAW_STATE_DATA 0x00000b0b |
1741 | |
1742 | #define REG_A7XX_CP_LPAC_ROQ_DBG_ADDR 0x00000b0c |
1743 | |
1744 | #define REG_A7XX_CP_SQE_AC_UCODE_DBG_ADDR 0x00000b27 |
1745 | |
1746 | #define REG_A7XX_CP_SQE_AC_UCODE_DBG_DATA 0x00000b28 |
1747 | |
1748 | #define REG_A7XX_CP_SQE_AC_STAT_ADDR 0x00000b29 |
1749 | |
1750 | #define REG_A7XX_CP_SQE_AC_STAT_DATA 0x00000b2a |
1751 | |
1752 | #define REG_A7XX_CP_LPAC_APRIV_CNTL 0x00000b31 |
1753 | |
1754 | #define REG_A6XX_CP_LPAC_PROG_FIFO_SIZE 0x00000b34 |
1755 | |
1756 | #define REG_A7XX_CP_LPAC_ROQ_DBG_DATA 0x00000b35 |
1757 | |
1758 | #define REG_A7XX_CP_LPAC_FIFO_DBG_DATA 0x00000b36 |
1759 | |
1760 | #define REG_A7XX_CP_LPAC_FIFO_DBG_ADDR 0x00000b40 |
1761 | |
1762 | #define REG_A6XX_CP_LPAC_SQE_INSTR_BASE 0x00000b82 |
1763 | |
1764 | #define REG_A6XX_VSC_ADDR_MODE_CNTL 0x00000c01 |
1765 | |
1766 | #define REG_A6XX_RBBM_GPR0_CNTL 0x00000018 |
1767 | |
1768 | #define REG_A6XX_RBBM_INT_0_STATUS 0x00000201 |
1769 | #define REG_A6XX_RBBM_STATUS 0x00000210 |
1770 | #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000 |
1771 | #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000 |
1772 | #define A6XX_RBBM_STATUS_HLSQ_BUSY 0x00200000 |
1773 | #define A6XX_RBBM_STATUS_VSC_BUSY 0x00100000 |
1774 | #define A6XX_RBBM_STATUS_TPL1_BUSY 0x00080000 |
1775 | #define A6XX_RBBM_STATUS_SP_BUSY 0x00040000 |
1776 | #define A6XX_RBBM_STATUS_UCHE_BUSY 0x00020000 |
1777 | #define A6XX_RBBM_STATUS_VPC_BUSY 0x00010000 |
1778 | #define A6XX_RBBM_STATUS_VFD_BUSY 0x00008000 |
1779 | #define A6XX_RBBM_STATUS_TESS_BUSY 0x00004000 |
1780 | #define A6XX_RBBM_STATUS_PC_VSD_BUSY 0x00002000 |
1781 | #define A6XX_RBBM_STATUS_PC_DCALL_BUSY 0x00001000 |
1782 | #define A6XX_RBBM_STATUS_COM_DCOM_BUSY 0x00000800 |
1783 | #define A6XX_RBBM_STATUS_LRZ_BUSY 0x00000400 |
1784 | #define A6XX_RBBM_STATUS_A2D_BUSY 0x00000200 |
1785 | #define A6XX_RBBM_STATUS_CCU_BUSY 0x00000100 |
1786 | #define A6XX_RBBM_STATUS_RB_BUSY 0x00000080 |
1787 | #define A6XX_RBBM_STATUS_RAS_BUSY 0x00000040 |
1788 | #define A6XX_RBBM_STATUS_TSE_BUSY 0x00000020 |
1789 | #define A6XX_RBBM_STATUS_VBIF_BUSY 0x00000010 |
1790 | #define A6XX_RBBM_STATUS_GFX_DBGC_BUSY 0x00000008 |
1791 | #define A6XX_RBBM_STATUS_CP_BUSY 0x00000004 |
1792 | #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CP_MASTER 0x00000002 |
1793 | #define A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER 0x00000001 |
1794 | |
1795 | #define REG_A6XX_RBBM_STATUS1 0x00000211 |
1796 | |
1797 | #define REG_A6XX_RBBM_STATUS2 0x00000212 |
1798 | |
1799 | #define REG_A6XX_RBBM_STATUS3 0x00000213 |
1800 | #define A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT 0x01000000 |
1801 | |
1802 | #define REG_A6XX_RBBM_VBIF_GX_RESET_STATUS 0x00000215 |
1803 | |
1804 | #define REG_A7XX_RBBM_CLOCK_MODE_CP 0x00000260 |
1805 | |
1806 | #define REG_A7XX_RBBM_CLOCK_MODE_BV_LRZ 0x00000284 |
1807 | |
1808 | #define REG_A7XX_RBBM_CLOCK_MODE_BV_GRAS 0x00000285 |
1809 | |
1810 | #define REG_A7XX_RBBM_CLOCK_MODE2_GRAS 0x00000286 |
1811 | |
1812 | #define REG_A7XX_RBBM_CLOCK_MODE_BV_VFD 0x00000287 |
1813 | |
1814 | #define REG_A7XX_RBBM_CLOCK_MODE_BV_GPC 0x00000288 |
1815 | |
1816 | #define REG_A6XX_RBBM_PERFCTR_CP(i0) (0x00000400 + 0x2*(i0)) |
1817 | |
1818 | #define REG_A6XX_RBBM_PERFCTR_RBBM(i0) (0x0000041c + 0x2*(i0)) |
1819 | |
1820 | #define REG_A6XX_RBBM_PERFCTR_PC(i0) (0x00000424 + 0x2*(i0)) |
1821 | |
1822 | #define REG_A6XX_RBBM_PERFCTR_VFD(i0) (0x00000434 + 0x2*(i0)) |
1823 | |
1824 | #define REG_A6XX_RBBM_PERFCTR_HLSQ(i0) (0x00000444 + 0x2*(i0)) |
1825 | |
1826 | #define REG_A6XX_RBBM_PERFCTR_VPC(i0) (0x00000450 + 0x2*(i0)) |
1827 | |
1828 | #define REG_A6XX_RBBM_PERFCTR_CCU(i0) (0x0000045c + 0x2*(i0)) |
1829 | |
1830 | #define REG_A6XX_RBBM_PERFCTR_TSE(i0) (0x00000466 + 0x2*(i0)) |
1831 | |
1832 | #define REG_A6XX_RBBM_PERFCTR_RAS(i0) (0x0000046e + 0x2*(i0)) |
1833 | |
1834 | #define REG_A6XX_RBBM_PERFCTR_UCHE(i0) (0x00000476 + 0x2*(i0)) |
1835 | |
1836 | #define REG_A6XX_RBBM_PERFCTR_TP(i0) (0x0000048e + 0x2*(i0)) |
1837 | |
1838 | #define REG_A6XX_RBBM_PERFCTR_SP(i0) (0x000004a6 + 0x2*(i0)) |
1839 | |
1840 | #define REG_A6XX_RBBM_PERFCTR_RB(i0) (0x000004d6 + 0x2*(i0)) |
1841 | |
1842 | #define REG_A6XX_RBBM_PERFCTR_VSC(i0) (0x000004e6 + 0x2*(i0)) |
1843 | |
1844 | #define REG_A6XX_RBBM_PERFCTR_LRZ(i0) (0x000004ea + 0x2*(i0)) |
1845 | |
1846 | #define REG_A6XX_RBBM_PERFCTR_CMP(i0) (0x000004f2 + 0x2*(i0)) |
1847 | |
1848 | #define REG_A7XX_RBBM_PERFCTR_CP(i0) (0x00000300 + 0x2*(i0)) |
1849 | |
1850 | #define REG_A7XX_RBBM_PERFCTR_RBBM(i0) (0x0000031c + 0x2*(i0)) |
1851 | |
1852 | #define REG_A7XX_RBBM_PERFCTR_PC(i0) (0x00000324 + 0x2*(i0)) |
1853 | |
1854 | #define REG_A7XX_RBBM_PERFCTR_VFD(i0) (0x00000334 + 0x2*(i0)) |
1855 | |
1856 | #define REG_A7XX_RBBM_PERFCTR_HLSQ(i0) (0x00000344 + 0x2*(i0)) |
1857 | |
1858 | #define REG_A7XX_RBBM_PERFCTR_VPC(i0) (0x00000350 + 0x2*(i0)) |
1859 | |
1860 | #define REG_A7XX_RBBM_PERFCTR_CCU(i0) (0x0000035c + 0x2*(i0)) |
1861 | |
1862 | #define REG_A7XX_RBBM_PERFCTR_TSE(i0) (0x00000366 + 0x2*(i0)) |
1863 | |
1864 | #define REG_A7XX_RBBM_PERFCTR_RAS(i0) (0x0000036e + 0x2*(i0)) |
1865 | |
1866 | #define REG_A7XX_RBBM_PERFCTR_UCHE(i0) (0x00000376 + 0x2*(i0)) |
1867 | |
1868 | #define REG_A7XX_RBBM_PERFCTR_TP(i0) (0x0000038e + 0x2*(i0)) |
1869 | |
1870 | #define REG_A7XX_RBBM_PERFCTR_SP(i0) (0x000003a6 + 0x2*(i0)) |
1871 | |
1872 | #define REG_A7XX_RBBM_PERFCTR_RB(i0) (0x000003d6 + 0x2*(i0)) |
1873 | |
1874 | #define REG_A7XX_RBBM_PERFCTR_VSC(i0) (0x000003e6 + 0x2*(i0)) |
1875 | |
1876 | #define REG_A7XX_RBBM_PERFCTR_LRZ(i0) (0x000003ea + 0x2*(i0)) |
1877 | |
1878 | #define REG_A7XX_RBBM_PERFCTR_CMP(i0) (0x000003f2 + 0x2*(i0)) |
1879 | |
1880 | #define REG_A7XX_RBBM_PERFCTR_UFC(i0) (0x000003fa + 0x2*(i0)) |
1881 | |
1882 | #define REG_A7XX_RBBM_PERFCTR2_HLSQ(i0) (0x00000410 + 0x2*(i0)) |
1883 | |
1884 | #define REG_A7XX_RBBM_PERFCTR2_CP(i0) (0x0000041c + 0x2*(i0)) |
1885 | |
1886 | #define REG_A7XX_RBBM_PERFCTR2_SP(i0) (0x0000042a + 0x2*(i0)) |
1887 | |
1888 | #define REG_A7XX_RBBM_PERFCTR2_TP(i0) (0x00000442 + 0x2*(i0)) |
1889 | |
1890 | #define REG_A7XX_RBBM_PERFCTR2_UFC(i0) (0x0000044e + 0x2*(i0)) |
1891 | |
1892 | #define REG_A7XX_RBBM_PERFCTR_BV_PC(i0) (0x00000460 + 0x2*(i0)) |
1893 | |
1894 | #define REG_A7XX_RBBM_PERFCTR_BV_VFD(i0) (0x00000470 + 0x2*(i0)) |
1895 | |
1896 | #define REG_A7XX_RBBM_PERFCTR_BV_VPC(i0) (0x00000480 + 0x2*(i0)) |
1897 | |
1898 | #define REG_A7XX_RBBM_PERFCTR_BV_TSE(i0) (0x0000048c + 0x2*(i0)) |
1899 | |
1900 | #define REG_A7XX_RBBM_PERFCTR_BV_RAS(i0) (0x00000494 + 0x2*(i0)) |
1901 | |
1902 | #define REG_A7XX_RBBM_PERFCTR_BV_LRZ(i0) (0x0000049c + 0x2*(i0)) |
1903 | |
1904 | #define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500 |
1905 | |
1906 | #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD0 0x00000501 |
1907 | |
1908 | #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD1 0x00000502 |
1909 | |
1910 | #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD2 0x00000503 |
1911 | |
1912 | #define REG_A6XX_RBBM_PERFCTR_LOAD_CMD3 0x00000504 |
1913 | |
1914 | #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000505 |
1915 | |
1916 | #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506 |
1917 | |
1918 | #define REG_A6XX_RBBM_PERFCTR_RBBM_SEL(i0) (0x00000507 + 0x1*(i0)) |
1919 | |
1920 | #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b |
1921 | |
1922 | #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD 0x0000050e |
1923 | |
1924 | #define REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS 0x0000050f |
1925 | |
1926 | #define REG_A6XX_RBBM_ISDB_CNT 0x00000533 |
1927 | |
1928 | #define REG_A7XX_RBBM_NC_MODE_CNTL 0x00000534 |
1929 | |
1930 | #define REG_A7XX_RBBM_SNAPSHOT_STATUS 0x00000535 |
1931 | |
1932 | #define REG_A6XX_RBBM_PRIMCTR_0_LO 0x00000540 |
1933 | |
1934 | #define REG_A6XX_RBBM_PRIMCTR_0_HI 0x00000541 |
1935 | |
1936 | #define REG_A6XX_RBBM_PRIMCTR_1_LO 0x00000542 |
1937 | |
1938 | #define REG_A6XX_RBBM_PRIMCTR_1_HI 0x00000543 |
1939 | |
1940 | #define REG_A6XX_RBBM_PRIMCTR_2_LO 0x00000544 |
1941 | |
1942 | #define REG_A6XX_RBBM_PRIMCTR_2_HI 0x00000545 |
1943 | |
1944 | #define REG_A6XX_RBBM_PRIMCTR_3_LO 0x00000546 |
1945 | |
1946 | #define REG_A6XX_RBBM_PRIMCTR_3_HI 0x00000547 |
1947 | |
1948 | #define REG_A6XX_RBBM_PRIMCTR_4_LO 0x00000548 |
1949 | |
1950 | #define REG_A6XX_RBBM_PRIMCTR_4_HI 0x00000549 |
1951 | |
1952 | #define REG_A6XX_RBBM_PRIMCTR_5_LO 0x0000054a |
1953 | |
1954 | #define REG_A6XX_RBBM_PRIMCTR_5_HI 0x0000054b |
1955 | |
1956 | #define REG_A6XX_RBBM_PRIMCTR_6_LO 0x0000054c |
1957 | |
1958 | #define REG_A6XX_RBBM_PRIMCTR_6_HI 0x0000054d |
1959 | |
1960 | #define REG_A6XX_RBBM_PRIMCTR_7_LO 0x0000054e |
1961 | |
1962 | #define REG_A6XX_RBBM_PRIMCTR_7_HI 0x0000054f |
1963 | |
1964 | #define REG_A6XX_RBBM_PRIMCTR_8_LO 0x00000550 |
1965 | |
1966 | #define REG_A6XX_RBBM_PRIMCTR_8_HI 0x00000551 |
1967 | |
1968 | #define REG_A6XX_RBBM_PRIMCTR_9_LO 0x00000552 |
1969 | |
1970 | #define REG_A6XX_RBBM_PRIMCTR_9_HI 0x00000553 |
1971 | |
1972 | #define REG_A6XX_RBBM_PRIMCTR_10_LO 0x00000554 |
1973 | |
1974 | #define REG_A6XX_RBBM_PRIMCTR_10_HI 0x00000555 |
1975 | |
1976 | #define REG_A6XX_RBBM_SECVID_TRUST_CNTL 0x0000f400 |
1977 | |
1978 | #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE 0x0000f800 |
1979 | |
1980 | #define REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE 0x0000f802 |
1981 | |
1982 | #define REG_A6XX_RBBM_SECVID_TSB_CNTL 0x0000f803 |
1983 | |
1984 | #define REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810 |
1985 | |
1986 | #define REG_A7XX_RBBM_SECVID_TSB_STATUS 0x0000fc00 |
1987 | |
1988 | #define REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL 0x00000010 |
1989 | |
1990 | #define REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL 0x00000011 |
1991 | |
1992 | #define REG_A6XX_RBBM_GBIF_HALT 0x00000016 |
1993 | |
1994 | #define REG_A6XX_RBBM_GBIF_HALT_ACK 0x00000017 |
1995 | |
1996 | #define REG_A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD 0x0000001c |
1997 | #define A6XX_RBBM_WAIT_FOR_GPU_IDLE_CMD_WAIT_GPU_IDLE 0x00000001 |
1998 | |
1999 | #define REG_A7XX_RBBM_GBIF_HALT 0x00000016 |
2000 | |
2001 | #define REG_A7XX_RBBM_GBIF_HALT_ACK 0x00000017 |
2002 | |
2003 | #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f |
2004 | |
2005 | #define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037 |
2006 | #define REG_A6XX_RBBM_INT_0_MASK 0x00000038 |
2007 | #define REG_A7XX_RBBM_INT_2_MASK 0x0000003a |
2008 | |
2009 | #define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042 |
2010 | |
2011 | #define REG_A6XX_RBBM_SW_RESET_CMD 0x00000043 |
2012 | |
2013 | #define REG_A6XX_RBBM_RAC_THRESHOLD_CNT 0x00000044 |
2014 | |
2015 | #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD 0x00000045 |
2016 | |
2017 | #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 |
2018 | |
2019 | #define REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL 0x000000ad |
2020 | |
2021 | #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae |
2022 | |
2023 | #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 |
2024 | |
2025 | #define REG_A6XX_RBBM_CLOCK_CNTL_SP1 0x000000b1 |
2026 | |
2027 | #define REG_A6XX_RBBM_CLOCK_CNTL_SP2 0x000000b2 |
2028 | |
2029 | #define REG_A6XX_RBBM_CLOCK_CNTL_SP3 0x000000b3 |
2030 | |
2031 | #define REG_A6XX_RBBM_CLOCK_CNTL2_SP0 0x000000b4 |
2032 | |
2033 | #define REG_A6XX_RBBM_CLOCK_CNTL2_SP1 0x000000b5 |
2034 | |
2035 | #define REG_A6XX_RBBM_CLOCK_CNTL2_SP2 0x000000b6 |
2036 | |
2037 | #define REG_A6XX_RBBM_CLOCK_CNTL2_SP3 0x000000b7 |
2038 | |
2039 | #define REG_A6XX_RBBM_CLOCK_DELAY_SP0 0x000000b8 |
2040 | |
2041 | #define REG_A6XX_RBBM_CLOCK_DELAY_SP1 0x000000b9 |
2042 | |
2043 | #define REG_A6XX_RBBM_CLOCK_DELAY_SP2 0x000000ba |
2044 | |
2045 | #define REG_A6XX_RBBM_CLOCK_DELAY_SP3 0x000000bb |
2046 | |
2047 | #define REG_A6XX_RBBM_CLOCK_HYST_SP0 0x000000bc |
2048 | |
2049 | #define REG_A6XX_RBBM_CLOCK_HYST_SP1 0x000000bd |
2050 | |
2051 | #define REG_A6XX_RBBM_CLOCK_HYST_SP2 0x000000be |
2052 | |
2053 | #define REG_A6XX_RBBM_CLOCK_HYST_SP3 0x000000bf |
2054 | |
2055 | #define REG_A6XX_RBBM_CLOCK_CNTL_TP0 0x000000c0 |
2056 | |
2057 | #define REG_A6XX_RBBM_CLOCK_CNTL_TP1 0x000000c1 |
2058 | |
2059 | #define REG_A6XX_RBBM_CLOCK_CNTL_TP2 0x000000c2 |
2060 | |
2061 | #define REG_A6XX_RBBM_CLOCK_CNTL_TP3 0x000000c3 |
2062 | |
2063 | #define REG_A6XX_RBBM_CLOCK_CNTL2_TP0 0x000000c4 |
2064 | |
2065 | #define REG_A6XX_RBBM_CLOCK_CNTL2_TP1 0x000000c5 |
2066 | |
2067 | #define REG_A6XX_RBBM_CLOCK_CNTL2_TP2 0x000000c6 |
2068 | |
2069 | #define REG_A6XX_RBBM_CLOCK_CNTL2_TP3 0x000000c7 |
2070 | |
2071 | #define REG_A6XX_RBBM_CLOCK_CNTL3_TP0 0x000000c8 |
2072 | |
2073 | #define REG_A6XX_RBBM_CLOCK_CNTL3_TP1 0x000000c9 |
2074 | |
2075 | #define REG_A6XX_RBBM_CLOCK_CNTL3_TP2 0x000000ca |
2076 | |
2077 | #define REG_A6XX_RBBM_CLOCK_CNTL3_TP3 0x000000cb |
2078 | |
2079 | #define REG_A6XX_RBBM_CLOCK_CNTL4_TP0 0x000000cc |
2080 | |
2081 | #define REG_A6XX_RBBM_CLOCK_CNTL4_TP1 0x000000cd |
2082 | |
2083 | #define REG_A6XX_RBBM_CLOCK_CNTL4_TP2 0x000000ce |
2084 | |
2085 | #define REG_A6XX_RBBM_CLOCK_CNTL4_TP3 0x000000cf |
2086 | |
2087 | #define REG_A6XX_RBBM_CLOCK_DELAY_TP0 0x000000d0 |
2088 | |
2089 | #define REG_A6XX_RBBM_CLOCK_DELAY_TP1 0x000000d1 |
2090 | |
2091 | #define REG_A6XX_RBBM_CLOCK_DELAY_TP2 0x000000d2 |
2092 | |
2093 | #define REG_A6XX_RBBM_CLOCK_DELAY_TP3 0x000000d3 |
2094 | |
2095 | #define REG_A6XX_RBBM_CLOCK_DELAY2_TP0 0x000000d4 |
2096 | |
2097 | #define REG_A6XX_RBBM_CLOCK_DELAY2_TP1 0x000000d5 |
2098 | |
2099 | #define REG_A6XX_RBBM_CLOCK_DELAY2_TP2 0x000000d6 |
2100 | |
2101 | #define REG_A6XX_RBBM_CLOCK_DELAY2_TP3 0x000000d7 |
2102 | |
2103 | #define REG_A6XX_RBBM_CLOCK_DELAY3_TP0 0x000000d8 |
2104 | |
2105 | #define REG_A6XX_RBBM_CLOCK_DELAY3_TP1 0x000000d9 |
2106 | |
2107 | #define REG_A6XX_RBBM_CLOCK_DELAY3_TP2 0x000000da |
2108 | |
2109 | #define REG_A6XX_RBBM_CLOCK_DELAY3_TP3 0x000000db |
2110 | |
2111 | #define REG_A6XX_RBBM_CLOCK_DELAY4_TP0 0x000000dc |
2112 | |
2113 | #define REG_A6XX_RBBM_CLOCK_DELAY4_TP1 0x000000dd |
2114 | |
2115 | #define REG_A6XX_RBBM_CLOCK_DELAY4_TP2 0x000000de |
2116 | |
2117 | #define REG_A6XX_RBBM_CLOCK_DELAY4_TP3 0x000000df |
2118 | |
2119 | #define REG_A6XX_RBBM_CLOCK_HYST_TP0 0x000000e0 |
2120 | |
2121 | #define REG_A6XX_RBBM_CLOCK_HYST_TP1 0x000000e1 |
2122 | |
2123 | #define REG_A6XX_RBBM_CLOCK_HYST_TP2 0x000000e2 |
2124 | |
2125 | #define REG_A6XX_RBBM_CLOCK_HYST_TP3 0x000000e3 |
2126 | |
2127 | #define REG_A6XX_RBBM_CLOCK_HYST2_TP0 0x000000e4 |
2128 | |
2129 | #define REG_A6XX_RBBM_CLOCK_HYST2_TP1 0x000000e5 |
2130 | |
2131 | #define REG_A6XX_RBBM_CLOCK_HYST2_TP2 0x000000e6 |
2132 | |
2133 | #define REG_A6XX_RBBM_CLOCK_HYST2_TP3 0x000000e7 |
2134 | |
2135 | #define REG_A6XX_RBBM_CLOCK_HYST3_TP0 0x000000e8 |
2136 | |
2137 | #define REG_A6XX_RBBM_CLOCK_HYST3_TP1 0x000000e9 |
2138 | |
2139 | #define REG_A6XX_RBBM_CLOCK_HYST3_TP2 0x000000ea |
2140 | |
2141 | #define REG_A6XX_RBBM_CLOCK_HYST3_TP3 0x000000eb |
2142 | |
2143 | #define REG_A6XX_RBBM_CLOCK_HYST4_TP0 0x000000ec |
2144 | |
2145 | #define REG_A6XX_RBBM_CLOCK_HYST4_TP1 0x000000ed |
2146 | |
2147 | #define REG_A6XX_RBBM_CLOCK_HYST4_TP2 0x000000ee |
2148 | |
2149 | #define REG_A6XX_RBBM_CLOCK_HYST4_TP3 0x000000ef |
2150 | |
2151 | #define REG_A6XX_RBBM_CLOCK_CNTL_RB0 0x000000f0 |
2152 | |
2153 | #define REG_A6XX_RBBM_CLOCK_CNTL_RB1 0x000000f1 |
2154 | |
2155 | #define REG_A6XX_RBBM_CLOCK_CNTL_RB2 0x000000f2 |
2156 | |
2157 | #define REG_A6XX_RBBM_CLOCK_CNTL_RB3 0x000000f3 |
2158 | |
2159 | #define REG_A6XX_RBBM_CLOCK_CNTL2_RB0 0x000000f4 |
2160 | |
2161 | #define REG_A6XX_RBBM_CLOCK_CNTL2_RB1 0x000000f5 |
2162 | |
2163 | #define REG_A6XX_RBBM_CLOCK_CNTL2_RB2 0x000000f6 |
2164 | |
2165 | #define REG_A6XX_RBBM_CLOCK_CNTL2_RB3 0x000000f7 |
2166 | |
2167 | #define REG_A6XX_RBBM_CLOCK_CNTL_CCU0 0x000000f8 |
2168 | |
2169 | #define REG_A6XX_RBBM_CLOCK_CNTL_CCU1 0x000000f9 |
2170 | |
2171 | #define REG_A6XX_RBBM_CLOCK_CNTL_CCU2 0x000000fa |
2172 | |
2173 | #define REG_A6XX_RBBM_CLOCK_CNTL_CCU3 0x000000fb |
2174 | |
2175 | #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0 0x00000100 |
2176 | |
2177 | #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1 0x00000101 |
2178 | |
2179 | #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2 0x00000102 |
2180 | |
2181 | #define REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3 0x00000103 |
2182 | |
2183 | #define REG_A6XX_RBBM_CLOCK_CNTL_RAC 0x00000104 |
2184 | |
2185 | #define REG_A6XX_RBBM_CLOCK_CNTL2_RAC 0x00000105 |
2186 | |
2187 | #define REG_A6XX_RBBM_CLOCK_DELAY_RAC 0x00000106 |
2188 | |
2189 | #define REG_A6XX_RBBM_CLOCK_HYST_RAC 0x00000107 |
2190 | |
2191 | #define REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM 0x00000108 |
2192 | |
2193 | #define REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM 0x00000109 |
2194 | |
2195 | #define REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM 0x0000010a |
2196 | |
2197 | #define REG_A6XX_RBBM_CLOCK_CNTL_UCHE 0x0000010b |
2198 | |
2199 | #define REG_A6XX_RBBM_CLOCK_CNTL2_UCHE 0x0000010c |
2200 | |
2201 | #define REG_A6XX_RBBM_CLOCK_CNTL3_UCHE 0x0000010d |
2202 | |
2203 | #define REG_A6XX_RBBM_CLOCK_CNTL4_UCHE 0x0000010e |
2204 | |
2205 | #define REG_A6XX_RBBM_CLOCK_DELAY_UCHE 0x0000010f |
2206 | |
2207 | #define REG_A6XX_RBBM_CLOCK_HYST_UCHE 0x00000110 |
2208 | |
2209 | #define REG_A6XX_RBBM_CLOCK_MODE_VFD 0x00000111 |
2210 | |
2211 | #define REG_A6XX_RBBM_CLOCK_DELAY_VFD 0x00000112 |
2212 | |
2213 | #define REG_A6XX_RBBM_CLOCK_HYST_VFD 0x00000113 |
2214 | |
2215 | #define REG_A6XX_RBBM_CLOCK_MODE_GPC 0x00000114 |
2216 | |
2217 | #define REG_A6XX_RBBM_CLOCK_DELAY_GPC 0x00000115 |
2218 | |
2219 | #define REG_A6XX_RBBM_CLOCK_HYST_GPC 0x00000116 |
2220 | |
2221 | #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2 0x00000117 |
2222 | |
2223 | #define REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX 0x00000118 |
2224 | |
2225 | #define REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX 0x00000119 |
2226 | |
2227 | #define REG_A6XX_RBBM_CLOCK_HYST_GMU_GX 0x0000011a |
2228 | |
2229 | #define REG_A6XX_RBBM_CLOCK_MODE_HLSQ 0x0000011b |
2230 | |
2231 | #define REG_A6XX_RBBM_CLOCK_DELAY_HLSQ 0x0000011c |
2232 | |
2233 | #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d |
2234 | |
2235 | #define REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD 0x0000011e |
2236 | |
2237 | #define REG_A7XX_RBBM_CGC_P2S_TRIG_CMD 0x0000011f |
2238 | |
2239 | #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120 |
2240 | |
2241 | #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121 |
2242 | |
2243 | #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 |
2244 | |
2245 | #define REG_A7XX_RBBM_CGC_P2S_STATUS 0x00000122 |
2246 | #define A7XX_RBBM_CGC_P2S_STATUS_TXDONE 0x00000001 |
2247 | |
2248 | #define REG_A6XX_RBBM_CLOCK_CNTL_FCHE 0x00000123 |
2249 | |
2250 | #define REG_A6XX_RBBM_CLOCK_DELAY_FCHE 0x00000124 |
2251 | |
2252 | #define REG_A6XX_RBBM_CLOCK_HYST_FCHE 0x00000125 |
2253 | |
2254 | #define REG_A6XX_RBBM_CLOCK_CNTL_MHUB 0x00000126 |
2255 | |
2256 | #define REG_A6XX_RBBM_CLOCK_DELAY_MHUB 0x00000127 |
2257 | |
2258 | #define REG_A6XX_RBBM_CLOCK_HYST_MHUB 0x00000128 |
2259 | |
2260 | #define REG_A6XX_RBBM_CLOCK_DELAY_GLC 0x00000129 |
2261 | |
2262 | #define REG_A6XX_RBBM_CLOCK_HYST_GLC 0x0000012a |
2263 | |
2264 | #define REG_A6XX_RBBM_CLOCK_CNTL_GLC 0x0000012b |
2265 | |
2266 | #define REG_A7XX_RBBM_CLOCK_HYST2_VFD 0x0000012f |
2267 | |
2268 | #define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff |
2269 | |
2270 | #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_A 0x00000600 |
2271 | |
2272 | #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_B 0x00000601 |
2273 | |
2274 | #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_C 0x00000602 |
2275 | |
2276 | #define REG_A6XX_DBGC_CFG_DBGBUS_SEL_D 0x00000603 |
2277 | #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK 0x000000ff |
2278 | #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT 0 |
2279 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX(uint32_t val) |
2280 | { |
2281 | return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_INDEX__MASK; |
2282 | } |
2283 | #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK 0x0000ff00 |
2284 | #define A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT 8 |
2285 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL(uint32_t val) |
2286 | { |
2287 | return ((val) << A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__SHIFT) & A6XX_DBGC_CFG_DBGBUS_SEL_D_PING_BLK_SEL__MASK; |
2288 | } |
2289 | |
2290 | #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLT 0x00000604 |
2291 | #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f |
2292 | #define A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 |
2293 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) |
2294 | { |
2295 | return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; |
2296 | } |
2297 | #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 |
2298 | #define A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 |
2299 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) |
2300 | { |
2301 | return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; |
2302 | } |
2303 | #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 |
2304 | #define A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 |
2305 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) |
2306 | { |
2307 | return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; |
2308 | } |
2309 | |
2310 | #define REG_A6XX_DBGC_CFG_DBGBUS_CNTLM 0x00000605 |
2311 | #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 |
2312 | #define A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 |
2313 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) |
2314 | { |
2315 | return ((val) << A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; |
2316 | } |
2317 | |
2318 | #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_0 0x00000608 |
2319 | |
2320 | #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_1 0x00000609 |
2321 | |
2322 | #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_2 0x0000060a |
2323 | |
2324 | #define REG_A6XX_DBGC_CFG_DBGBUS_IVTL_3 0x0000060b |
2325 | |
2326 | #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_0 0x0000060c |
2327 | |
2328 | #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_1 0x0000060d |
2329 | |
2330 | #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_2 0x0000060e |
2331 | |
2332 | #define REG_A6XX_DBGC_CFG_DBGBUS_MASKL_3 0x0000060f |
2333 | |
2334 | #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000610 |
2335 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f |
2336 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 |
2337 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) |
2338 | { |
2339 | return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; |
2340 | } |
2341 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 |
2342 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 |
2343 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) |
2344 | { |
2345 | return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; |
2346 | } |
2347 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 |
2348 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 |
2349 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) |
2350 | { |
2351 | return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; |
2352 | } |
2353 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 |
2354 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 |
2355 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) |
2356 | { |
2357 | return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; |
2358 | } |
2359 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 |
2360 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 |
2361 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) |
2362 | { |
2363 | return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; |
2364 | } |
2365 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 |
2366 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 |
2367 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) |
2368 | { |
2369 | return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; |
2370 | } |
2371 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 |
2372 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 |
2373 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) |
2374 | { |
2375 | return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; |
2376 | } |
2377 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 |
2378 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 |
2379 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) |
2380 | { |
2381 | return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; |
2382 | } |
2383 | |
2384 | #define REG_A6XX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000611 |
2385 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f |
2386 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 |
2387 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) |
2388 | { |
2389 | return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; |
2390 | } |
2391 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 |
2392 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 |
2393 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) |
2394 | { |
2395 | return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; |
2396 | } |
2397 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 |
2398 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 |
2399 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) |
2400 | { |
2401 | return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; |
2402 | } |
2403 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 |
2404 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 |
2405 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) |
2406 | { |
2407 | return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; |
2408 | } |
2409 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 |
2410 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 |
2411 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) |
2412 | { |
2413 | return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; |
2414 | } |
2415 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 |
2416 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 |
2417 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) |
2418 | { |
2419 | return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; |
2420 | } |
2421 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 |
2422 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 |
2423 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) |
2424 | { |
2425 | return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; |
2426 | } |
2427 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 |
2428 | #define A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 |
2429 | static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) |
2430 | { |
2431 | return ((val) << A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; |
2432 | } |
2433 | |
2434 | #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000062f |
2435 | |
2436 | #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630 |
2437 | |
2438 | #define REG_A6XX_VSC_PERFCTR_VSC_SEL(i0) (0x00000cd8 + 0x1*(i0)) |
2439 | |
2440 | #define REG_A7XX_VSC_UNKNOWN_0CD8 0x00000cd8 |
2441 | #define A7XX_VSC_UNKNOWN_0CD8_BINNING 0x00000001 |
2442 | |
2443 | #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800 |
2444 | |
2445 | #define REG_A6XX_HLSQ_DBG_READ_SEL 0x0000d000 |
2446 | |
2447 | #define REG_A6XX_UCHE_ADDR_MODE_CNTL 0x00000e00 |
2448 | |
2449 | #define REG_A6XX_UCHE_MODE_CNTL 0x00000e01 |
2450 | |
2451 | #define REG_A6XX_UCHE_WRITE_RANGE_MAX 0x00000e05 |
2452 | |
2453 | #define REG_A6XX_UCHE_WRITE_THRU_BASE 0x00000e07 |
2454 | |
2455 | #define REG_A6XX_UCHE_TRAP_BASE 0x00000e09 |
2456 | |
2457 | #define REG_A6XX_UCHE_GMEM_RANGE_MIN 0x00000e0b |
2458 | |
2459 | #define REG_A6XX_UCHE_GMEM_RANGE_MAX 0x00000e0d |
2460 | |
2461 | #define REG_A6XX_UCHE_CACHE_WAYS 0x00000e17 |
2462 | |
2463 | #define REG_A6XX_UCHE_FILTER_CNTL 0x00000e18 |
2464 | |
2465 | #define REG_A6XX_UCHE_CLIENT_PF 0x00000e19 |
2466 | #define A6XX_UCHE_CLIENT_PF_PERFSEL__MASK 0x000000ff |
2467 | #define A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT 0 |
2468 | static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) |
2469 | { |
2470 | return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK; |
2471 | } |
2472 | |
2473 | #define REG_A6XX_UCHE_PERFCTR_UCHE_SEL(i0) (0x00000e1c + 0x1*(i0)) |
2474 | |
2475 | #define REG_A6XX_UCHE_GBIF_GX_CONFIG 0x00000e3a |
2476 | |
2477 | #define REG_A6XX_UCHE_CMDQ_CONFIG 0x00000e3c |
2478 | |
2479 | #define REG_A6XX_VBIF_VERSION 0x00003000 |
2480 | |
2481 | #define REG_A6XX_VBIF_CLKON 0x00003001 |
2482 | #define A6XX_VBIF_CLKON_FORCE_ON_TESTBUS 0x00000002 |
2483 | |
2484 | #define REG_A6XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a |
2485 | |
2486 | #define REG_A6XX_VBIF_XIN_HALT_CTRL0 0x00003080 |
2487 | |
2488 | #define REG_A6XX_VBIF_XIN_HALT_CTRL1 0x00003081 |
2489 | |
2490 | #define REG_A6XX_VBIF_TEST_BUS_OUT_CTRL 0x00003084 |
2491 | |
2492 | #define REG_A6XX_VBIF_TEST_BUS1_CTRL0 0x00003085 |
2493 | |
2494 | #define REG_A6XX_VBIF_TEST_BUS1_CTRL1 0x00003086 |
2495 | #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK 0x0000000f |
2496 | #define A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT 0 |
2497 | static inline uint32_t A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL(uint32_t val) |
2498 | { |
2499 | return ((val) << A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS1_CTRL1_DATA_SEL__MASK; |
2500 | } |
2501 | |
2502 | #define REG_A6XX_VBIF_TEST_BUS2_CTRL0 0x00003087 |
2503 | |
2504 | #define REG_A6XX_VBIF_TEST_BUS2_CTRL1 0x00003088 |
2505 | #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK 0x000001ff |
2506 | #define A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT 0 |
2507 | static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) |
2508 | { |
2509 | return ((val) << A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__SHIFT) & A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL__MASK; |
2510 | } |
2511 | |
2512 | #define REG_A6XX_VBIF_TEST_BUS_OUT 0x0000308c |
2513 | |
2514 | #define REG_A6XX_VBIF_PERF_CNT_SEL0 0x000030d0 |
2515 | |
2516 | #define REG_A6XX_VBIF_PERF_CNT_SEL1 0x000030d1 |
2517 | |
2518 | #define REG_A6XX_VBIF_PERF_CNT_SEL2 0x000030d2 |
2519 | |
2520 | #define REG_A6XX_VBIF_PERF_CNT_SEL3 0x000030d3 |
2521 | |
2522 | #define REG_A6XX_VBIF_PERF_CNT_LOW0 0x000030d8 |
2523 | |
2524 | #define REG_A6XX_VBIF_PERF_CNT_LOW1 0x000030d9 |
2525 | |
2526 | #define REG_A6XX_VBIF_PERF_CNT_LOW2 0x000030da |
2527 | |
2528 | #define REG_A6XX_VBIF_PERF_CNT_LOW3 0x000030db |
2529 | |
2530 | #define REG_A6XX_VBIF_PERF_CNT_HIGH0 0x000030e0 |
2531 | |
2532 | #define REG_A6XX_VBIF_PERF_CNT_HIGH1 0x000030e1 |
2533 | |
2534 | #define REG_A6XX_VBIF_PERF_CNT_HIGH2 0x000030e2 |
2535 | |
2536 | #define REG_A6XX_VBIF_PERF_CNT_HIGH3 0x000030e3 |
2537 | |
2538 | #define REG_A6XX_VBIF_PERF_PWR_CNT_EN0 0x00003100 |
2539 | |
2540 | #define REG_A6XX_VBIF_PERF_PWR_CNT_EN1 0x00003101 |
2541 | |
2542 | #define REG_A6XX_VBIF_PERF_PWR_CNT_EN2 0x00003102 |
2543 | |
2544 | #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW0 0x00003110 |
2545 | |
2546 | #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW1 0x00003111 |
2547 | |
2548 | #define REG_A6XX_VBIF_PERF_PWR_CNT_LOW2 0x00003112 |
2549 | |
2550 | #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH0 0x00003118 |
2551 | |
2552 | #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH1 0x00003119 |
2553 | |
2554 | #define REG_A6XX_VBIF_PERF_PWR_CNT_HIGH2 0x0000311a |
2555 | |
2556 | #define REG_A6XX_GBIF_SCACHE_CNTL0 0x00003c01 |
2557 | |
2558 | #define REG_A6XX_GBIF_SCACHE_CNTL1 0x00003c02 |
2559 | |
2560 | #define REG_A6XX_GBIF_QSB_SIDE0 0x00003c03 |
2561 | |
2562 | #define REG_A6XX_GBIF_QSB_SIDE1 0x00003c04 |
2563 | |
2564 | #define REG_A6XX_GBIF_QSB_SIDE2 0x00003c05 |
2565 | |
2566 | #define REG_A6XX_GBIF_QSB_SIDE3 0x00003c06 |
2567 | |
2568 | #define REG_A6XX_GBIF_HALT 0x00003c45 |
2569 | |
2570 | #define REG_A6XX_GBIF_HALT_ACK 0x00003c46 |
2571 | |
2572 | #define REG_A6XX_GBIF_PERF_PWR_CNT_EN 0x00003cc0 |
2573 | |
2574 | #define REG_A6XX_GBIF_PERF_PWR_CNT_CLR 0x00003cc1 |
2575 | |
2576 | #define REG_A6XX_GBIF_PERF_CNT_SEL 0x00003cc2 |
2577 | |
2578 | #define REG_A6XX_GBIF_PERF_PWR_CNT_SEL 0x00003cc3 |
2579 | |
2580 | #define REG_A6XX_GBIF_PERF_CNT_LOW0 0x00003cc4 |
2581 | |
2582 | #define REG_A6XX_GBIF_PERF_CNT_LOW1 0x00003cc5 |
2583 | |
2584 | #define REG_A6XX_GBIF_PERF_CNT_LOW2 0x00003cc6 |
2585 | |
2586 | #define REG_A6XX_GBIF_PERF_CNT_LOW3 0x00003cc7 |
2587 | |
2588 | #define REG_A6XX_GBIF_PERF_CNT_HIGH0 0x00003cc8 |
2589 | |
2590 | #define REG_A6XX_GBIF_PERF_CNT_HIGH1 0x00003cc9 |
2591 | |
2592 | #define REG_A6XX_GBIF_PERF_CNT_HIGH2 0x00003cca |
2593 | |
2594 | #define REG_A6XX_GBIF_PERF_CNT_HIGH3 0x00003ccb |
2595 | |
2596 | #define REG_A6XX_GBIF_PWR_CNT_LOW0 0x00003ccc |
2597 | |
2598 | #define REG_A6XX_GBIF_PWR_CNT_LOW1 0x00003ccd |
2599 | |
2600 | #define REG_A6XX_GBIF_PWR_CNT_LOW2 0x00003cce |
2601 | |
2602 | #define REG_A6XX_GBIF_PWR_CNT_HIGH0 0x00003ccf |
2603 | |
2604 | #define REG_A6XX_GBIF_PWR_CNT_HIGH1 0x00003cd0 |
2605 | |
2606 | #define REG_A6XX_GBIF_PWR_CNT_HIGH2 0x00003cd1 |
2607 | |
2608 | #define REG_A6XX_VSC_DBG_ECO_CNTL 0x00000c00 |
2609 | |
2610 | #define REG_A6XX_VSC_BIN_SIZE 0x00000c02 |
2611 | #define A6XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff |
2612 | #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 |
2613 | static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val) |
2614 | { |
2615 | assert(!(val & 0x1f)); |
2616 | return (((val >> 5)) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK; |
2617 | } |
2618 | #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00 |
2619 | #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8 |
2620 | static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) |
2621 | { |
2622 | assert(!(val & 0xf)); |
2623 | return (((val >> 4)) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK; |
2624 | } |
2625 | |
2626 | #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03 |
2627 | |
2628 | #define REG_A6XX_VSC_BIN_COUNT 0x00000c06 |
2629 | #define A6XX_VSC_BIN_COUNT_NX__MASK 0x000007fe |
2630 | #define A6XX_VSC_BIN_COUNT_NX__SHIFT 1 |
2631 | static inline uint32_t A6XX_VSC_BIN_COUNT_NX(uint32_t val) |
2632 | { |
2633 | return ((val) << A6XX_VSC_BIN_COUNT_NX__SHIFT) & A6XX_VSC_BIN_COUNT_NX__MASK; |
2634 | } |
2635 | #define A6XX_VSC_BIN_COUNT_NY__MASK 0x001ff800 |
2636 | #define A6XX_VSC_BIN_COUNT_NY__SHIFT 11 |
2637 | static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val) |
2638 | { |
2639 | return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK; |
2640 | } |
2641 | |
2642 | #define REG_A6XX_VSC_PIPE_CONFIG(i0) (0x00000c10 + 0x1*(i0)) |
2643 | |
2644 | static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } |
2645 | #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff |
2646 | #define A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0 |
2647 | static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_X(uint32_t val) |
2648 | { |
2649 | return ((val) << A6XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_X__MASK; |
2650 | } |
2651 | #define A6XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00 |
2652 | #define A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10 |
2653 | static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val) |
2654 | { |
2655 | return ((val) << A6XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_Y__MASK; |
2656 | } |
2657 | #define A6XX_VSC_PIPE_CONFIG_REG_W__MASK 0x03f00000 |
2658 | #define A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20 |
2659 | static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_W(uint32_t val) |
2660 | { |
2661 | return ((val) << A6XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_W__MASK; |
2662 | } |
2663 | #define A6XX_VSC_PIPE_CONFIG_REG_H__MASK 0xfc000000 |
2664 | #define A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT 26 |
2665 | static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) |
2666 | { |
2667 | return ((val) << A6XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A6XX_VSC_PIPE_CONFIG_REG_H__MASK; |
2668 | } |
2669 | |
2670 | #define REG_A6XX_VSC_PRIM_STRM_ADDRESS 0x00000c30 |
2671 | |
2672 | #define REG_A6XX_VSC_PRIM_STRM_PITCH 0x00000c32 |
2673 | |
2674 | #define REG_A6XX_VSC_PRIM_STRM_LIMIT 0x00000c33 |
2675 | |
2676 | #define REG_A6XX_VSC_DRAW_STRM_ADDRESS 0x00000c34 |
2677 | |
2678 | #define REG_A6XX_VSC_DRAW_STRM_PITCH 0x00000c36 |
2679 | |
2680 | #define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37 |
2681 | |
2682 | #define REG_A6XX_VSC_STATE(i0) (0x00000c38 + 0x1*(i0)) |
2683 | |
2684 | static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; } |
2685 | |
2686 | #define REG_A6XX_VSC_PRIM_STRM_SIZE(i0) (0x00000c58 + 0x1*(i0)) |
2687 | |
2688 | static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; } |
2689 | |
2690 | #define REG_A6XX_VSC_DRAW_STRM_SIZE(i0) (0x00000c78 + 0x1*(i0)) |
2691 | |
2692 | static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; } |
2693 | |
2694 | #define REG_A7XX_UCHE_UNKNOWN_0E10 0x00000e10 |
2695 | |
2696 | #define REG_A7XX_UCHE_UNKNOWN_0E11 0x00000e11 |
2697 | |
2698 | #define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12 |
2699 | |
2700 | #define REG_A6XX_GRAS_CL_CNTL 0x00008000 |
2701 | #define A6XX_GRAS_CL_CNTL_CLIP_DISABLE 0x00000001 |
2702 | #define A6XX_GRAS_CL_CNTL_ZNEAR_CLIP_DISABLE 0x00000002 |
2703 | #define A6XX_GRAS_CL_CNTL_ZFAR_CLIP_DISABLE 0x00000004 |
2704 | #define A6XX_GRAS_CL_CNTL_Z_CLAMP_ENABLE 0x00000020 |
2705 | #define A6XX_GRAS_CL_CNTL_ZERO_GB_SCALE_Z 0x00000040 |
2706 | #define A6XX_GRAS_CL_CNTL_VP_CLIP_CODE_IGNORE 0x00000080 |
2707 | #define A6XX_GRAS_CL_CNTL_VP_XFORM_DISABLE 0x00000100 |
2708 | #define A6XX_GRAS_CL_CNTL_PERSP_DIVISION_DISABLE 0x00000200 |
2709 | |
2710 | #define REG_A6XX_GRAS_VS_CL_CNTL 0x00008001 |
2711 | #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK 0x000000ff |
2712 | #define A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT 0 |
2713 | static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(uint32_t val) |
2714 | { |
2715 | return ((val) << A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CLIP_MASK__MASK; |
2716 | } |
2717 | #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 |
2718 | #define A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT 8 |
2719 | static inline uint32_t A6XX_GRAS_VS_CL_CNTL_CULL_MASK(uint32_t val) |
2720 | { |
2721 | return ((val) << A6XX_GRAS_VS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_VS_CL_CNTL_CULL_MASK__MASK; |
2722 | } |
2723 | |
2724 | #define REG_A6XX_GRAS_DS_CL_CNTL 0x00008002 |
2725 | #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK 0x000000ff |
2726 | #define A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT 0 |
2727 | static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CLIP_MASK(uint32_t val) |
2728 | { |
2729 | return ((val) << A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CLIP_MASK__MASK; |
2730 | } |
2731 | #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 |
2732 | #define A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT 8 |
2733 | static inline uint32_t A6XX_GRAS_DS_CL_CNTL_CULL_MASK(uint32_t val) |
2734 | { |
2735 | return ((val) << A6XX_GRAS_DS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_DS_CL_CNTL_CULL_MASK__MASK; |
2736 | } |
2737 | |
2738 | #define REG_A6XX_GRAS_GS_CL_CNTL 0x00008003 |
2739 | #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK 0x000000ff |
2740 | #define A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT 0 |
2741 | static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CLIP_MASK(uint32_t val) |
2742 | { |
2743 | return ((val) << A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CLIP_MASK__MASK; |
2744 | } |
2745 | #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK 0x0000ff00 |
2746 | #define A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT 8 |
2747 | static inline uint32_t A6XX_GRAS_GS_CL_CNTL_CULL_MASK(uint32_t val) |
2748 | { |
2749 | return ((val) << A6XX_GRAS_GS_CL_CNTL_CULL_MASK__SHIFT) & A6XX_GRAS_GS_CL_CNTL_CULL_MASK__MASK; |
2750 | } |
2751 | |
2752 | #define REG_A6XX_GRAS_MAX_LAYER_INDEX 0x00008004 |
2753 | |
2754 | #define REG_A6XX_GRAS_CNTL 0x00008005 |
2755 | #define A6XX_GRAS_CNTL_IJ_PERSP_PIXEL 0x00000001 |
2756 | #define A6XX_GRAS_CNTL_IJ_PERSP_CENTROID 0x00000002 |
2757 | #define A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE 0x00000004 |
2758 | #define A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL 0x00000008 |
2759 | #define A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID 0x00000010 |
2760 | #define A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE 0x00000020 |
2761 | #define A6XX_GRAS_CNTL_COORD_MASK__MASK 0x000003c0 |
2762 | #define A6XX_GRAS_CNTL_COORD_MASK__SHIFT 6 |
2763 | static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val) |
2764 | { |
2765 | return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK; |
2766 | } |
2767 | #define A6XX_GRAS_CNTL_UNK10 0x00000400 |
2768 | #define A6XX_GRAS_CNTL_UNK11 0x00000800 |
2769 | |
2770 | #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006 |
2771 | #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000001ff |
2772 | #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT 0 |
2773 | static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ(uint32_t val) |
2774 | { |
2775 | return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK; |
2776 | } |
2777 | #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK 0x0007fc00 |
2778 | #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT 10 |
2779 | static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) |
2780 | { |
2781 | return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; |
2782 | } |
2783 | |
2784 | #define REG_A7XX_GRAS_UNKNOWN_8007 0x00008007 |
2785 | |
2786 | #define REG_A7XX_GRAS_UNKNOWN_8008 0x00008008 |
2787 | |
2788 | #define REG_A7XX_GRAS_UNKNOWN_8009 0x00008009 |
2789 | |
2790 | #define REG_A7XX_GRAS_UNKNOWN_800A 0x0000800a |
2791 | |
2792 | #define REG_A7XX_GRAS_UNKNOWN_800B 0x0000800b |
2793 | |
2794 | #define REG_A7XX_GRAS_UNKNOWN_800C 0x0000800c |
2795 | |
2796 | #define REG_A6XX_GRAS_CL_VPORT(i0) (0x00008010 + 0x6*(i0)) |
2797 | |
2798 | static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; } |
2799 | #define A6XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff |
2800 | #define A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0 |
2801 | static inline uint32_t A6XX_GRAS_CL_VPORT_XOFFSET(float val) |
2802 | { |
2803 | return ((fui(val)) << A6XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_XOFFSET__MASK; |
2804 | } |
2805 | |
2806 | static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) { return 0x00008011 + 0x6*i0; } |
2807 | #define A6XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff |
2808 | #define A6XX_GRAS_CL_VPORT_XSCALE__SHIFT 0 |
2809 | static inline uint32_t A6XX_GRAS_CL_VPORT_XSCALE(float val) |
2810 | { |
2811 | return ((fui(val)) << A6XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_XSCALE__MASK; |
2812 | } |
2813 | |
2814 | static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) { return 0x00008012 + 0x6*i0; } |
2815 | #define A6XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff |
2816 | #define A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0 |
2817 | static inline uint32_t A6XX_GRAS_CL_VPORT_YOFFSET(float val) |
2818 | { |
2819 | return ((fui(val)) << A6XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_YOFFSET__MASK; |
2820 | } |
2821 | |
2822 | static inline uint32_t REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) { return 0x00008013 + 0x6*i0; } |
2823 | #define A6XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff |
2824 | #define A6XX_GRAS_CL_VPORT_YSCALE__SHIFT 0 |
2825 | static inline uint32_t A6XX_GRAS_CL_VPORT_YSCALE(float val) |
2826 | { |
2827 | return ((fui(val)) << A6XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_YSCALE__MASK; |
2828 | } |
2829 | |
2830 | static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) { return 0x00008014 + 0x6*i0; } |
2831 | #define A6XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff |
2832 | #define A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0 |
2833 | static inline uint32_t A6XX_GRAS_CL_VPORT_ZOFFSET(float val) |
2834 | { |
2835 | return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A6XX_GRAS_CL_VPORT_ZOFFSET__MASK; |
2836 | } |
2837 | |
2838 | static inline uint32_t REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) { return 0x00008015 + 0x6*i0; } |
2839 | #define A6XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff |
2840 | #define A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0 |
2841 | static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val) |
2842 | { |
2843 | return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK; |
2844 | } |
2845 | |
2846 | #define REG_A6XX_GRAS_CL_Z_CLAMP(i0) (0x00008070 + 0x2*(i0)) |
2847 | |
2848 | static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; } |
2849 | #define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK 0xffffffff |
2850 | #define A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT 0 |
2851 | static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MIN(float val) |
2852 | { |
2853 | return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MIN__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MIN__MASK; |
2854 | } |
2855 | |
2856 | static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) { return 0x00008071 + 0x2*i0; } |
2857 | #define A6XX_GRAS_CL_Z_CLAMP_MAX__MASK 0xffffffff |
2858 | #define A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT 0 |
2859 | static inline uint32_t A6XX_GRAS_CL_Z_CLAMP_MAX(float val) |
2860 | { |
2861 | return ((fui(val)) << A6XX_GRAS_CL_Z_CLAMP_MAX__SHIFT) & A6XX_GRAS_CL_Z_CLAMP_MAX__MASK; |
2862 | } |
2863 | |
2864 | #define REG_A6XX_GRAS_SU_CNTL 0x00008090 |
2865 | #define A6XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001 |
2866 | #define A6XX_GRAS_SU_CNTL_CULL_BACK 0x00000002 |
2867 | #define A6XX_GRAS_SU_CNTL_FRONT_CW 0x00000004 |
2868 | #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8 |
2869 | #define A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3 |
2870 | static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) |
2871 | { |
2872 | return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; |
2873 | } |
2874 | #define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 |
2875 | #define A6XX_GRAS_SU_CNTL_UNK12 0x00001000 |
2876 | #define A6XX_GRAS_SU_CNTL_LINE_MODE__MASK 0x00002000 |
2877 | #define A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT 13 |
2878 | static inline uint32_t A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val) |
2879 | { |
2880 | return ((val) << A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT) & A6XX_GRAS_SU_CNTL_LINE_MODE__MASK; |
2881 | } |
2882 | #define A6XX_GRAS_SU_CNTL_UNK15__MASK 0x00018000 |
2883 | #define A6XX_GRAS_SU_CNTL_UNK15__SHIFT 15 |
2884 | static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val) |
2885 | { |
2886 | return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK; |
2887 | } |
2888 | #define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00020000 |
2889 | #define A6XX_GRAS_SU_CNTL_RENDERTARGETINDEXINCR 0x00040000 |
2890 | #define A6XX_GRAS_SU_CNTL_VIEWPORTINDEXINCR 0x00080000 |
2891 | #define A6XX_GRAS_SU_CNTL_UNK20__MASK 0x00700000 |
2892 | #define A6XX_GRAS_SU_CNTL_UNK20__SHIFT 20 |
2893 | static inline uint32_t A6XX_GRAS_SU_CNTL_UNK20(uint32_t val) |
2894 | { |
2895 | return ((val) << A6XX_GRAS_SU_CNTL_UNK20__SHIFT) & A6XX_GRAS_SU_CNTL_UNK20__MASK; |
2896 | } |
2897 | |
2898 | #define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091 |
2899 | #define A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff |
2900 | #define A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0 |
2901 | static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MIN(float val) |
2902 | { |
2903 | return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MIN__MASK; |
2904 | } |
2905 | #define A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000 |
2906 | #define A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16 |
2907 | static inline uint32_t A6XX_GRAS_SU_POINT_MINMAX_MAX(float val) |
2908 | { |
2909 | return ((((uint32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A6XX_GRAS_SU_POINT_MINMAX_MAX__MASK; |
2910 | } |
2911 | |
2912 | #define REG_A6XX_GRAS_SU_POINT_SIZE 0x00008092 |
2913 | #define A6XX_GRAS_SU_POINT_SIZE__MASK 0x0000ffff |
2914 | #define A6XX_GRAS_SU_POINT_SIZE__SHIFT 0 |
2915 | static inline uint32_t A6XX_GRAS_SU_POINT_SIZE(float val) |
2916 | { |
2917 | return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SU_POINT_SIZE__SHIFT) & A6XX_GRAS_SU_POINT_SIZE__MASK; |
2918 | } |
2919 | |
2920 | #define REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL 0x00008094 |
2921 | #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003 |
2922 | #define A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0 |
2923 | static inline uint32_t A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) |
2924 | { |
2925 | return ((val) << A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_GRAS_SU_DEPTH_PLANE_CNTL_Z_MODE__MASK; |
2926 | } |
2927 | |
2928 | #define REG_A6XX_GRAS_SU_POLY_OFFSET_SCALE 0x00008095 |
2929 | #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff |
2930 | #define A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT 0 |
2931 | static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_SCALE(float val) |
2932 | { |
2933 | return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_SCALE__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_SCALE__MASK; |
2934 | } |
2935 | |
2936 | #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET 0x00008096 |
2937 | #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff |
2938 | #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0 |
2939 | static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET(float val) |
2940 | { |
2941 | return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK; |
2942 | } |
2943 | |
2944 | #define REG_A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP 0x00008097 |
2945 | #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK 0xffffffff |
2946 | #define A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT 0 |
2947 | static inline uint32_t A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(float val) |
2948 | { |
2949 | return ((fui(val)) << A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__SHIFT) & A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP__MASK; |
2950 | } |
2951 | |
2952 | #define REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO 0x00008098 |
2953 | #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 |
2954 | #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 |
2955 | static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) |
2956 | { |
2957 | return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; |
2958 | } |
2959 | #define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3 0x00000008 |
2960 | |
2961 | #define REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x00008099 |
2962 | #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001 |
2963 | #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK 0x00000006 |
2964 | #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT 1 |
2965 | static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT(uint32_t val) |
2966 | { |
2967 | return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_SHIFTAMOUNT__MASK; |
2968 | } |
2969 | #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_INNERCONSERVATIVERASEN 0x00000008 |
2970 | #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK 0x00000030 |
2971 | #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT 4 |
2972 | static inline uint32_t A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4(uint32_t val) |
2973 | { |
2974 | return ((val) << A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__SHIFT) & A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_UNK4__MASK; |
2975 | } |
2976 | |
2977 | #define REG_A6XX_GRAS_SU_PATH_RENDERING_CNTL 0x0000809a |
2978 | #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_UNK0 0x00000001 |
2979 | #define A6XX_GRAS_SU_PATH_RENDERING_CNTL_LINELENGTHEN 0x00000002 |
2980 | |
2981 | #define REG_A6XX_GRAS_VS_LAYER_CNTL 0x0000809b |
2982 | #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_LAYER 0x00000001 |
2983 | #define A6XX_GRAS_VS_LAYER_CNTL_WRITES_VIEW 0x00000002 |
2984 | |
2985 | #define REG_A6XX_GRAS_GS_LAYER_CNTL 0x0000809c |
2986 | #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER 0x00000001 |
2987 | #define A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW 0x00000002 |
2988 | |
2989 | #define REG_A6XX_GRAS_DS_LAYER_CNTL 0x0000809d |
2990 | #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_LAYER 0x00000001 |
2991 | #define A6XX_GRAS_DS_LAYER_CNTL_WRITES_VIEW 0x00000002 |
2992 | |
2993 | #define REG_A6XX_GRAS_SC_CNTL 0x000080a0 |
2994 | #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000007 |
2995 | #define A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT 0 |
2996 | static inline uint32_t A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(uint32_t val) |
2997 | { |
2998 | return ((val) << A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE__MASK; |
2999 | } |
3000 | #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK 0x00000018 |
3001 | #define A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT 3 |
3002 | static inline uint32_t A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE(enum a6xx_single_prim_mode val) |
3003 | { |
3004 | return ((val) << A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_SINGLE_PRIM_MODE__MASK; |
3005 | } |
3006 | #define A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK 0x00000020 |
3007 | #define A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT 5 |
3008 | static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_MODE(enum a6xx_raster_mode val) |
3009 | { |
3010 | return ((val) << A6XX_GRAS_SC_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_MODE__MASK; |
3011 | } |
3012 | #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK 0x000000c0 |
3013 | #define A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT 6 |
3014 | static inline uint32_t A6XX_GRAS_SC_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) |
3015 | { |
3016 | return ((val) << A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_GRAS_SC_CNTL_RASTER_DIRECTION__MASK; |
3017 | } |
3018 | #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK 0x00000100 |
3019 | #define A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT 8 |
3020 | static inline uint32_t A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION(enum a6xx_sequenced_thread_dist val) |
3021 | { |
3022 | return ((val) << A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__SHIFT) & A6XX_GRAS_SC_CNTL_SEQUENCED_THREAD_DISTRIBUTION__MASK; |
3023 | } |
3024 | #define A6XX_GRAS_SC_CNTL_UNK9 0x00000200 |
3025 | #define A6XX_GRAS_SC_CNTL_ROTATION__MASK 0x00000c00 |
3026 | #define A6XX_GRAS_SC_CNTL_ROTATION__SHIFT 10 |
3027 | static inline uint32_t A6XX_GRAS_SC_CNTL_ROTATION(uint32_t val) |
3028 | { |
3029 | return ((val) << A6XX_GRAS_SC_CNTL_ROTATION__SHIFT) & A6XX_GRAS_SC_CNTL_ROTATION__MASK; |
3030 | } |
3031 | #define A6XX_GRAS_SC_CNTL_EARLYVIZOUTEN 0x00001000 |
3032 | |
3033 | #define REG_A6XX_GRAS_BIN_CONTROL 0x000080a1 |
3034 | #define A6XX_GRAS_BIN_CONTROL_BINW__MASK 0x0000003f |
3035 | #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0 |
3036 | static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val) |
3037 | { |
3038 | assert(!(val & 0x1f)); |
3039 | return (((val >> 5)) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK; |
3040 | } |
3041 | #define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x00007f00 |
3042 | #define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8 |
3043 | static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val) |
3044 | { |
3045 | assert(!(val & 0xf)); |
3046 | return (((val >> 4)) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK; |
3047 | } |
3048 | #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 |
3049 | #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT 18 |
3050 | static inline uint32_t A6XX_GRAS_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) |
3051 | { |
3052 | return ((val) << A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK; |
3053 | } |
3054 | #define A6XX_GRAS_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000 |
3055 | #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000 |
3056 | #define A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22 |
3057 | static inline uint32_t A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val) |
3058 | { |
3059 | return ((val) << A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_GRAS_BIN_CONTROL_BUFFERS_LOCATION__MASK; |
3060 | } |
3061 | #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000 |
3062 | #define A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24 |
3063 | static inline uint32_t A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) |
3064 | { |
3065 | return ((val) << A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; |
3066 | } |
3067 | #define A6XX_GRAS_BIN_CONTROL_UNK27 0x08000000 |
3068 | |
3069 | #define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2 |
3070 | #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 |
3071 | #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 |
3072 | static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) |
3073 | { |
3074 | return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK; |
3075 | } |
3076 | #define A6XX_GRAS_RAS_MSAA_CNTL_UNK2 0x00000004 |
3077 | #define A6XX_GRAS_RAS_MSAA_CNTL_UNK3 0x00000008 |
3078 | |
3079 | #define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3 |
3080 | #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 |
3081 | #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 |
3082 | static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) |
3083 | { |
3084 | return ((val) << A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK; |
3085 | } |
3086 | #define A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 |
3087 | |
3088 | #define REG_A6XX_GRAS_SAMPLE_CONFIG 0x000080a4 |
3089 | #define A6XX_GRAS_SAMPLE_CONFIG_UNK0 0x00000001 |
3090 | #define A6XX_GRAS_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 |
3091 | |
3092 | #define REG_A6XX_GRAS_SAMPLE_LOCATION_0 0x000080a5 |
3093 | #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f |
3094 | #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 |
3095 | static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) |
3096 | { |
3097 | return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; |
3098 | } |
3099 | #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 |
3100 | #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 |
3101 | static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) |
3102 | { |
3103 | return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; |
3104 | } |
3105 | #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 |
3106 | #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 |
3107 | static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) |
3108 | { |
3109 | return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; |
3110 | } |
3111 | #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 |
3112 | #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 |
3113 | static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) |
3114 | { |
3115 | return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; |
3116 | } |
3117 | #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 |
3118 | #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 |
3119 | static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) |
3120 | { |
3121 | return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; |
3122 | } |
3123 | #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 |
3124 | #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 |
3125 | static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) |
3126 | { |
3127 | return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; |
3128 | } |
3129 | #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 |
3130 | #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 |
3131 | static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) |
3132 | { |
3133 | return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; |
3134 | } |
3135 | #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 |
3136 | #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 |
3137 | static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) |
3138 | { |
3139 | return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; |
3140 | } |
3141 | |
3142 | #define REG_A6XX_GRAS_SAMPLE_LOCATION_1 0x000080a6 |
3143 | #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f |
3144 | #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 |
3145 | static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) |
3146 | { |
3147 | return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; |
3148 | } |
3149 | #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 |
3150 | #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 |
3151 | static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) |
3152 | { |
3153 | return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; |
3154 | } |
3155 | #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 |
3156 | #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 |
3157 | static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) |
3158 | { |
3159 | return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; |
3160 | } |
3161 | #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 |
3162 | #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 |
3163 | static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) |
3164 | { |
3165 | return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; |
3166 | } |
3167 | #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 |
3168 | #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 |
3169 | static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) |
3170 | { |
3171 | return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; |
3172 | } |
3173 | #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 |
3174 | #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 |
3175 | static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) |
3176 | { |
3177 | return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; |
3178 | } |
3179 | #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 |
3180 | #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 |
3181 | static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) |
3182 | { |
3183 | return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; |
3184 | } |
3185 | #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 |
3186 | #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 |
3187 | static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) |
3188 | { |
3189 | return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; |
3190 | } |
3191 | |
3192 | #define REG_A7XX_GRAS_UNKNOWN_80A7 0x000080a7 |
3193 | |
3194 | #define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af |
3195 | |
3196 | #define REG_A6XX_GRAS_SC_SCREEN_SCISSOR(i0) (0x000080b0 + 0x2*(i0)) |
3197 | |
3198 | static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; } |
3199 | #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x0000ffff |
3200 | #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 |
3201 | static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val) |
3202 | { |
3203 | return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK; |
3204 | } |
3205 | #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0xffff0000 |
3206 | #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 |
3207 | static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) |
3208 | { |
3209 | return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK; |
3210 | } |
3211 | |
3212 | static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) { return 0x000080b1 + 0x2*i0; } |
3213 | #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x0000ffff |
3214 | #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 |
3215 | static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val) |
3216 | { |
3217 | return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK; |
3218 | } |
3219 | #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0xffff0000 |
3220 | #define A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 |
3221 | static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) |
3222 | { |
3223 | return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; |
3224 | } |
3225 | |
3226 | #define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(i0) (0x000080d0 + 0x2*(i0)) |
3227 | |
3228 | static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; } |
3229 | #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK 0x0000ffff |
3230 | #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT 0 |
3231 | static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X(uint32_t val) |
3232 | { |
3233 | return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK; |
3234 | } |
3235 | #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK 0xffff0000 |
3236 | #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT 16 |
3237 | static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y(uint32_t val) |
3238 | { |
3239 | return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_Y__MASK; |
3240 | } |
3241 | |
3242 | static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) { return 0x000080d1 + 0x2*i0; } |
3243 | #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK 0x0000ffff |
3244 | #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT 0 |
3245 | static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X(uint32_t val) |
3246 | { |
3247 | return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_X__MASK; |
3248 | } |
3249 | #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK 0xffff0000 |
3250 | #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT 16 |
3251 | static inline uint32_t A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y(uint32_t val) |
3252 | { |
3253 | return ((val) << A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR_Y__MASK; |
3254 | } |
3255 | |
3256 | #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL 0x000080f0 |
3257 | #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00003fff |
3258 | #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 |
3259 | static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val) |
3260 | { |
3261 | return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK; |
3262 | } |
3263 | #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x3fff0000 |
3264 | #define A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 |
3265 | static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) |
3266 | { |
3267 | return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK; |
3268 | } |
3269 | |
3270 | #define REG_A6XX_GRAS_SC_WINDOW_SCISSOR_BR 0x000080f1 |
3271 | #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00003fff |
3272 | #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 |
3273 | static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val) |
3274 | { |
3275 | return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK; |
3276 | } |
3277 | #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x3fff0000 |
3278 | #define A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 |
3279 | static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) |
3280 | { |
3281 | return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; |
3282 | } |
3283 | |
3284 | #define REG_A7XX_GRAS_UNKNOWN_80F4 0x000080f4 |
3285 | |
3286 | #define REG_A7XX_GRAS_UNKNOWN_80F5 0x000080f5 |
3287 | |
3288 | #define REG_A7XX_GRAS_UNKNOWN_80F6 0x000080f6 |
3289 | |
3290 | #define REG_A7XX_GRAS_UNKNOWN_80F8 0x000080f8 |
3291 | |
3292 | #define REG_A7XX_GRAS_UNKNOWN_80F9 0x000080f9 |
3293 | |
3294 | #define REG_A7XX_GRAS_UNKNOWN_80FA 0x000080fa |
3295 | |
3296 | #define REG_A6XX_GRAS_LRZ_CNTL 0x00008100 |
3297 | #define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001 |
3298 | #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002 |
3299 | #define A6XX_GRAS_LRZ_CNTL_GREATER 0x00000004 |
3300 | #define A6XX_GRAS_LRZ_CNTL_FC_ENABLE 0x00000008 |
3301 | #define A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE 0x00000010 |
3302 | #define A6XX_GRAS_LRZ_CNTL_Z_BOUNDS_ENABLE 0x00000020 |
3303 | #define A6XX_GRAS_LRZ_CNTL_DIR__MASK 0x000000c0 |
3304 | #define A6XX_GRAS_LRZ_CNTL_DIR__SHIFT 6 |
3305 | static inline uint32_t A6XX_GRAS_LRZ_CNTL_DIR(enum a6xx_lrz_dir_status val) |
3306 | { |
3307 | return ((val) << A6XX_GRAS_LRZ_CNTL_DIR__SHIFT) & A6XX_GRAS_LRZ_CNTL_DIR__MASK; |
3308 | } |
3309 | #define A6XX_GRAS_LRZ_CNTL_DIR_WRITE 0x00000100 |
3310 | #define A6XX_GRAS_LRZ_CNTL_DISABLE_ON_WRONG_DIR 0x00000200 |
3311 | #define A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK 0x00003800 |
3312 | #define A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT 11 |
3313 | static inline uint32_t A6XX_GRAS_LRZ_CNTL_Z_FUNC(enum adreno_compare_func val) |
3314 | { |
3315 | return ((val) << A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT) & A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK; |
3316 | } |
3317 | |
3318 | #define REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL 0x00008101 |
3319 | #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID 0x00000001 |
3320 | #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK 0x00000006 |
3321 | #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT 1 |
3322 | static inline uint32_t A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val) |
3323 | { |
3324 | return ((val) << A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE__MASK; |
3325 | } |
3326 | |
3327 | #define REG_A6XX_GRAS_LRZ_MRT_BUF_INFO_0 0x00008102 |
3328 | #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK 0x000000ff |
3329 | #define A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT 0 |
3330 | static inline uint32_t A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(enum a6xx_format val) |
3331 | { |
3332 | return ((val) << A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__SHIFT) & A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT__MASK; |
3333 | } |
3334 | |
3335 | #define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103 |
3336 | |
3337 | #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105 |
3338 | #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000000ff |
3339 | #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0 |
3340 | static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val) |
3341 | { |
3342 | assert(!(val & 0x1f)); |
3343 | return (((val >> 5)) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK; |
3344 | } |
3345 | #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffffc00 |
3346 | #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 10 |
3347 | static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) |
3348 | { |
3349 | assert(!(val & 0xf)); |
3350 | return (((val >> 4)) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK; |
3351 | } |
3352 | |
3353 | #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106 |
3354 | |
3355 | #define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109 |
3356 | #define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 |
3357 | |
3358 | #define REG_A6XX_GRAS_LRZ_DEPTH_VIEW 0x0000810a |
3359 | #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK 0x000007ff |
3360 | #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT 0 |
3361 | static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER(uint32_t val) |
3362 | { |
3363 | return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER__MASK; |
3364 | } |
3365 | #define A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK 0x07ff0000 |
3366 | #define A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT 16 |
3367 | static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT(uint32_t val) |
3368 | { |
3369 | return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT__MASK; |
3370 | } |
3371 | #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK 0xf0000000 |
3372 | #define A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT 28 |
3373 | static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL(uint32_t val) |
3374 | { |
3375 | return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK; |
3376 | } |
3377 | |
3378 | #define REG_A7XX_GRAS_UNKNOWN_810B 0x0000810b |
3379 | |
3380 | #define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110 |
3381 | |
3382 | #define REG_A7XX_GRAS_LRZ_CLEAR_DEPTH_F32 0x00008111 |
3383 | #define A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK 0xffffffff |
3384 | #define A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT 0 |
3385 | static inline uint32_t A7XX_GRAS_LRZ_CLEAR_DEPTH_F32(float val) |
3386 | { |
3387 | return ((fui(val)) << A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT) & A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK; |
3388 | } |
3389 | |
3390 | #define REG_A7XX_GRAS_UNKNOWN_8113 0x00008113 |
3391 | |
3392 | #define REG_A7XX_GRAS_UNKNOWN_8120 0x00008120 |
3393 | |
3394 | #define REG_A7XX_GRAS_UNKNOWN_8121 0x00008121 |
3395 | |
3396 | #define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400 |
3397 | #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000007 |
3398 | #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0 |
3399 | static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) |
3400 | { |
3401 | return ((val) << A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK; |
3402 | } |
3403 | #define A6XX_GRAS_2D_BLIT_CNTL_OVERWRITEEN 0x00000008 |
3404 | #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK 0x00000070 |
3405 | #define A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT 4 |
3406 | static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK4(uint32_t val) |
3407 | { |
3408 | return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK4__MASK; |
3409 | } |
3410 | #define A6XX_GRAS_2D_BLIT_CNTL_SOLID_COLOR 0x00000080 |
3411 | #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 |
3412 | #define A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 |
3413 | static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) |
3414 | { |
3415 | return ((val) << A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_COLOR_FORMAT__MASK; |
3416 | } |
3417 | #define A6XX_GRAS_2D_BLIT_CNTL_SCISSOR 0x00010000 |
3418 | #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK 0x00060000 |
3419 | #define A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT 17 |
3420 | static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_UNK17(uint32_t val) |
3421 | { |
3422 | return ((val) << A6XX_GRAS_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_UNK17__MASK; |
3423 | } |
3424 | #define A6XX_GRAS_2D_BLIT_CNTL_D24S8 0x00080000 |
3425 | #define A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK 0x00f00000 |
3426 | #define A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT 20 |
3427 | static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_MASK(uint32_t val) |
3428 | { |
3429 | return ((val) << A6XX_GRAS_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_MASK__MASK; |
3430 | } |
3431 | #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 |
3432 | #define A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT 24 |
3433 | static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) |
3434 | { |
3435 | return ((val) << A6XX_GRAS_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_IFMT__MASK; |
3436 | } |
3437 | #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000 |
3438 | #define A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29 |
3439 | static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val) |
3440 | { |
3441 | return ((val) << A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK; |
3442 | } |
3443 | #define A6XX_GRAS_2D_BLIT_CNTL_UNK30 0x40000000 |
3444 | |
3445 | #define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401 |
3446 | #define A6XX_GRAS_2D_SRC_TL_X__MASK 0x01ffff00 |
3447 | #define A6XX_GRAS_2D_SRC_TL_X__SHIFT 8 |
3448 | static inline uint32_t A6XX_GRAS_2D_SRC_TL_X(int32_t val) |
3449 | { |
3450 | return ((val) << A6XX_GRAS_2D_SRC_TL_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X__MASK; |
3451 | } |
3452 | |
3453 | #define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402 |
3454 | #define A6XX_GRAS_2D_SRC_BR_X__MASK 0x01ffff00 |
3455 | #define A6XX_GRAS_2D_SRC_BR_X__SHIFT 8 |
3456 | static inline uint32_t A6XX_GRAS_2D_SRC_BR_X(int32_t val) |
3457 | { |
3458 | return ((val) << A6XX_GRAS_2D_SRC_BR_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X__MASK; |
3459 | } |
3460 | |
3461 | #define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403 |
3462 | #define A6XX_GRAS_2D_SRC_TL_Y__MASK 0x01ffff00 |
3463 | #define A6XX_GRAS_2D_SRC_TL_Y__SHIFT 8 |
3464 | static inline uint32_t A6XX_GRAS_2D_SRC_TL_Y(int32_t val) |
3465 | { |
3466 | return ((val) << A6XX_GRAS_2D_SRC_TL_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y__MASK; |
3467 | } |
3468 | |
3469 | #define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404 |
3470 | #define A6XX_GRAS_2D_SRC_BR_Y__MASK 0x01ffff00 |
3471 | #define A6XX_GRAS_2D_SRC_BR_Y__SHIFT 8 |
3472 | static inline uint32_t A6XX_GRAS_2D_SRC_BR_Y(int32_t val) |
3473 | { |
3474 | return ((val) << A6XX_GRAS_2D_SRC_BR_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y__MASK; |
3475 | } |
3476 | |
3477 | #define REG_A6XX_GRAS_2D_DST_TL 0x00008405 |
3478 | #define A6XX_GRAS_2D_DST_TL_X__MASK 0x00003fff |
3479 | #define A6XX_GRAS_2D_DST_TL_X__SHIFT 0 |
3480 | static inline uint32_t A6XX_GRAS_2D_DST_TL_X(uint32_t val) |
3481 | { |
3482 | return ((val) << A6XX_GRAS_2D_DST_TL_X__SHIFT) & A6XX_GRAS_2D_DST_TL_X__MASK; |
3483 | } |
3484 | #define A6XX_GRAS_2D_DST_TL_Y__MASK 0x3fff0000 |
3485 | #define A6XX_GRAS_2D_DST_TL_Y__SHIFT 16 |
3486 | static inline uint32_t A6XX_GRAS_2D_DST_TL_Y(uint32_t val) |
3487 | { |
3488 | return ((val) << A6XX_GRAS_2D_DST_TL_Y__SHIFT) & A6XX_GRAS_2D_DST_TL_Y__MASK; |
3489 | } |
3490 | |
3491 | #define REG_A6XX_GRAS_2D_DST_BR 0x00008406 |
3492 | #define A6XX_GRAS_2D_DST_BR_X__MASK 0x00003fff |
3493 | #define A6XX_GRAS_2D_DST_BR_X__SHIFT 0 |
3494 | static inline uint32_t A6XX_GRAS_2D_DST_BR_X(uint32_t val) |
3495 | { |
3496 | return ((val) << A6XX_GRAS_2D_DST_BR_X__SHIFT) & A6XX_GRAS_2D_DST_BR_X__MASK; |
3497 | } |
3498 | #define A6XX_GRAS_2D_DST_BR_Y__MASK 0x3fff0000 |
3499 | #define A6XX_GRAS_2D_DST_BR_Y__SHIFT 16 |
3500 | static inline uint32_t A6XX_GRAS_2D_DST_BR_Y(uint32_t val) |
3501 | { |
3502 | return ((val) << A6XX_GRAS_2D_DST_BR_Y__SHIFT) & A6XX_GRAS_2D_DST_BR_Y__MASK; |
3503 | } |
3504 | |
3505 | #define REG_A6XX_GRAS_2D_UNKNOWN_8407 0x00008407 |
3506 | |
3507 | #define REG_A6XX_GRAS_2D_UNKNOWN_8408 0x00008408 |
3508 | |
3509 | #define REG_A6XX_GRAS_2D_UNKNOWN_8409 0x00008409 |
3510 | |
3511 | #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_1 0x0000840a |
3512 | #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK 0x00003fff |
3513 | #define A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT 0 |
3514 | static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_X(uint32_t val) |
3515 | { |
3516 | return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_X__MASK; |
3517 | } |
3518 | #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK 0x3fff0000 |
3519 | #define A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT 16 |
3520 | static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(uint32_t val) |
3521 | { |
3522 | return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_1_Y__MASK; |
3523 | } |
3524 | |
3525 | #define REG_A6XX_GRAS_2D_RESOLVE_CNTL_2 0x0000840b |
3526 | #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK 0x00003fff |
3527 | #define A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT 0 |
3528 | static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_X(uint32_t val) |
3529 | { |
3530 | return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_X__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_X__MASK; |
3531 | } |
3532 | #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK 0x3fff0000 |
3533 | #define A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT 16 |
3534 | static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val) |
3535 | { |
3536 | return ((val) << A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__SHIFT) & A6XX_GRAS_2D_RESOLVE_CNTL_2_Y__MASK; |
3537 | } |
3538 | |
3539 | #define REG_A6XX_GRAS_DBG_ECO_CNTL 0x00008600 |
3540 | #define A6XX_GRAS_DBG_ECO_CNTL_UNK7 0x00000080 |
3541 | #define A6XX_GRAS_DBG_ECO_CNTL_LRZCACHELOCKDIS 0x00000800 |
3542 | |
3543 | #define REG_A6XX_GRAS_ADDR_MODE_CNTL 0x00008601 |
3544 | |
3545 | #define REG_A7XX_GRAS_NC_MODE_CNTL 0x00008602 |
3546 | |
3547 | #define REG_A6XX_GRAS_PERFCTR_TSE_SEL(i0) (0x00008610 + 0x1*(i0)) |
3548 | |
3549 | #define REG_A6XX_GRAS_PERFCTR_RAS_SEL(i0) (0x00008614 + 0x1*(i0)) |
3550 | |
3551 | #define REG_A6XX_GRAS_PERFCTR_LRZ_SEL(i0) (0x00008618 + 0x1*(i0)) |
3552 | |
3553 | #define REG_A6XX_RB_BIN_CONTROL 0x00008800 |
3554 | #define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f |
3555 | #define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0 |
3556 | static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val) |
3557 | { |
3558 | assert(!(val & 0x1f)); |
3559 | return (((val >> 5)) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK; |
3560 | } |
3561 | #define A6XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00 |
3562 | #define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8 |
3563 | static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val) |
3564 | { |
3565 | assert(!(val & 0xf)); |
3566 | return (((val >> 4)) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK; |
3567 | } |
3568 | #define A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 |
3569 | #define A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT 18 |
3570 | static inline uint32_t A6XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) |
3571 | { |
3572 | return ((val) << A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK; |
3573 | } |
3574 | #define A6XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000 |
3575 | #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK 0x00c00000 |
3576 | #define A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT 22 |
3577 | static inline uint32_t A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION(enum a6xx_buffers_location val) |
3578 | { |
3579 | return ((val) << A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__SHIFT) & A6XX_RB_BIN_CONTROL_BUFFERS_LOCATION__MASK; |
3580 | } |
3581 | #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000 |
3582 | #define A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24 |
3583 | static inline uint32_t A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) |
3584 | { |
3585 | return ((val) << A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; |
3586 | } |
3587 | |
3588 | #define REG_A7XX_RB_BIN_CONTROL 0x00008800 |
3589 | #define A7XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f |
3590 | #define A7XX_RB_BIN_CONTROL_BINW__SHIFT 0 |
3591 | static inline uint32_t A7XX_RB_BIN_CONTROL_BINW(uint32_t val) |
3592 | { |
3593 | assert(!(val & 0x1f)); |
3594 | return (((val >> 5)) << A7XX_RB_BIN_CONTROL_BINW__SHIFT) & A7XX_RB_BIN_CONTROL_BINW__MASK; |
3595 | } |
3596 | #define A7XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00 |
3597 | #define A7XX_RB_BIN_CONTROL_BINH__SHIFT 8 |
3598 | static inline uint32_t A7XX_RB_BIN_CONTROL_BINH(uint32_t val) |
3599 | { |
3600 | assert(!(val & 0xf)); |
3601 | return (((val >> 4)) << A7XX_RB_BIN_CONTROL_BINH__SHIFT) & A7XX_RB_BIN_CONTROL_BINH__MASK; |
3602 | } |
3603 | #define A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 |
3604 | #define A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT 18 |
3605 | static inline uint32_t A7XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) |
3606 | { |
3607 | return ((val) << A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK; |
3608 | } |
3609 | #define A7XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000 |
3610 | #define A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000 |
3611 | #define A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24 |
3612 | static inline uint32_t A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) |
3613 | { |
3614 | return ((val) << A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; |
3615 | } |
3616 | |
3617 | #define REG_A6XX_RB_RENDER_CNTL 0x00008801 |
3618 | #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000038 |
3619 | #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT 3 |
3620 | static inline uint32_t A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE(uint32_t val) |
3621 | { |
3622 | return ((val) << A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT) & A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK; |
3623 | } |
3624 | #define A6XX_RB_RENDER_CNTL_EARLYVIZOUTEN 0x00000040 |
3625 | #define A6XX_RB_RENDER_CNTL_BINNING 0x00000080 |
3626 | #define A6XX_RB_RENDER_CNTL_UNK8__MASK 0x00000700 |
3627 | #define A6XX_RB_RENDER_CNTL_UNK8__SHIFT 8 |
3628 | static inline uint32_t A6XX_RB_RENDER_CNTL_UNK8(uint32_t val) |
3629 | { |
3630 | return ((val) << A6XX_RB_RENDER_CNTL_UNK8__SHIFT) & A6XX_RB_RENDER_CNTL_UNK8__MASK; |
3631 | } |
3632 | #define A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK 0x00000100 |
3633 | #define A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT 8 |
3634 | static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val) |
3635 | { |
3636 | return ((val) << A6XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_MODE__MASK; |
3637 | } |
3638 | #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK 0x00000600 |
3639 | #define A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT 9 |
3640 | static inline uint32_t A6XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) |
3641 | { |
3642 | return ((val) << A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A6XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK; |
3643 | } |
3644 | #define A6XX_RB_RENDER_CNTL_CONSERVATIVERASEN 0x00000800 |
3645 | #define A6XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN 0x00001000 |
3646 | #define A6XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000 |
3647 | #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000 |
3648 | #define A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT 16 |
3649 | static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) |
3650 | { |
3651 | return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; |
3652 | } |
3653 | |
3654 | #define REG_A7XX_RB_RENDER_CNTL 0x00008801 |
3655 | #define A7XX_RB_RENDER_CNTL_EARLYVIZOUTEN 0x00000040 |
3656 | #define A7XX_RB_RENDER_CNTL_BINNING 0x00000080 |
3657 | #define A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK 0x00000100 |
3658 | #define A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT 8 |
3659 | static inline uint32_t A7XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val) |
3660 | { |
3661 | return ((val) << A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK; |
3662 | } |
3663 | #define A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK 0x00000600 |
3664 | #define A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT 9 |
3665 | static inline uint32_t A7XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) |
3666 | { |
3667 | return ((val) << A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK; |
3668 | } |
3669 | #define A7XX_RB_RENDER_CNTL_CONSERVATIVERASEN 0x00000800 |
3670 | #define A7XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN 0x00001000 |
3671 | |
3672 | #define REG_A7XX_GRAS_SU_RENDER_CNTL 0x00008116 |
3673 | #define A7XX_GRAS_SU_RENDER_CNTL_BINNING 0x00000080 |
3674 | |
3675 | #define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802 |
3676 | #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 |
3677 | #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 |
3678 | static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) |
3679 | { |
3680 | return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; |
3681 | } |
3682 | #define A6XX_RB_RAS_MSAA_CNTL_UNK2 0x00000004 |
3683 | #define A6XX_RB_RAS_MSAA_CNTL_UNK3 0x00000008 |
3684 | |
3685 | #define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803 |
3686 | #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 |
3687 | #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 |
3688 | static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) |
3689 | { |
3690 | return ((val) << A6XX_RB_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK; |
3691 | } |
3692 | #define A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 |
3693 | |
3694 | #define REG_A6XX_RB_SAMPLE_CONFIG 0x00008804 |
3695 | #define A6XX_RB_SAMPLE_CONFIG_UNK0 0x00000001 |
3696 | #define A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 |
3697 | |
3698 | #define REG_A6XX_RB_SAMPLE_LOCATION_0 0x00008805 |
3699 | #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f |
3700 | #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 |
3701 | static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) |
3702 | { |
3703 | return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; |
3704 | } |
3705 | #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 |
3706 | #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 |
3707 | static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) |
3708 | { |
3709 | return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; |
3710 | } |
3711 | #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 |
3712 | #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 |
3713 | static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) |
3714 | { |
3715 | return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; |
3716 | } |
3717 | #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 |
3718 | #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 |
3719 | static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) |
3720 | { |
3721 | return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; |
3722 | } |
3723 | #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 |
3724 | #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 |
3725 | static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) |
3726 | { |
3727 | return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; |
3728 | } |
3729 | #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 |
3730 | #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 |
3731 | static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) |
3732 | { |
3733 | return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; |
3734 | } |
3735 | #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 |
3736 | #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 |
3737 | static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) |
3738 | { |
3739 | return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; |
3740 | } |
3741 | #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 |
3742 | #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 |
3743 | static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) |
3744 | { |
3745 | return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; |
3746 | } |
3747 | |
3748 | #define REG_A6XX_RB_SAMPLE_LOCATION_1 0x00008806 |
3749 | #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f |
3750 | #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 |
3751 | static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) |
3752 | { |
3753 | return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; |
3754 | } |
3755 | #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 |
3756 | #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 |
3757 | static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) |
3758 | { |
3759 | return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; |
3760 | } |
3761 | #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 |
3762 | #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 |
3763 | static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) |
3764 | { |
3765 | return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; |
3766 | } |
3767 | #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 |
3768 | #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 |
3769 | static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) |
3770 | { |
3771 | return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; |
3772 | } |
3773 | #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 |
3774 | #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 |
3775 | static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) |
3776 | { |
3777 | return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; |
3778 | } |
3779 | #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 |
3780 | #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 |
3781 | static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) |
3782 | { |
3783 | return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; |
3784 | } |
3785 | #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 |
3786 | #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 |
3787 | static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) |
3788 | { |
3789 | return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; |
3790 | } |
3791 | #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 |
3792 | #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 |
3793 | static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) |
3794 | { |
3795 | return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; |
3796 | } |
3797 | |
3798 | #define REG_A6XX_RB_RENDER_CONTROL0 0x00008809 |
3799 | #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL 0x00000001 |
3800 | #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID 0x00000002 |
3801 | #define A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE 0x00000004 |
3802 | #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL 0x00000008 |
3803 | #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID 0x00000010 |
3804 | #define A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE 0x00000020 |
3805 | #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK 0x000003c0 |
3806 | #define A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT 6 |
3807 | static inline uint32_t A6XX_RB_RENDER_CONTROL0_COORD_MASK(uint32_t val) |
3808 | { |
3809 | return ((val) << A6XX_RB_RENDER_CONTROL0_COORD_MASK__SHIFT) & A6XX_RB_RENDER_CONTROL0_COORD_MASK__MASK; |
3810 | } |
3811 | #define A6XX_RB_RENDER_CONTROL0_UNK10 0x00000400 |
3812 | |
3813 | #define REG_A6XX_RB_RENDER_CONTROL1 0x0000880a |
3814 | #define A6XX_RB_RENDER_CONTROL1_SAMPLEMASK 0x00000001 |
3815 | #define A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE 0x00000002 |
3816 | #define A6XX_RB_RENDER_CONTROL1_FACENESS 0x00000004 |
3817 | #define A6XX_RB_RENDER_CONTROL1_SAMPLEID 0x00000008 |
3818 | #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK 0x00000030 |
3819 | #define A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT 4 |
3820 | static inline uint32_t A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(enum a6xx_fragcoord_sample_mode val) |
3821 | { |
3822 | return ((val) << A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__SHIFT) & A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE__MASK; |
3823 | } |
3824 | #define A6XX_RB_RENDER_CONTROL1_CENTERRHW 0x00000040 |
3825 | #define A6XX_RB_RENDER_CONTROL1_LINELENGTHEN 0x00000080 |
3826 | #define A6XX_RB_RENDER_CONTROL1_FOVEATION 0x00000100 |
3827 | |
3828 | #define REG_A6XX_RB_FS_OUTPUT_CNTL0 0x0000880b |
3829 | #define A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001 |
3830 | #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z 0x00000002 |
3831 | #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK 0x00000004 |
3832 | #define A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF 0x00000008 |
3833 | |
3834 | #define REG_A6XX_RB_FS_OUTPUT_CNTL1 0x0000880c |
3835 | #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f |
3836 | #define A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT 0 |
3837 | static inline uint32_t A6XX_RB_FS_OUTPUT_CNTL1_MRT(uint32_t val) |
3838 | { |
3839 | return ((val) << A6XX_RB_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_RB_FS_OUTPUT_CNTL1_MRT__MASK; |
3840 | } |
3841 | |
3842 | #define REG_A6XX_RB_RENDER_COMPONENTS 0x0000880d |
3843 | #define A6XX_RB_RENDER_COMPONENTS_RT0__MASK 0x0000000f |
3844 | #define A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT 0 |
3845 | static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT0(uint32_t val) |
3846 | { |
3847 | return ((val) << A6XX_RB_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT0__MASK; |
3848 | } |
3849 | #define A6XX_RB_RENDER_COMPONENTS_RT1__MASK 0x000000f0 |
3850 | #define A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT 4 |
3851 | static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT1(uint32_t val) |
3852 | { |
3853 | return ((val) << A6XX_RB_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT1__MASK; |
3854 | } |
3855 | #define A6XX_RB_RENDER_COMPONENTS_RT2__MASK 0x00000f00 |
3856 | #define A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT 8 |
3857 | static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT2(uint32_t val) |
3858 | { |
3859 | return ((val) << A6XX_RB_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT2__MASK; |
3860 | } |
3861 | #define A6XX_RB_RENDER_COMPONENTS_RT3__MASK 0x0000f000 |
3862 | #define A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT 12 |
3863 | static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT3(uint32_t val) |
3864 | { |
3865 | return ((val) << A6XX_RB_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT3__MASK; |
3866 | } |
3867 | #define A6XX_RB_RENDER_COMPONENTS_RT4__MASK 0x000f0000 |
3868 | #define A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT 16 |
3869 | static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT4(uint32_t val) |
3870 | { |
3871 | return ((val) << A6XX_RB_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT4__MASK; |
3872 | } |
3873 | #define A6XX_RB_RENDER_COMPONENTS_RT5__MASK 0x00f00000 |
3874 | #define A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT 20 |
3875 | static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT5(uint32_t val) |
3876 | { |
3877 | return ((val) << A6XX_RB_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT5__MASK; |
3878 | } |
3879 | #define A6XX_RB_RENDER_COMPONENTS_RT6__MASK 0x0f000000 |
3880 | #define A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT 24 |
3881 | static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT6(uint32_t val) |
3882 | { |
3883 | return ((val) << A6XX_RB_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT6__MASK; |
3884 | } |
3885 | #define A6XX_RB_RENDER_COMPONENTS_RT7__MASK 0xf0000000 |
3886 | #define A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT 28 |
3887 | static inline uint32_t A6XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) |
3888 | { |
3889 | return ((val) << A6XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_RB_RENDER_COMPONENTS_RT7__MASK; |
3890 | } |
3891 | |
3892 | #define REG_A6XX_RB_DITHER_CNTL 0x0000880e |
3893 | #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK 0x00000003 |
3894 | #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT 0 |
3895 | static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0(enum adreno_rb_dither_mode val) |
3896 | { |
3897 | return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT0__MASK; |
3898 | } |
3899 | #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK 0x0000000c |
3900 | #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT 2 |
3901 | static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1(enum adreno_rb_dither_mode val) |
3902 | { |
3903 | return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT1__MASK; |
3904 | } |
3905 | #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK 0x00000030 |
3906 | #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT 4 |
3907 | static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2(enum adreno_rb_dither_mode val) |
3908 | { |
3909 | return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT2__MASK; |
3910 | } |
3911 | #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK 0x000000c0 |
3912 | #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT 6 |
3913 | static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3(enum adreno_rb_dither_mode val) |
3914 | { |
3915 | return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT3__MASK; |
3916 | } |
3917 | #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK 0x00000300 |
3918 | #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT 8 |
3919 | static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4(enum adreno_rb_dither_mode val) |
3920 | { |
3921 | return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT4__MASK; |
3922 | } |
3923 | #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK 0x00000c00 |
3924 | #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT 10 |
3925 | static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dither_mode val) |
3926 | { |
3927 | return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK; |
3928 | } |
3929 | #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00003000 |
3930 | #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12 |
3931 | static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val) |
3932 | { |
3933 | return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK; |
3934 | } |
3935 | #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK 0x0000c000 |
3936 | #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT 14 |
3937 | static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dither_mode val) |
3938 | { |
3939 | return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7__MASK; |
3940 | } |
3941 | |
3942 | #define REG_A6XX_RB_SRGB_CNTL 0x0000880f |
3943 | #define A6XX_RB_SRGB_CNTL_SRGB_MRT0 0x00000001 |
3944 | #define A6XX_RB_SRGB_CNTL_SRGB_MRT1 0x00000002 |
3945 | #define A6XX_RB_SRGB_CNTL_SRGB_MRT2 0x00000004 |
3946 | #define A6XX_RB_SRGB_CNTL_SRGB_MRT3 0x00000008 |
3947 | #define A6XX_RB_SRGB_CNTL_SRGB_MRT4 0x00000010 |
3948 | #define A6XX_RB_SRGB_CNTL_SRGB_MRT5 0x00000020 |
3949 | #define A6XX_RB_SRGB_CNTL_SRGB_MRT6 0x00000040 |
3950 | #define A6XX_RB_SRGB_CNTL_SRGB_MRT7 0x00000080 |
3951 | |
3952 | #define REG_A6XX_RB_SAMPLE_CNTL 0x00008810 |
3953 | #define A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 |
3954 | |
3955 | #define REG_A6XX_RB_UNKNOWN_8811 0x00008811 |
3956 | |
3957 | #define REG_A7XX_RB_UNKNOWN_8812 0x00008812 |
3958 | |
3959 | #define REG_A6XX_RB_UNKNOWN_8818 0x00008818 |
3960 | |
3961 | #define REG_A6XX_RB_UNKNOWN_8819 0x00008819 |
3962 | |
3963 | #define REG_A6XX_RB_UNKNOWN_881A 0x0000881a |
3964 | |
3965 | #define REG_A6XX_RB_UNKNOWN_881B 0x0000881b |
3966 | |
3967 | #define REG_A6XX_RB_UNKNOWN_881C 0x0000881c |
3968 | |
3969 | #define REG_A6XX_RB_UNKNOWN_881D 0x0000881d |
3970 | |
3971 | #define REG_A6XX_RB_UNKNOWN_881E 0x0000881e |
3972 | |
3973 | #define REG_A6XX_RB_MRT(i0) (0x00008820 + 0x8*(i0)) |
3974 | |
3975 | static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; } |
3976 | #define A6XX_RB_MRT_CONTROL_BLEND 0x00000001 |
3977 | #define A6XX_RB_MRT_CONTROL_BLEND2 0x00000002 |
3978 | #define A6XX_RB_MRT_CONTROL_ROP_ENABLE 0x00000004 |
3979 | #define A6XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000078 |
3980 | #define A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 3 |
3981 | static inline uint32_t A6XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val) |
3982 | { |
3983 | return ((val) << A6XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A6XX_RB_MRT_CONTROL_ROP_CODE__MASK; |
3984 | } |
3985 | #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x00000780 |
3986 | #define A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 7 |
3987 | static inline uint32_t A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val) |
3988 | { |
3989 | return ((val) << A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A6XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK; |
3990 | } |
3991 | |
3992 | static inline uint32_t REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x00008821 + 0x8*i0; } |
3993 | #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f |
3994 | #define A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0 |
3995 | static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val) |
3996 | { |
3997 | return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK; |
3998 | } |
3999 | #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 |
4000 | #define A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 |
4001 | static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) |
4002 | { |
4003 | return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; |
4004 | } |
4005 | #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00 |
4006 | #define A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8 |
4007 | static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val) |
4008 | { |
4009 | return ((val) << A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK; |
4010 | } |
4011 | #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000 |
4012 | #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16 |
4013 | static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val) |
4014 | { |
4015 | return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK; |
4016 | } |
4017 | #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 |
4018 | #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 |
4019 | static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val) |
4020 | { |
4021 | return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; |
4022 | } |
4023 | #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000 |
4024 | #define A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24 |
4025 | static inline uint32_t A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val) |
4026 | { |
4027 | return ((val) << A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A6XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK; |
4028 | } |
4029 | |
4030 | static inline uint32_t REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; } |
4031 | #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff |
4032 | #define A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 |
4033 | static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val) |
4034 | { |
4035 | return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; |
4036 | } |
4037 | #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 |
4038 | #define A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 |
4039 | static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) |
4040 | { |
4041 | return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; |
4042 | } |
4043 | #define A6XX_RB_MRT_BUF_INFO_UNK10 0x00000400 |
4044 | #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 |
4045 | #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 |
4046 | static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) |
4047 | { |
4048 | return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; |
4049 | } |
4050 | |
4051 | static inline uint32_t REG_A7XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; } |
4052 | #define A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff |
4053 | #define A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 |
4054 | static inline uint32_t A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val) |
4055 | { |
4056 | return ((val) << A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; |
4057 | } |
4058 | #define A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 |
4059 | #define A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 |
4060 | static inline uint32_t A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) |
4061 | { |
4062 | return ((val) << A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; |
4063 | } |
4064 | #define A7XX_RB_MRT_BUF_INFO_UNK10 0x00000400 |
4065 | #define A7XX_RB_MRT_BUF_INFO_LOSSLESSCOMPEN 0x00000800 |
4066 | #define A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 |
4067 | #define A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 |
4068 | static inline uint32_t A7XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) |
4069 | { |
4070 | return ((val) << A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; |
4071 | } |
4072 | |
4073 | static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; } |
4074 | #define A6XX_RB_MRT_PITCH__MASK 0xffffffff |
4075 | #define A6XX_RB_MRT_PITCH__SHIFT 0 |
4076 | static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val) |
4077 | { |
4078 | assert(!(val & 0x3f)); |
4079 | return (((val >> 6)) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK; |
4080 | } |
4081 | |
4082 | static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; } |
4083 | #define A6XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff |
4084 | #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0 |
4085 | static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) |
4086 | { |
4087 | assert(!(val & 0x3f)); |
4088 | return (((val >> 6)) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK; |
4089 | } |
4090 | |
4091 | static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; } |
4092 | |
4093 | static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; } |
4094 | |
4095 | #define REG_A6XX_RB_BLEND_RED_F32 0x00008860 |
4096 | #define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff |
4097 | #define A6XX_RB_BLEND_RED_F32__SHIFT 0 |
4098 | static inline uint32_t A6XX_RB_BLEND_RED_F32(float val) |
4099 | { |
4100 | return ((fui(val)) << A6XX_RB_BLEND_RED_F32__SHIFT) & A6XX_RB_BLEND_RED_F32__MASK; |
4101 | } |
4102 | |
4103 | #define REG_A6XX_RB_BLEND_GREEN_F32 0x00008861 |
4104 | #define A6XX_RB_BLEND_GREEN_F32__MASK 0xffffffff |
4105 | #define A6XX_RB_BLEND_GREEN_F32__SHIFT 0 |
4106 | static inline uint32_t A6XX_RB_BLEND_GREEN_F32(float val) |
4107 | { |
4108 | return ((fui(val)) << A6XX_RB_BLEND_GREEN_F32__SHIFT) & A6XX_RB_BLEND_GREEN_F32__MASK; |
4109 | } |
4110 | |
4111 | #define REG_A6XX_RB_BLEND_BLUE_F32 0x00008862 |
4112 | #define A6XX_RB_BLEND_BLUE_F32__MASK 0xffffffff |
4113 | #define A6XX_RB_BLEND_BLUE_F32__SHIFT 0 |
4114 | static inline uint32_t A6XX_RB_BLEND_BLUE_F32(float val) |
4115 | { |
4116 | return ((fui(val)) << A6XX_RB_BLEND_BLUE_F32__SHIFT) & A6XX_RB_BLEND_BLUE_F32__MASK; |
4117 | } |
4118 | |
4119 | #define REG_A6XX_RB_BLEND_ALPHA_F32 0x00008863 |
4120 | #define A6XX_RB_BLEND_ALPHA_F32__MASK 0xffffffff |
4121 | #define A6XX_RB_BLEND_ALPHA_F32__SHIFT 0 |
4122 | static inline uint32_t A6XX_RB_BLEND_ALPHA_F32(float val) |
4123 | { |
4124 | return ((fui(val)) << A6XX_RB_BLEND_ALPHA_F32__SHIFT) & A6XX_RB_BLEND_ALPHA_F32__MASK; |
4125 | } |
4126 | |
4127 | #define REG_A6XX_RB_ALPHA_CONTROL 0x00008864 |
4128 | #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK 0x000000ff |
4129 | #define A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT 0 |
4130 | static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_REF(uint32_t val) |
4131 | { |
4132 | return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_REF__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_REF__MASK; |
4133 | } |
4134 | #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST 0x00000100 |
4135 | #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK 0x00000e00 |
4136 | #define A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT 9 |
4137 | static inline uint32_t A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val) |
4138 | { |
4139 | return ((val) << A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC__MASK; |
4140 | } |
4141 | |
4142 | #define REG_A6XX_RB_BLEND_CNTL 0x00008865 |
4143 | #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff |
4144 | #define A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 |
4145 | static inline uint32_t A6XX_RB_BLEND_CNTL_ENABLE_BLEND(uint32_t val) |
4146 | { |
4147 | return ((val) << A6XX_RB_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_RB_BLEND_CNTL_ENABLE_BLEND__MASK; |
4148 | } |
4149 | #define A6XX_RB_BLEND_CNTL_INDEPENDENT_BLEND 0x00000100 |
4150 | #define A6XX_RB_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200 |
4151 | #define A6XX_RB_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 |
4152 | #define A6XX_RB_BLEND_CNTL_ALPHA_TO_ONE 0x00000800 |
4153 | #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK 0xffff0000 |
4154 | #define A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT 16 |
4155 | static inline uint32_t A6XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val) |
4156 | { |
4157 | return ((val) << A6XX_RB_BLEND_CNTL_SAMPLE_MASK__SHIFT) & A6XX_RB_BLEND_CNTL_SAMPLE_MASK__MASK; |
4158 | } |
4159 | |
4160 | #define REG_A6XX_RB_DEPTH_PLANE_CNTL 0x00008870 |
4161 | #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK 0x00000003 |
4162 | #define A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT 0 |
4163 | static inline uint32_t A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE(enum a6xx_ztest_mode val) |
4164 | { |
4165 | return ((val) << A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__SHIFT) & A6XX_RB_DEPTH_PLANE_CNTL_Z_MODE__MASK; |
4166 | } |
4167 | |
4168 | #define REG_A6XX_RB_DEPTH_CNTL 0x00008871 |
4169 | #define A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE 0x00000001 |
4170 | #define A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE 0x00000002 |
4171 | #define A6XX_RB_DEPTH_CNTL_ZFUNC__MASK 0x0000001c |
4172 | #define A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT 2 |
4173 | static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) |
4174 | { |
4175 | return ((val) << A6XX_RB_DEPTH_CNTL_ZFUNC__SHIFT) & A6XX_RB_DEPTH_CNTL_ZFUNC__MASK; |
4176 | } |
4177 | #define A6XX_RB_DEPTH_CNTL_Z_CLAMP_ENABLE 0x00000020 |
4178 | #define A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE 0x00000040 |
4179 | #define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE 0x00000080 |
4180 | |
4181 | #define REG_A6XX_GRAS_SU_DEPTH_CNTL 0x00008114 |
4182 | #define A6XX_GRAS_SU_DEPTH_CNTL_Z_TEST_ENABLE 0x00000001 |
4183 | |
4184 | #define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872 |
4185 | #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 |
4186 | #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 |
4187 | static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) |
4188 | { |
4189 | return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; |
4190 | } |
4191 | #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000018 |
4192 | #define A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 |
4193 | static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val) |
4194 | { |
4195 | return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK; |
4196 | } |
4197 | |
4198 | #define REG_A7XX_RB_DEPTH_BUFFER_INFO 0x00008872 |
4199 | #define A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 |
4200 | #define A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 |
4201 | static inline uint32_t A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) |
4202 | { |
4203 | return ((val) << A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; |
4204 | } |
4205 | #define A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000018 |
4206 | #define A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 |
4207 | static inline uint32_t A7XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val) |
4208 | { |
4209 | return ((val) << A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK; |
4210 | } |
4211 | #define A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK 0x00000060 |
4212 | #define A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT 5 |
4213 | static inline uint32_t A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE(enum a6xx_tile_mode val) |
4214 | { |
4215 | return ((val) << A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK; |
4216 | } |
4217 | #define A7XX_RB_DEPTH_BUFFER_INFO_LOSSLESSCOMPEN 0x00000080 |
4218 | |
4219 | #define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873 |
4220 | #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0x00003fff |
4221 | #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 |
4222 | static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) |
4223 | { |
4224 | assert(!(val & 0x3f)); |
4225 | return (((val >> 6)) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK; |
4226 | } |
4227 | |
4228 | #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874 |
4229 | #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK 0x0fffffff |
4230 | #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 |
4231 | static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) |
4232 | { |
4233 | assert(!(val & 0x3f)); |
4234 | return (((val >> 6)) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; |
4235 | } |
4236 | |
4237 | #define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875 |
4238 | |
4239 | #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877 |
4240 | |
4241 | #define REG_A6XX_RB_Z_BOUNDS_MIN 0x00008878 |
4242 | #define A6XX_RB_Z_BOUNDS_MIN__MASK 0xffffffff |
4243 | #define A6XX_RB_Z_BOUNDS_MIN__SHIFT 0 |
4244 | static inline uint32_t A6XX_RB_Z_BOUNDS_MIN(float val) |
4245 | { |
4246 | return ((fui(val)) << A6XX_RB_Z_BOUNDS_MIN__SHIFT) & A6XX_RB_Z_BOUNDS_MIN__MASK; |
4247 | } |
4248 | |
4249 | #define REG_A6XX_RB_Z_BOUNDS_MAX 0x00008879 |
4250 | #define A6XX_RB_Z_BOUNDS_MAX__MASK 0xffffffff |
4251 | #define A6XX_RB_Z_BOUNDS_MAX__SHIFT 0 |
4252 | static inline uint32_t A6XX_RB_Z_BOUNDS_MAX(float val) |
4253 | { |
4254 | return ((fui(val)) << A6XX_RB_Z_BOUNDS_MAX__SHIFT) & A6XX_RB_Z_BOUNDS_MAX__MASK; |
4255 | } |
4256 | |
4257 | #define REG_A6XX_RB_STENCIL_CONTROL 0x00008880 |
4258 | #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001 |
4259 | #define A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002 |
4260 | #define A6XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004 |
4261 | #define A6XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700 |
4262 | #define A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8 |
4263 | static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val) |
4264 | { |
4265 | return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC__MASK; |
4266 | } |
4267 | #define A6XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800 |
4268 | #define A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11 |
4269 | static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val) |
4270 | { |
4271 | return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL__MASK; |
4272 | } |
4273 | #define A6XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000 |
4274 | #define A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14 |
4275 | static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val) |
4276 | { |
4277 | return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS__MASK; |
4278 | } |
4279 | #define A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000 |
4280 | #define A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17 |
4281 | static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val) |
4282 | { |
4283 | return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL__MASK; |
4284 | } |
4285 | #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000 |
4286 | #define A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20 |
4287 | static inline uint32_t A6XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val) |
4288 | { |
4289 | return ((val) << A6XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FUNC_BF__MASK; |
4290 | } |
4291 | #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000 |
4292 | #define A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23 |
4293 | static inline uint32_t A6XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val) |
4294 | { |
4295 | return ((val) << A6XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_FAIL_BF__MASK; |
4296 | } |
4297 | #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000 |
4298 | #define A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26 |
4299 | static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val) |
4300 | { |
4301 | return ((val) << A6XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK; |
4302 | } |
4303 | #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000 |
4304 | #define A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29 |
4305 | static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val) |
4306 | { |
4307 | return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; |
4308 | } |
4309 | |
4310 | #define REG_A6XX_GRAS_SU_STENCIL_CNTL 0x00008115 |
4311 | #define A6XX_GRAS_SU_STENCIL_CNTL_STENCIL_ENABLE 0x00000001 |
4312 | |
4313 | #define REG_A6XX_RB_STENCIL_INFO 0x00008881 |
4314 | #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 |
4315 | #define A6XX_RB_STENCIL_INFO_UNK1 0x00000002 |
4316 | |
4317 | #define REG_A7XX_RB_STENCIL_INFO 0x00008881 |
4318 | #define A7XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 |
4319 | #define A7XX_RB_STENCIL_INFO_UNK1 0x00000002 |
4320 | #define A7XX_RB_STENCIL_INFO_TILEMODE__MASK 0x0000000c |
4321 | #define A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT 2 |
4322 | static inline uint32_t A7XX_RB_STENCIL_INFO_TILEMODE(enum a6xx_tile_mode val) |
4323 | { |
4324 | return ((val) << A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT) & A7XX_RB_STENCIL_INFO_TILEMODE__MASK; |
4325 | } |
4326 | |
4327 | #define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882 |
4328 | #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0x00000fff |
4329 | #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0 |
4330 | static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) |
4331 | { |
4332 | assert(!(val & 0x3f)); |
4333 | return (((val >> 6)) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK; |
4334 | } |
4335 | |
4336 | #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883 |
4337 | #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK 0x00ffffff |
4338 | #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0 |
4339 | static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) |
4340 | { |
4341 | assert(!(val & 0x3f)); |
4342 | return (((val >> 6)) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK; |
4343 | } |
4344 | |
4345 | #define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884 |
4346 | |
4347 | #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886 |
4348 | |
4349 | #define REG_A6XX_RB_STENCILREF 0x00008887 |
4350 | #define A6XX_RB_STENCILREF_REF__MASK 0x000000ff |
4351 | #define A6XX_RB_STENCILREF_REF__SHIFT 0 |
4352 | static inline uint32_t A6XX_RB_STENCILREF_REF(uint32_t val) |
4353 | { |
4354 | return ((val) << A6XX_RB_STENCILREF_REF__SHIFT) & A6XX_RB_STENCILREF_REF__MASK; |
4355 | } |
4356 | #define A6XX_RB_STENCILREF_BFREF__MASK 0x0000ff00 |
4357 | #define A6XX_RB_STENCILREF_BFREF__SHIFT 8 |
4358 | static inline uint32_t A6XX_RB_STENCILREF_BFREF(uint32_t val) |
4359 | { |
4360 | return ((val) << A6XX_RB_STENCILREF_BFREF__SHIFT) & A6XX_RB_STENCILREF_BFREF__MASK; |
4361 | } |
4362 | |
4363 | #define REG_A6XX_RB_STENCILMASK 0x00008888 |
4364 | #define A6XX_RB_STENCILMASK_MASK__MASK 0x000000ff |
4365 | #define A6XX_RB_STENCILMASK_MASK__SHIFT 0 |
4366 | static inline uint32_t A6XX_RB_STENCILMASK_MASK(uint32_t val) |
4367 | { |
4368 | return ((val) << A6XX_RB_STENCILMASK_MASK__SHIFT) & A6XX_RB_STENCILMASK_MASK__MASK; |
4369 | } |
4370 | #define A6XX_RB_STENCILMASK_BFMASK__MASK 0x0000ff00 |
4371 | #define A6XX_RB_STENCILMASK_BFMASK__SHIFT 8 |
4372 | static inline uint32_t A6XX_RB_STENCILMASK_BFMASK(uint32_t val) |
4373 | { |
4374 | return ((val) << A6XX_RB_STENCILMASK_BFMASK__SHIFT) & A6XX_RB_STENCILMASK_BFMASK__MASK; |
4375 | } |
4376 | |
4377 | #define REG_A6XX_RB_STENCILWRMASK 0x00008889 |
4378 | #define A6XX_RB_STENCILWRMASK_WRMASK__MASK 0x000000ff |
4379 | #define A6XX_RB_STENCILWRMASK_WRMASK__SHIFT 0 |
4380 | static inline uint32_t A6XX_RB_STENCILWRMASK_WRMASK(uint32_t val) |
4381 | { |
4382 | return ((val) << A6XX_RB_STENCILWRMASK_WRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_WRMASK__MASK; |
4383 | } |
4384 | #define A6XX_RB_STENCILWRMASK_BFWRMASK__MASK 0x0000ff00 |
4385 | #define A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT 8 |
4386 | static inline uint32_t A6XX_RB_STENCILWRMASK_BFWRMASK(uint32_t val) |
4387 | { |
4388 | return ((val) << A6XX_RB_STENCILWRMASK_BFWRMASK__SHIFT) & A6XX_RB_STENCILWRMASK_BFWRMASK__MASK; |
4389 | } |
4390 | |
4391 | #define REG_A6XX_RB_WINDOW_OFFSET 0x00008890 |
4392 | #define A6XX_RB_WINDOW_OFFSET_X__MASK 0x00003fff |
4393 | #define A6XX_RB_WINDOW_OFFSET_X__SHIFT 0 |
4394 | static inline uint32_t A6XX_RB_WINDOW_OFFSET_X(uint32_t val) |
4395 | { |
4396 | return ((val) << A6XX_RB_WINDOW_OFFSET_X__SHIFT) & A6XX_RB_WINDOW_OFFSET_X__MASK; |
4397 | } |
4398 | #define A6XX_RB_WINDOW_OFFSET_Y__MASK 0x3fff0000 |
4399 | #define A6XX_RB_WINDOW_OFFSET_Y__SHIFT 16 |
4400 | static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val) |
4401 | { |
4402 | return ((val) << A6XX_RB_WINDOW_OFFSET_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET_Y__MASK; |
4403 | } |
4404 | |
4405 | #define REG_A6XX_RB_SAMPLE_COUNT_CONTROL 0x00008891 |
4406 | #define A6XX_RB_SAMPLE_COUNT_CONTROL_DISABLE 0x00000001 |
4407 | #define A6XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002 |
4408 | |
4409 | #define REG_A6XX_RB_LRZ_CNTL 0x00008898 |
4410 | #define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001 |
4411 | |
4412 | #define REG_A7XX_RB_UNKNOWN_8899 0x00008899 |
4413 | |
4414 | #define REG_A6XX_RB_Z_CLAMP_MIN 0x000088c0 |
4415 | #define A6XX_RB_Z_CLAMP_MIN__MASK 0xffffffff |
4416 | #define A6XX_RB_Z_CLAMP_MIN__SHIFT 0 |
4417 | static inline uint32_t A6XX_RB_Z_CLAMP_MIN(float val) |
4418 | { |
4419 | return ((fui(val)) << A6XX_RB_Z_CLAMP_MIN__SHIFT) & A6XX_RB_Z_CLAMP_MIN__MASK; |
4420 | } |
4421 | |
4422 | #define REG_A6XX_RB_Z_CLAMP_MAX 0x000088c1 |
4423 | #define A6XX_RB_Z_CLAMP_MAX__MASK 0xffffffff |
4424 | #define A6XX_RB_Z_CLAMP_MAX__SHIFT 0 |
4425 | static inline uint32_t A6XX_RB_Z_CLAMP_MAX(float val) |
4426 | { |
4427 | return ((fui(val)) << A6XX_RB_Z_CLAMP_MAX__SHIFT) & A6XX_RB_Z_CLAMP_MAX__MASK; |
4428 | } |
4429 | |
4430 | #define REG_A6XX_RB_UNKNOWN_88D0 0x000088d0 |
4431 | #define A6XX_RB_UNKNOWN_88D0_UNK0__MASK 0x00001fff |
4432 | #define A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT 0 |
4433 | static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK0(uint32_t val) |
4434 | { |
4435 | return ((val) << A6XX_RB_UNKNOWN_88D0_UNK0__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK0__MASK; |
4436 | } |
4437 | #define A6XX_RB_UNKNOWN_88D0_UNK16__MASK 0x07ff0000 |
4438 | #define A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT 16 |
4439 | static inline uint32_t A6XX_RB_UNKNOWN_88D0_UNK16(uint32_t val) |
4440 | { |
4441 | return ((val) << A6XX_RB_UNKNOWN_88D0_UNK16__SHIFT) & A6XX_RB_UNKNOWN_88D0_UNK16__MASK; |
4442 | } |
4443 | |
4444 | #define REG_A6XX_RB_BLIT_SCISSOR_TL 0x000088d1 |
4445 | #define A6XX_RB_BLIT_SCISSOR_TL_X__MASK 0x00003fff |
4446 | #define A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT 0 |
4447 | static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_X(uint32_t val) |
4448 | { |
4449 | return ((val) << A6XX_RB_BLIT_SCISSOR_TL_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_X__MASK; |
4450 | } |
4451 | #define A6XX_RB_BLIT_SCISSOR_TL_Y__MASK 0x3fff0000 |
4452 | #define A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT 16 |
4453 | static inline uint32_t A6XX_RB_BLIT_SCISSOR_TL_Y(uint32_t val) |
4454 | { |
4455 | return ((val) << A6XX_RB_BLIT_SCISSOR_TL_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_TL_Y__MASK; |
4456 | } |
4457 | |
4458 | #define REG_A6XX_RB_BLIT_SCISSOR_BR 0x000088d2 |
4459 | #define A6XX_RB_BLIT_SCISSOR_BR_X__MASK 0x00003fff |
4460 | #define A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT 0 |
4461 | static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_X(uint32_t val) |
4462 | { |
4463 | return ((val) << A6XX_RB_BLIT_SCISSOR_BR_X__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_X__MASK; |
4464 | } |
4465 | #define A6XX_RB_BLIT_SCISSOR_BR_Y__MASK 0x3fff0000 |
4466 | #define A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT 16 |
4467 | static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val) |
4468 | { |
4469 | return ((val) << A6XX_RB_BLIT_SCISSOR_BR_Y__SHIFT) & A6XX_RB_BLIT_SCISSOR_BR_Y__MASK; |
4470 | } |
4471 | |
4472 | #define REG_A6XX_RB_BIN_CONTROL2 0x000088d3 |
4473 | #define A6XX_RB_BIN_CONTROL2_BINW__MASK 0x0000003f |
4474 | #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0 |
4475 | static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val) |
4476 | { |
4477 | assert(!(val & 0x1f)); |
4478 | return (((val >> 5)) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK; |
4479 | } |
4480 | #define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x00007f00 |
4481 | #define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8 |
4482 | static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val) |
4483 | { |
4484 | assert(!(val & 0xf)); |
4485 | return (((val >> 4)) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK; |
4486 | } |
4487 | |
4488 | #define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4 |
4489 | #define A6XX_RB_WINDOW_OFFSET2_X__MASK 0x00003fff |
4490 | #define A6XX_RB_WINDOW_OFFSET2_X__SHIFT 0 |
4491 | static inline uint32_t A6XX_RB_WINDOW_OFFSET2_X(uint32_t val) |
4492 | { |
4493 | return ((val) << A6XX_RB_WINDOW_OFFSET2_X__SHIFT) & A6XX_RB_WINDOW_OFFSET2_X__MASK; |
4494 | } |
4495 | #define A6XX_RB_WINDOW_OFFSET2_Y__MASK 0x3fff0000 |
4496 | #define A6XX_RB_WINDOW_OFFSET2_Y__SHIFT 16 |
4497 | static inline uint32_t A6XX_RB_WINDOW_OFFSET2_Y(uint32_t val) |
4498 | { |
4499 | return ((val) << A6XX_RB_WINDOW_OFFSET2_Y__SHIFT) & A6XX_RB_WINDOW_OFFSET2_Y__MASK; |
4500 | } |
4501 | |
4502 | #define REG_A6XX_RB_BLIT_GMEM_MSAA_CNTL 0x000088d5 |
4503 | #define A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK 0x00000018 |
4504 | #define A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT 3 |
4505 | static inline uint32_t A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) |
4506 | { |
4507 | return ((val) << A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES__MASK; |
4508 | } |
4509 | |
4510 | #define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6 |
4511 | |
4512 | #define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7 |
4513 | #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003 |
4514 | #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT 0 |
4515 | static inline uint32_t A6XX_RB_BLIT_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) |
4516 | { |
4517 | return ((val) << A6XX_RB_BLIT_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK; |
4518 | } |
4519 | #define A6XX_RB_BLIT_DST_INFO_FLAGS 0x00000004 |
4520 | #define A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK 0x00000018 |
4521 | #define A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT 3 |
4522 | static inline uint32_t A6XX_RB_BLIT_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) |
4523 | { |
4524 | return ((val) << A6XX_RB_BLIT_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_BLIT_DST_INFO_SAMPLES__MASK; |
4525 | } |
4526 | #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK 0x00000060 |
4527 | #define A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT 5 |
4528 | static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) |
4529 | { |
4530 | return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_SWAP__MASK; |
4531 | } |
4532 | #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK 0x00007f80 |
4533 | #define A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT 7 |
4534 | static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val) |
4535 | { |
4536 | return ((val) << A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT__MASK; |
4537 | } |
4538 | #define A6XX_RB_BLIT_DST_INFO_UNK15 0x00008000 |
4539 | |
4540 | #define REG_A6XX_RB_BLIT_DST 0x000088d8 |
4541 | |
4542 | #define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da |
4543 | #define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff |
4544 | #define A6XX_RB_BLIT_DST_PITCH__SHIFT 0 |
4545 | static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val) |
4546 | { |
4547 | assert(!(val & 0x3f)); |
4548 | return (((val >> 6)) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK; |
4549 | } |
4550 | |
4551 | #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db |
4552 | #define A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK 0x1fffffff |
4553 | #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 |
4554 | static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) |
4555 | { |
4556 | assert(!(val & 0x3f)); |
4557 | return (((val >> 6)) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK; |
4558 | } |
4559 | |
4560 | #define REG_A6XX_RB_BLIT_FLAG_DST 0x000088dc |
4561 | |
4562 | #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de |
4563 | #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff |
4564 | #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0 |
4565 | static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val) |
4566 | { |
4567 | assert(!(val & 0x3f)); |
4568 | return (((val >> 6)) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK; |
4569 | } |
4570 | #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x0ffff800 |
4571 | #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11 |
4572 | static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val) |
4573 | { |
4574 | assert(!(val & 0x7f)); |
4575 | return (((val >> 7)) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK; |
4576 | } |
4577 | |
4578 | #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df |
4579 | |
4580 | #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW1 0x000088e0 |
4581 | |
4582 | #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW2 0x000088e1 |
4583 | |
4584 | #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW3 0x000088e2 |
4585 | |
4586 | #define REG_A6XX_RB_BLIT_INFO 0x000088e3 |
4587 | #define A6XX_RB_BLIT_INFO_UNK0 0x00000001 |
4588 | #define A6XX_RB_BLIT_INFO_GMEM 0x00000002 |
4589 | #define A6XX_RB_BLIT_INFO_SAMPLE_0 0x00000004 |
4590 | #define A6XX_RB_BLIT_INFO_DEPTH 0x00000008 |
4591 | #define A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK 0x000000f0 |
4592 | #define A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT 4 |
4593 | static inline uint32_t A6XX_RB_BLIT_INFO_CLEAR_MASK(uint32_t val) |
4594 | { |
4595 | return ((val) << A6XX_RB_BLIT_INFO_CLEAR_MASK__SHIFT) & A6XX_RB_BLIT_INFO_CLEAR_MASK__MASK; |
4596 | } |
4597 | #define A6XX_RB_BLIT_INFO_LAST__MASK 0x00000300 |
4598 | #define A6XX_RB_BLIT_INFO_LAST__SHIFT 8 |
4599 | static inline uint32_t A6XX_RB_BLIT_INFO_LAST(uint32_t val) |
4600 | { |
4601 | return ((val) << A6XX_RB_BLIT_INFO_LAST__SHIFT) & A6XX_RB_BLIT_INFO_LAST__MASK; |
4602 | } |
4603 | #define A6XX_RB_BLIT_INFO_BUFFER_ID__MASK 0x0000f000 |
4604 | #define A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT 12 |
4605 | static inline uint32_t A6XX_RB_BLIT_INFO_BUFFER_ID(uint32_t val) |
4606 | { |
4607 | return ((val) << A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT) & A6XX_RB_BLIT_INFO_BUFFER_ID__MASK; |
4608 | } |
4609 | |
4610 | #define REG_A7XX_RB_UNKNOWN_88E4 0x000088e4 |
4611 | #define A7XX_RB_UNKNOWN_88E4_UNK0 0x00000001 |
4612 | |
4613 | #define REG_A7XX_RB_CCU_CNTL2 0x000088e5 |
4614 | #define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK 0x00000001 |
4615 | #define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT 0 |
4616 | static inline uint32_t A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI(uint32_t val) |
4617 | { |
4618 | return ((val) << A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK; |
4619 | } |
4620 | #define A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK 0x00000004 |
4621 | #define A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT 2 |
4622 | static inline uint32_t A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI(uint32_t val) |
4623 | { |
4624 | return ((val) << A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK; |
4625 | } |
4626 | #define A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK 0x00000c00 |
4627 | #define A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT 10 |
4628 | static inline uint32_t A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE(enum a6xx_ccu_cache_size val) |
4629 | { |
4630 | return ((val) << A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK; |
4631 | } |
4632 | #define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK 0x001ff000 |
4633 | #define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT 12 |
4634 | static inline uint32_t A7XX_RB_CCU_CNTL2_DEPTH_OFFSET(uint32_t val) |
4635 | { |
4636 | assert(!(val & 0xfff)); |
4637 | return (((val >> 12)) << A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK; |
4638 | } |
4639 | #define A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK 0x00600000 |
4640 | #define A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT 21 |
4641 | static inline uint32_t A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE(enum a6xx_ccu_cache_size val) |
4642 | { |
4643 | return ((val) << A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK; |
4644 | } |
4645 | #define A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK 0xff800000 |
4646 | #define A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT 23 |
4647 | static inline uint32_t A7XX_RB_CCU_CNTL2_COLOR_OFFSET(uint32_t val) |
4648 | { |
4649 | assert(!(val & 0xfff)); |
4650 | return (((val >> 12)) << A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK; |
4651 | } |
4652 | |
4653 | #define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0 |
4654 | |
4655 | #define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE 0x000088f1 |
4656 | |
4657 | #define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH 0x000088f3 |
4658 | #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff |
4659 | #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 |
4660 | static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val) |
4661 | { |
4662 | assert(!(val & 0x3f)); |
4663 | return (((val >> 6)) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK; |
4664 | } |
4665 | #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x00fff800 |
4666 | #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 |
4667 | static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) |
4668 | { |
4669 | assert(!(val & 0x7f)); |
4670 | return (((val >> 7)) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; |
4671 | } |
4672 | |
4673 | #define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4 |
4674 | |
4675 | #define REG_A7XX_RB_UNKNOWN_88F5 0x000088f5 |
4676 | |
4677 | #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900 |
4678 | |
4679 | #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902 |
4680 | #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x0000007f |
4681 | #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 |
4682 | static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val) |
4683 | { |
4684 | assert(!(val & 0x3f)); |
4685 | return (((val >> 6)) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK; |
4686 | } |
4687 | #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK 0x00000700 |
4688 | #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT 8 |
4689 | static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val) |
4690 | { |
4691 | return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK; |
4692 | } |
4693 | #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x0ffff800 |
4694 | #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 |
4695 | static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) |
4696 | { |
4697 | assert(!(val & 0x7f)); |
4698 | return (((val >> 7)) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; |
4699 | } |
4700 | |
4701 | #define REG_A6XX_RB_MRT_FLAG_BUFFER(i0) (0x00008903 + 0x3*(i0)) |
4702 | |
4703 | static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; } |
4704 | |
4705 | static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; } |
4706 | #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff |
4707 | #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 |
4708 | static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val) |
4709 | { |
4710 | assert(!(val & 0x3f)); |
4711 | return (((val >> 6)) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK; |
4712 | } |
4713 | #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffff800 |
4714 | #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 |
4715 | static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) |
4716 | { |
4717 | assert(!(val & 0x7f)); |
4718 | return (((val >> 7)) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; |
4719 | } |
4720 | |
4721 | #define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927 |
4722 | |
4723 | #define REG_A6XX_RB_UNKNOWN_8A00 0x00008a00 |
4724 | |
4725 | #define REG_A6XX_RB_UNKNOWN_8A10 0x00008a10 |
4726 | |
4727 | #define REG_A6XX_RB_UNKNOWN_8A20 0x00008a20 |
4728 | |
4729 | #define REG_A6XX_RB_UNKNOWN_8A30 0x00008a30 |
4730 | |
4731 | #define REG_A6XX_RB_2D_BLIT_CNTL 0x00008c00 |
4732 | #define A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK 0x00000007 |
4733 | #define A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT 0 |
4734 | static inline uint32_t A6XX_RB_2D_BLIT_CNTL_ROTATE(enum a6xx_rotation val) |
4735 | { |
4736 | return ((val) << A6XX_RB_2D_BLIT_CNTL_ROTATE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_ROTATE__MASK; |
4737 | } |
4738 | #define A6XX_RB_2D_BLIT_CNTL_OVERWRITEEN 0x00000008 |
4739 | #define A6XX_RB_2D_BLIT_CNTL_UNK4__MASK 0x00000070 |
4740 | #define A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT 4 |
4741 | static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK4(uint32_t val) |
4742 | { |
4743 | return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK4__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK4__MASK; |
4744 | } |
4745 | #define A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR 0x00000080 |
4746 | #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK 0x0000ff00 |
4747 | #define A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT 8 |
4748 | static inline uint32_t A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(enum a6xx_format val) |
4749 | { |
4750 | return ((val) << A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT__MASK; |
4751 | } |
4752 | #define A6XX_RB_2D_BLIT_CNTL_SCISSOR 0x00010000 |
4753 | #define A6XX_RB_2D_BLIT_CNTL_UNK17__MASK 0x00060000 |
4754 | #define A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT 17 |
4755 | static inline uint32_t A6XX_RB_2D_BLIT_CNTL_UNK17(uint32_t val) |
4756 | { |
4757 | return ((val) << A6XX_RB_2D_BLIT_CNTL_UNK17__SHIFT) & A6XX_RB_2D_BLIT_CNTL_UNK17__MASK; |
4758 | } |
4759 | #define A6XX_RB_2D_BLIT_CNTL_D24S8 0x00080000 |
4760 | #define A6XX_RB_2D_BLIT_CNTL_MASK__MASK 0x00f00000 |
4761 | #define A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT 20 |
4762 | static inline uint32_t A6XX_RB_2D_BLIT_CNTL_MASK(uint32_t val) |
4763 | { |
4764 | return ((val) << A6XX_RB_2D_BLIT_CNTL_MASK__SHIFT) & A6XX_RB_2D_BLIT_CNTL_MASK__MASK; |
4765 | } |
4766 | #define A6XX_RB_2D_BLIT_CNTL_IFMT__MASK 0x1f000000 |
4767 | #define A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT 24 |
4768 | static inline uint32_t A6XX_RB_2D_BLIT_CNTL_IFMT(enum a6xx_2d_ifmt val) |
4769 | { |
4770 | return ((val) << A6XX_RB_2D_BLIT_CNTL_IFMT__SHIFT) & A6XX_RB_2D_BLIT_CNTL_IFMT__MASK; |
4771 | } |
4772 | #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK 0x20000000 |
4773 | #define A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT 29 |
4774 | static inline uint32_t A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode val) |
4775 | { |
4776 | return ((val) << A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK; |
4777 | } |
4778 | #define A6XX_RB_2D_BLIT_CNTL_UNK30 0x40000000 |
4779 | |
4780 | #define REG_A6XX_RB_2D_UNKNOWN_8C01 0x00008c01 |
4781 | |
4782 | #define REG_A6XX_RB_2D_DST_INFO 0x00008c17 |
4783 | #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff |
4784 | #define A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0 |
4785 | static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_FORMAT(enum a6xx_format val) |
4786 | { |
4787 | return ((val) << A6XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK; |
4788 | } |
4789 | #define A6XX_RB_2D_DST_INFO_TILE_MODE__MASK 0x00000300 |
4790 | #define A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT 8 |
4791 | static inline uint32_t A6XX_RB_2D_DST_INFO_TILE_MODE(enum a6xx_tile_mode val) |
4792 | { |
4793 | return ((val) << A6XX_RB_2D_DST_INFO_TILE_MODE__SHIFT) & A6XX_RB_2D_DST_INFO_TILE_MODE__MASK; |
4794 | } |
4795 | #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK 0x00000c00 |
4796 | #define A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT 10 |
4797 | static inline uint32_t A6XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) |
4798 | { |
4799 | return ((val) << A6XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_2D_DST_INFO_COLOR_SWAP__MASK; |
4800 | } |
4801 | #define A6XX_RB_2D_DST_INFO_FLAGS 0x00001000 |
4802 | #define A6XX_RB_2D_DST_INFO_SRGB 0x00002000 |
4803 | #define A6XX_RB_2D_DST_INFO_SAMPLES__MASK 0x0000c000 |
4804 | #define A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT 14 |
4805 | static inline uint32_t A6XX_RB_2D_DST_INFO_SAMPLES(enum a3xx_msaa_samples val) |
4806 | { |
4807 | return ((val) << A6XX_RB_2D_DST_INFO_SAMPLES__SHIFT) & A6XX_RB_2D_DST_INFO_SAMPLES__MASK; |
4808 | } |
4809 | #define A6XX_RB_2D_DST_INFO_FILTER 0x00010000 |
4810 | #define A6XX_RB_2D_DST_INFO_UNK17 0x00020000 |
4811 | #define A6XX_RB_2D_DST_INFO_SAMPLES_AVERAGE 0x00040000 |
4812 | #define A6XX_RB_2D_DST_INFO_UNK19 0x00080000 |
4813 | #define A6XX_RB_2D_DST_INFO_UNK20 0x00100000 |
4814 | #define A6XX_RB_2D_DST_INFO_UNK21 0x00200000 |
4815 | #define A6XX_RB_2D_DST_INFO_UNK22 0x00400000 |
4816 | #define A6XX_RB_2D_DST_INFO_UNK23__MASK 0x07800000 |
4817 | #define A6XX_RB_2D_DST_INFO_UNK23__SHIFT 23 |
4818 | static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val) |
4819 | { |
4820 | return ((val) << A6XX_RB_2D_DST_INFO_UNK23__SHIFT) & A6XX_RB_2D_DST_INFO_UNK23__MASK; |
4821 | } |
4822 | #define A6XX_RB_2D_DST_INFO_UNK28 0x10000000 |
4823 | |
4824 | #define REG_A6XX_RB_2D_DST 0x00008c18 |
4825 | |
4826 | #define REG_A6XX_RB_2D_DST_PITCH 0x00008c1a |
4827 | #define A6XX_RB_2D_DST_PITCH__MASK 0x0000ffff |
4828 | #define A6XX_RB_2D_DST_PITCH__SHIFT 0 |
4829 | static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val) |
4830 | { |
4831 | assert(!(val & 0x3f)); |
4832 | return (((val >> 6)) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK; |
4833 | } |
4834 | |
4835 | #define REG_A6XX_RB_2D_DST_PLANE1 0x00008c1b |
4836 | |
4837 | #define REG_A6XX_RB_2D_DST_PLANE_PITCH 0x00008c1d |
4838 | #define A6XX_RB_2D_DST_PLANE_PITCH__MASK 0x0000ffff |
4839 | #define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT 0 |
4840 | static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val) |
4841 | { |
4842 | assert(!(val & 0x3f)); |
4843 | return (((val >> 6)) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK; |
4844 | } |
4845 | |
4846 | #define REG_A6XX_RB_2D_DST_PLANE2 0x00008c1e |
4847 | |
4848 | #define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20 |
4849 | |
4850 | #define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22 |
4851 | #define A6XX_RB_2D_DST_FLAGS_PITCH__MASK 0x000000ff |
4852 | #define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0 |
4853 | static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val) |
4854 | { |
4855 | assert(!(val & 0x3f)); |
4856 | return (((val >> 6)) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK; |
4857 | } |
4858 | |
4859 | #define REG_A6XX_RB_2D_DST_FLAGS_PLANE 0x00008c23 |
4860 | |
4861 | #define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH 0x00008c25 |
4862 | #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK 0x000000ff |
4863 | #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT 0 |
4864 | static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val) |
4865 | { |
4866 | assert(!(val & 0x3f)); |
4867 | return (((val >> 6)) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK; |
4868 | } |
4869 | |
4870 | #define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c |
4871 | |
4872 | #define REG_A6XX_RB_2D_SRC_SOLID_C1 0x00008c2d |
4873 | |
4874 | #define REG_A6XX_RB_2D_SRC_SOLID_C2 0x00008c2e |
4875 | |
4876 | #define REG_A6XX_RB_2D_SRC_SOLID_C3 0x00008c2f |
4877 | |
4878 | #define REG_A6XX_RB_UNKNOWN_8E01 0x00008e01 |
4879 | |
4880 | #define REG_A6XX_RB_DBG_ECO_CNTL 0x00008e04 |
4881 | |
4882 | #define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05 |
4883 | |
4884 | #define REG_A7XX_RB_UNKNOWN_8E06 0x00008e06 |
4885 | |
4886 | #define REG_A6XX_RB_CCU_CNTL 0x00008e07 |
4887 | #define A6XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE 0x00000001 |
4888 | #define A6XX_RB_CCU_CNTL_CONCURRENT_RESOLVE 0x00000004 |
4889 | #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK 0x00000080 |
4890 | #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT 7 |
4891 | static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI(uint32_t val) |
4892 | { |
4893 | return ((val) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK; |
4894 | } |
4895 | #define A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK 0x00000200 |
4896 | #define A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT 9 |
4897 | static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI(uint32_t val) |
4898 | { |
4899 | return ((val) << A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK; |
4900 | } |
4901 | #define A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK 0x00000c00 |
4902 | #define A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT 10 |
4903 | static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE(enum a6xx_ccu_cache_size val) |
4904 | { |
4905 | return ((val) << A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK; |
4906 | } |
4907 | #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK 0x001ff000 |
4908 | #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT 12 |
4909 | static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET(uint32_t val) |
4910 | { |
4911 | assert(!(val & 0xfff)); |
4912 | return (((val >> 12)) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK; |
4913 | } |
4914 | #define A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK 0x00600000 |
4915 | #define A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT 21 |
4916 | static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE(enum a6xx_ccu_cache_size val) |
4917 | { |
4918 | return ((val) << A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK; |
4919 | } |
4920 | #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK 0xff800000 |
4921 | #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT 23 |
4922 | static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET(uint32_t val) |
4923 | { |
4924 | assert(!(val & 0xfff)); |
4925 | return (((val >> 12)) << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK; |
4926 | } |
4927 | |
4928 | #define REG_A7XX_RB_CCU_CNTL 0x00008e07 |
4929 | #define A7XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE 0x00000001 |
4930 | #define A7XX_RB_CCU_CNTL_CONCURRENT_RESOLVE 0x00000004 |
4931 | |
4932 | #define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08 |
4933 | #define A6XX_RB_NC_MODE_CNTL_MODE 0x00000001 |
4934 | #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006 |
4935 | #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT 1 |
4936 | static inline uint32_t A6XX_RB_NC_MODE_CNTL_LOWER_BIT(uint32_t val) |
4937 | { |
4938 | return ((val) << A6XX_RB_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK; |
4939 | } |
4940 | #define A6XX_RB_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008 |
4941 | #define A6XX_RB_NC_MODE_CNTL_AMSBC 0x00000010 |
4942 | #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000400 |
4943 | #define A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT 10 |
4944 | static inline uint32_t A6XX_RB_NC_MODE_CNTL_UPPER_BIT(uint32_t val) |
4945 | { |
4946 | return ((val) << A6XX_RB_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_RB_NC_MODE_CNTL_UPPER_BIT__MASK; |
4947 | } |
4948 | #define A6XX_RB_NC_MODE_CNTL_RGB565_PREDICATOR 0x00000800 |
4949 | #define A6XX_RB_NC_MODE_CNTL_UNK12__MASK 0x00003000 |
4950 | #define A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT 12 |
4951 | static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val) |
4952 | { |
4953 | return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK; |
4954 | } |
4955 | |
4956 | #define REG_A7XX_RB_UNKNOWN_8E09 0x00008e09 |
4957 | |
4958 | #define REG_A6XX_RB_PERFCTR_RB_SEL(i0) (0x00008e10 + 0x1*(i0)) |
4959 | |
4960 | #define REG_A6XX_RB_PERFCTR_CCU_SEL(i0) (0x00008e18 + 0x1*(i0)) |
4961 | |
4962 | #define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28 |
4963 | |
4964 | #define REG_A6XX_RB_PERFCTR_CMP_SEL(i0) (0x00008e2c + 0x1*(i0)) |
4965 | |
4966 | #define REG_A7XX_RB_PERFCTR_UFC_SEL(i0) (0x00008e30 + 0x1*(i0)) |
4967 | |
4968 | #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b |
4969 | |
4970 | #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD 0x00008e3d |
4971 | |
4972 | #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50 |
4973 | |
4974 | #define REG_A6XX_RB_UNKNOWN_8E51 0x00008e51 |
4975 | |
4976 | #define REG_A7XX_RB_UNKNOWN_8E79 0x00008e79 |
4977 | |
4978 | #define REG_A6XX_VPC_GS_PARAM 0x00009100 |
4979 | #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK 0x000000ff |
4980 | #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT 0 |
4981 | static inline uint32_t A6XX_VPC_GS_PARAM_LINELENGTHLOC(uint32_t val) |
4982 | { |
4983 | return ((val) << A6XX_VPC_GS_PARAM_LINELENGTHLOC__SHIFT) & A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK; |
4984 | } |
4985 | |
4986 | #define REG_A6XX_VPC_VS_CLIP_CNTL 0x00009101 |
4987 | #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff |
4988 | #define A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT 0 |
4989 | static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(uint32_t val) |
4990 | { |
4991 | return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK__MASK; |
4992 | } |
4993 | #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 |
4994 | #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 |
4995 | static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) |
4996 | { |
4997 | return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; |
4998 | } |
4999 | #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 |
5000 | #define A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 |
5001 | static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) |
5002 | { |
5003 | return ((val) << A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; |
5004 | } |
5005 | |
5006 | #define REG_A6XX_VPC_GS_CLIP_CNTL 0x00009102 |
5007 | #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff |
5008 | #define A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT 0 |
5009 | static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK(uint32_t val) |
5010 | { |
5011 | return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_MASK__MASK; |
5012 | } |
5013 | #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 |
5014 | #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 |
5015 | static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) |
5016 | { |
5017 | return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; |
5018 | } |
5019 | #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 |
5020 | #define A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 |
5021 | static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) |
5022 | { |
5023 | return ((val) << A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; |
5024 | } |
5025 | |
5026 | #define REG_A6XX_VPC_DS_CLIP_CNTL 0x00009103 |
5027 | #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK 0x000000ff |
5028 | #define A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT 0 |
5029 | static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK(uint32_t val) |
5030 | { |
5031 | return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_MASK__MASK; |
5032 | } |
5033 | #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK 0x0000ff00 |
5034 | #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT 8 |
5035 | static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC(uint32_t val) |
5036 | { |
5037 | return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_03_LOC__MASK; |
5038 | } |
5039 | #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK 0x00ff0000 |
5040 | #define A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT 16 |
5041 | static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) |
5042 | { |
5043 | return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; |
5044 | } |
5045 | |
5046 | #define REG_A6XX_VPC_VS_CLIP_CNTL_V2 0x00009311 |
5047 | #define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK 0x000000ff |
5048 | #define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT 0 |
5049 | static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val) |
5050 | { |
5051 | return ((val) << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK; |
5052 | } |
5053 | #define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK 0x0000ff00 |
5054 | #define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT 8 |
5055 | static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val) |
5056 | { |
5057 | return ((val) << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK; |
5058 | } |
5059 | #define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK 0x00ff0000 |
5060 | #define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT 16 |
5061 | static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val) |
5062 | { |
5063 | return ((val) << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK; |
5064 | } |
5065 | |
5066 | #define REG_A6XX_VPC_GS_CLIP_CNTL_V2 0x00009312 |
5067 | #define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK 0x000000ff |
5068 | #define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT 0 |
5069 | static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val) |
5070 | { |
5071 | return ((val) << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK; |
5072 | } |
5073 | #define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK 0x0000ff00 |
5074 | #define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT 8 |
5075 | static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val) |
5076 | { |
5077 | return ((val) << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK; |
5078 | } |
5079 | #define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK 0x00ff0000 |
5080 | #define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT 16 |
5081 | static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val) |
5082 | { |
5083 | return ((val) << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK; |
5084 | } |
5085 | |
5086 | #define REG_A6XX_VPC_DS_CLIP_CNTL_V2 0x00009313 |
5087 | #define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK 0x000000ff |
5088 | #define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT 0 |
5089 | static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val) |
5090 | { |
5091 | return ((val) << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK; |
5092 | } |
5093 | #define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK 0x0000ff00 |
5094 | #define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT 8 |
5095 | static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val) |
5096 | { |
5097 | return ((val) << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK; |
5098 | } |
5099 | #define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK 0x00ff0000 |
5100 | #define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT 16 |
5101 | static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val) |
5102 | { |
5103 | return ((val) << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK; |
5104 | } |
5105 | |
5106 | #define REG_A6XX_VPC_VS_LAYER_CNTL 0x00009104 |
5107 | #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff |
5108 | #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT 0 |
5109 | static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(uint32_t val) |
5110 | { |
5111 | return ((val) << A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK; |
5112 | } |
5113 | #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 |
5114 | #define A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT 8 |
5115 | static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val) |
5116 | { |
5117 | return ((val) << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK; |
5118 | } |
5119 | #define A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK 0x00ff0000 |
5120 | #define A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT 16 |
5121 | static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC(uint32_t val) |
5122 | { |
5123 | return ((val) << A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK; |
5124 | } |
5125 | |
5126 | #define REG_A6XX_VPC_GS_LAYER_CNTL 0x00009105 |
5127 | #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff |
5128 | #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT 0 |
5129 | static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_LAYERLOC(uint32_t val) |
5130 | { |
5131 | return ((val) << A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK; |
5132 | } |
5133 | #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 |
5134 | #define A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT 8 |
5135 | static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val) |
5136 | { |
5137 | return ((val) << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK; |
5138 | } |
5139 | #define A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK 0x00ff0000 |
5140 | #define A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT 16 |
5141 | static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC(uint32_t val) |
5142 | { |
5143 | return ((val) << A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK; |
5144 | } |
5145 | |
5146 | #define REG_A6XX_VPC_DS_LAYER_CNTL 0x00009106 |
5147 | #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff |
5148 | #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT 0 |
5149 | static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_LAYERLOC(uint32_t val) |
5150 | { |
5151 | return ((val) << A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK; |
5152 | } |
5153 | #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK 0x0000ff00 |
5154 | #define A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT 8 |
5155 | static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val) |
5156 | { |
5157 | return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK; |
5158 | } |
5159 | #define A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK 0x00ff0000 |
5160 | #define A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT 16 |
5161 | static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC(uint32_t val) |
5162 | { |
5163 | return ((val) << A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK; |
5164 | } |
5165 | |
5166 | #define REG_A6XX_VPC_VS_LAYER_CNTL_V2 0x00009314 |
5167 | #define A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK 0x000000ff |
5168 | #define A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT 0 |
5169 | static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC(uint32_t val) |
5170 | { |
5171 | return ((val) << A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK; |
5172 | } |
5173 | #define A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK 0x0000ff00 |
5174 | #define A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT 8 |
5175 | static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC(uint32_t val) |
5176 | { |
5177 | return ((val) << A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK; |
5178 | } |
5179 | #define A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK 0x00ff0000 |
5180 | #define A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT 16 |
5181 | static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val) |
5182 | { |
5183 | return ((val) << A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK; |
5184 | } |
5185 | |
5186 | #define REG_A6XX_VPC_GS_LAYER_CNTL_V2 0x00009315 |
5187 | #define A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK 0x000000ff |
5188 | #define A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT 0 |
5189 | static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC(uint32_t val) |
5190 | { |
5191 | return ((val) << A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK; |
5192 | } |
5193 | #define A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK 0x0000ff00 |
5194 | #define A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT 8 |
5195 | static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC(uint32_t val) |
5196 | { |
5197 | return ((val) << A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK; |
5198 | } |
5199 | #define A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK 0x00ff0000 |
5200 | #define A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT 16 |
5201 | static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val) |
5202 | { |
5203 | return ((val) << A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK; |
5204 | } |
5205 | |
5206 | #define REG_A6XX_VPC_DS_LAYER_CNTL_V2 0x00009316 |
5207 | #define A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK 0x000000ff |
5208 | #define A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT 0 |
5209 | static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC(uint32_t val) |
5210 | { |
5211 | return ((val) << A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK; |
5212 | } |
5213 | #define A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK 0x0000ff00 |
5214 | #define A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT 8 |
5215 | static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC(uint32_t val) |
5216 | { |
5217 | return ((val) << A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK; |
5218 | } |
5219 | #define A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK 0x00ff0000 |
5220 | #define A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT 16 |
5221 | static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val) |
5222 | { |
5223 | return ((val) << A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK; |
5224 | } |
5225 | |
5226 | #define REG_A6XX_VPC_UNKNOWN_9107 0x00009107 |
5227 | #define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001 |
5228 | #define A6XX_VPC_UNKNOWN_9107_UNK2 0x00000004 |
5229 | |
5230 | #define REG_A6XX_VPC_POLYGON_MODE 0x00009108 |
5231 | #define A6XX_VPC_POLYGON_MODE_MODE__MASK 0x00000003 |
5232 | #define A6XX_VPC_POLYGON_MODE_MODE__SHIFT 0 |
5233 | static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) |
5234 | { |
5235 | return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK; |
5236 | } |
5237 | |
5238 | #define REG_A7XX_VPC_PRIMITIVE_CNTL_0 0x00009109 |
5239 | #define A7XX_VPC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 |
5240 | #define A7XX_VPC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002 |
5241 | #define A7XX_VPC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING 0x00000004 |
5242 | #define A7XX_VPC_PRIMITIVE_CNTL_0_UNK3 0x00000008 |
5243 | |
5244 | #define REG_A7XX_VPC_PRIMITIVE_CNTL_5 0x0000910a |
5245 | #define A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff |
5246 | #define A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0 |
5247 | static inline uint32_t A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val) |
5248 | { |
5249 | return ((val) << A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK; |
5250 | } |
5251 | #define A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00 |
5252 | #define A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10 |
5253 | static inline uint32_t A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val) |
5254 | { |
5255 | return ((val) << A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK; |
5256 | } |
5257 | #define A7XX_VPC_PRIMITIVE_CNTL_5_LINELENGTHEN 0x00008000 |
5258 | #define A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000 |
5259 | #define A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16 |
5260 | static inline uint32_t A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val) |
5261 | { |
5262 | return ((val) << A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK; |
5263 | } |
5264 | #define A7XX_VPC_PRIMITIVE_CNTL_5_UNK18 0x00040000 |
5265 | |
5266 | #define REG_A7XX_VPC_MULTIVIEW_MASK 0x0000910b |
5267 | |
5268 | #define REG_A7XX_VPC_MULTIVIEW_CNTL 0x0000910c |
5269 | #define A7XX_VPC_MULTIVIEW_CNTL_ENABLE 0x00000001 |
5270 | #define A7XX_VPC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 |
5271 | #define A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c |
5272 | #define A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT 2 |
5273 | static inline uint32_t A7XX_VPC_MULTIVIEW_CNTL_VIEWS(uint32_t val) |
5274 | { |
5275 | return ((val) << A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK; |
5276 | } |
5277 | |
5278 | #define REG_A6XX_VPC_VARYING_INTERP(i0) (0x00009200 + 0x1*(i0)) |
5279 | |
5280 | static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; } |
5281 | |
5282 | #define REG_A6XX_VPC_VARYING_PS_REPL(i0) (0x00009208 + 0x1*(i0)) |
5283 | |
5284 | static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; } |
5285 | |
5286 | #define REG_A6XX_VPC_UNKNOWN_9210 0x00009210 |
5287 | |
5288 | #define REG_A6XX_VPC_UNKNOWN_9211 0x00009211 |
5289 | |
5290 | #define REG_A6XX_VPC_VAR(i0) (0x00009212 + 0x1*(i0)) |
5291 | |
5292 | static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; } |
5293 | |
5294 | #define REG_A6XX_VPC_SO_CNTL 0x00009216 |
5295 | #define A6XX_VPC_SO_CNTL_ADDR__MASK 0x000000ff |
5296 | #define A6XX_VPC_SO_CNTL_ADDR__SHIFT 0 |
5297 | static inline uint32_t A6XX_VPC_SO_CNTL_ADDR(uint32_t val) |
5298 | { |
5299 | return ((val) << A6XX_VPC_SO_CNTL_ADDR__SHIFT) & A6XX_VPC_SO_CNTL_ADDR__MASK; |
5300 | } |
5301 | #define A6XX_VPC_SO_CNTL_RESET 0x00010000 |
5302 | |
5303 | #define REG_A6XX_VPC_SO_PROG 0x00009217 |
5304 | #define A6XX_VPC_SO_PROG_A_BUF__MASK 0x00000003 |
5305 | #define A6XX_VPC_SO_PROG_A_BUF__SHIFT 0 |
5306 | static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val) |
5307 | { |
5308 | return ((val) << A6XX_VPC_SO_PROG_A_BUF__SHIFT) & A6XX_VPC_SO_PROG_A_BUF__MASK; |
5309 | } |
5310 | #define A6XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc |
5311 | #define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2 |
5312 | static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val) |
5313 | { |
5314 | assert(!(val & 0x3)); |
5315 | return (((val >> 2)) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK; |
5316 | } |
5317 | #define A6XX_VPC_SO_PROG_A_EN 0x00000800 |
5318 | #define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000 |
5319 | #define A6XX_VPC_SO_PROG_B_BUF__SHIFT 12 |
5320 | static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val) |
5321 | { |
5322 | return ((val) << A6XX_VPC_SO_PROG_B_BUF__SHIFT) & A6XX_VPC_SO_PROG_B_BUF__MASK; |
5323 | } |
5324 | #define A6XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000 |
5325 | #define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14 |
5326 | static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val) |
5327 | { |
5328 | assert(!(val & 0x3)); |
5329 | return (((val >> 2)) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK; |
5330 | } |
5331 | #define A6XX_VPC_SO_PROG_B_EN 0x00800000 |
5332 | |
5333 | #define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218 |
5334 | |
5335 | #define REG_A6XX_VPC_SO(i0) (0x0000921a + 0x7*(i0)) |
5336 | |
5337 | static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; } |
5338 | |
5339 | static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; } |
5340 | |
5341 | static inline uint32_t REG_A6XX_VPC_SO_BUFFER_STRIDE(uint32_t i0) { return 0x0000921d + 0x7*i0; } |
5342 | |
5343 | static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; } |
5344 | |
5345 | static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; } |
5346 | |
5347 | #define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236 |
5348 | #define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001 |
5349 | |
5350 | #define REG_A6XX_VPC_UNKNOWN_9300 0x00009300 |
5351 | |
5352 | #define REG_A6XX_VPC_VS_PACK 0x00009301 |
5353 | #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK 0x000000ff |
5354 | #define A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT 0 |
5355 | static inline uint32_t A6XX_VPC_VS_PACK_STRIDE_IN_VPC(uint32_t val) |
5356 | { |
5357 | return ((val) << A6XX_VPC_VS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_VS_PACK_STRIDE_IN_VPC__MASK; |
5358 | } |
5359 | #define A6XX_VPC_VS_PACK_POSITIONLOC__MASK 0x0000ff00 |
5360 | #define A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT 8 |
5361 | static inline uint32_t A6XX_VPC_VS_PACK_POSITIONLOC(uint32_t val) |
5362 | { |
5363 | return ((val) << A6XX_VPC_VS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_VS_PACK_POSITIONLOC__MASK; |
5364 | } |
5365 | #define A6XX_VPC_VS_PACK_PSIZELOC__MASK 0x00ff0000 |
5366 | #define A6XX_VPC_VS_PACK_PSIZELOC__SHIFT 16 |
5367 | static inline uint32_t A6XX_VPC_VS_PACK_PSIZELOC(uint32_t val) |
5368 | { |
5369 | return ((val) << A6XX_VPC_VS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_VS_PACK_PSIZELOC__MASK; |
5370 | } |
5371 | #define 0x0f000000 |
5372 | #define 24 |
5373 | static inline uint32_t (uint32_t val) |
5374 | { |
5375 | return ((val) << A6XX_VPC_VS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_VS_PACK_EXTRAPOS__MASK; |
5376 | } |
5377 | |
5378 | #define REG_A6XX_VPC_GS_PACK 0x00009302 |
5379 | #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK 0x000000ff |
5380 | #define A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT 0 |
5381 | static inline uint32_t A6XX_VPC_GS_PACK_STRIDE_IN_VPC(uint32_t val) |
5382 | { |
5383 | return ((val) << A6XX_VPC_GS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_GS_PACK_STRIDE_IN_VPC__MASK; |
5384 | } |
5385 | #define A6XX_VPC_GS_PACK_POSITIONLOC__MASK 0x0000ff00 |
5386 | #define A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT 8 |
5387 | static inline uint32_t A6XX_VPC_GS_PACK_POSITIONLOC(uint32_t val) |
5388 | { |
5389 | return ((val) << A6XX_VPC_GS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_GS_PACK_POSITIONLOC__MASK; |
5390 | } |
5391 | #define A6XX_VPC_GS_PACK_PSIZELOC__MASK 0x00ff0000 |
5392 | #define A6XX_VPC_GS_PACK_PSIZELOC__SHIFT 16 |
5393 | static inline uint32_t A6XX_VPC_GS_PACK_PSIZELOC(uint32_t val) |
5394 | { |
5395 | return ((val) << A6XX_VPC_GS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_GS_PACK_PSIZELOC__MASK; |
5396 | } |
5397 | #define 0x0f000000 |
5398 | #define 24 |
5399 | static inline uint32_t (uint32_t val) |
5400 | { |
5401 | return ((val) << A6XX_VPC_GS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_GS_PACK_EXTRAPOS__MASK; |
5402 | } |
5403 | |
5404 | #define REG_A6XX_VPC_DS_PACK 0x00009303 |
5405 | #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK 0x000000ff |
5406 | #define A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT 0 |
5407 | static inline uint32_t A6XX_VPC_DS_PACK_STRIDE_IN_VPC(uint32_t val) |
5408 | { |
5409 | return ((val) << A6XX_VPC_DS_PACK_STRIDE_IN_VPC__SHIFT) & A6XX_VPC_DS_PACK_STRIDE_IN_VPC__MASK; |
5410 | } |
5411 | #define A6XX_VPC_DS_PACK_POSITIONLOC__MASK 0x0000ff00 |
5412 | #define A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT 8 |
5413 | static inline uint32_t A6XX_VPC_DS_PACK_POSITIONLOC(uint32_t val) |
5414 | { |
5415 | return ((val) << A6XX_VPC_DS_PACK_POSITIONLOC__SHIFT) & A6XX_VPC_DS_PACK_POSITIONLOC__MASK; |
5416 | } |
5417 | #define A6XX_VPC_DS_PACK_PSIZELOC__MASK 0x00ff0000 |
5418 | #define A6XX_VPC_DS_PACK_PSIZELOC__SHIFT 16 |
5419 | static inline uint32_t A6XX_VPC_DS_PACK_PSIZELOC(uint32_t val) |
5420 | { |
5421 | return ((val) << A6XX_VPC_DS_PACK_PSIZELOC__SHIFT) & A6XX_VPC_DS_PACK_PSIZELOC__MASK; |
5422 | } |
5423 | #define 0x0f000000 |
5424 | #define 24 |
5425 | static inline uint32_t (uint32_t val) |
5426 | { |
5427 | return ((val) << A6XX_VPC_DS_PACK_EXTRAPOS__SHIFT) & A6XX_VPC_DS_PACK_EXTRAPOS__MASK; |
5428 | } |
5429 | |
5430 | #define REG_A6XX_VPC_CNTL_0 0x00009304 |
5431 | #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK 0x000000ff |
5432 | #define A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT 0 |
5433 | static inline uint32_t A6XX_VPC_CNTL_0_NUMNONPOSVAR(uint32_t val) |
5434 | { |
5435 | return ((val) << A6XX_VPC_CNTL_0_NUMNONPOSVAR__SHIFT) & A6XX_VPC_CNTL_0_NUMNONPOSVAR__MASK; |
5436 | } |
5437 | #define A6XX_VPC_CNTL_0_PRIMIDLOC__MASK 0x0000ff00 |
5438 | #define A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT 8 |
5439 | static inline uint32_t A6XX_VPC_CNTL_0_PRIMIDLOC(uint32_t val) |
5440 | { |
5441 | return ((val) << A6XX_VPC_CNTL_0_PRIMIDLOC__SHIFT) & A6XX_VPC_CNTL_0_PRIMIDLOC__MASK; |
5442 | } |
5443 | #define A6XX_VPC_CNTL_0_VARYING 0x00010000 |
5444 | #define A6XX_VPC_CNTL_0_VIEWIDLOC__MASK 0xff000000 |
5445 | #define A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT 24 |
5446 | static inline uint32_t A6XX_VPC_CNTL_0_VIEWIDLOC(uint32_t val) |
5447 | { |
5448 | return ((val) << A6XX_VPC_CNTL_0_VIEWIDLOC__SHIFT) & A6XX_VPC_CNTL_0_VIEWIDLOC__MASK; |
5449 | } |
5450 | |
5451 | #define REG_A6XX_VPC_SO_STREAM_CNTL 0x00009305 |
5452 | #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK 0x00000007 |
5453 | #define A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT 0 |
5454 | static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(uint32_t val) |
5455 | { |
5456 | return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM__MASK; |
5457 | } |
5458 | #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK 0x00000038 |
5459 | #define A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT 3 |
5460 | static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(uint32_t val) |
5461 | { |
5462 | return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM__MASK; |
5463 | } |
5464 | #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK 0x000001c0 |
5465 | #define A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT 6 |
5466 | static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(uint32_t val) |
5467 | { |
5468 | return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM__MASK; |
5469 | } |
5470 | #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK 0x00000e00 |
5471 | #define A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT 9 |
5472 | static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(uint32_t val) |
5473 | { |
5474 | return ((val) << A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM__MASK; |
5475 | } |
5476 | #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000 |
5477 | #define A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15 |
5478 | static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) |
5479 | { |
5480 | return ((val) << A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE__MASK; |
5481 | } |
5482 | |
5483 | #define REG_A6XX_VPC_SO_DISABLE 0x00009306 |
5484 | #define A6XX_VPC_SO_DISABLE_DISABLE 0x00000001 |
5485 | |
5486 | #define REG_A7XX_VPC_POLYGON_MODE2 0x00009307 |
5487 | #define A7XX_VPC_POLYGON_MODE2_MODE__MASK 0x00000003 |
5488 | #define A7XX_VPC_POLYGON_MODE2_MODE__SHIFT 0 |
5489 | static inline uint32_t A7XX_VPC_POLYGON_MODE2_MODE(enum a6xx_polygon_mode val) |
5490 | { |
5491 | return ((val) << A7XX_VPC_POLYGON_MODE2_MODE__SHIFT) & A7XX_VPC_POLYGON_MODE2_MODE__MASK; |
5492 | } |
5493 | |
5494 | #define REG_A7XX_VPC_ATTR_BUF_SIZE_GMEM 0x00009308 |
5495 | #define A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK 0xffffffff |
5496 | #define A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT 0 |
5497 | static inline uint32_t A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(uint32_t val) |
5498 | { |
5499 | return ((val) << A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT) & A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK; |
5500 | } |
5501 | |
5502 | #define REG_A7XX_VPC_ATTR_BUF_BASE_GMEM 0x00009309 |
5503 | #define A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK 0xffffffff |
5504 | #define A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT 0 |
5505 | static inline uint32_t A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM(uint32_t val) |
5506 | { |
5507 | return ((val) << A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT) & A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK; |
5508 | } |
5509 | |
5510 | #define REG_A7XX_PC_ATTR_BUF_SIZE_GMEM 0x00009b09 |
5511 | #define A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK 0xffffffff |
5512 | #define A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT 0 |
5513 | static inline uint32_t A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(uint32_t val) |
5514 | { |
5515 | return ((val) << A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT) & A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK; |
5516 | } |
5517 | |
5518 | #define REG_A6XX_VPC_DBG_ECO_CNTL 0x00009600 |
5519 | |
5520 | #define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601 |
5521 | |
5522 | #define REG_A6XX_VPC_UNKNOWN_9602 0x00009602 |
5523 | |
5524 | #define REG_A6XX_VPC_UNKNOWN_9603 0x00009603 |
5525 | |
5526 | #define REG_A6XX_VPC_PERFCTR_VPC_SEL(i0) (0x00009604 + 0x1*(i0)) |
5527 | |
5528 | #define REG_A7XX_VPC_PERFCTR_VPC_SEL(i0) (0x0000960b + 0x1*(i0)) |
5529 | |
5530 | #define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800 |
5531 | |
5532 | #define REG_A6XX_PC_HS_INPUT_SIZE 0x00009801 |
5533 | #define A6XX_PC_HS_INPUT_SIZE_SIZE__MASK 0x000007ff |
5534 | #define A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT 0 |
5535 | static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val) |
5536 | { |
5537 | return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK; |
5538 | } |
5539 | #define A6XX_PC_HS_INPUT_SIZE_UNK13 0x00002000 |
5540 | |
5541 | #define REG_A6XX_PC_TESS_CNTL 0x00009802 |
5542 | #define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003 |
5543 | #define A6XX_PC_TESS_CNTL_SPACING__SHIFT 0 |
5544 | static inline uint32_t A6XX_PC_TESS_CNTL_SPACING(enum a6xx_tess_spacing val) |
5545 | { |
5546 | return ((val) << A6XX_PC_TESS_CNTL_SPACING__SHIFT) & A6XX_PC_TESS_CNTL_SPACING__MASK; |
5547 | } |
5548 | #define A6XX_PC_TESS_CNTL_OUTPUT__MASK 0x0000000c |
5549 | #define A6XX_PC_TESS_CNTL_OUTPUT__SHIFT 2 |
5550 | static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val) |
5551 | { |
5552 | return ((val) << A6XX_PC_TESS_CNTL_OUTPUT__SHIFT) & A6XX_PC_TESS_CNTL_OUTPUT__MASK; |
5553 | } |
5554 | |
5555 | #define REG_A6XX_PC_RESTART_INDEX 0x00009803 |
5556 | |
5557 | #define REG_A6XX_PC_MODE_CNTL 0x00009804 |
5558 | |
5559 | #define REG_A6XX_PC_POWER_CNTL 0x00009805 |
5560 | |
5561 | #define REG_A6XX_PC_PS_CNTL 0x00009806 |
5562 | #define A6XX_PC_PS_CNTL_PRIMITIVEIDEN 0x00000001 |
5563 | |
5564 | #define REG_A6XX_PC_SO_STREAM_CNTL 0x00009808 |
5565 | #define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000 |
5566 | #define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT 15 |
5567 | static inline uint32_t A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) |
5568 | { |
5569 | return ((val) << A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__SHIFT) & A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK; |
5570 | } |
5571 | |
5572 | #define REG_A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL 0x0000980a |
5573 | #define A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001 |
5574 | |
5575 | #define REG_A6XX_PC_DRAW_CMD 0x00009840 |
5576 | #define A6XX_PC_DRAW_CMD_STATE_ID__MASK 0x000000ff |
5577 | #define A6XX_PC_DRAW_CMD_STATE_ID__SHIFT 0 |
5578 | static inline uint32_t A6XX_PC_DRAW_CMD_STATE_ID(uint32_t val) |
5579 | { |
5580 | return ((val) << A6XX_PC_DRAW_CMD_STATE_ID__SHIFT) & A6XX_PC_DRAW_CMD_STATE_ID__MASK; |
5581 | } |
5582 | |
5583 | #define REG_A6XX_PC_DISPATCH_CMD 0x00009841 |
5584 | #define A6XX_PC_DISPATCH_CMD_STATE_ID__MASK 0x000000ff |
5585 | #define A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT 0 |
5586 | static inline uint32_t A6XX_PC_DISPATCH_CMD_STATE_ID(uint32_t val) |
5587 | { |
5588 | return ((val) << A6XX_PC_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_PC_DISPATCH_CMD_STATE_ID__MASK; |
5589 | } |
5590 | |
5591 | #define REG_A6XX_PC_EVENT_CMD 0x00009842 |
5592 | #define A6XX_PC_EVENT_CMD_STATE_ID__MASK 0x00ff0000 |
5593 | #define A6XX_PC_EVENT_CMD_STATE_ID__SHIFT 16 |
5594 | static inline uint32_t A6XX_PC_EVENT_CMD_STATE_ID(uint32_t val) |
5595 | { |
5596 | return ((val) << A6XX_PC_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_EVENT_CMD_STATE_ID__MASK; |
5597 | } |
5598 | #define A6XX_PC_EVENT_CMD_EVENT__MASK 0x0000007f |
5599 | #define A6XX_PC_EVENT_CMD_EVENT__SHIFT 0 |
5600 | static inline uint32_t A6XX_PC_EVENT_CMD_EVENT(enum vgt_event_type val) |
5601 | { |
5602 | return ((val) << A6XX_PC_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_EVENT_CMD_EVENT__MASK; |
5603 | } |
5604 | |
5605 | #define REG_A6XX_PC_MARKER 0x00009880 |
5606 | |
5607 | #define REG_A6XX_PC_POLYGON_MODE 0x00009981 |
5608 | #define A6XX_PC_POLYGON_MODE_MODE__MASK 0x00000003 |
5609 | #define A6XX_PC_POLYGON_MODE_MODE__SHIFT 0 |
5610 | static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) |
5611 | { |
5612 | return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK; |
5613 | } |
5614 | |
5615 | #define REG_A7XX_PC_POLYGON_MODE 0x00009809 |
5616 | #define A7XX_PC_POLYGON_MODE_MODE__MASK 0x00000003 |
5617 | #define A7XX_PC_POLYGON_MODE_MODE__SHIFT 0 |
5618 | static inline uint32_t A7XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) |
5619 | { |
5620 | return ((val) << A7XX_PC_POLYGON_MODE_MODE__SHIFT) & A7XX_PC_POLYGON_MODE_MODE__MASK; |
5621 | } |
5622 | |
5623 | #define REG_A6XX_PC_RASTER_CNTL 0x00009980 |
5624 | #define A6XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003 |
5625 | #define A6XX_PC_RASTER_CNTL_STREAM__SHIFT 0 |
5626 | static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val) |
5627 | { |
5628 | return ((val) << A6XX_PC_RASTER_CNTL_STREAM__SHIFT) & A6XX_PC_RASTER_CNTL_STREAM__MASK; |
5629 | } |
5630 | #define A6XX_PC_RASTER_CNTL_DISCARD 0x00000004 |
5631 | |
5632 | #define REG_A7XX_PC_RASTER_CNTL 0x00009107 |
5633 | #define A7XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003 |
5634 | #define A7XX_PC_RASTER_CNTL_STREAM__SHIFT 0 |
5635 | static inline uint32_t A7XX_PC_RASTER_CNTL_STREAM(uint32_t val) |
5636 | { |
5637 | return ((val) << A7XX_PC_RASTER_CNTL_STREAM__SHIFT) & A7XX_PC_RASTER_CNTL_STREAM__MASK; |
5638 | } |
5639 | #define A7XX_PC_RASTER_CNTL_DISCARD 0x00000004 |
5640 | |
5641 | #define REG_A7XX_PC_RASTER_CNTL_V2 0x00009317 |
5642 | #define A7XX_PC_RASTER_CNTL_V2_STREAM__MASK 0x00000003 |
5643 | #define A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT 0 |
5644 | static inline uint32_t A7XX_PC_RASTER_CNTL_V2_STREAM(uint32_t val) |
5645 | { |
5646 | return ((val) << A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT) & A7XX_PC_RASTER_CNTL_V2_STREAM__MASK; |
5647 | } |
5648 | #define A7XX_PC_RASTER_CNTL_V2_DISCARD 0x00000004 |
5649 | |
5650 | #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00 |
5651 | #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 |
5652 | #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002 |
5653 | #define A6XX_PC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING 0x00000004 |
5654 | #define A6XX_PC_PRIMITIVE_CNTL_0_UNK3 0x00000008 |
5655 | |
5656 | #define REG_A6XX_PC_VS_OUT_CNTL 0x00009b01 |
5657 | #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff |
5658 | #define A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 |
5659 | static inline uint32_t A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) |
5660 | { |
5661 | return ((val) << A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC__MASK; |
5662 | } |
5663 | #define A6XX_PC_VS_OUT_CNTL_PSIZE 0x00000100 |
5664 | #define A6XX_PC_VS_OUT_CNTL_LAYER 0x00000200 |
5665 | #define A6XX_PC_VS_OUT_CNTL_VIEW 0x00000400 |
5666 | #define A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID 0x00000800 |
5667 | #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 |
5668 | #define A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT 16 |
5669 | static inline uint32_t A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val) |
5670 | { |
5671 | return ((val) << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK; |
5672 | } |
5673 | #define A6XX_PC_VS_OUT_CNTL_SHADINGRATE 0x01000000 |
5674 | |
5675 | #define REG_A6XX_PC_GS_OUT_CNTL 0x00009b02 |
5676 | #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff |
5677 | #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 |
5678 | static inline uint32_t A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) |
5679 | { |
5680 | return ((val) << A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK; |
5681 | } |
5682 | #define A6XX_PC_GS_OUT_CNTL_PSIZE 0x00000100 |
5683 | #define A6XX_PC_GS_OUT_CNTL_LAYER 0x00000200 |
5684 | #define A6XX_PC_GS_OUT_CNTL_VIEW 0x00000400 |
5685 | #define A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID 0x00000800 |
5686 | #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 |
5687 | #define A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT 16 |
5688 | static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val) |
5689 | { |
5690 | return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK; |
5691 | } |
5692 | #define A6XX_PC_GS_OUT_CNTL_SHADINGRATE 0x01000000 |
5693 | |
5694 | #define REG_A6XX_PC_HS_OUT_CNTL 0x00009b03 |
5695 | #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff |
5696 | #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 |
5697 | static inline uint32_t A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) |
5698 | { |
5699 | return ((val) << A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK; |
5700 | } |
5701 | #define A6XX_PC_HS_OUT_CNTL_PSIZE 0x00000100 |
5702 | #define A6XX_PC_HS_OUT_CNTL_LAYER 0x00000200 |
5703 | #define A6XX_PC_HS_OUT_CNTL_VIEW 0x00000400 |
5704 | #define A6XX_PC_HS_OUT_CNTL_PRIMITIVE_ID 0x00000800 |
5705 | #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 |
5706 | #define A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT 16 |
5707 | static inline uint32_t A6XX_PC_HS_OUT_CNTL_CLIP_MASK(uint32_t val) |
5708 | { |
5709 | return ((val) << A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK; |
5710 | } |
5711 | #define A6XX_PC_HS_OUT_CNTL_SHADINGRATE 0x01000000 |
5712 | |
5713 | #define REG_A6XX_PC_DS_OUT_CNTL 0x00009b04 |
5714 | #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff |
5715 | #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT 0 |
5716 | static inline uint32_t A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC(uint32_t val) |
5717 | { |
5718 | return ((val) << A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__SHIFT) & A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK; |
5719 | } |
5720 | #define A6XX_PC_DS_OUT_CNTL_PSIZE 0x00000100 |
5721 | #define A6XX_PC_DS_OUT_CNTL_LAYER 0x00000200 |
5722 | #define A6XX_PC_DS_OUT_CNTL_VIEW 0x00000400 |
5723 | #define A6XX_PC_DS_OUT_CNTL_PRIMITIVE_ID 0x00000800 |
5724 | #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK 0x00ff0000 |
5725 | #define A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT 16 |
5726 | static inline uint32_t A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val) |
5727 | { |
5728 | return ((val) << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK; |
5729 | } |
5730 | #define A6XX_PC_DS_OUT_CNTL_SHADINGRATE 0x01000000 |
5731 | |
5732 | #define REG_A6XX_PC_PRIMITIVE_CNTL_5 0x00009b05 |
5733 | #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff |
5734 | #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0 |
5735 | static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val) |
5736 | { |
5737 | return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK; |
5738 | } |
5739 | #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00 |
5740 | #define A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10 |
5741 | static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val) |
5742 | { |
5743 | return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK; |
5744 | } |
5745 | #define A6XX_PC_PRIMITIVE_CNTL_5_LINELENGTHEN 0x00008000 |
5746 | #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000 |
5747 | #define A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16 |
5748 | static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val) |
5749 | { |
5750 | return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK; |
5751 | } |
5752 | #define A6XX_PC_PRIMITIVE_CNTL_5_UNK18 0x00040000 |
5753 | |
5754 | #define REG_A6XX_PC_PRIMITIVE_CNTL_6 0x00009b06 |
5755 | #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK 0x000007ff |
5756 | #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT 0 |
5757 | static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(uint32_t val) |
5758 | { |
5759 | return ((val) << A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK; |
5760 | } |
5761 | |
5762 | #define REG_A6XX_PC_MULTIVIEW_CNTL 0x00009b07 |
5763 | #define A6XX_PC_MULTIVIEW_CNTL_ENABLE 0x00000001 |
5764 | #define A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 |
5765 | #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c |
5766 | #define A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT 2 |
5767 | static inline uint32_t A6XX_PC_MULTIVIEW_CNTL_VIEWS(uint32_t val) |
5768 | { |
5769 | return ((val) << A6XX_PC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_PC_MULTIVIEW_CNTL_VIEWS__MASK; |
5770 | } |
5771 | |
5772 | #define REG_A6XX_PC_MULTIVIEW_MASK 0x00009b08 |
5773 | |
5774 | #define REG_A6XX_PC_2D_EVENT_CMD 0x00009c00 |
5775 | #define A6XX_PC_2D_EVENT_CMD_EVENT__MASK 0x0000007f |
5776 | #define A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT 0 |
5777 | static inline uint32_t A6XX_PC_2D_EVENT_CMD_EVENT(enum vgt_event_type val) |
5778 | { |
5779 | return ((val) << A6XX_PC_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_PC_2D_EVENT_CMD_EVENT__MASK; |
5780 | } |
5781 | #define A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00 |
5782 | #define A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT 8 |
5783 | static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val) |
5784 | { |
5785 | return ((val) << A6XX_PC_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_PC_2D_EVENT_CMD_STATE_ID__MASK; |
5786 | } |
5787 | |
5788 | #define REG_A6XX_PC_DBG_ECO_CNTL 0x00009e00 |
5789 | |
5790 | #define REG_A6XX_PC_ADDR_MODE_CNTL 0x00009e01 |
5791 | |
5792 | #define REG_A6XX_PC_DRAW_INDX_BASE 0x00009e04 |
5793 | |
5794 | #define REG_A6XX_PC_DRAW_FIRST_INDX 0x00009e06 |
5795 | |
5796 | #define REG_A6XX_PC_DRAW_MAX_INDICES 0x00009e07 |
5797 | |
5798 | #define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08 |
5799 | |
5800 | #define REG_A7XX_PC_TESSFACTOR_ADDR 0x00009810 |
5801 | |
5802 | #define REG_A6XX_PC_DRAW_INITIATOR 0x00009e0b |
5803 | #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f |
5804 | #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 |
5805 | static inline uint32_t A6XX_PC_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) |
5806 | { |
5807 | return ((val) << A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK; |
5808 | } |
5809 | #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 |
5810 | #define A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 |
5811 | static inline uint32_t A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) |
5812 | { |
5813 | return ((val) << A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A6XX_PC_DRAW_INITIATOR_SOURCE_SELECT__MASK; |
5814 | } |
5815 | #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK 0x00000300 |
5816 | #define A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT 8 |
5817 | static inline uint32_t A6XX_PC_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) |
5818 | { |
5819 | return ((val) << A6XX_PC_DRAW_INITIATOR_VIS_CULL__SHIFT) & A6XX_PC_DRAW_INITIATOR_VIS_CULL__MASK; |
5820 | } |
5821 | #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000c00 |
5822 | #define A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT 10 |
5823 | static inline uint32_t A6XX_PC_DRAW_INITIATOR_INDEX_SIZE(enum a4xx_index_size val) |
5824 | { |
5825 | return ((val) << A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A6XX_PC_DRAW_INITIATOR_INDEX_SIZE__MASK; |
5826 | } |
5827 | #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK 0x00003000 |
5828 | #define A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT 12 |
5829 | static inline uint32_t A6XX_PC_DRAW_INITIATOR_PATCH_TYPE(enum a6xx_patch_type val) |
5830 | { |
5831 | return ((val) << A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__SHIFT) & A6XX_PC_DRAW_INITIATOR_PATCH_TYPE__MASK; |
5832 | } |
5833 | #define A6XX_PC_DRAW_INITIATOR_GS_ENABLE 0x00010000 |
5834 | #define A6XX_PC_DRAW_INITIATOR_TESS_ENABLE 0x00020000 |
5835 | |
5836 | #define REG_A6XX_PC_DRAW_NUM_INSTANCES 0x00009e0c |
5837 | |
5838 | #define REG_A6XX_PC_DRAW_NUM_INDICES 0x00009e0d |
5839 | |
5840 | #define REG_A6XX_PC_VSTREAM_CONTROL 0x00009e11 |
5841 | #define A6XX_PC_VSTREAM_CONTROL_UNK0__MASK 0x0000ffff |
5842 | #define A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT 0 |
5843 | static inline uint32_t A6XX_PC_VSTREAM_CONTROL_UNK0(uint32_t val) |
5844 | { |
5845 | return ((val) << A6XX_PC_VSTREAM_CONTROL_UNK0__SHIFT) & A6XX_PC_VSTREAM_CONTROL_UNK0__MASK; |
5846 | } |
5847 | #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK 0x003f0000 |
5848 | #define A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT 16 |
5849 | static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_SIZE(uint32_t val) |
5850 | { |
5851 | return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_SIZE__MASK; |
5852 | } |
5853 | #define A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK 0x07c00000 |
5854 | #define A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT 22 |
5855 | static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val) |
5856 | { |
5857 | return ((val) << A6XX_PC_VSTREAM_CONTROL_VSC_N__SHIFT) & A6XX_PC_VSTREAM_CONTROL_VSC_N__MASK; |
5858 | } |
5859 | |
5860 | #define REG_A6XX_PC_BIN_PRIM_STRM 0x00009e12 |
5861 | |
5862 | #define REG_A6XX_PC_BIN_DRAW_STRM 0x00009e14 |
5863 | |
5864 | #define REG_A6XX_PC_VISIBILITY_OVERRIDE 0x00009e1c |
5865 | #define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE 0x00000001 |
5866 | |
5867 | #define REG_A7XX_PC_UNKNOWN_9E24 0x00009e24 |
5868 | |
5869 | #define REG_A6XX_PC_PERFCTR_PC_SEL(i0) (0x00009e34 + 0x1*(i0)) |
5870 | |
5871 | #define REG_A7XX_PC_PERFCTR_PC_SEL(i0) (0x00009e42 + 0x1*(i0)) |
5872 | |
5873 | #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72 |
5874 | |
5875 | #define REG_A6XX_VFD_CONTROL_0 0x0000a000 |
5876 | #define A6XX_VFD_CONTROL_0_FETCH_CNT__MASK 0x0000003f |
5877 | #define A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT 0 |
5878 | static inline uint32_t A6XX_VFD_CONTROL_0_FETCH_CNT(uint32_t val) |
5879 | { |
5880 | return ((val) << A6XX_VFD_CONTROL_0_FETCH_CNT__SHIFT) & A6XX_VFD_CONTROL_0_FETCH_CNT__MASK; |
5881 | } |
5882 | #define A6XX_VFD_CONTROL_0_DECODE_CNT__MASK 0x00003f00 |
5883 | #define A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT 8 |
5884 | static inline uint32_t A6XX_VFD_CONTROL_0_DECODE_CNT(uint32_t val) |
5885 | { |
5886 | return ((val) << A6XX_VFD_CONTROL_0_DECODE_CNT__SHIFT) & A6XX_VFD_CONTROL_0_DECODE_CNT__MASK; |
5887 | } |
5888 | |
5889 | #define REG_A6XX_VFD_CONTROL_1 0x0000a001 |
5890 | #define A6XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff |
5891 | #define A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0 |
5892 | static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VTX(uint32_t val) |
5893 | { |
5894 | return ((val) << A6XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VTX__MASK; |
5895 | } |
5896 | #define A6XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00 |
5897 | #define A6XX_VFD_CONTROL_1_REGID4INST__SHIFT 8 |
5898 | static inline uint32_t A6XX_VFD_CONTROL_1_REGID4INST(uint32_t val) |
5899 | { |
5900 | return ((val) << A6XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A6XX_VFD_CONTROL_1_REGID4INST__MASK; |
5901 | } |
5902 | #define A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK 0x00ff0000 |
5903 | #define A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT 16 |
5904 | static inline uint32_t A6XX_VFD_CONTROL_1_REGID4PRIMID(uint32_t val) |
5905 | { |
5906 | return ((val) << A6XX_VFD_CONTROL_1_REGID4PRIMID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4PRIMID__MASK; |
5907 | } |
5908 | #define A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK 0xff000000 |
5909 | #define A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT 24 |
5910 | static inline uint32_t A6XX_VFD_CONTROL_1_REGID4VIEWID(uint32_t val) |
5911 | { |
5912 | return ((val) << A6XX_VFD_CONTROL_1_REGID4VIEWID__SHIFT) & A6XX_VFD_CONTROL_1_REGID4VIEWID__MASK; |
5913 | } |
5914 | |
5915 | #define REG_A6XX_VFD_CONTROL_2 0x0000a002 |
5916 | #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK 0x000000ff |
5917 | #define A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT 0 |
5918 | static inline uint32_t A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(uint32_t val) |
5919 | { |
5920 | return ((val) << A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID__MASK; |
5921 | } |
5922 | #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK 0x0000ff00 |
5923 | #define A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT 8 |
5924 | static inline uint32_t A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(uint32_t val) |
5925 | { |
5926 | return ((val) << A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__SHIFT) & A6XX_VFD_CONTROL_2_REGID_INVOCATIONID__MASK; |
5927 | } |
5928 | |
5929 | #define REG_A6XX_VFD_CONTROL_3 0x0000a003 |
5930 | #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK 0x000000ff |
5931 | #define A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT 0 |
5932 | static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSPRIMID(uint32_t val) |
5933 | { |
5934 | return ((val) << A6XX_VFD_CONTROL_3_REGID_DSPRIMID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSPRIMID__MASK; |
5935 | } |
5936 | #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK 0x0000ff00 |
5937 | #define A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT 8 |
5938 | static inline uint32_t A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(uint32_t val) |
5939 | { |
5940 | return ((val) << A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__SHIFT) & A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID__MASK; |
5941 | } |
5942 | #define A6XX_VFD_CONTROL_3_REGID_TESSX__MASK 0x00ff0000 |
5943 | #define A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT 16 |
5944 | static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSX(uint32_t val) |
5945 | { |
5946 | return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSX__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSX__MASK; |
5947 | } |
5948 | #define A6XX_VFD_CONTROL_3_REGID_TESSY__MASK 0xff000000 |
5949 | #define A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT 24 |
5950 | static inline uint32_t A6XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) |
5951 | { |
5952 | return ((val) << A6XX_VFD_CONTROL_3_REGID_TESSY__SHIFT) & A6XX_VFD_CONTROL_3_REGID_TESSY__MASK; |
5953 | } |
5954 | |
5955 | #define REG_A6XX_VFD_CONTROL_4 0x0000a004 |
5956 | #define A6XX_VFD_CONTROL_4_UNK0__MASK 0x000000ff |
5957 | #define A6XX_VFD_CONTROL_4_UNK0__SHIFT 0 |
5958 | static inline uint32_t A6XX_VFD_CONTROL_4_UNK0(uint32_t val) |
5959 | { |
5960 | return ((val) << A6XX_VFD_CONTROL_4_UNK0__SHIFT) & A6XX_VFD_CONTROL_4_UNK0__MASK; |
5961 | } |
5962 | |
5963 | #define REG_A6XX_VFD_CONTROL_5 0x0000a005 |
5964 | #define 0x000000ff |
5965 | #define 0 |
5966 | static inline uint32_t (uint32_t val) |
5967 | { |
5968 | return ((val) << A6XX_VFD_CONTROL_5_REGID_GSHEADER__SHIFT) & A6XX_VFD_CONTROL_5_REGID_GSHEADER__MASK; |
5969 | } |
5970 | #define A6XX_VFD_CONTROL_5_UNK8__MASK 0x0000ff00 |
5971 | #define A6XX_VFD_CONTROL_5_UNK8__SHIFT 8 |
5972 | static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val) |
5973 | { |
5974 | return ((val) << A6XX_VFD_CONTROL_5_UNK8__SHIFT) & A6XX_VFD_CONTROL_5_UNK8__MASK; |
5975 | } |
5976 | |
5977 | #define REG_A6XX_VFD_CONTROL_6 0x0000a006 |
5978 | #define A6XX_VFD_CONTROL_6_PRIMID4PSEN 0x00000001 |
5979 | |
5980 | #define REG_A6XX_VFD_MODE_CNTL 0x0000a007 |
5981 | #define A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK 0x00000007 |
5982 | #define A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT 0 |
5983 | static inline uint32_t A6XX_VFD_MODE_CNTL_RENDER_MODE(enum a6xx_render_mode val) |
5984 | { |
5985 | return ((val) << A6XX_VFD_MODE_CNTL_RENDER_MODE__SHIFT) & A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK; |
5986 | } |
5987 | |
5988 | #define REG_A6XX_VFD_MULTIVIEW_CNTL 0x0000a008 |
5989 | #define A6XX_VFD_MULTIVIEW_CNTL_ENABLE 0x00000001 |
5990 | #define A6XX_VFD_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 |
5991 | #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c |
5992 | #define A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT 2 |
5993 | static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val) |
5994 | { |
5995 | return ((val) << A6XX_VFD_MULTIVIEW_CNTL_VIEWS__SHIFT) & A6XX_VFD_MULTIVIEW_CNTL_VIEWS__MASK; |
5996 | } |
5997 | |
5998 | #define REG_A6XX_VFD_ADD_OFFSET 0x0000a009 |
5999 | #define A6XX_VFD_ADD_OFFSET_VERTEX 0x00000001 |
6000 | #define A6XX_VFD_ADD_OFFSET_INSTANCE 0x00000002 |
6001 | |
6002 | #define REG_A6XX_VFD_INDEX_OFFSET 0x0000a00e |
6003 | |
6004 | #define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f |
6005 | |
6006 | #define REG_A6XX_VFD_FETCH(i0) (0x0000a010 + 0x4*(i0)) |
6007 | |
6008 | static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; } |
6009 | |
6010 | static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; } |
6011 | |
6012 | static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; } |
6013 | |
6014 | #define REG_A6XX_VFD_DECODE(i0) (0x0000a090 + 0x2*(i0)) |
6015 | |
6016 | static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; } |
6017 | #define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f |
6018 | #define A6XX_VFD_DECODE_INSTR_IDX__SHIFT 0 |
6019 | static inline uint32_t A6XX_VFD_DECODE_INSTR_IDX(uint32_t val) |
6020 | { |
6021 | return ((val) << A6XX_VFD_DECODE_INSTR_IDX__SHIFT) & A6XX_VFD_DECODE_INSTR_IDX__MASK; |
6022 | } |
6023 | #define A6XX_VFD_DECODE_INSTR_OFFSET__MASK 0x0001ffe0 |
6024 | #define A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT 5 |
6025 | static inline uint32_t A6XX_VFD_DECODE_INSTR_OFFSET(uint32_t val) |
6026 | { |
6027 | return ((val) << A6XX_VFD_DECODE_INSTR_OFFSET__SHIFT) & A6XX_VFD_DECODE_INSTR_OFFSET__MASK; |
6028 | } |
6029 | #define A6XX_VFD_DECODE_INSTR_INSTANCED 0x00020000 |
6030 | #define A6XX_VFD_DECODE_INSTR_FORMAT__MASK 0x0ff00000 |
6031 | #define A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20 |
6032 | static inline uint32_t A6XX_VFD_DECODE_INSTR_FORMAT(enum a6xx_format val) |
6033 | { |
6034 | return ((val) << A6XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A6XX_VFD_DECODE_INSTR_FORMAT__MASK; |
6035 | } |
6036 | #define A6XX_VFD_DECODE_INSTR_SWAP__MASK 0x30000000 |
6037 | #define A6XX_VFD_DECODE_INSTR_SWAP__SHIFT 28 |
6038 | static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) |
6039 | { |
6040 | return ((val) << A6XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A6XX_VFD_DECODE_INSTR_SWAP__MASK; |
6041 | } |
6042 | #define A6XX_VFD_DECODE_INSTR_UNK30 0x40000000 |
6043 | #define A6XX_VFD_DECODE_INSTR_FLOAT 0x80000000 |
6044 | |
6045 | static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; } |
6046 | |
6047 | #define REG_A6XX_VFD_DEST_CNTL(i0) (0x0000a0d0 + 0x1*(i0)) |
6048 | |
6049 | static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } |
6050 | #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f |
6051 | #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT 0 |
6052 | static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(uint32_t val) |
6053 | { |
6054 | return ((val) << A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK; |
6055 | } |
6056 | #define A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK 0x00000ff0 |
6057 | #define A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT 4 |
6058 | static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) |
6059 | { |
6060 | return ((val) << A6XX_VFD_DEST_CNTL_INSTR_REGID__SHIFT) & A6XX_VFD_DEST_CNTL_INSTR_REGID__MASK; |
6061 | } |
6062 | |
6063 | #define REG_A6XX_VFD_POWER_CNTL 0x0000a0f8 |
6064 | |
6065 | #define REG_A7XX_VFD_UNKNOWN_A600 0x0000a600 |
6066 | |
6067 | #define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601 |
6068 | |
6069 | #define REG_A6XX_VFD_PERFCTR_VFD_SEL(i0) (0x0000a610 + 0x1*(i0)) |
6070 | |
6071 | #define REG_A7XX_VFD_PERFCTR_VFD_SEL(i0) (0x0000a610 + 0x1*(i0)) |
6072 | |
6073 | #define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800 |
6074 | #define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 |
6075 | #define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 |
6076 | static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) |
6077 | { |
6078 | return ((val) << A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK; |
6079 | } |
6080 | #define 0x0000007e |
6081 | #define 1 |
6082 | static inline uint32_t (uint32_t val) |
6083 | { |
6084 | return ((val) << A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK; |
6085 | } |
6086 | #define 0x00001f80 |
6087 | #define 7 |
6088 | static inline uint32_t (uint32_t val) |
6089 | { |
6090 | return ((val) << A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK; |
6091 | } |
6092 | #define A6XX_SP_VS_CTRL_REG0_UNK13 0x00002000 |
6093 | #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 |
6094 | #define A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 14 |
6095 | static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) |
6096 | { |
6097 | return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; |
6098 | } |
6099 | #define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000 |
6100 | #define A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE 0x00200000 |
6101 | |
6102 | #define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801 |
6103 | |
6104 | #define REG_A6XX_SP_VS_PRIMITIVE_CNTL 0x0000a802 |
6105 | #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f |
6106 | #define A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT 0 |
6107 | static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_OUT(uint32_t val) |
6108 | { |
6109 | return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_OUT__MASK; |
6110 | } |
6111 | #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 |
6112 | #define A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 |
6113 | static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) |
6114 | { |
6115 | return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; |
6116 | } |
6117 | |
6118 | #define REG_A6XX_SP_VS_OUT(i0) (0x0000a803 + 0x1*(i0)) |
6119 | |
6120 | static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; } |
6121 | #define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff |
6122 | #define A6XX_SP_VS_OUT_REG_A_REGID__SHIFT 0 |
6123 | static inline uint32_t A6XX_SP_VS_OUT_REG_A_REGID(uint32_t val) |
6124 | { |
6125 | return ((val) << A6XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_A_REGID__MASK; |
6126 | } |
6127 | #define A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00000f00 |
6128 | #define A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 8 |
6129 | static inline uint32_t A6XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val) |
6130 | { |
6131 | return ((val) << A6XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_A_COMPMASK__MASK; |
6132 | } |
6133 | #define A6XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000 |
6134 | #define A6XX_SP_VS_OUT_REG_B_REGID__SHIFT 16 |
6135 | static inline uint32_t A6XX_SP_VS_OUT_REG_B_REGID(uint32_t val) |
6136 | { |
6137 | return ((val) << A6XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_VS_OUT_REG_B_REGID__MASK; |
6138 | } |
6139 | #define A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x0f000000 |
6140 | #define A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 24 |
6141 | static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) |
6142 | { |
6143 | return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK; |
6144 | } |
6145 | |
6146 | #define REG_A6XX_SP_VS_VPC_DST(i0) (0x0000a813 + 0x1*(i0)) |
6147 | |
6148 | static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; } |
6149 | #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff |
6150 | #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0 |
6151 | static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val) |
6152 | { |
6153 | return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK; |
6154 | } |
6155 | #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 |
6156 | #define A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8 |
6157 | static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val) |
6158 | { |
6159 | return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK; |
6160 | } |
6161 | #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 |
6162 | #define A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16 |
6163 | static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val) |
6164 | { |
6165 | return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK; |
6166 | } |
6167 | #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 |
6168 | #define A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24 |
6169 | static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) |
6170 | { |
6171 | return ((val) << A6XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK; |
6172 | } |
6173 | |
6174 | #define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET 0x0000a81b |
6175 | |
6176 | #define REG_A6XX_SP_VS_OBJ_START 0x0000a81c |
6177 | |
6178 | #define REG_A6XX_SP_VS_PVT_MEM_PARAM 0x0000a81e |
6179 | #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff |
6180 | #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 |
6181 | static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) |
6182 | { |
6183 | assert(!(val & 0x1ff)); |
6184 | return (((val >> 9)) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; |
6185 | } |
6186 | #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 |
6187 | #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 |
6188 | static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) |
6189 | { |
6190 | return ((val) << A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; |
6191 | } |
6192 | |
6193 | #define REG_A6XX_SP_VS_PVT_MEM_ADDR 0x0000a81f |
6194 | |
6195 | #define REG_A6XX_SP_VS_PVT_MEM_SIZE 0x0000a821 |
6196 | #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff |
6197 | #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 |
6198 | static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) |
6199 | { |
6200 | assert(!(val & 0xfff)); |
6201 | return (((val >> 12)) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; |
6202 | } |
6203 | #define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 |
6204 | |
6205 | #define REG_A6XX_SP_VS_TEX_COUNT 0x0000a822 |
6206 | |
6207 | #define REG_A6XX_SP_VS_CONFIG 0x0000a823 |
6208 | #define A6XX_SP_VS_CONFIG_BINDLESS_TEX 0x00000001 |
6209 | #define A6XX_SP_VS_CONFIG_BINDLESS_SAMP 0x00000002 |
6210 | #define A6XX_SP_VS_CONFIG_BINDLESS_IBO 0x00000004 |
6211 | #define A6XX_SP_VS_CONFIG_BINDLESS_UBO 0x00000008 |
6212 | #define A6XX_SP_VS_CONFIG_ENABLED 0x00000100 |
6213 | #define A6XX_SP_VS_CONFIG_NTEX__MASK 0x0001fe00 |
6214 | #define A6XX_SP_VS_CONFIG_NTEX__SHIFT 9 |
6215 | static inline uint32_t A6XX_SP_VS_CONFIG_NTEX(uint32_t val) |
6216 | { |
6217 | return ((val) << A6XX_SP_VS_CONFIG_NTEX__SHIFT) & A6XX_SP_VS_CONFIG_NTEX__MASK; |
6218 | } |
6219 | #define A6XX_SP_VS_CONFIG_NSAMP__MASK 0x003e0000 |
6220 | #define A6XX_SP_VS_CONFIG_NSAMP__SHIFT 17 |
6221 | static inline uint32_t A6XX_SP_VS_CONFIG_NSAMP(uint32_t val) |
6222 | { |
6223 | return ((val) << A6XX_SP_VS_CONFIG_NSAMP__SHIFT) & A6XX_SP_VS_CONFIG_NSAMP__MASK; |
6224 | } |
6225 | #define A6XX_SP_VS_CONFIG_NIBO__MASK 0x1fc00000 |
6226 | #define A6XX_SP_VS_CONFIG_NIBO__SHIFT 22 |
6227 | static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val) |
6228 | { |
6229 | return ((val) << A6XX_SP_VS_CONFIG_NIBO__SHIFT) & A6XX_SP_VS_CONFIG_NIBO__MASK; |
6230 | } |
6231 | |
6232 | #define REG_A6XX_SP_VS_INSTRLEN 0x0000a824 |
6233 | |
6234 | #define REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET 0x0000a825 |
6235 | #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff |
6236 | #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 |
6237 | static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) |
6238 | { |
6239 | assert(!(val & 0x7ff)); |
6240 | return (((val >> 11)) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; |
6241 | } |
6242 | |
6243 | #define REG_A7XX_SP_VS_VGPR_CONFIG 0x0000a82d |
6244 | |
6245 | #define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830 |
6246 | #define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK 0x00000001 |
6247 | #define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT 0 |
6248 | static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) |
6249 | { |
6250 | return ((val) << A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK; |
6251 | } |
6252 | #define 0x0000007e |
6253 | #define 1 |
6254 | static inline uint32_t (uint32_t val) |
6255 | { |
6256 | return ((val) << A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT__MASK; |
6257 | } |
6258 | #define 0x00001f80 |
6259 | #define 7 |
6260 | static inline uint32_t (uint32_t val) |
6261 | { |
6262 | return ((val) << A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT__MASK; |
6263 | } |
6264 | #define A6XX_SP_HS_CTRL_REG0_UNK13 0x00002000 |
6265 | #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 |
6266 | #define A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT 14 |
6267 | static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) |
6268 | { |
6269 | return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK; |
6270 | } |
6271 | #define A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE 0x00100000 |
6272 | |
6273 | #define REG_A6XX_SP_HS_WAVE_INPUT_SIZE 0x0000a831 |
6274 | |
6275 | #define REG_A6XX_SP_HS_BRANCH_COND 0x0000a832 |
6276 | |
6277 | #define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET 0x0000a833 |
6278 | |
6279 | #define REG_A6XX_SP_HS_OBJ_START 0x0000a834 |
6280 | |
6281 | #define REG_A6XX_SP_HS_PVT_MEM_PARAM 0x0000a836 |
6282 | #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff |
6283 | #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 |
6284 | static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) |
6285 | { |
6286 | assert(!(val & 0x1ff)); |
6287 | return (((val >> 9)) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; |
6288 | } |
6289 | #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 |
6290 | #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 |
6291 | static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) |
6292 | { |
6293 | return ((val) << A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; |
6294 | } |
6295 | |
6296 | #define REG_A6XX_SP_HS_PVT_MEM_ADDR 0x0000a837 |
6297 | |
6298 | #define REG_A6XX_SP_HS_PVT_MEM_SIZE 0x0000a839 |
6299 | #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff |
6300 | #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 |
6301 | static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) |
6302 | { |
6303 | assert(!(val & 0xfff)); |
6304 | return (((val >> 12)) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; |
6305 | } |
6306 | #define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 |
6307 | |
6308 | #define REG_A6XX_SP_HS_TEX_COUNT 0x0000a83a |
6309 | |
6310 | #define REG_A6XX_SP_HS_CONFIG 0x0000a83b |
6311 | #define A6XX_SP_HS_CONFIG_BINDLESS_TEX 0x00000001 |
6312 | #define A6XX_SP_HS_CONFIG_BINDLESS_SAMP 0x00000002 |
6313 | #define A6XX_SP_HS_CONFIG_BINDLESS_IBO 0x00000004 |
6314 | #define A6XX_SP_HS_CONFIG_BINDLESS_UBO 0x00000008 |
6315 | #define A6XX_SP_HS_CONFIG_ENABLED 0x00000100 |
6316 | #define A6XX_SP_HS_CONFIG_NTEX__MASK 0x0001fe00 |
6317 | #define A6XX_SP_HS_CONFIG_NTEX__SHIFT 9 |
6318 | static inline uint32_t A6XX_SP_HS_CONFIG_NTEX(uint32_t val) |
6319 | { |
6320 | return ((val) << A6XX_SP_HS_CONFIG_NTEX__SHIFT) & A6XX_SP_HS_CONFIG_NTEX__MASK; |
6321 | } |
6322 | #define A6XX_SP_HS_CONFIG_NSAMP__MASK 0x003e0000 |
6323 | #define A6XX_SP_HS_CONFIG_NSAMP__SHIFT 17 |
6324 | static inline uint32_t A6XX_SP_HS_CONFIG_NSAMP(uint32_t val) |
6325 | { |
6326 | return ((val) << A6XX_SP_HS_CONFIG_NSAMP__SHIFT) & A6XX_SP_HS_CONFIG_NSAMP__MASK; |
6327 | } |
6328 | #define A6XX_SP_HS_CONFIG_NIBO__MASK 0x1fc00000 |
6329 | #define A6XX_SP_HS_CONFIG_NIBO__SHIFT 22 |
6330 | static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val) |
6331 | { |
6332 | return ((val) << A6XX_SP_HS_CONFIG_NIBO__SHIFT) & A6XX_SP_HS_CONFIG_NIBO__MASK; |
6333 | } |
6334 | |
6335 | #define REG_A6XX_SP_HS_INSTRLEN 0x0000a83c |
6336 | |
6337 | #define REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET 0x0000a83d |
6338 | #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff |
6339 | #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 |
6340 | static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) |
6341 | { |
6342 | assert(!(val & 0x7ff)); |
6343 | return (((val >> 11)) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; |
6344 | } |
6345 | |
6346 | #define REG_A7XX_SP_HS_VGPR_CONFIG 0x0000a82f |
6347 | |
6348 | #define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840 |
6349 | #define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK 0x00000001 |
6350 | #define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT 0 |
6351 | static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) |
6352 | { |
6353 | return ((val) << A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK; |
6354 | } |
6355 | #define 0x0000007e |
6356 | #define 1 |
6357 | static inline uint32_t (uint32_t val) |
6358 | { |
6359 | return ((val) << A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT__MASK; |
6360 | } |
6361 | #define 0x00001f80 |
6362 | #define 7 |
6363 | static inline uint32_t (uint32_t val) |
6364 | { |
6365 | return ((val) << A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT__MASK; |
6366 | } |
6367 | #define A6XX_SP_DS_CTRL_REG0_UNK13 0x00002000 |
6368 | #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 |
6369 | #define A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT 14 |
6370 | static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) |
6371 | { |
6372 | return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK; |
6373 | } |
6374 | #define A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE 0x00100000 |
6375 | |
6376 | #define REG_A6XX_SP_DS_BRANCH_COND 0x0000a841 |
6377 | |
6378 | #define REG_A6XX_SP_DS_PRIMITIVE_CNTL 0x0000a842 |
6379 | #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f |
6380 | #define A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT 0 |
6381 | static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_OUT(uint32_t val) |
6382 | { |
6383 | return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_OUT__MASK; |
6384 | } |
6385 | #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 |
6386 | #define A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 |
6387 | static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) |
6388 | { |
6389 | return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; |
6390 | } |
6391 | |
6392 | #define REG_A6XX_SP_DS_OUT(i0) (0x0000a843 + 0x1*(i0)) |
6393 | |
6394 | static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; } |
6395 | #define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff |
6396 | #define A6XX_SP_DS_OUT_REG_A_REGID__SHIFT 0 |
6397 | static inline uint32_t A6XX_SP_DS_OUT_REG_A_REGID(uint32_t val) |
6398 | { |
6399 | return ((val) << A6XX_SP_DS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_A_REGID__MASK; |
6400 | } |
6401 | #define A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK 0x00000f00 |
6402 | #define A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT 8 |
6403 | static inline uint32_t A6XX_SP_DS_OUT_REG_A_COMPMASK(uint32_t val) |
6404 | { |
6405 | return ((val) << A6XX_SP_DS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_A_COMPMASK__MASK; |
6406 | } |
6407 | #define A6XX_SP_DS_OUT_REG_B_REGID__MASK 0x00ff0000 |
6408 | #define A6XX_SP_DS_OUT_REG_B_REGID__SHIFT 16 |
6409 | static inline uint32_t A6XX_SP_DS_OUT_REG_B_REGID(uint32_t val) |
6410 | { |
6411 | return ((val) << A6XX_SP_DS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_DS_OUT_REG_B_REGID__MASK; |
6412 | } |
6413 | #define A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK 0x0f000000 |
6414 | #define A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT 24 |
6415 | static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) |
6416 | { |
6417 | return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK; |
6418 | } |
6419 | |
6420 | #define REG_A6XX_SP_DS_VPC_DST(i0) (0x0000a853 + 0x1*(i0)) |
6421 | |
6422 | static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; } |
6423 | #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff |
6424 | #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT 0 |
6425 | static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC0(uint32_t val) |
6426 | { |
6427 | return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK; |
6428 | } |
6429 | #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 |
6430 | #define A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT 8 |
6431 | static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC1(uint32_t val) |
6432 | { |
6433 | return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC1__MASK; |
6434 | } |
6435 | #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 |
6436 | #define A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT 16 |
6437 | static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC2(uint32_t val) |
6438 | { |
6439 | return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC2__MASK; |
6440 | } |
6441 | #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 |
6442 | #define A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT 24 |
6443 | static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) |
6444 | { |
6445 | return ((val) << A6XX_SP_DS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_DS_VPC_DST_REG_OUTLOC3__MASK; |
6446 | } |
6447 | |
6448 | #define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET 0x0000a85b |
6449 | |
6450 | #define REG_A6XX_SP_DS_OBJ_START 0x0000a85c |
6451 | |
6452 | #define REG_A6XX_SP_DS_PVT_MEM_PARAM 0x0000a85e |
6453 | #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff |
6454 | #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 |
6455 | static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) |
6456 | { |
6457 | assert(!(val & 0x1ff)); |
6458 | return (((val >> 9)) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; |
6459 | } |
6460 | #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 |
6461 | #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 |
6462 | static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) |
6463 | { |
6464 | return ((val) << A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; |
6465 | } |
6466 | |
6467 | #define REG_A6XX_SP_DS_PVT_MEM_ADDR 0x0000a85f |
6468 | |
6469 | #define REG_A6XX_SP_DS_PVT_MEM_SIZE 0x0000a861 |
6470 | #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff |
6471 | #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 |
6472 | static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) |
6473 | { |
6474 | assert(!(val & 0xfff)); |
6475 | return (((val >> 12)) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; |
6476 | } |
6477 | #define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 |
6478 | |
6479 | #define REG_A6XX_SP_DS_TEX_COUNT 0x0000a862 |
6480 | |
6481 | #define REG_A6XX_SP_DS_CONFIG 0x0000a863 |
6482 | #define A6XX_SP_DS_CONFIG_BINDLESS_TEX 0x00000001 |
6483 | #define A6XX_SP_DS_CONFIG_BINDLESS_SAMP 0x00000002 |
6484 | #define A6XX_SP_DS_CONFIG_BINDLESS_IBO 0x00000004 |
6485 | #define A6XX_SP_DS_CONFIG_BINDLESS_UBO 0x00000008 |
6486 | #define A6XX_SP_DS_CONFIG_ENABLED 0x00000100 |
6487 | #define A6XX_SP_DS_CONFIG_NTEX__MASK 0x0001fe00 |
6488 | #define A6XX_SP_DS_CONFIG_NTEX__SHIFT 9 |
6489 | static inline uint32_t A6XX_SP_DS_CONFIG_NTEX(uint32_t val) |
6490 | { |
6491 | return ((val) << A6XX_SP_DS_CONFIG_NTEX__SHIFT) & A6XX_SP_DS_CONFIG_NTEX__MASK; |
6492 | } |
6493 | #define A6XX_SP_DS_CONFIG_NSAMP__MASK 0x003e0000 |
6494 | #define A6XX_SP_DS_CONFIG_NSAMP__SHIFT 17 |
6495 | static inline uint32_t A6XX_SP_DS_CONFIG_NSAMP(uint32_t val) |
6496 | { |
6497 | return ((val) << A6XX_SP_DS_CONFIG_NSAMP__SHIFT) & A6XX_SP_DS_CONFIG_NSAMP__MASK; |
6498 | } |
6499 | #define A6XX_SP_DS_CONFIG_NIBO__MASK 0x1fc00000 |
6500 | #define A6XX_SP_DS_CONFIG_NIBO__SHIFT 22 |
6501 | static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val) |
6502 | { |
6503 | return ((val) << A6XX_SP_DS_CONFIG_NIBO__SHIFT) & A6XX_SP_DS_CONFIG_NIBO__MASK; |
6504 | } |
6505 | |
6506 | #define REG_A6XX_SP_DS_INSTRLEN 0x0000a864 |
6507 | |
6508 | #define REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET 0x0000a865 |
6509 | #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff |
6510 | #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 |
6511 | static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) |
6512 | { |
6513 | assert(!(val & 0x7ff)); |
6514 | return (((val >> 11)) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; |
6515 | } |
6516 | |
6517 | #define REG_A7XX_SP_DS_VGPR_CONFIG 0x0000a868 |
6518 | |
6519 | #define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870 |
6520 | #define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK 0x00000001 |
6521 | #define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT 0 |
6522 | static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) |
6523 | { |
6524 | return ((val) << A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK; |
6525 | } |
6526 | #define 0x0000007e |
6527 | #define 1 |
6528 | static inline uint32_t (uint32_t val) |
6529 | { |
6530 | return ((val) << A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT__MASK; |
6531 | } |
6532 | #define 0x00001f80 |
6533 | #define 7 |
6534 | static inline uint32_t (uint32_t val) |
6535 | { |
6536 | return ((val) << A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT__MASK; |
6537 | } |
6538 | #define A6XX_SP_GS_CTRL_REG0_UNK13 0x00002000 |
6539 | #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 |
6540 | #define A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT 14 |
6541 | static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) |
6542 | { |
6543 | return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK; |
6544 | } |
6545 | #define A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE 0x00100000 |
6546 | |
6547 | #define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871 |
6548 | |
6549 | #define REG_A6XX_SP_GS_BRANCH_COND 0x0000a872 |
6550 | |
6551 | #define REG_A6XX_SP_GS_PRIMITIVE_CNTL 0x0000a873 |
6552 | #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK 0x0000003f |
6553 | #define A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT 0 |
6554 | static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_OUT(uint32_t val) |
6555 | { |
6556 | return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_OUT__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_OUT__MASK; |
6557 | } |
6558 | #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK 0x00003fc0 |
6559 | #define A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT 6 |
6560 | static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) |
6561 | { |
6562 | return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; |
6563 | } |
6564 | |
6565 | #define REG_A6XX_SP_GS_OUT(i0) (0x0000a874 + 0x1*(i0)) |
6566 | |
6567 | static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; } |
6568 | #define A6XX_SP_GS_OUT_REG_A_REGID__MASK 0x000000ff |
6569 | #define A6XX_SP_GS_OUT_REG_A_REGID__SHIFT 0 |
6570 | static inline uint32_t A6XX_SP_GS_OUT_REG_A_REGID(uint32_t val) |
6571 | { |
6572 | return ((val) << A6XX_SP_GS_OUT_REG_A_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_A_REGID__MASK; |
6573 | } |
6574 | #define A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK 0x00000f00 |
6575 | #define A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT 8 |
6576 | static inline uint32_t A6XX_SP_GS_OUT_REG_A_COMPMASK(uint32_t val) |
6577 | { |
6578 | return ((val) << A6XX_SP_GS_OUT_REG_A_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_A_COMPMASK__MASK; |
6579 | } |
6580 | #define A6XX_SP_GS_OUT_REG_B_REGID__MASK 0x00ff0000 |
6581 | #define A6XX_SP_GS_OUT_REG_B_REGID__SHIFT 16 |
6582 | static inline uint32_t A6XX_SP_GS_OUT_REG_B_REGID(uint32_t val) |
6583 | { |
6584 | return ((val) << A6XX_SP_GS_OUT_REG_B_REGID__SHIFT) & A6XX_SP_GS_OUT_REG_B_REGID__MASK; |
6585 | } |
6586 | #define A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK 0x0f000000 |
6587 | #define A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT 24 |
6588 | static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) |
6589 | { |
6590 | return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK; |
6591 | } |
6592 | |
6593 | #define REG_A6XX_SP_GS_VPC_DST(i0) (0x0000a884 + 0x1*(i0)) |
6594 | |
6595 | static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; } |
6596 | #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff |
6597 | #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT 0 |
6598 | static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC0(uint32_t val) |
6599 | { |
6600 | return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC0__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK; |
6601 | } |
6602 | #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK 0x0000ff00 |
6603 | #define A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT 8 |
6604 | static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC1(uint32_t val) |
6605 | { |
6606 | return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC1__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC1__MASK; |
6607 | } |
6608 | #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK 0x00ff0000 |
6609 | #define A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT 16 |
6610 | static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC2(uint32_t val) |
6611 | { |
6612 | return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC2__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC2__MASK; |
6613 | } |
6614 | #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK 0xff000000 |
6615 | #define A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT 24 |
6616 | static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) |
6617 | { |
6618 | return ((val) << A6XX_SP_GS_VPC_DST_REG_OUTLOC3__SHIFT) & A6XX_SP_GS_VPC_DST_REG_OUTLOC3__MASK; |
6619 | } |
6620 | |
6621 | #define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET 0x0000a88c |
6622 | |
6623 | #define REG_A6XX_SP_GS_OBJ_START 0x0000a88d |
6624 | |
6625 | #define REG_A6XX_SP_GS_PVT_MEM_PARAM 0x0000a88f |
6626 | #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff |
6627 | #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 |
6628 | static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) |
6629 | { |
6630 | assert(!(val & 0x1ff)); |
6631 | return (((val >> 9)) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; |
6632 | } |
6633 | #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 |
6634 | #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 |
6635 | static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) |
6636 | { |
6637 | return ((val) << A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; |
6638 | } |
6639 | |
6640 | #define REG_A6XX_SP_GS_PVT_MEM_ADDR 0x0000a890 |
6641 | |
6642 | #define REG_A6XX_SP_GS_PVT_MEM_SIZE 0x0000a892 |
6643 | #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff |
6644 | #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 |
6645 | static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) |
6646 | { |
6647 | assert(!(val & 0xfff)); |
6648 | return (((val >> 12)) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; |
6649 | } |
6650 | #define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 |
6651 | |
6652 | #define REG_A6XX_SP_GS_TEX_COUNT 0x0000a893 |
6653 | |
6654 | #define REG_A6XX_SP_GS_CONFIG 0x0000a894 |
6655 | #define A6XX_SP_GS_CONFIG_BINDLESS_TEX 0x00000001 |
6656 | #define A6XX_SP_GS_CONFIG_BINDLESS_SAMP 0x00000002 |
6657 | #define A6XX_SP_GS_CONFIG_BINDLESS_IBO 0x00000004 |
6658 | #define A6XX_SP_GS_CONFIG_BINDLESS_UBO 0x00000008 |
6659 | #define A6XX_SP_GS_CONFIG_ENABLED 0x00000100 |
6660 | #define A6XX_SP_GS_CONFIG_NTEX__MASK 0x0001fe00 |
6661 | #define A6XX_SP_GS_CONFIG_NTEX__SHIFT 9 |
6662 | static inline uint32_t A6XX_SP_GS_CONFIG_NTEX(uint32_t val) |
6663 | { |
6664 | return ((val) << A6XX_SP_GS_CONFIG_NTEX__SHIFT) & A6XX_SP_GS_CONFIG_NTEX__MASK; |
6665 | } |
6666 | #define A6XX_SP_GS_CONFIG_NSAMP__MASK 0x003e0000 |
6667 | #define A6XX_SP_GS_CONFIG_NSAMP__SHIFT 17 |
6668 | static inline uint32_t A6XX_SP_GS_CONFIG_NSAMP(uint32_t val) |
6669 | { |
6670 | return ((val) << A6XX_SP_GS_CONFIG_NSAMP__SHIFT) & A6XX_SP_GS_CONFIG_NSAMP__MASK; |
6671 | } |
6672 | #define A6XX_SP_GS_CONFIG_NIBO__MASK 0x1fc00000 |
6673 | #define A6XX_SP_GS_CONFIG_NIBO__SHIFT 22 |
6674 | static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val) |
6675 | { |
6676 | return ((val) << A6XX_SP_GS_CONFIG_NIBO__SHIFT) & A6XX_SP_GS_CONFIG_NIBO__MASK; |
6677 | } |
6678 | |
6679 | #define REG_A6XX_SP_GS_INSTRLEN 0x0000a895 |
6680 | |
6681 | #define REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET 0x0000a896 |
6682 | #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff |
6683 | #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 |
6684 | static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) |
6685 | { |
6686 | assert(!(val & 0x7ff)); |
6687 | return (((val >> 11)) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; |
6688 | } |
6689 | |
6690 | #define REG_A7XX_SP_GS_VGPR_CONFIG 0x0000a899 |
6691 | |
6692 | #define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0 |
6693 | |
6694 | #define REG_A6XX_SP_HS_TEX_SAMP 0x0000a8a2 |
6695 | |
6696 | #define REG_A6XX_SP_DS_TEX_SAMP 0x0000a8a4 |
6697 | |
6698 | #define REG_A6XX_SP_GS_TEX_SAMP 0x0000a8a6 |
6699 | |
6700 | #define REG_A6XX_SP_VS_TEX_CONST 0x0000a8a8 |
6701 | |
6702 | #define REG_A6XX_SP_HS_TEX_CONST 0x0000a8aa |
6703 | |
6704 | #define REG_A6XX_SP_DS_TEX_CONST 0x0000a8ac |
6705 | |
6706 | #define REG_A6XX_SP_GS_TEX_CONST 0x0000a8ae |
6707 | |
6708 | #define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980 |
6709 | #define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 |
6710 | #define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 |
6711 | static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) |
6712 | { |
6713 | return ((val) << A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK; |
6714 | } |
6715 | #define 0x0000007e |
6716 | #define 1 |
6717 | static inline uint32_t (uint32_t val) |
6718 | { |
6719 | return ((val) << A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK; |
6720 | } |
6721 | #define 0x00001f80 |
6722 | #define 7 |
6723 | static inline uint32_t (uint32_t val) |
6724 | { |
6725 | return ((val) << A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK; |
6726 | } |
6727 | #define A6XX_SP_FS_CTRL_REG0_UNK13 0x00002000 |
6728 | #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 |
6729 | #define A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 14 |
6730 | static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) |
6731 | { |
6732 | return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; |
6733 | } |
6734 | #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 |
6735 | #define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 |
6736 | static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) |
6737 | { |
6738 | return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; |
6739 | } |
6740 | #define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000 |
6741 | #define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000 |
6742 | #define A6XX_SP_FS_CTRL_REG0_LODPIXMASK 0x00800000 |
6743 | #define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000 |
6744 | #define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000 |
6745 | #define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000 |
6746 | #define A6XX_SP_FS_CTRL_REG0_UNK27 0x08000000 |
6747 | #define A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE 0x10000000 |
6748 | #define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000 |
6749 | |
6750 | #define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981 |
6751 | |
6752 | #define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET 0x0000a982 |
6753 | |
6754 | #define REG_A6XX_SP_FS_OBJ_START 0x0000a983 |
6755 | |
6756 | #define REG_A6XX_SP_FS_PVT_MEM_PARAM 0x0000a985 |
6757 | #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff |
6758 | #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 |
6759 | static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) |
6760 | { |
6761 | assert(!(val & 0x1ff)); |
6762 | return (((val >> 9)) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; |
6763 | } |
6764 | #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 |
6765 | #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 |
6766 | static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) |
6767 | { |
6768 | return ((val) << A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; |
6769 | } |
6770 | |
6771 | #define REG_A6XX_SP_FS_PVT_MEM_ADDR 0x0000a986 |
6772 | |
6773 | #define REG_A6XX_SP_FS_PVT_MEM_SIZE 0x0000a988 |
6774 | #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff |
6775 | #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 |
6776 | static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) |
6777 | { |
6778 | assert(!(val & 0xfff)); |
6779 | return (((val >> 12)) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; |
6780 | } |
6781 | #define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 |
6782 | |
6783 | #define REG_A6XX_SP_BLEND_CNTL 0x0000a989 |
6784 | #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff |
6785 | #define A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 |
6786 | static inline uint32_t A6XX_SP_BLEND_CNTL_ENABLE_BLEND(uint32_t val) |
6787 | { |
6788 | return ((val) << A6XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT) & A6XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK; |
6789 | } |
6790 | #define A6XX_SP_BLEND_CNTL_UNK8 0x00000100 |
6791 | #define A6XX_SP_BLEND_CNTL_DUAL_COLOR_IN_ENABLE 0x00000200 |
6792 | #define A6XX_SP_BLEND_CNTL_ALPHA_TO_COVERAGE 0x00000400 |
6793 | |
6794 | #define REG_A6XX_SP_SRGB_CNTL 0x0000a98a |
6795 | #define A6XX_SP_SRGB_CNTL_SRGB_MRT0 0x00000001 |
6796 | #define A6XX_SP_SRGB_CNTL_SRGB_MRT1 0x00000002 |
6797 | #define A6XX_SP_SRGB_CNTL_SRGB_MRT2 0x00000004 |
6798 | #define A6XX_SP_SRGB_CNTL_SRGB_MRT3 0x00000008 |
6799 | #define A6XX_SP_SRGB_CNTL_SRGB_MRT4 0x00000010 |
6800 | #define A6XX_SP_SRGB_CNTL_SRGB_MRT5 0x00000020 |
6801 | #define A6XX_SP_SRGB_CNTL_SRGB_MRT6 0x00000040 |
6802 | #define A6XX_SP_SRGB_CNTL_SRGB_MRT7 0x00000080 |
6803 | |
6804 | #define REG_A6XX_SP_FS_RENDER_COMPONENTS 0x0000a98b |
6805 | #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK 0x0000000f |
6806 | #define A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT 0 |
6807 | static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT0(uint32_t val) |
6808 | { |
6809 | return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT0__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT0__MASK; |
6810 | } |
6811 | #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK 0x000000f0 |
6812 | #define A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT 4 |
6813 | static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT1(uint32_t val) |
6814 | { |
6815 | return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT1__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT1__MASK; |
6816 | } |
6817 | #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK 0x00000f00 |
6818 | #define A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT 8 |
6819 | static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT2(uint32_t val) |
6820 | { |
6821 | return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT2__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT2__MASK; |
6822 | } |
6823 | #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK 0x0000f000 |
6824 | #define A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT 12 |
6825 | static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT3(uint32_t val) |
6826 | { |
6827 | return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT3__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT3__MASK; |
6828 | } |
6829 | #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK 0x000f0000 |
6830 | #define A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT 16 |
6831 | static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT4(uint32_t val) |
6832 | { |
6833 | return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT4__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT4__MASK; |
6834 | } |
6835 | #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK 0x00f00000 |
6836 | #define A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT 20 |
6837 | static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT5(uint32_t val) |
6838 | { |
6839 | return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT5__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT5__MASK; |
6840 | } |
6841 | #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK 0x0f000000 |
6842 | #define A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT 24 |
6843 | static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT6(uint32_t val) |
6844 | { |
6845 | return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT6__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT6__MASK; |
6846 | } |
6847 | #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK 0xf0000000 |
6848 | #define A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT 28 |
6849 | static inline uint32_t A6XX_SP_FS_RENDER_COMPONENTS_RT7(uint32_t val) |
6850 | { |
6851 | return ((val) << A6XX_SP_FS_RENDER_COMPONENTS_RT7__SHIFT) & A6XX_SP_FS_RENDER_COMPONENTS_RT7__MASK; |
6852 | } |
6853 | |
6854 | #define REG_A6XX_SP_FS_OUTPUT_CNTL0 0x0000a98c |
6855 | #define A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE 0x00000001 |
6856 | #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK 0x0000ff00 |
6857 | #define A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT 8 |
6858 | static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(uint32_t val) |
6859 | { |
6860 | return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID__MASK; |
6861 | } |
6862 | #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK 0x00ff0000 |
6863 | #define A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT 16 |
6864 | static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(uint32_t val) |
6865 | { |
6866 | return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID__MASK; |
6867 | } |
6868 | #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK 0xff000000 |
6869 | #define A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT 24 |
6870 | static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(uint32_t val) |
6871 | { |
6872 | return ((val) << A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID__MASK; |
6873 | } |
6874 | |
6875 | #define REG_A6XX_SP_FS_OUTPUT_CNTL1 0x0000a98d |
6876 | #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK 0x0000000f |
6877 | #define A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT 0 |
6878 | static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) |
6879 | { |
6880 | return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK; |
6881 | } |
6882 | |
6883 | #define REG_A6XX_SP_FS_OUTPUT(i0) (0x0000a98e + 0x1*(i0)) |
6884 | |
6885 | static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; } |
6886 | #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff |
6887 | #define A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT 0 |
6888 | static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) |
6889 | { |
6890 | return ((val) << A6XX_SP_FS_OUTPUT_REG_REGID__SHIFT) & A6XX_SP_FS_OUTPUT_REG_REGID__MASK; |
6891 | } |
6892 | #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 |
6893 | |
6894 | #define REG_A6XX_SP_FS_MRT(i0) (0x0000a996 + 0x1*(i0)) |
6895 | |
6896 | static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; } |
6897 | #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff |
6898 | #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT 0 |
6899 | static inline uint32_t A6XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a6xx_format val) |
6900 | { |
6901 | return ((val) << A6XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK; |
6902 | } |
6903 | #define A6XX_SP_FS_MRT_REG_COLOR_SINT 0x00000100 |
6904 | #define A6XX_SP_FS_MRT_REG_COLOR_UINT 0x00000200 |
6905 | #define A6XX_SP_FS_MRT_REG_UNK10 0x00000400 |
6906 | |
6907 | #define REG_A6XX_SP_FS_PREFETCH_CNTL 0x0000a99e |
6908 | #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK 0x00000007 |
6909 | #define A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT 0 |
6910 | static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val) |
6911 | { |
6912 | return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK; |
6913 | } |
6914 | #define A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE 0x00000008 |
6915 | #define A6XX_SP_FS_PREFETCH_CNTL_ENDOFQUAD 0x00000010 |
6916 | #define A6XX_SP_FS_PREFETCH_CNTL_WRITE_COLOR_TO_OUTPUT 0x00000020 |
6917 | #define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK 0x00007fc0 |
6918 | #define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT 6 |
6919 | static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID(uint32_t val) |
6920 | { |
6921 | return ((val) << A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK; |
6922 | } |
6923 | #define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK 0x01ff0000 |
6924 | #define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT 16 |
6925 | static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD(uint32_t val) |
6926 | { |
6927 | return ((val) << A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK; |
6928 | } |
6929 | |
6930 | #define REG_A6XX_SP_FS_PREFETCH(i0) (0x0000a99f + 0x1*(i0)) |
6931 | |
6932 | static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; } |
6933 | #define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f |
6934 | #define A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0 |
6935 | static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val) |
6936 | { |
6937 | return ((val) << A6XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SRC__MASK; |
6938 | } |
6939 | #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000780 |
6940 | #define A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7 |
6941 | static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val) |
6942 | { |
6943 | return ((val) << A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK; |
6944 | } |
6945 | #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x0000f800 |
6946 | #define A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 11 |
6947 | static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val) |
6948 | { |
6949 | return ((val) << A6XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK; |
6950 | } |
6951 | #define A6XX_SP_FS_PREFETCH_CMD_DST__MASK 0x003f0000 |
6952 | #define A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT 16 |
6953 | static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_DST(uint32_t val) |
6954 | { |
6955 | return ((val) << A6XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_DST__MASK; |
6956 | } |
6957 | #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x03c00000 |
6958 | #define A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 22 |
6959 | static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val) |
6960 | { |
6961 | return ((val) << A6XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_WRMASK__MASK; |
6962 | } |
6963 | #define A6XX_SP_FS_PREFETCH_CMD_HALF 0x04000000 |
6964 | #define A6XX_SP_FS_PREFETCH_CMD_UNK27 0x08000000 |
6965 | #define A6XX_SP_FS_PREFETCH_CMD_BINDLESS 0x10000000 |
6966 | #define A6XX_SP_FS_PREFETCH_CMD_CMD__MASK 0xe0000000 |
6967 | #define A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 29 |
6968 | static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd val) |
6969 | { |
6970 | return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK; |
6971 | } |
6972 | |
6973 | #define REG_A7XX_SP_FS_PREFETCH(i0) (0x0000a99f + 0x1*(i0)) |
6974 | |
6975 | static inline uint32_t REG_A7XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; } |
6976 | #define A7XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f |
6977 | #define A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0 |
6978 | static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val) |
6979 | { |
6980 | return ((val) << A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_SRC__MASK; |
6981 | } |
6982 | #define A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000380 |
6983 | #define A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7 |
6984 | static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val) |
6985 | { |
6986 | return ((val) << A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK; |
6987 | } |
6988 | #define A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x00001c00 |
6989 | #define A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 10 |
6990 | static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val) |
6991 | { |
6992 | return ((val) << A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK; |
6993 | } |
6994 | #define A7XX_SP_FS_PREFETCH_CMD_DST__MASK 0x0007e000 |
6995 | #define A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT 13 |
6996 | static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_DST(uint32_t val) |
6997 | { |
6998 | return ((val) << A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_DST__MASK; |
6999 | } |
7000 | #define A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x00780000 |
7001 | #define A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 19 |
7002 | static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val) |
7003 | { |
7004 | return ((val) << A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK; |
7005 | } |
7006 | #define A7XX_SP_FS_PREFETCH_CMD_HALF 0x00800000 |
7007 | #define A7XX_SP_FS_PREFETCH_CMD_BINDLESS 0x02000000 |
7008 | #define A7XX_SP_FS_PREFETCH_CMD_CMD__MASK 0x3c000000 |
7009 | #define A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 26 |
7010 | static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd val) |
7011 | { |
7012 | return ((val) << A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_CMD__MASK; |
7013 | } |
7014 | |
7015 | #define REG_A6XX_SP_FS_BINDLESS_PREFETCH(i0) (0x0000a9a3 + 0x1*(i0)) |
7016 | |
7017 | static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } |
7018 | #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x0000ffff |
7019 | #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT 0 |
7020 | static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(uint32_t val) |
7021 | { |
7022 | return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK; |
7023 | } |
7024 | #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK 0xffff0000 |
7025 | #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT 16 |
7026 | static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val) |
7027 | { |
7028 | return ((val) << A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__SHIFT) & A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID__MASK; |
7029 | } |
7030 | |
7031 | #define REG_A6XX_SP_FS_TEX_COUNT 0x0000a9a7 |
7032 | |
7033 | #define REG_A6XX_SP_UNKNOWN_A9A8 0x0000a9a8 |
7034 | |
7035 | #define REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET 0x0000a9a9 |
7036 | #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff |
7037 | #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 |
7038 | static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) |
7039 | { |
7040 | assert(!(val & 0x7ff)); |
7041 | return (((val >> 11)) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; |
7042 | } |
7043 | |
7044 | #define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0 |
7045 | #define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001 |
7046 | #define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0 |
7047 | static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) |
7048 | { |
7049 | return ((val) << A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK; |
7050 | } |
7051 | #define 0x0000007e |
7052 | #define 1 |
7053 | static inline uint32_t (uint32_t val) |
7054 | { |
7055 | return ((val) << A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK; |
7056 | } |
7057 | #define 0x00001f80 |
7058 | #define 7 |
7059 | static inline uint32_t (uint32_t val) |
7060 | { |
7061 | return ((val) << A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK; |
7062 | } |
7063 | #define A6XX_SP_CS_CTRL_REG0_UNK13 0x00002000 |
7064 | #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0x000fc000 |
7065 | #define A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 14 |
7066 | static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) |
7067 | { |
7068 | return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; |
7069 | } |
7070 | #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000 |
7071 | #define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20 |
7072 | static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) |
7073 | { |
7074 | return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; |
7075 | } |
7076 | #define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000 |
7077 | #define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000 |
7078 | #define A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE 0x00800000 |
7079 | #define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000 |
7080 | |
7081 | #define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1 |
7082 | #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK 0x0000001f |
7083 | #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT 0 |
7084 | static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val) |
7085 | { |
7086 | return ((val) << A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__SHIFT) & A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK; |
7087 | } |
7088 | #define A6XX_SP_CS_UNKNOWN_A9B1_UNK5 0x00000020 |
7089 | #define A6XX_SP_CS_UNKNOWN_A9B1_UNK6 0x00000040 |
7090 | |
7091 | #define REG_A6XX_SP_CS_BRANCH_COND 0x0000a9b2 |
7092 | |
7093 | #define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET 0x0000a9b3 |
7094 | |
7095 | #define REG_A6XX_SP_CS_OBJ_START 0x0000a9b4 |
7096 | |
7097 | #define REG_A6XX_SP_CS_PVT_MEM_PARAM 0x0000a9b6 |
7098 | #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff |
7099 | #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 |
7100 | static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) |
7101 | { |
7102 | assert(!(val & 0x1ff)); |
7103 | return (((val >> 9)) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; |
7104 | } |
7105 | #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 |
7106 | #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 |
7107 | static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) |
7108 | { |
7109 | return ((val) << A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; |
7110 | } |
7111 | |
7112 | #define REG_A6XX_SP_CS_PVT_MEM_ADDR 0x0000a9b7 |
7113 | |
7114 | #define REG_A6XX_SP_CS_PVT_MEM_SIZE 0x0000a9b9 |
7115 | #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff |
7116 | #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 |
7117 | static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) |
7118 | { |
7119 | assert(!(val & 0xfff)); |
7120 | return (((val >> 12)) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; |
7121 | } |
7122 | #define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 |
7123 | |
7124 | #define REG_A6XX_SP_CS_TEX_COUNT 0x0000a9ba |
7125 | |
7126 | #define REG_A6XX_SP_CS_CONFIG 0x0000a9bb |
7127 | #define A6XX_SP_CS_CONFIG_BINDLESS_TEX 0x00000001 |
7128 | #define A6XX_SP_CS_CONFIG_BINDLESS_SAMP 0x00000002 |
7129 | #define A6XX_SP_CS_CONFIG_BINDLESS_IBO 0x00000004 |
7130 | #define A6XX_SP_CS_CONFIG_BINDLESS_UBO 0x00000008 |
7131 | #define A6XX_SP_CS_CONFIG_ENABLED 0x00000100 |
7132 | #define A6XX_SP_CS_CONFIG_NTEX__MASK 0x0001fe00 |
7133 | #define A6XX_SP_CS_CONFIG_NTEX__SHIFT 9 |
7134 | static inline uint32_t A6XX_SP_CS_CONFIG_NTEX(uint32_t val) |
7135 | { |
7136 | return ((val) << A6XX_SP_CS_CONFIG_NTEX__SHIFT) & A6XX_SP_CS_CONFIG_NTEX__MASK; |
7137 | } |
7138 | #define A6XX_SP_CS_CONFIG_NSAMP__MASK 0x003e0000 |
7139 | #define A6XX_SP_CS_CONFIG_NSAMP__SHIFT 17 |
7140 | static inline uint32_t A6XX_SP_CS_CONFIG_NSAMP(uint32_t val) |
7141 | { |
7142 | return ((val) << A6XX_SP_CS_CONFIG_NSAMP__SHIFT) & A6XX_SP_CS_CONFIG_NSAMP__MASK; |
7143 | } |
7144 | #define A6XX_SP_CS_CONFIG_NIBO__MASK 0x1fc00000 |
7145 | #define A6XX_SP_CS_CONFIG_NIBO__SHIFT 22 |
7146 | static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val) |
7147 | { |
7148 | return ((val) << A6XX_SP_CS_CONFIG_NIBO__SHIFT) & A6XX_SP_CS_CONFIG_NIBO__MASK; |
7149 | } |
7150 | |
7151 | #define REG_A6XX_SP_CS_INSTRLEN 0x0000a9bc |
7152 | |
7153 | #define REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET 0x0000a9bd |
7154 | #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK 0x0007ffff |
7155 | #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 |
7156 | static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) |
7157 | { |
7158 | assert(!(val & 0x7ff)); |
7159 | return (((val >> 11)) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; |
7160 | } |
7161 | |
7162 | #define REG_A7XX_SP_CS_UNKNOWN_A9BE 0x0000a9be |
7163 | |
7164 | #define REG_A7XX_SP_CS_VGPR_CONFIG 0x0000a9c5 |
7165 | |
7166 | #define REG_A6XX_SP_CS_CNTL_0 0x0000a9c2 |
7167 | #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff |
7168 | #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT 0 |
7169 | static inline uint32_t A6XX_SP_CS_CNTL_0_WGIDCONSTID(uint32_t val) |
7170 | { |
7171 | return ((val) << A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK; |
7172 | } |
7173 | #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00 |
7174 | #define A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT 8 |
7175 | static inline uint32_t A6XX_SP_CS_CNTL_0_WGSIZECONSTID(uint32_t val) |
7176 | { |
7177 | return ((val) << A6XX_SP_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGSIZECONSTID__MASK; |
7178 | } |
7179 | #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000 |
7180 | #define A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16 |
7181 | static inline uint32_t A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val) |
7182 | { |
7183 | return ((val) << A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID__MASK; |
7184 | } |
7185 | #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 |
7186 | #define A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT 24 |
7187 | static inline uint32_t A6XX_SP_CS_CNTL_0_LOCALIDREGID(uint32_t val) |
7188 | { |
7189 | return ((val) << A6XX_SP_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_0_LOCALIDREGID__MASK; |
7190 | } |
7191 | |
7192 | #define REG_A6XX_SP_CS_CNTL_1 0x0000a9c3 |
7193 | #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff |
7194 | #define A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 |
7195 | static inline uint32_t A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) |
7196 | { |
7197 | return ((val) << A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK; |
7198 | } |
7199 | #define A6XX_SP_CS_CNTL_1_SINGLE_SP_CORE 0x00000100 |
7200 | #define A6XX_SP_CS_CNTL_1_THREADSIZE__MASK 0x00000200 |
7201 | #define A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT 9 |
7202 | static inline uint32_t A6XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) |
7203 | { |
7204 | return ((val) << A6XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_SP_CS_CNTL_1_THREADSIZE__MASK; |
7205 | } |
7206 | #define A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400 |
7207 | |
7208 | #define REG_A7XX_SP_CS_CNTL_1 0x0000a9c3 |
7209 | #define A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff |
7210 | #define A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 |
7211 | static inline uint32_t A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) |
7212 | { |
7213 | return ((val) << A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK; |
7214 | } |
7215 | #define A7XX_SP_CS_CNTL_1_THREADSIZE__MASK 0x00000100 |
7216 | #define A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT 8 |
7217 | static inline uint32_t A7XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) |
7218 | { |
7219 | return ((val) << A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A7XX_SP_CS_CNTL_1_THREADSIZE__MASK; |
7220 | } |
7221 | #define A7XX_SP_CS_CNTL_1_THREADSIZE_SCALAR 0x00000200 |
7222 | #define A7XX_SP_CS_CNTL_1_UNK15 0x00008000 |
7223 | |
7224 | #define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0 |
7225 | |
7226 | #define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2 |
7227 | |
7228 | #define REG_A6XX_SP_FS_TEX_CONST 0x0000a9e4 |
7229 | |
7230 | #define REG_A6XX_SP_CS_TEX_CONST 0x0000a9e6 |
7231 | |
7232 | #define REG_A6XX_SP_CS_BINDLESS_BASE(i0) (0x0000a9e8 + 0x2*(i0)) |
7233 | |
7234 | static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } |
7235 | #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 |
7236 | #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 |
7237 | static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) |
7238 | { |
7239 | return ((val) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; |
7240 | } |
7241 | #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc |
7242 | #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 |
7243 | static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) |
7244 | { |
7245 | assert(!(val & 0x3)); |
7246 | return (((val >> 2)) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; |
7247 | } |
7248 | |
7249 | #define REG_A7XX_SP_CS_BINDLESS_BASE(i0) (0x0000a9e8 + 0x2*(i0)) |
7250 | |
7251 | static inline uint32_t REG_A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } |
7252 | #define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 |
7253 | #define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 |
7254 | static inline uint32_t A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) |
7255 | { |
7256 | return ((val) << A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; |
7257 | } |
7258 | #define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc |
7259 | #define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 |
7260 | static inline uint32_t A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) |
7261 | { |
7262 | assert(!(val & 0x3)); |
7263 | return (((val >> 2)) << A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; |
7264 | } |
7265 | |
7266 | #define REG_A6XX_SP_CS_IBO 0x0000a9f2 |
7267 | |
7268 | #define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00 |
7269 | |
7270 | #define REG_A7XX_SP_FS_VGPR_CONFIG 0x0000aa01 |
7271 | |
7272 | #define REG_A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL 0x0000aa02 |
7273 | #define A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL_ENABLED 0x00000001 |
7274 | |
7275 | #define REG_A7XX_SP_PS_ALIASED_COMPONENTS 0x0000aa03 |
7276 | #define A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK 0x0000000f |
7277 | #define A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT 0 |
7278 | static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT0(uint32_t val) |
7279 | { |
7280 | return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK; |
7281 | } |
7282 | #define A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK 0x000000f0 |
7283 | #define A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT 4 |
7284 | static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT1(uint32_t val) |
7285 | { |
7286 | return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK; |
7287 | } |
7288 | #define A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK 0x00000f00 |
7289 | #define A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT 8 |
7290 | static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT2(uint32_t val) |
7291 | { |
7292 | return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK; |
7293 | } |
7294 | #define A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK 0x0000f000 |
7295 | #define A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT 12 |
7296 | static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT3(uint32_t val) |
7297 | { |
7298 | return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK; |
7299 | } |
7300 | #define A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK 0x000f0000 |
7301 | #define A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT 16 |
7302 | static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT4(uint32_t val) |
7303 | { |
7304 | return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK; |
7305 | } |
7306 | #define A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK 0x00f00000 |
7307 | #define A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT 20 |
7308 | static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT5(uint32_t val) |
7309 | { |
7310 | return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK; |
7311 | } |
7312 | #define A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK 0x0f000000 |
7313 | #define A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT 24 |
7314 | static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT6(uint32_t val) |
7315 | { |
7316 | return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK; |
7317 | } |
7318 | #define A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK 0xf0000000 |
7319 | #define A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT 28 |
7320 | static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT7(uint32_t val) |
7321 | { |
7322 | return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK; |
7323 | } |
7324 | |
7325 | #define REG_A6XX_SP_UNKNOWN_AAF2 0x0000aaf2 |
7326 | |
7327 | #define REG_A6XX_SP_MODE_CONTROL 0x0000ab00 |
7328 | #define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001 |
7329 | #define A6XX_SP_MODE_CONTROL_ISAMMODE__MASK 0x00000006 |
7330 | #define A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT 1 |
7331 | static inline uint32_t A6XX_SP_MODE_CONTROL_ISAMMODE(enum a6xx_isam_mode val) |
7332 | { |
7333 | return ((val) << A6XX_SP_MODE_CONTROL_ISAMMODE__SHIFT) & A6XX_SP_MODE_CONTROL_ISAMMODE__MASK; |
7334 | } |
7335 | #define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008 |
7336 | |
7337 | #define REG_A7XX_SP_UNKNOWN_AB01 0x0000ab01 |
7338 | |
7339 | #define REG_A7XX_SP_UNKNOWN_AB02 0x0000ab02 |
7340 | |
7341 | #define REG_A6XX_SP_FS_CONFIG 0x0000ab04 |
7342 | #define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001 |
7343 | #define A6XX_SP_FS_CONFIG_BINDLESS_SAMP 0x00000002 |
7344 | #define A6XX_SP_FS_CONFIG_BINDLESS_IBO 0x00000004 |
7345 | #define A6XX_SP_FS_CONFIG_BINDLESS_UBO 0x00000008 |
7346 | #define A6XX_SP_FS_CONFIG_ENABLED 0x00000100 |
7347 | #define A6XX_SP_FS_CONFIG_NTEX__MASK 0x0001fe00 |
7348 | #define A6XX_SP_FS_CONFIG_NTEX__SHIFT 9 |
7349 | static inline uint32_t A6XX_SP_FS_CONFIG_NTEX(uint32_t val) |
7350 | { |
7351 | return ((val) << A6XX_SP_FS_CONFIG_NTEX__SHIFT) & A6XX_SP_FS_CONFIG_NTEX__MASK; |
7352 | } |
7353 | #define A6XX_SP_FS_CONFIG_NSAMP__MASK 0x003e0000 |
7354 | #define A6XX_SP_FS_CONFIG_NSAMP__SHIFT 17 |
7355 | static inline uint32_t A6XX_SP_FS_CONFIG_NSAMP(uint32_t val) |
7356 | { |
7357 | return ((val) << A6XX_SP_FS_CONFIG_NSAMP__SHIFT) & A6XX_SP_FS_CONFIG_NSAMP__MASK; |
7358 | } |
7359 | #define A6XX_SP_FS_CONFIG_NIBO__MASK 0x1fc00000 |
7360 | #define A6XX_SP_FS_CONFIG_NIBO__SHIFT 22 |
7361 | static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val) |
7362 | { |
7363 | return ((val) << A6XX_SP_FS_CONFIG_NIBO__SHIFT) & A6XX_SP_FS_CONFIG_NIBO__MASK; |
7364 | } |
7365 | |
7366 | #define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05 |
7367 | |
7368 | #define REG_A6XX_SP_BINDLESS_BASE(i0) (0x0000ab10 + 0x2*(i0)) |
7369 | |
7370 | static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; } |
7371 | #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 |
7372 | #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 |
7373 | static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) |
7374 | { |
7375 | return ((val) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; |
7376 | } |
7377 | #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc |
7378 | #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 |
7379 | static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) |
7380 | { |
7381 | assert(!(val & 0x3)); |
7382 | return (((val >> 2)) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; |
7383 | } |
7384 | |
7385 | #define REG_A7XX_SP_BINDLESS_BASE(i0) (0x0000ab0a + 0x2*(i0)) |
7386 | |
7387 | static inline uint32_t REG_A7XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000ab0a + 0x2*i0; } |
7388 | #define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 |
7389 | #define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 |
7390 | static inline uint32_t A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) |
7391 | { |
7392 | return ((val) << A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; |
7393 | } |
7394 | #define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc |
7395 | #define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 |
7396 | static inline uint32_t A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) |
7397 | { |
7398 | assert(!(val & 0x3)); |
7399 | return (((val >> 2)) << A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; |
7400 | } |
7401 | |
7402 | #define REG_A6XX_SP_IBO 0x0000ab1a |
7403 | |
7404 | #define REG_A6XX_SP_IBO_COUNT 0x0000ab20 |
7405 | |
7406 | #define REG_A7XX_SP_UNKNOWN_AB22 0x0000ab22 |
7407 | |
7408 | #define REG_A6XX_SP_2D_DST_FORMAT 0x0000acc0 |
7409 | #define A6XX_SP_2D_DST_FORMAT_NORM 0x00000001 |
7410 | #define A6XX_SP_2D_DST_FORMAT_SINT 0x00000002 |
7411 | #define A6XX_SP_2D_DST_FORMAT_UINT 0x00000004 |
7412 | #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8 |
7413 | #define A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3 |
7414 | static inline uint32_t A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val) |
7415 | { |
7416 | return ((val) << A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A6XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK; |
7417 | } |
7418 | #define A6XX_SP_2D_DST_FORMAT_SRGB 0x00000800 |
7419 | #define A6XX_SP_2D_DST_FORMAT_MASK__MASK 0x0000f000 |
7420 | #define A6XX_SP_2D_DST_FORMAT_MASK__SHIFT 12 |
7421 | static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val) |
7422 | { |
7423 | return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK; |
7424 | } |
7425 | |
7426 | #define REG_A7XX_SP_2D_DST_FORMAT 0x0000a9bf |
7427 | #define A7XX_SP_2D_DST_FORMAT_NORM 0x00000001 |
7428 | #define A7XX_SP_2D_DST_FORMAT_SINT 0x00000002 |
7429 | #define A7XX_SP_2D_DST_FORMAT_UINT 0x00000004 |
7430 | #define A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8 |
7431 | #define A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3 |
7432 | static inline uint32_t A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val) |
7433 | { |
7434 | return ((val) << A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK; |
7435 | } |
7436 | #define A7XX_SP_2D_DST_FORMAT_SRGB 0x00000800 |
7437 | #define A7XX_SP_2D_DST_FORMAT_MASK__MASK 0x0000f000 |
7438 | #define A7XX_SP_2D_DST_FORMAT_MASK__SHIFT 12 |
7439 | static inline uint32_t A7XX_SP_2D_DST_FORMAT_MASK(uint32_t val) |
7440 | { |
7441 | return ((val) << A7XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A7XX_SP_2D_DST_FORMAT_MASK__MASK; |
7442 | } |
7443 | |
7444 | #define REG_A6XX_SP_DBG_ECO_CNTL 0x0000ae00 |
7445 | |
7446 | #define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01 |
7447 | |
7448 | #define REG_A6XX_SP_NC_MODE_CNTL 0x0000ae02 |
7449 | |
7450 | #define REG_A6XX_SP_CHICKEN_BITS 0x0000ae03 |
7451 | |
7452 | #define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04 |
7453 | #define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008 |
7454 | |
7455 | #define REG_A7XX_SP_UNKNOWN_AE06 0x0000ae06 |
7456 | |
7457 | #define REG_A7XX_SP_UNKNOWN_AE08 0x0000ae08 |
7458 | |
7459 | #define REG_A7XX_SP_UNKNOWN_AE09 0x0000ae09 |
7460 | |
7461 | #define REG_A7XX_SP_UNKNOWN_AE0A 0x0000ae0a |
7462 | |
7463 | #define REG_A6XX_SP_PERFCTR_ENABLE 0x0000ae0f |
7464 | #define A6XX_SP_PERFCTR_ENABLE_VS 0x00000001 |
7465 | #define A6XX_SP_PERFCTR_ENABLE_HS 0x00000002 |
7466 | #define A6XX_SP_PERFCTR_ENABLE_DS 0x00000004 |
7467 | #define A6XX_SP_PERFCTR_ENABLE_GS 0x00000008 |
7468 | #define A6XX_SP_PERFCTR_ENABLE_FS 0x00000010 |
7469 | #define A6XX_SP_PERFCTR_ENABLE_CS 0x00000020 |
7470 | |
7471 | #define REG_A6XX_SP_PERFCTR_SP_SEL(i0) (0x0000ae10 + 0x1*(i0)) |
7472 | |
7473 | #define REG_A7XX_SP_PERFCTR_HLSQ_SEL(i0) (0x0000ae60 + 0x1*(i0)) |
7474 | |
7475 | #define REG_A7XX_SP_UNKNOWN_AE6A 0x0000ae6a |
7476 | |
7477 | #define REG_A7XX_SP_UNKNOWN_AE6B 0x0000ae6b |
7478 | |
7479 | #define REG_A7XX_SP_UNKNOWN_AE6C 0x0000ae6c |
7480 | |
7481 | #define REG_A7XX_SP_READ_SEL 0x0000ae6d |
7482 | #define A7XX_SP_READ_SEL_LOCATION__MASK 0x000c0000 |
7483 | #define A7XX_SP_READ_SEL_LOCATION__SHIFT 18 |
7484 | static inline uint32_t A7XX_SP_READ_SEL_LOCATION(enum a7xx_state_location val) |
7485 | { |
7486 | return ((val) << A7XX_SP_READ_SEL_LOCATION__SHIFT) & A7XX_SP_READ_SEL_LOCATION__MASK; |
7487 | } |
7488 | #define A7XX_SP_READ_SEL_PIPE__MASK 0x00030000 |
7489 | #define A7XX_SP_READ_SEL_PIPE__SHIFT 16 |
7490 | static inline uint32_t A7XX_SP_READ_SEL_PIPE(enum a7xx_pipe val) |
7491 | { |
7492 | return ((val) << A7XX_SP_READ_SEL_PIPE__SHIFT) & A7XX_SP_READ_SEL_PIPE__MASK; |
7493 | } |
7494 | #define A7XX_SP_READ_SEL_STATETYPE__MASK 0x0000ff00 |
7495 | #define A7XX_SP_READ_SEL_STATETYPE__SHIFT 8 |
7496 | static inline uint32_t A7XX_SP_READ_SEL_STATETYPE(enum a7xx_statetype_id val) |
7497 | { |
7498 | return ((val) << A7XX_SP_READ_SEL_STATETYPE__SHIFT) & A7XX_SP_READ_SEL_STATETYPE__MASK; |
7499 | } |
7500 | #define A7XX_SP_READ_SEL_USPTP__MASK 0x000000f0 |
7501 | #define A7XX_SP_READ_SEL_USPTP__SHIFT 4 |
7502 | static inline uint32_t A7XX_SP_READ_SEL_USPTP(uint32_t val) |
7503 | { |
7504 | return ((val) << A7XX_SP_READ_SEL_USPTP__SHIFT) & A7XX_SP_READ_SEL_USPTP__MASK; |
7505 | } |
7506 | #define A7XX_SP_READ_SEL_SPTP__MASK 0x0000000f |
7507 | #define A7XX_SP_READ_SEL_SPTP__SHIFT 0 |
7508 | static inline uint32_t A7XX_SP_READ_SEL_SPTP(uint32_t val) |
7509 | { |
7510 | return ((val) << A7XX_SP_READ_SEL_SPTP__SHIFT) & A7XX_SP_READ_SEL_SPTP__MASK; |
7511 | } |
7512 | |
7513 | #define REG_A7XX_SP_DBG_CNTL 0x0000ae71 |
7514 | |
7515 | #define REG_A7XX_SP_UNKNOWN_AE73 0x0000ae73 |
7516 | |
7517 | #define REG_A7XX_SP_PERFCTR_SP_SEL(i0) (0x0000ae80 + 0x1*(i0)) |
7518 | |
7519 | #define REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22 |
7520 | |
7521 | #define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180 |
7522 | |
7523 | #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182 |
7524 | |
7525 | #define REG_A6XX_SP_UNKNOWN_B183 0x0000b183 |
7526 | |
7527 | #define REG_A6XX_SP_UNKNOWN_B190 0x0000b190 |
7528 | |
7529 | #define REG_A6XX_SP_UNKNOWN_B191 0x0000b191 |
7530 | |
7531 | #define REG_A6XX_SP_TP_RAS_MSAA_CNTL 0x0000b300 |
7532 | #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 |
7533 | #define A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 |
7534 | static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) |
7535 | { |
7536 | return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES__MASK; |
7537 | } |
7538 | #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK 0x0000000c |
7539 | #define A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT 2 |
7540 | static inline uint32_t A6XX_SP_TP_RAS_MSAA_CNTL_UNK2(uint32_t val) |
7541 | { |
7542 | return ((val) << A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_SP_TP_RAS_MSAA_CNTL_UNK2__MASK; |
7543 | } |
7544 | |
7545 | #define REG_A6XX_SP_TP_DEST_MSAA_CNTL 0x0000b301 |
7546 | #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 |
7547 | #define A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT 0 |
7548 | static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) |
7549 | { |
7550 | return ((val) << A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES__MASK; |
7551 | } |
7552 | #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 |
7553 | |
7554 | #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302 |
7555 | |
7556 | #define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304 |
7557 | #define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001 |
7558 | #define A6XX_SP_TP_SAMPLE_CONFIG_LOCATION_ENABLE 0x00000002 |
7559 | |
7560 | #define REG_A6XX_SP_TP_SAMPLE_LOCATION_0 0x0000b305 |
7561 | #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK 0x0000000f |
7562 | #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 |
7563 | static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) |
7564 | { |
7565 | return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; |
7566 | } |
7567 | #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 |
7568 | #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 |
7569 | static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) |
7570 | { |
7571 | return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; |
7572 | } |
7573 | #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 |
7574 | #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 |
7575 | static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) |
7576 | { |
7577 | return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; |
7578 | } |
7579 | #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 |
7580 | #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 |
7581 | static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) |
7582 | { |
7583 | return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; |
7584 | } |
7585 | #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 |
7586 | #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 |
7587 | static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) |
7588 | { |
7589 | return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; |
7590 | } |
7591 | #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 |
7592 | #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 |
7593 | static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) |
7594 | { |
7595 | return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; |
7596 | } |
7597 | #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 |
7598 | #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 |
7599 | static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) |
7600 | { |
7601 | return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; |
7602 | } |
7603 | #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 |
7604 | #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 |
7605 | static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) |
7606 | { |
7607 | return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; |
7608 | } |
7609 | |
7610 | #define REG_A6XX_SP_TP_SAMPLE_LOCATION_1 0x0000b306 |
7611 | #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK 0x0000000f |
7612 | #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 |
7613 | static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) |
7614 | { |
7615 | return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; |
7616 | } |
7617 | #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 |
7618 | #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 |
7619 | static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) |
7620 | { |
7621 | return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; |
7622 | } |
7623 | #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 |
7624 | #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 |
7625 | static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) |
7626 | { |
7627 | return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; |
7628 | } |
7629 | #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 |
7630 | #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 |
7631 | static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) |
7632 | { |
7633 | return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; |
7634 | } |
7635 | #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 |
7636 | #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 |
7637 | static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) |
7638 | { |
7639 | return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; |
7640 | } |
7641 | #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 |
7642 | #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 |
7643 | static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) |
7644 | { |
7645 | return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; |
7646 | } |
7647 | #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 |
7648 | #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 |
7649 | static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) |
7650 | { |
7651 | return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; |
7652 | } |
7653 | #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 |
7654 | #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 |
7655 | static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) |
7656 | { |
7657 | return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; |
7658 | } |
7659 | |
7660 | #define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307 |
7661 | #define A6XX_SP_TP_WINDOW_OFFSET_X__MASK 0x00003fff |
7662 | #define A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT 0 |
7663 | static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_X(uint32_t val) |
7664 | { |
7665 | return ((val) << A6XX_SP_TP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_X__MASK; |
7666 | } |
7667 | #define A6XX_SP_TP_WINDOW_OFFSET_Y__MASK 0x3fff0000 |
7668 | #define A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT 16 |
7669 | static inline uint32_t A6XX_SP_TP_WINDOW_OFFSET_Y(uint32_t val) |
7670 | { |
7671 | return ((val) << A6XX_SP_TP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_TP_WINDOW_OFFSET_Y__MASK; |
7672 | } |
7673 | |
7674 | #define REG_A6XX_SP_TP_MODE_CNTL 0x0000b309 |
7675 | #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK 0x00000003 |
7676 | #define A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT 0 |
7677 | static inline uint32_t A6XX_SP_TP_MODE_CNTL_ISAMMODE(enum a6xx_isam_mode val) |
7678 | { |
7679 | return ((val) << A6XX_SP_TP_MODE_CNTL_ISAMMODE__SHIFT) & A6XX_SP_TP_MODE_CNTL_ISAMMODE__MASK; |
7680 | } |
7681 | #define A6XX_SP_TP_MODE_CNTL_UNK3__MASK 0x000000fc |
7682 | #define A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT 2 |
7683 | static inline uint32_t A6XX_SP_TP_MODE_CNTL_UNK3(uint32_t val) |
7684 | { |
7685 | return ((val) << A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT) & A6XX_SP_TP_MODE_CNTL_UNK3__MASK; |
7686 | } |
7687 | |
7688 | #define REG_A7XX_SP_UNKNOWN_B310 0x0000b310 |
7689 | |
7690 | #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0 |
7691 | #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff |
7692 | #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 |
7693 | static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val) |
7694 | { |
7695 | return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK; |
7696 | } |
7697 | #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 |
7698 | #define A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8 |
7699 | static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) |
7700 | { |
7701 | return ((val) << A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK; |
7702 | } |
7703 | #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 |
7704 | #define A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 |
7705 | static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) |
7706 | { |
7707 | return ((val) << A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK; |
7708 | } |
7709 | #define A6XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000 |
7710 | #define A6XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000 |
7711 | #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000 |
7712 | #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14 |
7713 | static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val) |
7714 | { |
7715 | return ((val) << A6XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK; |
7716 | } |
7717 | #define A6XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000 |
7718 | #define A6XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000 |
7719 | #define A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000 |
7720 | #define A6XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000 |
7721 | #define A6XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000 |
7722 | #define A6XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000 |
7723 | #define A6XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000 |
7724 | #define A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000 |
7725 | #define A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23 |
7726 | static inline uint32_t A6XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val) |
7727 | { |
7728 | return ((val) << A6XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A6XX_SP_PS_2D_SRC_INFO_UNK23__MASK; |
7729 | } |
7730 | #define A6XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000 |
7731 | |
7732 | #define REG_A6XX_SP_PS_2D_SRC_SIZE 0x0000b4c1 |
7733 | #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff |
7734 | #define A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0 |
7735 | static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) |
7736 | { |
7737 | return ((val) << A6XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK; |
7738 | } |
7739 | #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000 |
7740 | #define A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15 |
7741 | static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) |
7742 | { |
7743 | return ((val) << A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A6XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK; |
7744 | } |
7745 | |
7746 | #define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2 |
7747 | |
7748 | #define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4 |
7749 | #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff |
7750 | #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0 |
7751 | static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val) |
7752 | { |
7753 | return ((val) << A6XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK; |
7754 | } |
7755 | #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00 |
7756 | #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9 |
7757 | static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) |
7758 | { |
7759 | assert(!(val & 0x3f)); |
7760 | return (((val >> 6)) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; |
7761 | } |
7762 | |
7763 | #define REG_A7XX_SP_PS_2D_SRC_INFO 0x0000b2c0 |
7764 | #define A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff |
7765 | #define A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 |
7766 | static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val) |
7767 | { |
7768 | return ((val) << A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK; |
7769 | } |
7770 | #define A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 |
7771 | #define A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8 |
7772 | static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) |
7773 | { |
7774 | return ((val) << A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK; |
7775 | } |
7776 | #define A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 |
7777 | #define A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 |
7778 | static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) |
7779 | { |
7780 | return ((val) << A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK; |
7781 | } |
7782 | #define A7XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000 |
7783 | #define A7XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000 |
7784 | #define A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000 |
7785 | #define A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14 |
7786 | static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val) |
7787 | { |
7788 | return ((val) << A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK; |
7789 | } |
7790 | #define A7XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000 |
7791 | #define A7XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000 |
7792 | #define A7XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000 |
7793 | #define A7XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000 |
7794 | #define A7XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000 |
7795 | #define A7XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000 |
7796 | #define A7XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000 |
7797 | #define A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000 |
7798 | #define A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23 |
7799 | static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val) |
7800 | { |
7801 | return ((val) << A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK; |
7802 | } |
7803 | #define A7XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000 |
7804 | |
7805 | #define REG_A7XX_SP_PS_2D_SRC_SIZE 0x0000b2c1 |
7806 | #define A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff |
7807 | #define A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0 |
7808 | static inline uint32_t A7XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) |
7809 | { |
7810 | return ((val) << A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK; |
7811 | } |
7812 | #define A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000 |
7813 | #define A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15 |
7814 | static inline uint32_t A7XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) |
7815 | { |
7816 | return ((val) << A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK; |
7817 | } |
7818 | |
7819 | #define REG_A7XX_SP_PS_2D_SRC 0x0000b2c2 |
7820 | |
7821 | #define REG_A7XX_SP_PS_2D_SRC_PITCH 0x0000b2c4 |
7822 | #define A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff |
7823 | #define A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0 |
7824 | static inline uint32_t A7XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val) |
7825 | { |
7826 | return ((val) << A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK; |
7827 | } |
7828 | #define A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00 |
7829 | #define A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9 |
7830 | static inline uint32_t A7XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) |
7831 | { |
7832 | assert(!(val & 0x3f)); |
7833 | return (((val >> 6)) << A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; |
7834 | } |
7835 | |
7836 | #define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5 |
7837 | |
7838 | #define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b4c7 |
7839 | #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff |
7840 | #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0 |
7841 | static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val) |
7842 | { |
7843 | assert(!(val & 0x3f)); |
7844 | return (((val >> 6)) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK; |
7845 | } |
7846 | |
7847 | #define REG_A6XX_SP_PS_2D_SRC_PLANE2 0x0000b4c8 |
7848 | |
7849 | #define REG_A7XX_SP_PS_2D_SRC_PLANE1 0x0000b2c5 |
7850 | |
7851 | #define REG_A7XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b2c7 |
7852 | #define A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff |
7853 | #define A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0 |
7854 | static inline uint32_t A7XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val) |
7855 | { |
7856 | assert(!(val & 0x3f)); |
7857 | return (((val >> 6)) << A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK; |
7858 | } |
7859 | |
7860 | #define REG_A7XX_SP_PS_2D_SRC_PLANE2 0x0000b2c8 |
7861 | |
7862 | #define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca |
7863 | |
7864 | #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc |
7865 | #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff |
7866 | #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0 |
7867 | static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val) |
7868 | { |
7869 | assert(!(val & 0x3f)); |
7870 | return (((val >> 6)) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK; |
7871 | } |
7872 | |
7873 | #define REG_A7XX_SP_PS_2D_SRC_FLAGS 0x0000b2ca |
7874 | |
7875 | #define REG_A7XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b2cc |
7876 | #define A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff |
7877 | #define A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0 |
7878 | static inline uint32_t A7XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val) |
7879 | { |
7880 | assert(!(val & 0x3f)); |
7881 | return (((val >> 6)) << A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK; |
7882 | } |
7883 | |
7884 | #define REG_A6XX_SP_PS_UNKNOWN_B4CD 0x0000b4cd |
7885 | |
7886 | #define REG_A6XX_SP_PS_UNKNOWN_B4CE 0x0000b4ce |
7887 | |
7888 | #define REG_A6XX_SP_PS_UNKNOWN_B4CF 0x0000b4cf |
7889 | |
7890 | #define REG_A6XX_SP_PS_UNKNOWN_B4D0 0x0000b4d0 |
7891 | |
7892 | #define REG_A6XX_SP_WINDOW_OFFSET 0x0000b4d1 |
7893 | #define A6XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff |
7894 | #define A6XX_SP_WINDOW_OFFSET_X__SHIFT 0 |
7895 | static inline uint32_t A6XX_SP_WINDOW_OFFSET_X(uint32_t val) |
7896 | { |
7897 | return ((val) << A6XX_SP_WINDOW_OFFSET_X__SHIFT) & A6XX_SP_WINDOW_OFFSET_X__MASK; |
7898 | } |
7899 | #define A6XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000 |
7900 | #define A6XX_SP_WINDOW_OFFSET_Y__SHIFT 16 |
7901 | static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val) |
7902 | { |
7903 | return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK; |
7904 | } |
7905 | |
7906 | #define REG_A7XX_SP_PS_UNKNOWN_B4CD 0x0000b2cd |
7907 | |
7908 | #define REG_A7XX_SP_PS_UNKNOWN_B4CE 0x0000b2ce |
7909 | |
7910 | #define REG_A7XX_SP_PS_UNKNOWN_B4CF 0x0000b2cf |
7911 | |
7912 | #define REG_A7XX_SP_PS_UNKNOWN_B4D0 0x0000b2d0 |
7913 | |
7914 | #define REG_A7XX_SP_PS_2D_WINDOW_OFFSET 0x0000b2d1 |
7915 | #define A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK 0x00003fff |
7916 | #define A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT 0 |
7917 | static inline uint32_t A7XX_SP_PS_2D_WINDOW_OFFSET_X(uint32_t val) |
7918 | { |
7919 | return ((val) << A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT) & A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK; |
7920 | } |
7921 | #define A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK 0x3fff0000 |
7922 | #define A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT 16 |
7923 | static inline uint32_t A7XX_SP_PS_2D_WINDOW_OFFSET_Y(uint32_t val) |
7924 | { |
7925 | return ((val) << A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT) & A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK; |
7926 | } |
7927 | |
7928 | #define REG_A7XX_SP_PS_UNKNOWN_B2D2 0x0000b2d2 |
7929 | |
7930 | #define REG_A7XX_SP_WINDOW_OFFSET 0x0000ab21 |
7931 | #define A7XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff |
7932 | #define A7XX_SP_WINDOW_OFFSET_X__SHIFT 0 |
7933 | static inline uint32_t A7XX_SP_WINDOW_OFFSET_X(uint32_t val) |
7934 | { |
7935 | return ((val) << A7XX_SP_WINDOW_OFFSET_X__SHIFT) & A7XX_SP_WINDOW_OFFSET_X__MASK; |
7936 | } |
7937 | #define A7XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000 |
7938 | #define A7XX_SP_WINDOW_OFFSET_Y__SHIFT 16 |
7939 | static inline uint32_t A7XX_SP_WINDOW_OFFSET_Y(uint32_t val) |
7940 | { |
7941 | return ((val) << A7XX_SP_WINDOW_OFFSET_Y__SHIFT) & A7XX_SP_WINDOW_OFFSET_Y__MASK; |
7942 | } |
7943 | |
7944 | #define REG_A6XX_TPL1_DBG_ECO_CNTL 0x0000b600 |
7945 | |
7946 | #define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601 |
7947 | |
7948 | #define REG_A6XX_TPL1_UNKNOWN_B602 0x0000b602 |
7949 | |
7950 | #define REG_A6XX_TPL1_NC_MODE_CNTL 0x0000b604 |
7951 | #define A6XX_TPL1_NC_MODE_CNTL_MODE 0x00000001 |
7952 | #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006 |
7953 | #define A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT 1 |
7954 | static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT(uint32_t val) |
7955 | { |
7956 | return ((val) << A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_LOWER_BIT__MASK; |
7957 | } |
7958 | #define A6XX_TPL1_NC_MODE_CNTL_MIN_ACCESS_LENGTH 0x00000008 |
7959 | #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK 0x00000010 |
7960 | #define A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT 4 |
7961 | static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT(uint32_t val) |
7962 | { |
7963 | return ((val) << A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UPPER_BIT__MASK; |
7964 | } |
7965 | #define A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK 0x000000c0 |
7966 | #define A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT 6 |
7967 | static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val) |
7968 | { |
7969 | return ((val) << A6XX_TPL1_NC_MODE_CNTL_UNK6__SHIFT) & A6XX_TPL1_NC_MODE_CNTL_UNK6__MASK; |
7970 | } |
7971 | |
7972 | #define REG_A6XX_TPL1_UNKNOWN_B605 0x0000b605 |
7973 | |
7974 | #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608 |
7975 | |
7976 | #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609 |
7977 | |
7978 | #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a |
7979 | |
7980 | #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b |
7981 | |
7982 | #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c |
7983 | |
7984 | #define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608 |
7985 | |
7986 | #define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609 |
7987 | |
7988 | #define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a |
7989 | |
7990 | #define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b |
7991 | |
7992 | #define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c |
7993 | |
7994 | #define REG_A6XX_TPL1_PERFCTR_TP_SEL(i0) (0x0000b610 + 0x1*(i0)) |
7995 | |
7996 | #define REG_A6XX_HLSQ_VS_CNTL 0x0000b800 |
7997 | #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff |
7998 | #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0 |
7999 | static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) |
8000 | { |
8001 | assert(!(val & 0x3)); |
8002 | return (((val >> 2)) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK; |
8003 | } |
8004 | #define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100 |
8005 | #define A6XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 |
8006 | |
8007 | #define REG_A6XX_HLSQ_HS_CNTL 0x0000b801 |
8008 | #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff |
8009 | #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0 |
8010 | static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) |
8011 | { |
8012 | assert(!(val & 0x3)); |
8013 | return (((val >> 2)) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK; |
8014 | } |
8015 | #define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100 |
8016 | #define A6XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 |
8017 | |
8018 | #define REG_A6XX_HLSQ_DS_CNTL 0x0000b802 |
8019 | #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff |
8020 | #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0 |
8021 | static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) |
8022 | { |
8023 | assert(!(val & 0x3)); |
8024 | return (((val >> 2)) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK; |
8025 | } |
8026 | #define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100 |
8027 | #define A6XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 |
8028 | |
8029 | #define REG_A6XX_HLSQ_GS_CNTL 0x0000b803 |
8030 | #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff |
8031 | #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0 |
8032 | static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) |
8033 | { |
8034 | assert(!(val & 0x3)); |
8035 | return (((val >> 2)) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK; |
8036 | } |
8037 | #define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100 |
8038 | #define A6XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 |
8039 | |
8040 | #define REG_A7XX_HLSQ_VS_CNTL 0x0000a827 |
8041 | #define A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff |
8042 | #define A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0 |
8043 | static inline uint32_t A7XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) |
8044 | { |
8045 | assert(!(val & 0x3)); |
8046 | return (((val >> 2)) << A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK; |
8047 | } |
8048 | #define A7XX_HLSQ_VS_CNTL_ENABLED 0x00000100 |
8049 | #define A7XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 |
8050 | |
8051 | #define REG_A7XX_HLSQ_HS_CNTL 0x0000a83f |
8052 | #define A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff |
8053 | #define A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0 |
8054 | static inline uint32_t A7XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) |
8055 | { |
8056 | assert(!(val & 0x3)); |
8057 | return (((val >> 2)) << A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK; |
8058 | } |
8059 | #define A7XX_HLSQ_HS_CNTL_ENABLED 0x00000100 |
8060 | #define A7XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 |
8061 | |
8062 | #define REG_A7XX_HLSQ_DS_CNTL 0x0000a867 |
8063 | #define A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff |
8064 | #define A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0 |
8065 | static inline uint32_t A7XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) |
8066 | { |
8067 | assert(!(val & 0x3)); |
8068 | return (((val >> 2)) << A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK; |
8069 | } |
8070 | #define A7XX_HLSQ_DS_CNTL_ENABLED 0x00000100 |
8071 | #define A7XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 |
8072 | |
8073 | #define REG_A7XX_HLSQ_GS_CNTL 0x0000a898 |
8074 | #define A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff |
8075 | #define A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0 |
8076 | static inline uint32_t A7XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) |
8077 | { |
8078 | assert(!(val & 0x3)); |
8079 | return (((val >> 2)) << A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK; |
8080 | } |
8081 | #define A7XX_HLSQ_GS_CNTL_ENABLED 0x00000100 |
8082 | #define A7XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 |
8083 | |
8084 | #define REG_A7XX_HLSQ_FS_UNKNOWN_A9AA 0x0000a9aa |
8085 | #define A7XX_HLSQ_FS_UNKNOWN_A9AA_CONSTS_LOAD_DISABLE 0x00000001 |
8086 | |
8087 | #define REG_A7XX_HLSQ_UNKNOWN_A9AC 0x0000a9ac |
8088 | |
8089 | #define REG_A7XX_HLSQ_UNKNOWN_A9AD 0x0000a9ad |
8090 | |
8091 | #define REG_A7XX_HLSQ_UNKNOWN_A9AE 0x0000a9ae |
8092 | #define A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK 0x000000ff |
8093 | #define A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT 0 |
8094 | static inline uint32_t A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT(uint32_t val) |
8095 | { |
8096 | return ((val) << A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT) & A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK; |
8097 | } |
8098 | #define A7XX_HLSQ_UNKNOWN_A9AE_UNK8 0x00000100 |
8099 | #define A7XX_HLSQ_UNKNOWN_A9AE_UNK9 0x00000200 |
8100 | |
8101 | #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820 |
8102 | |
8103 | #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821 |
8104 | |
8105 | #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823 |
8106 | |
8107 | #define REG_A6XX_HLSQ_FS_CNTL_0 0x0000b980 |
8108 | #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001 |
8109 | #define A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0 |
8110 | static inline uint32_t A6XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val) |
8111 | { |
8112 | return ((val) << A6XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A6XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK; |
8113 | } |
8114 | #define A6XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002 |
8115 | #define A6XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc |
8116 | #define A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2 |
8117 | static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val) |
8118 | { |
8119 | return ((val) << A6XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A6XX_HLSQ_FS_CNTL_0_UNK2__MASK; |
8120 | } |
8121 | |
8122 | #define REG_A6XX_HLSQ_UNKNOWN_B981 0x0000b981 |
8123 | |
8124 | #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982 |
8125 | #define A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x00000007 |
8126 | #define A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0 |
8127 | static inline uint32_t A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val) |
8128 | { |
8129 | return ((val) << A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK; |
8130 | } |
8131 | |
8132 | #define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983 |
8133 | #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff |
8134 | #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 |
8135 | static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) |
8136 | { |
8137 | return ((val) << A6XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; |
8138 | } |
8139 | #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 |
8140 | #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 |
8141 | static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) |
8142 | { |
8143 | return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; |
8144 | } |
8145 | #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 |
8146 | #define A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 |
8147 | static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) |
8148 | { |
8149 | return ((val) << A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; |
8150 | } |
8151 | #define A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK 0xff000000 |
8152 | #define A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT 24 |
8153 | static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val) |
8154 | { |
8155 | return ((val) << A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK; |
8156 | } |
8157 | |
8158 | #define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984 |
8159 | #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff |
8160 | #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 |
8161 | static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) |
8162 | { |
8163 | return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK; |
8164 | } |
8165 | #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00 |
8166 | #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8 |
8167 | static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) |
8168 | { |
8169 | return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK; |
8170 | } |
8171 | #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000 |
8172 | #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16 |
8173 | static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) |
8174 | { |
8175 | return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK; |
8176 | } |
8177 | #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000 |
8178 | #define A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24 |
8179 | static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) |
8180 | { |
8181 | return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; |
8182 | } |
8183 | |
8184 | #define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985 |
8185 | #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff |
8186 | #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0 |
8187 | static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) |
8188 | { |
8189 | return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK; |
8190 | } |
8191 | #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00 |
8192 | #define A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8 |
8193 | static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) |
8194 | { |
8195 | return ((val) << A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK; |
8196 | } |
8197 | #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 |
8198 | #define A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 |
8199 | static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) |
8200 | { |
8201 | return ((val) << A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; |
8202 | } |
8203 | #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 |
8204 | #define A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 |
8205 | static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) |
8206 | { |
8207 | return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; |
8208 | } |
8209 | |
8210 | #define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986 |
8211 | #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff |
8212 | #define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0 |
8213 | static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val) |
8214 | { |
8215 | return ((val) << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK; |
8216 | } |
8217 | #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00 |
8218 | #define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8 |
8219 | static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val) |
8220 | { |
8221 | return ((val) << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK; |
8222 | } |
8223 | |
8224 | #define REG_A6XX_HLSQ_CS_CNTL 0x0000b987 |
8225 | #define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff |
8226 | #define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0 |
8227 | static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) |
8228 | { |
8229 | assert(!(val & 0x3)); |
8230 | return (((val >> 2)) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK; |
8231 | } |
8232 | #define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100 |
8233 | #define A6XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 |
8234 | |
8235 | #define REG_A7XX_HLSQ_FS_CNTL_0 0x0000a9c6 |
8236 | #define A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001 |
8237 | #define A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0 |
8238 | static inline uint32_t A7XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val) |
8239 | { |
8240 | return ((val) << A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK; |
8241 | } |
8242 | #define A7XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002 |
8243 | #define A7XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc |
8244 | #define A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2 |
8245 | static inline uint32_t A7XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val) |
8246 | { |
8247 | return ((val) << A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A7XX_HLSQ_FS_CNTL_0_UNK2__MASK; |
8248 | } |
8249 | |
8250 | #define REG_A7XX_HLSQ_CONTROL_1_REG 0x0000a9c7 |
8251 | #define A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x00000007 |
8252 | #define A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0 |
8253 | static inline uint32_t A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val) |
8254 | { |
8255 | return ((val) << A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK; |
8256 | } |
8257 | |
8258 | #define REG_A7XX_HLSQ_CONTROL_2_REG 0x0000a9c8 |
8259 | #define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff |
8260 | #define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 |
8261 | static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) |
8262 | { |
8263 | return ((val) << A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; |
8264 | } |
8265 | #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 |
8266 | #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 |
8267 | static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) |
8268 | { |
8269 | return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; |
8270 | } |
8271 | #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 |
8272 | #define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 |
8273 | static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) |
8274 | { |
8275 | return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; |
8276 | } |
8277 | #define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK 0xff000000 |
8278 | #define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT 24 |
8279 | static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val) |
8280 | { |
8281 | return ((val) << A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK; |
8282 | } |
8283 | |
8284 | #define REG_A7XX_HLSQ_CONTROL_3_REG 0x0000a9c9 |
8285 | #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff |
8286 | #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 |
8287 | static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) |
8288 | { |
8289 | return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK; |
8290 | } |
8291 | #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00 |
8292 | #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8 |
8293 | static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) |
8294 | { |
8295 | return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK; |
8296 | } |
8297 | #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000 |
8298 | #define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16 |
8299 | static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) |
8300 | { |
8301 | return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK; |
8302 | } |
8303 | #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000 |
8304 | #define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24 |
8305 | static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) |
8306 | { |
8307 | return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; |
8308 | } |
8309 | |
8310 | #define REG_A7XX_HLSQ_CONTROL_4_REG 0x0000a9ca |
8311 | #define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff |
8312 | #define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0 |
8313 | static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE(uint32_t val) |
8314 | { |
8315 | return ((val) << A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK; |
8316 | } |
8317 | #define A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK 0x0000ff00 |
8318 | #define A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT 8 |
8319 | static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE(uint32_t val) |
8320 | { |
8321 | return ((val) << A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_IJ_LINEAR_SAMPLE__MASK; |
8322 | } |
8323 | #define A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK 0x00ff0000 |
8324 | #define A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT 16 |
8325 | static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(uint32_t val) |
8326 | { |
8327 | return ((val) << A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_XYCOORDREGID__MASK; |
8328 | } |
8329 | #define A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK 0xff000000 |
8330 | #define A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT 24 |
8331 | static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) |
8332 | { |
8333 | return ((val) << A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; |
8334 | } |
8335 | |
8336 | #define REG_A7XX_HLSQ_CONTROL_5_REG 0x0000a9cb |
8337 | #define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff |
8338 | #define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0 |
8339 | static inline uint32_t A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val) |
8340 | { |
8341 | return ((val) << A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK; |
8342 | } |
8343 | #define A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00 |
8344 | #define A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8 |
8345 | static inline uint32_t A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val) |
8346 | { |
8347 | return ((val) << A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK; |
8348 | } |
8349 | |
8350 | #define REG_A7XX_HLSQ_CS_CNTL 0x0000a9cd |
8351 | #define A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff |
8352 | #define A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0 |
8353 | static inline uint32_t A7XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) |
8354 | { |
8355 | assert(!(val & 0x3)); |
8356 | return (((val >> 2)) << A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK; |
8357 | } |
8358 | #define A7XX_HLSQ_CS_CNTL_ENABLED 0x00000100 |
8359 | #define A7XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 |
8360 | |
8361 | #define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990 |
8362 | #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 |
8363 | #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 |
8364 | static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) |
8365 | { |
8366 | return ((val) << A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; |
8367 | } |
8368 | #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc |
8369 | #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 |
8370 | static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) |
8371 | { |
8372 | return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; |
8373 | } |
8374 | #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 |
8375 | #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 |
8376 | static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) |
8377 | { |
8378 | return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; |
8379 | } |
8380 | #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 |
8381 | #define A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 |
8382 | static inline uint32_t A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) |
8383 | { |
8384 | return ((val) << A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A6XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; |
8385 | } |
8386 | |
8387 | #define REG_A6XX_HLSQ_CS_NDRANGE_1 0x0000b991 |
8388 | #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff |
8389 | #define A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0 |
8390 | static inline uint32_t A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) |
8391 | { |
8392 | return ((val) << A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; |
8393 | } |
8394 | |
8395 | #define REG_A6XX_HLSQ_CS_NDRANGE_2 0x0000b992 |
8396 | #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff |
8397 | #define A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0 |
8398 | static inline uint32_t A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) |
8399 | { |
8400 | return ((val) << A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A6XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; |
8401 | } |
8402 | |
8403 | #define REG_A6XX_HLSQ_CS_NDRANGE_3 0x0000b993 |
8404 | #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff |
8405 | #define A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0 |
8406 | static inline uint32_t A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) |
8407 | { |
8408 | return ((val) << A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; |
8409 | } |
8410 | |
8411 | #define REG_A6XX_HLSQ_CS_NDRANGE_4 0x0000b994 |
8412 | #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff |
8413 | #define A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0 |
8414 | static inline uint32_t A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) |
8415 | { |
8416 | return ((val) << A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A6XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; |
8417 | } |
8418 | |
8419 | #define REG_A6XX_HLSQ_CS_NDRANGE_5 0x0000b995 |
8420 | #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff |
8421 | #define A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0 |
8422 | static inline uint32_t A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) |
8423 | { |
8424 | return ((val) << A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; |
8425 | } |
8426 | |
8427 | #define REG_A6XX_HLSQ_CS_NDRANGE_6 0x0000b996 |
8428 | #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff |
8429 | #define A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0 |
8430 | static inline uint32_t A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) |
8431 | { |
8432 | return ((val) << A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A6XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; |
8433 | } |
8434 | |
8435 | #define REG_A6XX_HLSQ_CS_CNTL_0 0x0000b997 |
8436 | #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff |
8437 | #define A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0 |
8438 | static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val) |
8439 | { |
8440 | return ((val) << A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK; |
8441 | } |
8442 | #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK 0x0000ff00 |
8443 | #define A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT 8 |
8444 | static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(uint32_t val) |
8445 | { |
8446 | return ((val) << A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID__MASK; |
8447 | } |
8448 | #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK 0x00ff0000 |
8449 | #define A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT 16 |
8450 | static inline uint32_t A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(uint32_t val) |
8451 | { |
8452 | return ((val) << A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID__MASK; |
8453 | } |
8454 | #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000 |
8455 | #define A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24 |
8456 | static inline uint32_t A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val) |
8457 | { |
8458 | return ((val) << A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK; |
8459 | } |
8460 | |
8461 | #define REG_A6XX_HLSQ_CS_CNTL_1 0x0000b998 |
8462 | #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff |
8463 | #define A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 |
8464 | static inline uint32_t A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) |
8465 | { |
8466 | return ((val) << A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK; |
8467 | } |
8468 | #define A6XX_HLSQ_CS_CNTL_1_SINGLE_SP_CORE 0x00000100 |
8469 | #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200 |
8470 | #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9 |
8471 | static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) |
8472 | { |
8473 | return ((val) << A6XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A6XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK; |
8474 | } |
8475 | #define A6XX_HLSQ_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400 |
8476 | |
8477 | #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_X 0x0000b999 |
8478 | |
8479 | #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000b99a |
8480 | |
8481 | #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b |
8482 | |
8483 | #define REG_A7XX_HLSQ_CS_NDRANGE_0 0x0000a9d4 |
8484 | #define A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 |
8485 | #define A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 |
8486 | static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) |
8487 | { |
8488 | return ((val) << A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; |
8489 | } |
8490 | #define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc |
8491 | #define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 |
8492 | static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) |
8493 | { |
8494 | return ((val) << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; |
8495 | } |
8496 | #define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 |
8497 | #define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 |
8498 | static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) |
8499 | { |
8500 | return ((val) << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; |
8501 | } |
8502 | #define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 |
8503 | #define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 |
8504 | static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) |
8505 | { |
8506 | return ((val) << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; |
8507 | } |
8508 | |
8509 | #define REG_A7XX_HLSQ_CS_NDRANGE_1 0x0000a9d5 |
8510 | #define A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff |
8511 | #define A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0 |
8512 | static inline uint32_t A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) |
8513 | { |
8514 | return ((val) << A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; |
8515 | } |
8516 | |
8517 | #define REG_A7XX_HLSQ_CS_NDRANGE_2 0x0000a9d6 |
8518 | #define A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff |
8519 | #define A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0 |
8520 | static inline uint32_t A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) |
8521 | { |
8522 | return ((val) << A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; |
8523 | } |
8524 | |
8525 | #define REG_A7XX_HLSQ_CS_NDRANGE_3 0x0000a9d7 |
8526 | #define A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff |
8527 | #define A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0 |
8528 | static inline uint32_t A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) |
8529 | { |
8530 | return ((val) << A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; |
8531 | } |
8532 | |
8533 | #define REG_A7XX_HLSQ_CS_NDRANGE_4 0x0000a9d8 |
8534 | #define A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff |
8535 | #define A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0 |
8536 | static inline uint32_t A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) |
8537 | { |
8538 | return ((val) << A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; |
8539 | } |
8540 | |
8541 | #define REG_A7XX_HLSQ_CS_NDRANGE_5 0x0000a9d9 |
8542 | #define A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff |
8543 | #define A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0 |
8544 | static inline uint32_t A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) |
8545 | { |
8546 | return ((val) << A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; |
8547 | } |
8548 | |
8549 | #define REG_A7XX_HLSQ_CS_NDRANGE_6 0x0000a9da |
8550 | #define A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff |
8551 | #define A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0 |
8552 | static inline uint32_t A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) |
8553 | { |
8554 | return ((val) << A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; |
8555 | } |
8556 | |
8557 | #define REG_A7XX_HLSQ_CS_KERNEL_GROUP_X 0x0000a9dc |
8558 | |
8559 | #define REG_A7XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000a9dd |
8560 | |
8561 | #define REG_A7XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000a9de |
8562 | |
8563 | #define REG_A7XX_HLSQ_CS_CNTL_1 0x0000a9db |
8564 | #define A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff |
8565 | #define A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 |
8566 | static inline uint32_t A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) |
8567 | { |
8568 | return ((val) << A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK; |
8569 | } |
8570 | #define A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200 |
8571 | #define A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9 |
8572 | static inline uint32_t A7XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) |
8573 | { |
8574 | return ((val) << A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK; |
8575 | } |
8576 | #define A7XX_HLSQ_CS_CNTL_1_UNK11 0x00000800 |
8577 | #define A7XX_HLSQ_CS_CNTL_1_UNK22 0x00400000 |
8578 | #define A7XX_HLSQ_CS_CNTL_1_UNK26 0x04000000 |
8579 | #define A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK 0x78000000 |
8580 | #define A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT 27 |
8581 | static inline uint32_t A7XX_HLSQ_CS_CNTL_1_YALIGN(enum a7xx_cs_yalign val) |
8582 | { |
8583 | return ((val) << A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT) & A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK; |
8584 | } |
8585 | |
8586 | #define REG_A7XX_HLSQ_CS_LOCAL_SIZE 0x0000a9df |
8587 | #define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK 0x00000ffc |
8588 | #define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT 2 |
8589 | static inline uint32_t A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX(uint32_t val) |
8590 | { |
8591 | return ((val) << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK; |
8592 | } |
8593 | #define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK 0x003ff000 |
8594 | #define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT 12 |
8595 | static inline uint32_t A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY(uint32_t val) |
8596 | { |
8597 | return ((val) << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK; |
8598 | } |
8599 | #define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK 0xffc00000 |
8600 | #define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT 22 |
8601 | static inline uint32_t A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ(uint32_t val) |
8602 | { |
8603 | return ((val) << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK; |
8604 | } |
8605 | |
8606 | #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0 |
8607 | |
8608 | #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1 |
8609 | |
8610 | #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3 |
8611 | |
8612 | #define REG_A6XX_HLSQ_CS_BINDLESS_BASE(i0) (0x0000b9c0 + 0x2*(i0)) |
8613 | |
8614 | static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; } |
8615 | #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 |
8616 | #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 |
8617 | static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) |
8618 | { |
8619 | return ((val) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; |
8620 | } |
8621 | #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc |
8622 | #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 |
8623 | static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) |
8624 | { |
8625 | assert(!(val & 0x3)); |
8626 | return (((val >> 2)) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; |
8627 | } |
8628 | |
8629 | #define REG_A6XX_HLSQ_CS_UNKNOWN_B9D0 0x0000b9d0 |
8630 | #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK 0x0000001f |
8631 | #define A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT 0 |
8632 | static inline uint32_t A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE(uint32_t val) |
8633 | { |
8634 | return ((val) << A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__SHIFT) & A6XX_HLSQ_CS_UNKNOWN_B9D0_SHARED_SIZE__MASK; |
8635 | } |
8636 | #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK5 0x00000020 |
8637 | #define A6XX_HLSQ_CS_UNKNOWN_B9D0_UNK6 0x00000040 |
8638 | |
8639 | #define REG_A6XX_HLSQ_DRAW_CMD 0x0000bb00 |
8640 | #define A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK 0x000000ff |
8641 | #define A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT 0 |
8642 | static inline uint32_t A6XX_HLSQ_DRAW_CMD_STATE_ID(uint32_t val) |
8643 | { |
8644 | return ((val) << A6XX_HLSQ_DRAW_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DRAW_CMD_STATE_ID__MASK; |
8645 | } |
8646 | |
8647 | #define REG_A6XX_HLSQ_DISPATCH_CMD 0x0000bb01 |
8648 | #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK 0x000000ff |
8649 | #define A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT 0 |
8650 | static inline uint32_t A6XX_HLSQ_DISPATCH_CMD_STATE_ID(uint32_t val) |
8651 | { |
8652 | return ((val) << A6XX_HLSQ_DISPATCH_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_DISPATCH_CMD_STATE_ID__MASK; |
8653 | } |
8654 | |
8655 | #define REG_A6XX_HLSQ_EVENT_CMD 0x0000bb02 |
8656 | #define A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK 0x00ff0000 |
8657 | #define A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT 16 |
8658 | static inline uint32_t A6XX_HLSQ_EVENT_CMD_STATE_ID(uint32_t val) |
8659 | { |
8660 | return ((val) << A6XX_HLSQ_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_EVENT_CMD_STATE_ID__MASK; |
8661 | } |
8662 | #define A6XX_HLSQ_EVENT_CMD_EVENT__MASK 0x0000007f |
8663 | #define A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT 0 |
8664 | static inline uint32_t A6XX_HLSQ_EVENT_CMD_EVENT(enum vgt_event_type val) |
8665 | { |
8666 | return ((val) << A6XX_HLSQ_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_EVENT_CMD_EVENT__MASK; |
8667 | } |
8668 | |
8669 | #define REG_A6XX_HLSQ_INVALIDATE_CMD 0x0000bb08 |
8670 | #define A6XX_HLSQ_INVALIDATE_CMD_VS_STATE 0x00000001 |
8671 | #define A6XX_HLSQ_INVALIDATE_CMD_HS_STATE 0x00000002 |
8672 | #define A6XX_HLSQ_INVALIDATE_CMD_DS_STATE 0x00000004 |
8673 | #define A6XX_HLSQ_INVALIDATE_CMD_GS_STATE 0x00000008 |
8674 | #define A6XX_HLSQ_INVALIDATE_CMD_FS_STATE 0x00000010 |
8675 | #define A6XX_HLSQ_INVALIDATE_CMD_CS_STATE 0x00000020 |
8676 | #define A6XX_HLSQ_INVALIDATE_CMD_CS_IBO 0x00000040 |
8677 | #define A6XX_HLSQ_INVALIDATE_CMD_GFX_IBO 0x00000080 |
8678 | #define A6XX_HLSQ_INVALIDATE_CMD_CS_SHARED_CONST 0x00080000 |
8679 | #define A6XX_HLSQ_INVALIDATE_CMD_GFX_SHARED_CONST 0x00000100 |
8680 | #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK 0x00003e00 |
8681 | #define A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT 9 |
8682 | static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val) |
8683 | { |
8684 | return ((val) << A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK; |
8685 | } |
8686 | #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK 0x0007c000 |
8687 | #define A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT 14 |
8688 | static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val) |
8689 | { |
8690 | return ((val) << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK; |
8691 | } |
8692 | |
8693 | #define REG_A7XX_HLSQ_INVALIDATE_CMD 0x0000ab1f |
8694 | #define A7XX_HLSQ_INVALIDATE_CMD_VS_STATE 0x00000001 |
8695 | #define A7XX_HLSQ_INVALIDATE_CMD_HS_STATE 0x00000002 |
8696 | #define A7XX_HLSQ_INVALIDATE_CMD_DS_STATE 0x00000004 |
8697 | #define A7XX_HLSQ_INVALIDATE_CMD_GS_STATE 0x00000008 |
8698 | #define A7XX_HLSQ_INVALIDATE_CMD_FS_STATE 0x00000010 |
8699 | #define A7XX_HLSQ_INVALIDATE_CMD_CS_STATE 0x00000020 |
8700 | #define A7XX_HLSQ_INVALIDATE_CMD_CS_IBO 0x00000040 |
8701 | #define A7XX_HLSQ_INVALIDATE_CMD_GFX_IBO 0x00000080 |
8702 | #define A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK 0x0001fe00 |
8703 | #define A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT 9 |
8704 | static inline uint32_t A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val) |
8705 | { |
8706 | return ((val) << A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK; |
8707 | } |
8708 | #define A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK 0x01fe0000 |
8709 | #define A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT 17 |
8710 | static inline uint32_t A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val) |
8711 | { |
8712 | return ((val) << A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK; |
8713 | } |
8714 | |
8715 | #define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10 |
8716 | #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff |
8717 | #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0 |
8718 | static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) |
8719 | { |
8720 | assert(!(val & 0x3)); |
8721 | return (((val >> 2)) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK; |
8722 | } |
8723 | #define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100 |
8724 | #define A6XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 |
8725 | |
8726 | #define REG_A7XX_HLSQ_FS_CNTL 0x0000ab03 |
8727 | #define A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff |
8728 | #define A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0 |
8729 | static inline uint32_t A7XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) |
8730 | { |
8731 | assert(!(val & 0x3)); |
8732 | return (((val >> 2)) << A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK; |
8733 | } |
8734 | #define A7XX_HLSQ_FS_CNTL_ENABLED 0x00000100 |
8735 | #define A7XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 |
8736 | |
8737 | #define REG_A7XX_HLSQ_SHARED_CONSTS_IMM(i0) (0x0000ab40 + 0x1*(i0)) |
8738 | |
8739 | #define REG_A6XX_HLSQ_SHARED_CONSTS 0x0000bb11 |
8740 | #define A6XX_HLSQ_SHARED_CONSTS_ENABLE 0x00000001 |
8741 | |
8742 | #define REG_A6XX_HLSQ_BINDLESS_BASE(i0) (0x0000bb20 + 0x2*(i0)) |
8743 | |
8744 | static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; } |
8745 | #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 |
8746 | #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 |
8747 | static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) |
8748 | { |
8749 | return ((val) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; |
8750 | } |
8751 | #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc |
8752 | #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 |
8753 | static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) |
8754 | { |
8755 | assert(!(val & 0x3)); |
8756 | return (((val >> 2)) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; |
8757 | } |
8758 | |
8759 | #define REG_A6XX_HLSQ_2D_EVENT_CMD 0x0000bd80 |
8760 | #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK 0x0000ff00 |
8761 | #define A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT 8 |
8762 | static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_STATE_ID(uint32_t val) |
8763 | { |
8764 | return ((val) << A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_STATE_ID__MASK; |
8765 | } |
8766 | #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK 0x0000007f |
8767 | #define A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT 0 |
8768 | static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val) |
8769 | { |
8770 | return ((val) << A6XX_HLSQ_2D_EVENT_CMD_EVENT__SHIFT) & A6XX_HLSQ_2D_EVENT_CMD_EVENT__MASK; |
8771 | } |
8772 | |
8773 | #define REG_A6XX_HLSQ_UNKNOWN_BE00 0x0000be00 |
8774 | |
8775 | #define REG_A6XX_HLSQ_UNKNOWN_BE01 0x0000be01 |
8776 | |
8777 | #define REG_A6XX_HLSQ_DBG_ECO_CNTL 0x0000be04 |
8778 | |
8779 | #define REG_A6XX_HLSQ_ADDR_MODE_CNTL 0x0000be05 |
8780 | |
8781 | #define REG_A6XX_HLSQ_UNKNOWN_BE08 0x0000be08 |
8782 | |
8783 | #define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(i0) (0x0000be10 + 0x1*(i0)) |
8784 | |
8785 | #define REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22 |
8786 | |
8787 | #define REG_A7XX_SP_AHB_READ_APERTURE 0x0000c000 |
8788 | |
8789 | #define REG_A7XX_SP_UNKNOWN_0CE2 0x00000ce2 |
8790 | |
8791 | #define REG_A7XX_SP_UNKNOWN_0CE4 0x00000ce4 |
8792 | |
8793 | #define REG_A7XX_SP_UNKNOWN_0CE6 0x00000ce6 |
8794 | |
8795 | #define REG_A6XX_CP_EVENT_START 0x0000d600 |
8796 | #define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff |
8797 | #define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0 |
8798 | static inline uint32_t A6XX_CP_EVENT_START_STATE_ID(uint32_t val) |
8799 | { |
8800 | return ((val) << A6XX_CP_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_EVENT_START_STATE_ID__MASK; |
8801 | } |
8802 | |
8803 | #define REG_A6XX_CP_EVENT_END 0x0000d601 |
8804 | #define A6XX_CP_EVENT_END_STATE_ID__MASK 0x000000ff |
8805 | #define A6XX_CP_EVENT_END_STATE_ID__SHIFT 0 |
8806 | static inline uint32_t A6XX_CP_EVENT_END_STATE_ID(uint32_t val) |
8807 | { |
8808 | return ((val) << A6XX_CP_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_EVENT_END_STATE_ID__MASK; |
8809 | } |
8810 | |
8811 | #define REG_A6XX_CP_2D_EVENT_START 0x0000d700 |
8812 | #define A6XX_CP_2D_EVENT_START_STATE_ID__MASK 0x000000ff |
8813 | #define A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT 0 |
8814 | static inline uint32_t A6XX_CP_2D_EVENT_START_STATE_ID(uint32_t val) |
8815 | { |
8816 | return ((val) << A6XX_CP_2D_EVENT_START_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_START_STATE_ID__MASK; |
8817 | } |
8818 | |
8819 | #define REG_A6XX_CP_2D_EVENT_END 0x0000d701 |
8820 | #define A6XX_CP_2D_EVENT_END_STATE_ID__MASK 0x000000ff |
8821 | #define A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT 0 |
8822 | static inline uint32_t A6XX_CP_2D_EVENT_END_STATE_ID(uint32_t val) |
8823 | { |
8824 | return ((val) << A6XX_CP_2D_EVENT_END_STATE_ID__SHIFT) & A6XX_CP_2D_EVENT_END_STATE_ID__MASK; |
8825 | } |
8826 | |
8827 | #define REG_A6XX_TEX_SAMP_0 0x00000000 |
8828 | #define A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001 |
8829 | #define A6XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006 |
8830 | #define A6XX_TEX_SAMP_0_XY_MAG__SHIFT 1 |
8831 | static inline uint32_t A6XX_TEX_SAMP_0_XY_MAG(enum a6xx_tex_filter val) |
8832 | { |
8833 | return ((val) << A6XX_TEX_SAMP_0_XY_MAG__SHIFT) & A6XX_TEX_SAMP_0_XY_MAG__MASK; |
8834 | } |
8835 | #define A6XX_TEX_SAMP_0_XY_MIN__MASK 0x00000018 |
8836 | #define A6XX_TEX_SAMP_0_XY_MIN__SHIFT 3 |
8837 | static inline uint32_t A6XX_TEX_SAMP_0_XY_MIN(enum a6xx_tex_filter val) |
8838 | { |
8839 | return ((val) << A6XX_TEX_SAMP_0_XY_MIN__SHIFT) & A6XX_TEX_SAMP_0_XY_MIN__MASK; |
8840 | } |
8841 | #define A6XX_TEX_SAMP_0_WRAP_S__MASK 0x000000e0 |
8842 | #define A6XX_TEX_SAMP_0_WRAP_S__SHIFT 5 |
8843 | static inline uint32_t A6XX_TEX_SAMP_0_WRAP_S(enum a6xx_tex_clamp val) |
8844 | { |
8845 | return ((val) << A6XX_TEX_SAMP_0_WRAP_S__SHIFT) & A6XX_TEX_SAMP_0_WRAP_S__MASK; |
8846 | } |
8847 | #define A6XX_TEX_SAMP_0_WRAP_T__MASK 0x00000700 |
8848 | #define A6XX_TEX_SAMP_0_WRAP_T__SHIFT 8 |
8849 | static inline uint32_t A6XX_TEX_SAMP_0_WRAP_T(enum a6xx_tex_clamp val) |
8850 | { |
8851 | return ((val) << A6XX_TEX_SAMP_0_WRAP_T__SHIFT) & A6XX_TEX_SAMP_0_WRAP_T__MASK; |
8852 | } |
8853 | #define A6XX_TEX_SAMP_0_WRAP_R__MASK 0x00003800 |
8854 | #define A6XX_TEX_SAMP_0_WRAP_R__SHIFT 11 |
8855 | static inline uint32_t A6XX_TEX_SAMP_0_WRAP_R(enum a6xx_tex_clamp val) |
8856 | { |
8857 | return ((val) << A6XX_TEX_SAMP_0_WRAP_R__SHIFT) & A6XX_TEX_SAMP_0_WRAP_R__MASK; |
8858 | } |
8859 | #define A6XX_TEX_SAMP_0_ANISO__MASK 0x0001c000 |
8860 | #define A6XX_TEX_SAMP_0_ANISO__SHIFT 14 |
8861 | static inline uint32_t A6XX_TEX_SAMP_0_ANISO(enum a6xx_tex_aniso val) |
8862 | { |
8863 | return ((val) << A6XX_TEX_SAMP_0_ANISO__SHIFT) & A6XX_TEX_SAMP_0_ANISO__MASK; |
8864 | } |
8865 | #define A6XX_TEX_SAMP_0_LOD_BIAS__MASK 0xfff80000 |
8866 | #define A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT 19 |
8867 | static inline uint32_t A6XX_TEX_SAMP_0_LOD_BIAS(float val) |
8868 | { |
8869 | return ((((int32_t)(val * 256.0))) << A6XX_TEX_SAMP_0_LOD_BIAS__SHIFT) & A6XX_TEX_SAMP_0_LOD_BIAS__MASK; |
8870 | } |
8871 | |
8872 | #define REG_A6XX_TEX_SAMP_1 0x00000001 |
8873 | #define A6XX_TEX_SAMP_1_CLAMPENABLE 0x00000001 |
8874 | #define A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK 0x0000000e |
8875 | #define A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT 1 |
8876 | static inline uint32_t A6XX_TEX_SAMP_1_COMPARE_FUNC(enum adreno_compare_func val) |
8877 | { |
8878 | return ((val) << A6XX_TEX_SAMP_1_COMPARE_FUNC__SHIFT) & A6XX_TEX_SAMP_1_COMPARE_FUNC__MASK; |
8879 | } |
8880 | #define A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF 0x00000010 |
8881 | #define A6XX_TEX_SAMP_1_UNNORM_COORDS 0x00000020 |
8882 | #define A6XX_TEX_SAMP_1_MIPFILTER_LINEAR_FAR 0x00000040 |
8883 | #define A6XX_TEX_SAMP_1_MAX_LOD__MASK 0x000fff00 |
8884 | #define A6XX_TEX_SAMP_1_MAX_LOD__SHIFT 8 |
8885 | static inline uint32_t A6XX_TEX_SAMP_1_MAX_LOD(float val) |
8886 | { |
8887 | return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A6XX_TEX_SAMP_1_MAX_LOD__MASK; |
8888 | } |
8889 | #define A6XX_TEX_SAMP_1_MIN_LOD__MASK 0xfff00000 |
8890 | #define A6XX_TEX_SAMP_1_MIN_LOD__SHIFT 20 |
8891 | static inline uint32_t A6XX_TEX_SAMP_1_MIN_LOD(float val) |
8892 | { |
8893 | return ((((uint32_t)(val * 256.0))) << A6XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A6XX_TEX_SAMP_1_MIN_LOD__MASK; |
8894 | } |
8895 | |
8896 | #define REG_A6XX_TEX_SAMP_2 0x00000002 |
8897 | #define A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK 0x00000003 |
8898 | #define A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT 0 |
8899 | static inline uint32_t A6XX_TEX_SAMP_2_REDUCTION_MODE(enum a6xx_reduction_mode val) |
8900 | { |
8901 | return ((val) << A6XX_TEX_SAMP_2_REDUCTION_MODE__SHIFT) & A6XX_TEX_SAMP_2_REDUCTION_MODE__MASK; |
8902 | } |
8903 | #define A6XX_TEX_SAMP_2_CHROMA_LINEAR 0x00000020 |
8904 | #define A6XX_TEX_SAMP_2_BCOLOR__MASK 0xffffff80 |
8905 | #define A6XX_TEX_SAMP_2_BCOLOR__SHIFT 7 |
8906 | static inline uint32_t A6XX_TEX_SAMP_2_BCOLOR(uint32_t val) |
8907 | { |
8908 | return ((val) << A6XX_TEX_SAMP_2_BCOLOR__SHIFT) & A6XX_TEX_SAMP_2_BCOLOR__MASK; |
8909 | } |
8910 | |
8911 | #define REG_A6XX_TEX_SAMP_3 0x00000003 |
8912 | |
8913 | #define REG_A6XX_TEX_CONST_0 0x00000000 |
8914 | #define A6XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003 |
8915 | #define A6XX_TEX_CONST_0_TILE_MODE__SHIFT 0 |
8916 | static inline uint32_t A6XX_TEX_CONST_0_TILE_MODE(enum a6xx_tile_mode val) |
8917 | { |
8918 | return ((val) << A6XX_TEX_CONST_0_TILE_MODE__SHIFT) & A6XX_TEX_CONST_0_TILE_MODE__MASK; |
8919 | } |
8920 | #define A6XX_TEX_CONST_0_SRGB 0x00000004 |
8921 | #define A6XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 |
8922 | #define A6XX_TEX_CONST_0_SWIZ_X__SHIFT 4 |
8923 | static inline uint32_t A6XX_TEX_CONST_0_SWIZ_X(enum a6xx_tex_swiz val) |
8924 | { |
8925 | return ((val) << A6XX_TEX_CONST_0_SWIZ_X__SHIFT) & A6XX_TEX_CONST_0_SWIZ_X__MASK; |
8926 | } |
8927 | #define A6XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380 |
8928 | #define A6XX_TEX_CONST_0_SWIZ_Y__SHIFT 7 |
8929 | static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Y(enum a6xx_tex_swiz val) |
8930 | { |
8931 | return ((val) << A6XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Y__MASK; |
8932 | } |
8933 | #define A6XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00 |
8934 | #define A6XX_TEX_CONST_0_SWIZ_Z__SHIFT 10 |
8935 | static inline uint32_t A6XX_TEX_CONST_0_SWIZ_Z(enum a6xx_tex_swiz val) |
8936 | { |
8937 | return ((val) << A6XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A6XX_TEX_CONST_0_SWIZ_Z__MASK; |
8938 | } |
8939 | #define A6XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000 |
8940 | #define A6XX_TEX_CONST_0_SWIZ_W__SHIFT 13 |
8941 | static inline uint32_t A6XX_TEX_CONST_0_SWIZ_W(enum a6xx_tex_swiz val) |
8942 | { |
8943 | return ((val) << A6XX_TEX_CONST_0_SWIZ_W__SHIFT) & A6XX_TEX_CONST_0_SWIZ_W__MASK; |
8944 | } |
8945 | #define A6XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000 |
8946 | #define A6XX_TEX_CONST_0_MIPLVLS__SHIFT 16 |
8947 | static inline uint32_t A6XX_TEX_CONST_0_MIPLVLS(uint32_t val) |
8948 | { |
8949 | return ((val) << A6XX_TEX_CONST_0_MIPLVLS__SHIFT) & A6XX_TEX_CONST_0_MIPLVLS__MASK; |
8950 | } |
8951 | #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_X 0x00010000 |
8952 | #define A6XX_TEX_CONST_0_CHROMA_MIDPOINT_Y 0x00040000 |
8953 | #define A6XX_TEX_CONST_0_SAMPLES__MASK 0x00300000 |
8954 | #define A6XX_TEX_CONST_0_SAMPLES__SHIFT 20 |
8955 | static inline uint32_t A6XX_TEX_CONST_0_SAMPLES(enum a3xx_msaa_samples val) |
8956 | { |
8957 | return ((val) << A6XX_TEX_CONST_0_SAMPLES__SHIFT) & A6XX_TEX_CONST_0_SAMPLES__MASK; |
8958 | } |
8959 | #define A6XX_TEX_CONST_0_FMT__MASK 0x3fc00000 |
8960 | #define A6XX_TEX_CONST_0_FMT__SHIFT 22 |
8961 | static inline uint32_t A6XX_TEX_CONST_0_FMT(enum a6xx_format val) |
8962 | { |
8963 | return ((val) << A6XX_TEX_CONST_0_FMT__SHIFT) & A6XX_TEX_CONST_0_FMT__MASK; |
8964 | } |
8965 | #define A6XX_TEX_CONST_0_SWAP__MASK 0xc0000000 |
8966 | #define A6XX_TEX_CONST_0_SWAP__SHIFT 30 |
8967 | static inline uint32_t A6XX_TEX_CONST_0_SWAP(enum a3xx_color_swap val) |
8968 | { |
8969 | return ((val) << A6XX_TEX_CONST_0_SWAP__SHIFT) & A6XX_TEX_CONST_0_SWAP__MASK; |
8970 | } |
8971 | |
8972 | #define REG_A6XX_TEX_CONST_1 0x00000001 |
8973 | #define A6XX_TEX_CONST_1_WIDTH__MASK 0x00007fff |
8974 | #define A6XX_TEX_CONST_1_WIDTH__SHIFT 0 |
8975 | static inline uint32_t A6XX_TEX_CONST_1_WIDTH(uint32_t val) |
8976 | { |
8977 | return ((val) << A6XX_TEX_CONST_1_WIDTH__SHIFT) & A6XX_TEX_CONST_1_WIDTH__MASK; |
8978 | } |
8979 | #define A6XX_TEX_CONST_1_HEIGHT__MASK 0x3fff8000 |
8980 | #define A6XX_TEX_CONST_1_HEIGHT__SHIFT 15 |
8981 | static inline uint32_t A6XX_TEX_CONST_1_HEIGHT(uint32_t val) |
8982 | { |
8983 | return ((val) << A6XX_TEX_CONST_1_HEIGHT__SHIFT) & A6XX_TEX_CONST_1_HEIGHT__MASK; |
8984 | } |
8985 | |
8986 | #define REG_A6XX_TEX_CONST_2 0x00000002 |
8987 | #define A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK 0x0000fff0 |
8988 | #define A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT 4 |
8989 | static inline uint32_t A6XX_TEX_CONST_2_STRUCTSIZETEXELS(uint32_t val) |
8990 | { |
8991 | return ((val) << A6XX_TEX_CONST_2_STRUCTSIZETEXELS__SHIFT) & A6XX_TEX_CONST_2_STRUCTSIZETEXELS__MASK; |
8992 | } |
8993 | #define A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK 0x003f0000 |
8994 | #define A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT 16 |
8995 | static inline uint32_t A6XX_TEX_CONST_2_STARTOFFSETTEXELS(uint32_t val) |
8996 | { |
8997 | return ((val) << A6XX_TEX_CONST_2_STARTOFFSETTEXELS__SHIFT) & A6XX_TEX_CONST_2_STARTOFFSETTEXELS__MASK; |
8998 | } |
8999 | #define A6XX_TEX_CONST_2_PITCHALIGN__MASK 0x0000000f |
9000 | #define A6XX_TEX_CONST_2_PITCHALIGN__SHIFT 0 |
9001 | static inline uint32_t A6XX_TEX_CONST_2_PITCHALIGN(uint32_t val) |
9002 | { |
9003 | return ((val) << A6XX_TEX_CONST_2_PITCHALIGN__SHIFT) & A6XX_TEX_CONST_2_PITCHALIGN__MASK; |
9004 | } |
9005 | #define A6XX_TEX_CONST_2_PITCH__MASK 0x1fffff80 |
9006 | #define A6XX_TEX_CONST_2_PITCH__SHIFT 7 |
9007 | static inline uint32_t A6XX_TEX_CONST_2_PITCH(uint32_t val) |
9008 | { |
9009 | return ((val) << A6XX_TEX_CONST_2_PITCH__SHIFT) & A6XX_TEX_CONST_2_PITCH__MASK; |
9010 | } |
9011 | #define A6XX_TEX_CONST_2_TYPE__MASK 0xe0000000 |
9012 | #define A6XX_TEX_CONST_2_TYPE__SHIFT 29 |
9013 | static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val) |
9014 | { |
9015 | return ((val) << A6XX_TEX_CONST_2_TYPE__SHIFT) & A6XX_TEX_CONST_2_TYPE__MASK; |
9016 | } |
9017 | |
9018 | #define REG_A6XX_TEX_CONST_3 0x00000003 |
9019 | #define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x007fffff |
9020 | #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 |
9021 | static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) |
9022 | { |
9023 | assert(!(val & 0xfff)); |
9024 | return (((val >> 12)) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK; |
9025 | } |
9026 | #define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000 |
9027 | #define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23 |
9028 | static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) |
9029 | { |
9030 | assert(!(val & 0xfff)); |
9031 | return (((val >> 12)) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK; |
9032 | } |
9033 | #define A6XX_TEX_CONST_3_TILE_ALL 0x08000000 |
9034 | #define A6XX_TEX_CONST_3_FLAG 0x10000000 |
9035 | |
9036 | #define REG_A6XX_TEX_CONST_4 0x00000004 |
9037 | #define A6XX_TEX_CONST_4_BASE_LO__MASK 0xffffffe0 |
9038 | #define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5 |
9039 | static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val) |
9040 | { |
9041 | assert(!(val & 0x1f)); |
9042 | return (((val >> 5)) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK; |
9043 | } |
9044 | |
9045 | #define REG_A6XX_TEX_CONST_5 0x00000005 |
9046 | #define A6XX_TEX_CONST_5_BASE_HI__MASK 0x0001ffff |
9047 | #define A6XX_TEX_CONST_5_BASE_HI__SHIFT 0 |
9048 | static inline uint32_t A6XX_TEX_CONST_5_BASE_HI(uint32_t val) |
9049 | { |
9050 | return ((val) << A6XX_TEX_CONST_5_BASE_HI__SHIFT) & A6XX_TEX_CONST_5_BASE_HI__MASK; |
9051 | } |
9052 | #define A6XX_TEX_CONST_5_DEPTH__MASK 0x3ffe0000 |
9053 | #define A6XX_TEX_CONST_5_DEPTH__SHIFT 17 |
9054 | static inline uint32_t A6XX_TEX_CONST_5_DEPTH(uint32_t val) |
9055 | { |
9056 | return ((val) << A6XX_TEX_CONST_5_DEPTH__SHIFT) & A6XX_TEX_CONST_5_DEPTH__MASK; |
9057 | } |
9058 | |
9059 | #define REG_A6XX_TEX_CONST_6 0x00000006 |
9060 | #define A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK 0x00000fff |
9061 | #define A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT 0 |
9062 | static inline uint32_t A6XX_TEX_CONST_6_MIN_LOD_CLAMP(float val) |
9063 | { |
9064 | return ((((uint32_t)(val * 256.0))) << A6XX_TEX_CONST_6_MIN_LOD_CLAMP__SHIFT) & A6XX_TEX_CONST_6_MIN_LOD_CLAMP__MASK; |
9065 | } |
9066 | #define A6XX_TEX_CONST_6_PLANE_PITCH__MASK 0xffffff00 |
9067 | #define A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT 8 |
9068 | static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val) |
9069 | { |
9070 | return ((val) << A6XX_TEX_CONST_6_PLANE_PITCH__SHIFT) & A6XX_TEX_CONST_6_PLANE_PITCH__MASK; |
9071 | } |
9072 | |
9073 | #define REG_A6XX_TEX_CONST_7 0x00000007 |
9074 | #define A6XX_TEX_CONST_7_FLAG_LO__MASK 0xffffffe0 |
9075 | #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5 |
9076 | static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val) |
9077 | { |
9078 | assert(!(val & 0x1f)); |
9079 | return (((val >> 5)) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK; |
9080 | } |
9081 | |
9082 | #define REG_A6XX_TEX_CONST_8 0x00000008 |
9083 | #define A6XX_TEX_CONST_8_FLAG_HI__MASK 0x0001ffff |
9084 | #define A6XX_TEX_CONST_8_FLAG_HI__SHIFT 0 |
9085 | static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val) |
9086 | { |
9087 | return ((val) << A6XX_TEX_CONST_8_FLAG_HI__SHIFT) & A6XX_TEX_CONST_8_FLAG_HI__MASK; |
9088 | } |
9089 | |
9090 | #define REG_A6XX_TEX_CONST_9 0x00000009 |
9091 | #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK 0x0001ffff |
9092 | #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 |
9093 | static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) |
9094 | { |
9095 | assert(!(val & 0xf)); |
9096 | return (((val >> 4)) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK; |
9097 | } |
9098 | |
9099 | #define REG_A6XX_TEX_CONST_10 0x0000000a |
9100 | #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK 0x0000007f |
9101 | #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0 |
9102 | static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val) |
9103 | { |
9104 | assert(!(val & 0x3f)); |
9105 | return (((val >> 6)) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK; |
9106 | } |
9107 | #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK 0x00000f00 |
9108 | #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT 8 |
9109 | static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW(uint32_t val) |
9110 | { |
9111 | return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK; |
9112 | } |
9113 | #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK 0x0000f000 |
9114 | #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT 12 |
9115 | static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH(uint32_t val) |
9116 | { |
9117 | return ((val) << A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_LOGH__MASK; |
9118 | } |
9119 | |
9120 | #define REG_A6XX_TEX_CONST_11 0x0000000b |
9121 | |
9122 | #define REG_A6XX_TEX_CONST_12 0x0000000c |
9123 | |
9124 | #define REG_A6XX_TEX_CONST_13 0x0000000d |
9125 | |
9126 | #define REG_A6XX_TEX_CONST_14 0x0000000e |
9127 | |
9128 | #define REG_A6XX_TEX_CONST_15 0x0000000f |
9129 | |
9130 | #define REG_A6XX_UBO_0 0x00000000 |
9131 | #define A6XX_UBO_0_BASE_LO__MASK 0xffffffff |
9132 | #define A6XX_UBO_0_BASE_LO__SHIFT 0 |
9133 | static inline uint32_t A6XX_UBO_0_BASE_LO(uint32_t val) |
9134 | { |
9135 | return ((val) << A6XX_UBO_0_BASE_LO__SHIFT) & A6XX_UBO_0_BASE_LO__MASK; |
9136 | } |
9137 | |
9138 | #define REG_A6XX_UBO_1 0x00000001 |
9139 | #define A6XX_UBO_1_BASE_HI__MASK 0x0001ffff |
9140 | #define A6XX_UBO_1_BASE_HI__SHIFT 0 |
9141 | static inline uint32_t A6XX_UBO_1_BASE_HI(uint32_t val) |
9142 | { |
9143 | return ((val) << A6XX_UBO_1_BASE_HI__SHIFT) & A6XX_UBO_1_BASE_HI__MASK; |
9144 | } |
9145 | #define A6XX_UBO_1_SIZE__MASK 0xfffe0000 |
9146 | #define A6XX_UBO_1_SIZE__SHIFT 17 |
9147 | static inline uint32_t A6XX_UBO_1_SIZE(uint32_t val) |
9148 | { |
9149 | return ((val) << A6XX_UBO_1_SIZE__SHIFT) & A6XX_UBO_1_SIZE__MASK; |
9150 | } |
9151 | |
9152 | #define REG_A6XX_PDC_GPU_ENABLE_PDC 0x00001140 |
9153 | |
9154 | #define REG_A6XX_PDC_GPU_SEQ_START_ADDR 0x00001148 |
9155 | |
9156 | #define REG_A6XX_PDC_GPU_TCS0_CONTROL 0x00001540 |
9157 | |
9158 | #define REG_A6XX_PDC_GPU_TCS0_CMD_ENABLE_BANK 0x00001541 |
9159 | |
9160 | #define REG_A6XX_PDC_GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK 0x00001542 |
9161 | |
9162 | #define REG_A6XX_PDC_GPU_TCS0_CMD0_MSGID 0x00001543 |
9163 | |
9164 | #define REG_A6XX_PDC_GPU_TCS0_CMD0_ADDR 0x00001544 |
9165 | |
9166 | #define REG_A6XX_PDC_GPU_TCS0_CMD0_DATA 0x00001545 |
9167 | |
9168 | #define REG_A6XX_PDC_GPU_TCS1_CONTROL 0x00001572 |
9169 | |
9170 | #define REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK 0x00001573 |
9171 | |
9172 | #define REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK 0x00001574 |
9173 | |
9174 | #define REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID 0x00001575 |
9175 | |
9176 | #define REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR 0x00001576 |
9177 | |
9178 | #define REG_A6XX_PDC_GPU_TCS1_CMD0_DATA 0x00001577 |
9179 | |
9180 | #define REG_A6XX_PDC_GPU_TCS2_CONTROL 0x000015a4 |
9181 | |
9182 | #define REG_A6XX_PDC_GPU_TCS2_CMD_ENABLE_BANK 0x000015a5 |
9183 | |
9184 | #define REG_A6XX_PDC_GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK 0x000015a6 |
9185 | |
9186 | #define REG_A6XX_PDC_GPU_TCS2_CMD0_MSGID 0x000015a7 |
9187 | |
9188 | #define REG_A6XX_PDC_GPU_TCS2_CMD0_ADDR 0x000015a8 |
9189 | |
9190 | #define REG_A6XX_PDC_GPU_TCS2_CMD0_DATA 0x000015a9 |
9191 | |
9192 | #define REG_A6XX_PDC_GPU_TCS3_CONTROL 0x000015d6 |
9193 | |
9194 | #define REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK 0x000015d7 |
9195 | |
9196 | #define REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK 0x000015d8 |
9197 | |
9198 | #define REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID 0x000015d9 |
9199 | |
9200 | #define REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR 0x000015da |
9201 | |
9202 | #define REG_A6XX_PDC_GPU_TCS3_CMD0_DATA 0x000015db |
9203 | |
9204 | #define REG_A6XX_PDC_GPU_SEQ_MEM_0 0x00000000 |
9205 | |
9206 | #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_A 0x00000000 |
9207 | #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK 0x000000ff |
9208 | #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT 0 |
9209 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX(uint32_t val) |
9210 | { |
9211 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_INDEX__MASK; |
9212 | } |
9213 | #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK 0x0000ff00 |
9214 | #define A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT 8 |
9215 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL(uint32_t val) |
9216 | { |
9217 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_SEL_A_PING_BLK_SEL__MASK; |
9218 | } |
9219 | |
9220 | #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_B 0x00000001 |
9221 | |
9222 | #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_C 0x00000002 |
9223 | |
9224 | #define REG_A6XX_CX_DBGC_CFG_DBGBUS_SEL_D 0x00000003 |
9225 | |
9226 | #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLT 0x00000004 |
9227 | #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK 0x0000003f |
9228 | #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT 0 |
9229 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN(uint32_t val) |
9230 | { |
9231 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_TRACEEN__MASK; |
9232 | } |
9233 | #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK 0x00007000 |
9234 | #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT 12 |
9235 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU(uint32_t val) |
9236 | { |
9237 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_GRANU__MASK; |
9238 | } |
9239 | #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK 0xf0000000 |
9240 | #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT 28 |
9241 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT(uint32_t val) |
9242 | { |
9243 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLT_SEGT__MASK; |
9244 | } |
9245 | |
9246 | #define REG_A6XX_CX_DBGC_CFG_DBGBUS_CNTLM 0x00000005 |
9247 | #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK 0x0f000000 |
9248 | #define A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT 24 |
9249 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE(uint32_t val) |
9250 | { |
9251 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_CNTLM_ENABLE__MASK; |
9252 | } |
9253 | |
9254 | #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 0x00000008 |
9255 | |
9256 | #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 0x00000009 |
9257 | |
9258 | #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 0x0000000a |
9259 | |
9260 | #define REG_A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 0x0000000b |
9261 | |
9262 | #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 0x0000000c |
9263 | |
9264 | #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 0x0000000d |
9265 | |
9266 | #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 0x0000000e |
9267 | |
9268 | #define REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 0x0000000f |
9269 | |
9270 | #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 0x00000010 |
9271 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK 0x0000000f |
9272 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT 0 |
9273 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0(uint32_t val) |
9274 | { |
9275 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL0__MASK; |
9276 | } |
9277 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK 0x000000f0 |
9278 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT 4 |
9279 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1(uint32_t val) |
9280 | { |
9281 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL1__MASK; |
9282 | } |
9283 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK 0x00000f00 |
9284 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT 8 |
9285 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2(uint32_t val) |
9286 | { |
9287 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL2__MASK; |
9288 | } |
9289 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK 0x0000f000 |
9290 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT 12 |
9291 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3(uint32_t val) |
9292 | { |
9293 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL3__MASK; |
9294 | } |
9295 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK 0x000f0000 |
9296 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT 16 |
9297 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4(uint32_t val) |
9298 | { |
9299 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL4__MASK; |
9300 | } |
9301 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK 0x00f00000 |
9302 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT 20 |
9303 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5(uint32_t val) |
9304 | { |
9305 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL5__MASK; |
9306 | } |
9307 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK 0x0f000000 |
9308 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT 24 |
9309 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6(uint32_t val) |
9310 | { |
9311 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL6__MASK; |
9312 | } |
9313 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK 0xf0000000 |
9314 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT 28 |
9315 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7(uint32_t val) |
9316 | { |
9317 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0_BYTEL7__MASK; |
9318 | } |
9319 | |
9320 | #define REG_A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 0x00000011 |
9321 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK 0x0000000f |
9322 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT 0 |
9323 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8(uint32_t val) |
9324 | { |
9325 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL8__MASK; |
9326 | } |
9327 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK 0x000000f0 |
9328 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT 4 |
9329 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9(uint32_t val) |
9330 | { |
9331 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL9__MASK; |
9332 | } |
9333 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK 0x00000f00 |
9334 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT 8 |
9335 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10(uint32_t val) |
9336 | { |
9337 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL10__MASK; |
9338 | } |
9339 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK 0x0000f000 |
9340 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT 12 |
9341 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11(uint32_t val) |
9342 | { |
9343 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL11__MASK; |
9344 | } |
9345 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK 0x000f0000 |
9346 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT 16 |
9347 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12(uint32_t val) |
9348 | { |
9349 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL12__MASK; |
9350 | } |
9351 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK 0x00f00000 |
9352 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT 20 |
9353 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13(uint32_t val) |
9354 | { |
9355 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL13__MASK; |
9356 | } |
9357 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK 0x0f000000 |
9358 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT 24 |
9359 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14(uint32_t val) |
9360 | { |
9361 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL14__MASK; |
9362 | } |
9363 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK 0xf0000000 |
9364 | #define A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT 28 |
9365 | static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) |
9366 | { |
9367 | return ((val) << A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__SHIFT) & A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15__MASK; |
9368 | } |
9369 | |
9370 | #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 0x0000002f |
9371 | |
9372 | #define REG_A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000030 |
9373 | |
9374 | #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0 0x00000001 |
9375 | |
9376 | #define REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1 0x00000002 |
9377 | |
9378 | #define REG_A7XX_CX_MISC_TCM_RET_CNTL 0x00000039 |
9379 | |
9380 | #ifdef __cplusplus |
9381 | template<chip CHIP> constexpr inline uint16_t CMD_REGS[] = {}; |
9382 | template<chip CHIP> constexpr inline uint16_t RP_BLIT_REGS[] = {}; |
9383 | template<> constexpr inline uint16_t CMD_REGS<A6XX>[] = { |
9384 | 0xc03, |
9385 | 0xc04, |
9386 | 0xc30, |
9387 | 0xc31, |
9388 | 0xc32, |
9389 | 0xc33, |
9390 | 0xc34, |
9391 | 0xc35, |
9392 | 0xc36, |
9393 | 0xc37, |
9394 | 0xe12, |
9395 | 0xe17, |
9396 | 0xe19, |
9397 | 0x8099, |
9398 | 0x80af, |
9399 | 0x810a, |
9400 | 0x8110, |
9401 | 0x8600, |
9402 | 0x880e, |
9403 | 0x8811, |
9404 | 0x8818, |
9405 | 0x8819, |
9406 | 0x881a, |
9407 | 0x881b, |
9408 | 0x881c, |
9409 | 0x881d, |
9410 | 0x881e, |
9411 | 0x8864, |
9412 | 0x8891, |
9413 | 0x88f0, |
9414 | 0x8927, |
9415 | 0x8928, |
9416 | 0x8e01, |
9417 | 0x8e04, |
9418 | 0x8e07, |
9419 | 0x9210, |
9420 | 0x9211, |
9421 | 0x9218, |
9422 | 0x9219, |
9423 | 0x921a, |
9424 | 0x921b, |
9425 | 0x921c, |
9426 | 0x921d, |
9427 | 0x921e, |
9428 | 0x921f, |
9429 | 0x9220, |
9430 | 0x9221, |
9431 | 0x9222, |
9432 | 0x9223, |
9433 | 0x9224, |
9434 | 0x9225, |
9435 | 0x9226, |
9436 | 0x9227, |
9437 | 0x9228, |
9438 | 0x9229, |
9439 | 0x922a, |
9440 | 0x922b, |
9441 | 0x922c, |
9442 | 0x922d, |
9443 | 0x922e, |
9444 | 0x922f, |
9445 | 0x9230, |
9446 | 0x9231, |
9447 | 0x9232, |
9448 | 0x9233, |
9449 | 0x9234, |
9450 | 0x9235, |
9451 | 0x9236, |
9452 | 0x9300, |
9453 | 0x9600, |
9454 | 0x9601, |
9455 | 0x9602, |
9456 | 0x9e08, |
9457 | 0x9e09, |
9458 | 0x9e72, |
9459 | 0xa007, |
9460 | 0xa009, |
9461 | 0xa8a0, |
9462 | 0xa8a1, |
9463 | 0xa8a2, |
9464 | 0xa8a3, |
9465 | 0xa8a4, |
9466 | 0xa8a5, |
9467 | 0xa8a6, |
9468 | 0xa8a7, |
9469 | 0xa8a8, |
9470 | 0xa8a9, |
9471 | 0xa8aa, |
9472 | 0xa8ab, |
9473 | 0xa8ac, |
9474 | 0xa8ad, |
9475 | 0xa8ae, |
9476 | 0xa8af, |
9477 | 0xa9a8, |
9478 | 0xa9b0, |
9479 | 0xa9b1, |
9480 | 0xa9b2, |
9481 | 0xa9b3, |
9482 | 0xa9b4, |
9483 | 0xa9b5, |
9484 | 0xa9b6, |
9485 | 0xa9b7, |
9486 | 0xa9b8, |
9487 | 0xa9b9, |
9488 | 0xa9ba, |
9489 | 0xa9bb, |
9490 | 0xa9bc, |
9491 | 0xa9bd, |
9492 | 0xa9c2, |
9493 | 0xa9c3, |
9494 | 0xa9e2, |
9495 | 0xa9e3, |
9496 | 0xa9e6, |
9497 | 0xa9e7, |
9498 | 0xa9e8, |
9499 | 0xa9e9, |
9500 | 0xa9ea, |
9501 | 0xa9eb, |
9502 | 0xa9ec, |
9503 | 0xa9ed, |
9504 | 0xa9ee, |
9505 | 0xa9ef, |
9506 | 0xa9f0, |
9507 | 0xa9f1, |
9508 | 0xaaf2, |
9509 | 0xab1a, |
9510 | 0xab1b, |
9511 | 0xab20, |
9512 | 0xae00, |
9513 | 0xae03, |
9514 | 0xae04, |
9515 | 0xae0f, |
9516 | 0xb180, |
9517 | 0xb181, |
9518 | 0xb182, |
9519 | 0xb183, |
9520 | 0xb302, |
9521 | 0xb303, |
9522 | 0xb309, |
9523 | 0xb600, |
9524 | 0xb602, |
9525 | 0xb605, |
9526 | 0xb987, |
9527 | 0xb9d0, |
9528 | 0xbb08, |
9529 | 0xbb11, |
9530 | 0xbb20, |
9531 | 0xbb21, |
9532 | 0xbb22, |
9533 | 0xbb23, |
9534 | 0xbb24, |
9535 | 0xbb25, |
9536 | 0xbb26, |
9537 | 0xbb27, |
9538 | 0xbb28, |
9539 | 0xbb29, |
9540 | 0xbe00, |
9541 | 0xbe01, |
9542 | 0xbe04, |
9543 | }; |
9544 | template<> constexpr inline uint16_t CMD_REGS<A7XX>[] = { |
9545 | 0xc03, |
9546 | 0xc04, |
9547 | 0xc30, |
9548 | 0xc31, |
9549 | 0xc32, |
9550 | 0xc33, |
9551 | 0xc34, |
9552 | 0xc35, |
9553 | 0xc36, |
9554 | 0xc37, |
9555 | 0xce2, |
9556 | 0xce3, |
9557 | 0xce4, |
9558 | 0xce5, |
9559 | 0xce6, |
9560 | 0xce7, |
9561 | 0xe10, |
9562 | 0xe11, |
9563 | 0xe12, |
9564 | 0xe17, |
9565 | 0xe19, |
9566 | 0x8008, |
9567 | 0x8009, |
9568 | 0x800a, |
9569 | 0x800b, |
9570 | 0x800c, |
9571 | 0x8099, |
9572 | 0x80a7, |
9573 | 0x80af, |
9574 | 0x80f4, |
9575 | 0x80f5, |
9576 | 0x80f5, |
9577 | 0x80f6, |
9578 | 0x80f6, |
9579 | 0x80f7, |
9580 | 0x80f8, |
9581 | 0x80f9, |
9582 | 0x80f9, |
9583 | 0x80fa, |
9584 | 0x80fa, |
9585 | 0x80fb, |
9586 | 0x810a, |
9587 | 0x810b, |
9588 | 0x8110, |
9589 | 0x8120, |
9590 | 0x8121, |
9591 | 0x8600, |
9592 | 0x880e, |
9593 | 0x8811, |
9594 | 0x8818, |
9595 | 0x8819, |
9596 | 0x881a, |
9597 | 0x881b, |
9598 | 0x881c, |
9599 | 0x881d, |
9600 | 0x881e, |
9601 | 0x8864, |
9602 | 0x8891, |
9603 | 0x8899, |
9604 | 0x88e5, |
9605 | 0x88f0, |
9606 | 0x8927, |
9607 | 0x8928, |
9608 | 0x8e01, |
9609 | 0x8e04, |
9610 | 0x8e06, |
9611 | 0x8e07, |
9612 | 0x8e09, |
9613 | 0x8e79, |
9614 | 0x9218, |
9615 | 0x9219, |
9616 | 0x921a, |
9617 | 0x921b, |
9618 | 0x921c, |
9619 | 0x921d, |
9620 | 0x921e, |
9621 | 0x921f, |
9622 | 0x9220, |
9623 | 0x9221, |
9624 | 0x9222, |
9625 | 0x9223, |
9626 | 0x9224, |
9627 | 0x9225, |
9628 | 0x9226, |
9629 | 0x9227, |
9630 | 0x9228, |
9631 | 0x9229, |
9632 | 0x922a, |
9633 | 0x922b, |
9634 | 0x922c, |
9635 | 0x922d, |
9636 | 0x922e, |
9637 | 0x922f, |
9638 | 0x9230, |
9639 | 0x9231, |
9640 | 0x9232, |
9641 | 0x9233, |
9642 | 0x9234, |
9643 | 0x9235, |
9644 | 0x9236, |
9645 | 0x9300, |
9646 | 0x9600, |
9647 | 0x9601, |
9648 | 0x9602, |
9649 | 0x9810, |
9650 | 0x9811, |
9651 | 0x9e24, |
9652 | 0x9e72, |
9653 | 0xa007, |
9654 | 0xa009, |
9655 | 0xa600, |
9656 | 0xa82d, |
9657 | 0xa82f, |
9658 | 0xa868, |
9659 | 0xa899, |
9660 | 0xa8a0, |
9661 | 0xa8a1, |
9662 | 0xa8a2, |
9663 | 0xa8a3, |
9664 | 0xa8a4, |
9665 | 0xa8a5, |
9666 | 0xa8a6, |
9667 | 0xa8a7, |
9668 | 0xa8a8, |
9669 | 0xa8a9, |
9670 | 0xa8aa, |
9671 | 0xa8ab, |
9672 | 0xa8ac, |
9673 | 0xa8ad, |
9674 | 0xa8ae, |
9675 | 0xa8af, |
9676 | 0xa9a8, |
9677 | 0xa9ac, |
9678 | 0xa9ad, |
9679 | 0xa9b0, |
9680 | 0xa9b1, |
9681 | 0xa9b2, |
9682 | 0xa9b3, |
9683 | 0xa9b4, |
9684 | 0xa9b5, |
9685 | 0xa9b6, |
9686 | 0xa9b7, |
9687 | 0xa9b8, |
9688 | 0xa9b9, |
9689 | 0xa9ba, |
9690 | 0xa9bb, |
9691 | 0xa9bc, |
9692 | 0xa9bd, |
9693 | 0xa9be, |
9694 | 0xa9c2, |
9695 | 0xa9c3, |
9696 | 0xa9c5, |
9697 | 0xa9cd, |
9698 | 0xa9df, |
9699 | 0xa9e2, |
9700 | 0xa9e3, |
9701 | 0xa9e6, |
9702 | 0xa9e7, |
9703 | 0xa9e8, |
9704 | 0xa9e9, |
9705 | 0xa9ea, |
9706 | 0xa9eb, |
9707 | 0xa9ec, |
9708 | 0xa9ed, |
9709 | 0xa9ee, |
9710 | 0xa9ef, |
9711 | 0xa9f0, |
9712 | 0xa9f1, |
9713 | 0xa9f2, |
9714 | 0xa9f3, |
9715 | 0xa9f4, |
9716 | 0xa9f5, |
9717 | 0xa9f6, |
9718 | 0xa9f7, |
9719 | 0xaa01, |
9720 | 0xaa02, |
9721 | 0xaa03, |
9722 | 0xaaf2, |
9723 | 0xab01, |
9724 | 0xab02, |
9725 | 0xab1a, |
9726 | 0xab1b, |
9727 | 0xab1f, |
9728 | 0xab20, |
9729 | 0xab22, |
9730 | 0xae00, |
9731 | 0xae03, |
9732 | 0xae04, |
9733 | 0xae06, |
9734 | 0xae08, |
9735 | 0xae09, |
9736 | 0xae0a, |
9737 | 0xae0f, |
9738 | 0xae6a, |
9739 | 0xae6b, |
9740 | 0xae6c, |
9741 | 0xae73, |
9742 | 0xb180, |
9743 | 0xb181, |
9744 | 0xb182, |
9745 | 0xb183, |
9746 | 0xb302, |
9747 | 0xb303, |
9748 | 0xb309, |
9749 | 0xb310, |
9750 | 0xb600, |
9751 | 0xb602, |
9752 | 0xb608, |
9753 | 0xb609, |
9754 | 0xb60a, |
9755 | 0xb60b, |
9756 | 0xb60c, |
9757 | }; |
9758 | template<> constexpr inline uint16_t RP_BLIT_REGS<A6XX>[] = { |
9759 | 0xc02, |
9760 | 0xc06, |
9761 | 0xc10, |
9762 | 0xc11, |
9763 | 0xc12, |
9764 | 0xc13, |
9765 | 0xc14, |
9766 | 0xc15, |
9767 | 0xc16, |
9768 | 0xc17, |
9769 | 0xc18, |
9770 | 0xc19, |
9771 | 0xc1a, |
9772 | 0xc1b, |
9773 | 0xc1c, |
9774 | 0xc1d, |
9775 | 0xc1e, |
9776 | 0xc1f, |
9777 | 0xc20, |
9778 | 0xc21, |
9779 | 0xc22, |
9780 | 0xc23, |
9781 | 0xc24, |
9782 | 0xc25, |
9783 | 0xc26, |
9784 | 0xc27, |
9785 | 0xc28, |
9786 | 0xc29, |
9787 | 0xc2a, |
9788 | 0xc2b, |
9789 | 0xc2c, |
9790 | 0xc2d, |
9791 | 0xc2e, |
9792 | 0xc2f, |
9793 | 0xc38, |
9794 | 0xc39, |
9795 | 0xc3a, |
9796 | 0xc3b, |
9797 | 0xc3c, |
9798 | 0xc3d, |
9799 | 0xc3e, |
9800 | 0xc3f, |
9801 | 0xc40, |
9802 | 0xc41, |
9803 | 0xc42, |
9804 | 0xc43, |
9805 | 0xc44, |
9806 | 0xc45, |
9807 | 0xc46, |
9808 | 0xc47, |
9809 | 0xc48, |
9810 | 0xc49, |
9811 | 0xc4a, |
9812 | 0xc4b, |
9813 | 0xc4c, |
9814 | 0xc4d, |
9815 | 0xc4e, |
9816 | 0xc4f, |
9817 | 0xc50, |
9818 | 0xc51, |
9819 | 0xc52, |
9820 | 0xc53, |
9821 | 0xc54, |
9822 | 0xc55, |
9823 | 0xc56, |
9824 | 0xc57, |
9825 | 0xc58, |
9826 | 0xc59, |
9827 | 0xc5a, |
9828 | 0xc5b, |
9829 | 0xc5c, |
9830 | 0xc5d, |
9831 | 0xc5e, |
9832 | 0xc5f, |
9833 | 0xc60, |
9834 | 0xc61, |
9835 | 0xc62, |
9836 | 0xc63, |
9837 | 0xc64, |
9838 | 0xc65, |
9839 | 0xc66, |
9840 | 0xc67, |
9841 | 0xc68, |
9842 | 0xc69, |
9843 | 0xc6a, |
9844 | 0xc6b, |
9845 | 0xc6c, |
9846 | 0xc6d, |
9847 | 0xc6e, |
9848 | 0xc6f, |
9849 | 0xc70, |
9850 | 0xc71, |
9851 | 0xc72, |
9852 | 0xc73, |
9853 | 0xc74, |
9854 | 0xc75, |
9855 | 0xc76, |
9856 | 0xc77, |
9857 | 0xc78, |
9858 | 0xc79, |
9859 | 0xc7a, |
9860 | 0xc7b, |
9861 | 0xc7c, |
9862 | 0xc7d, |
9863 | 0xc7e, |
9864 | 0xc7f, |
9865 | 0xc80, |
9866 | 0xc81, |
9867 | 0xc82, |
9868 | 0xc83, |
9869 | 0xc84, |
9870 | 0xc85, |
9871 | 0xc86, |
9872 | 0xc87, |
9873 | 0xc88, |
9874 | 0xc89, |
9875 | 0xc8a, |
9876 | 0xc8b, |
9877 | 0xc8c, |
9878 | 0xc8d, |
9879 | 0xc8e, |
9880 | 0xc8f, |
9881 | 0xc90, |
9882 | 0xc91, |
9883 | 0xc92, |
9884 | 0xc93, |
9885 | 0xc94, |
9886 | 0xc95, |
9887 | 0xc96, |
9888 | 0xc97, |
9889 | 0x8000, |
9890 | 0x8001, |
9891 | 0x8002, |
9892 | 0x8003, |
9893 | 0x8004, |
9894 | 0x8005, |
9895 | 0x8006, |
9896 | 0x8010, |
9897 | 0x8011, |
9898 | 0x8012, |
9899 | 0x8013, |
9900 | 0x8014, |
9901 | 0x8015, |
9902 | 0x8016, |
9903 | 0x8017, |
9904 | 0x8018, |
9905 | 0x8019, |
9906 | 0x801a, |
9907 | 0x801b, |
9908 | 0x801c, |
9909 | 0x801d, |
9910 | 0x801e, |
9911 | 0x801f, |
9912 | 0x8020, |
9913 | 0x8021, |
9914 | 0x8022, |
9915 | 0x8023, |
9916 | 0x8024, |
9917 | 0x8025, |
9918 | 0x8026, |
9919 | 0x8027, |
9920 | 0x8028, |
9921 | 0x8029, |
9922 | 0x802a, |
9923 | 0x802b, |
9924 | 0x802c, |
9925 | 0x802d, |
9926 | 0x802e, |
9927 | 0x802f, |
9928 | 0x8030, |
9929 | 0x8031, |
9930 | 0x8032, |
9931 | 0x8033, |
9932 | 0x8034, |
9933 | 0x8035, |
9934 | 0x8036, |
9935 | 0x8037, |
9936 | 0x8038, |
9937 | 0x8039, |
9938 | 0x803a, |
9939 | 0x803b, |
9940 | 0x803c, |
9941 | 0x803d, |
9942 | 0x803e, |
9943 | 0x803f, |
9944 | 0x8040, |
9945 | 0x8041, |
9946 | 0x8042, |
9947 | 0x8043, |
9948 | 0x8044, |
9949 | 0x8045, |
9950 | 0x8046, |
9951 | 0x8047, |
9952 | 0x8048, |
9953 | 0x8049, |
9954 | 0x804a, |
9955 | 0x804b, |
9956 | 0x804c, |
9957 | 0x804d, |
9958 | 0x804e, |
9959 | 0x804f, |
9960 | 0x8050, |
9961 | 0x8051, |
9962 | 0x8052, |
9963 | 0x8053, |
9964 | 0x8054, |
9965 | 0x8055, |
9966 | 0x8056, |
9967 | 0x8057, |
9968 | 0x8058, |
9969 | 0x8059, |
9970 | 0x805a, |
9971 | 0x805b, |
9972 | 0x805c, |
9973 | 0x805d, |
9974 | 0x805e, |
9975 | 0x805f, |
9976 | 0x8060, |
9977 | 0x8061, |
9978 | 0x8062, |
9979 | 0x8063, |
9980 | 0x8064, |
9981 | 0x8065, |
9982 | 0x8066, |
9983 | 0x8067, |
9984 | 0x8068, |
9985 | 0x8069, |
9986 | 0x806a, |
9987 | 0x806b, |
9988 | 0x806c, |
9989 | 0x806d, |
9990 | 0x806e, |
9991 | 0x806f, |
9992 | 0x8070, |
9993 | 0x8071, |
9994 | 0x8072, |
9995 | 0x8073, |
9996 | 0x8074, |
9997 | 0x8075, |
9998 | 0x8076, |
9999 | 0x8077, |
10000 | 0x8078, |
10001 | 0x8079, |
10002 | 0x807a, |
10003 | 0x807b, |
10004 | 0x807c, |
10005 | 0x807d, |
10006 | 0x807e, |
10007 | 0x807f, |
10008 | 0x8080, |
10009 | 0x8081, |
10010 | 0x8082, |
10011 | 0x8083, |
10012 | 0x8084, |
10013 | 0x8085, |
10014 | 0x8086, |
10015 | 0x8087, |
10016 | 0x8088, |
10017 | 0x8089, |
10018 | 0x808a, |
10019 | 0x808b, |
10020 | 0x808c, |
10021 | 0x808d, |
10022 | 0x808e, |
10023 | 0x808f, |
10024 | 0x8090, |
10025 | 0x8091, |
10026 | 0x8092, |
10027 | 0x8094, |
10028 | 0x8095, |
10029 | 0x8096, |
10030 | 0x8097, |
10031 | 0x8098, |
10032 | 0x809b, |
10033 | 0x809c, |
10034 | 0x809d, |
10035 | 0x80a0, |
10036 | 0x80a1, |
10037 | 0x80a2, |
10038 | 0x80a3, |
10039 | 0x80a4, |
10040 | 0x80a5, |
10041 | 0x80a6, |
10042 | 0x80b0, |
10043 | 0x80b1, |
10044 | 0x80b2, |
10045 | 0x80b3, |
10046 | 0x80b4, |
10047 | 0x80b5, |
10048 | 0x80b6, |
10049 | 0x80b7, |
10050 | 0x80b8, |
10051 | 0x80b9, |
10052 | 0x80ba, |
10053 | 0x80bb, |
10054 | 0x80bc, |
10055 | 0x80bd, |
10056 | 0x80be, |
10057 | 0x80bf, |
10058 | 0x80c0, |
10059 | 0x80c1, |
10060 | 0x80c2, |
10061 | 0x80c3, |
10062 | 0x80c4, |
10063 | 0x80c5, |
10064 | 0x80c6, |
10065 | 0x80c7, |
10066 | 0x80c8, |
10067 | 0x80c9, |
10068 | 0x80ca, |
10069 | 0x80cb, |
10070 | 0x80cc, |
10071 | 0x80cd, |
10072 | 0x80ce, |
10073 | 0x80cf, |
10074 | 0x80d0, |
10075 | 0x80d1, |
10076 | 0x80d2, |
10077 | 0x80d3, |
10078 | 0x80d4, |
10079 | 0x80d5, |
10080 | 0x80d6, |
10081 | 0x80d7, |
10082 | 0x80d8, |
10083 | 0x80d9, |
10084 | 0x80da, |
10085 | 0x80db, |
10086 | 0x80dc, |
10087 | 0x80dd, |
10088 | 0x80de, |
10089 | 0x80df, |
10090 | 0x80e0, |
10091 | 0x80e1, |
10092 | 0x80e2, |
10093 | 0x80e3, |
10094 | 0x80e4, |
10095 | 0x80e5, |
10096 | 0x80e6, |
10097 | 0x80e7, |
10098 | 0x80e8, |
10099 | 0x80e9, |
10100 | 0x80ea, |
10101 | 0x80eb, |
10102 | 0x80ec, |
10103 | 0x80ed, |
10104 | 0x80ee, |
10105 | 0x80ef, |
10106 | 0x80f0, |
10107 | 0x80f1, |
10108 | 0x8100, |
10109 | 0x8101, |
10110 | 0x8102, |
10111 | 0x8103, |
10112 | 0x8104, |
10113 | 0x8105, |
10114 | 0x8106, |
10115 | 0x8107, |
10116 | 0x8109, |
10117 | 0x8114, |
10118 | 0x8115, |
10119 | 0x8400, |
10120 | 0x8401, |
10121 | 0x8402, |
10122 | 0x8403, |
10123 | 0x8404, |
10124 | 0x8405, |
10125 | 0x8406, |
10126 | 0x840a, |
10127 | 0x840b, |
10128 | 0x8800, |
10129 | 0x8801, |
10130 | 0x8802, |
10131 | 0x8803, |
10132 | 0x8804, |
10133 | 0x8805, |
10134 | 0x8806, |
10135 | 0x8809, |
10136 | 0x880a, |
10137 | 0x880b, |
10138 | 0x880c, |
10139 | 0x880d, |
10140 | 0x880f, |
10141 | 0x8810, |
10142 | 0x8820, |
10143 | 0x8821, |
10144 | 0x8822, |
10145 | 0x8823, |
10146 | 0x8824, |
10147 | 0x8825, |
10148 | 0x8826, |
10149 | 0x8827, |
10150 | 0x8828, |
10151 | 0x8829, |
10152 | 0x882a, |
10153 | 0x882b, |
10154 | 0x882c, |
10155 | 0x882d, |
10156 | 0x882e, |
10157 | 0x882f, |
10158 | 0x8830, |
10159 | 0x8831, |
10160 | 0x8832, |
10161 | 0x8833, |
10162 | 0x8834, |
10163 | 0x8835, |
10164 | 0x8836, |
10165 | 0x8837, |
10166 | 0x8838, |
10167 | 0x8839, |
10168 | 0x883a, |
10169 | 0x883b, |
10170 | 0x883c, |
10171 | 0x883d, |
10172 | 0x883e, |
10173 | 0x883f, |
10174 | 0x8840, |
10175 | 0x8841, |
10176 | 0x8842, |
10177 | 0x8843, |
10178 | 0x8844, |
10179 | 0x8845, |
10180 | 0x8846, |
10181 | 0x8847, |
10182 | 0x8848, |
10183 | 0x8849, |
10184 | 0x884a, |
10185 | 0x884b, |
10186 | 0x884c, |
10187 | 0x884d, |
10188 | 0x884e, |
10189 | 0x884f, |
10190 | 0x8850, |
10191 | 0x8851, |
10192 | 0x8852, |
10193 | 0x8853, |
10194 | 0x8854, |
10195 | 0x8855, |
10196 | 0x8856, |
10197 | 0x8857, |
10198 | 0x8858, |
10199 | 0x8859, |
10200 | 0x885a, |
10201 | 0x885b, |
10202 | 0x885c, |
10203 | 0x885d, |
10204 | 0x885e, |
10205 | 0x885f, |
10206 | 0x8860, |
10207 | 0x8861, |
10208 | 0x8862, |
10209 | 0x8863, |
10210 | 0x8865, |
10211 | 0x8870, |
10212 | 0x8871, |
10213 | 0x8872, |
10214 | 0x8873, |
10215 | 0x8874, |
10216 | 0x8875, |
10217 | 0x8876, |
10218 | 0x8877, |
10219 | 0x8878, |
10220 | 0x8879, |
10221 | 0x8880, |
10222 | 0x8881, |
10223 | 0x8882, |
10224 | 0x8883, |
10225 | 0x8884, |
10226 | 0x8885, |
10227 | 0x8886, |
10228 | 0x8887, |
10229 | 0x8888, |
10230 | 0x8889, |
10231 | 0x8890, |
10232 | 0x8898, |
10233 | 0x88c0, |
10234 | 0x88c1, |
10235 | 0x88d0, |
10236 | 0x88d1, |
10237 | 0x88d2, |
10238 | 0x88d3, |
10239 | 0x88d4, |
10240 | 0x88d5, |
10241 | 0x88d6, |
10242 | 0x88d7, |
10243 | 0x88d8, |
10244 | 0x88d9, |
10245 | 0x88da, |
10246 | 0x88db, |
10247 | 0x88dc, |
10248 | 0x88dd, |
10249 | 0x88de, |
10250 | 0x88df, |
10251 | 0x88e0, |
10252 | 0x88e1, |
10253 | 0x88e2, |
10254 | 0x88e3, |
10255 | 0x8900, |
10256 | 0x8901, |
10257 | 0x8902, |
10258 | 0x8903, |
10259 | 0x8904, |
10260 | 0x8905, |
10261 | 0x8906, |
10262 | 0x8907, |
10263 | 0x8908, |
10264 | 0x8909, |
10265 | 0x890a, |
10266 | 0x890b, |
10267 | 0x890c, |
10268 | 0x890d, |
10269 | 0x890e, |
10270 | 0x890f, |
10271 | 0x8910, |
10272 | 0x8911, |
10273 | 0x8912, |
10274 | 0x8913, |
10275 | 0x8914, |
10276 | 0x8915, |
10277 | 0x8916, |
10278 | 0x8917, |
10279 | 0x8918, |
10280 | 0x8919, |
10281 | 0x891a, |
10282 | 0x8a00, |
10283 | 0x8a10, |
10284 | 0x8a20, |
10285 | 0x8a30, |
10286 | 0x8c00, |
10287 | 0x8c01, |
10288 | 0x8c17, |
10289 | 0x8c18, |
10290 | 0x8c19, |
10291 | 0x8c1a, |
10292 | 0x8c1b, |
10293 | 0x8c1c, |
10294 | 0x8c1d, |
10295 | 0x8c1e, |
10296 | 0x8c1f, |
10297 | 0x8c20, |
10298 | 0x8c21, |
10299 | 0x8c22, |
10300 | 0x8c23, |
10301 | 0x8c24, |
10302 | 0x8c25, |
10303 | 0x8c2c, |
10304 | 0x8c2d, |
10305 | 0x8c2e, |
10306 | 0x8c2f, |
10307 | 0x9100, |
10308 | 0x9101, |
10309 | 0x9102, |
10310 | 0x9103, |
10311 | 0x9104, |
10312 | 0x9105, |
10313 | 0x9106, |
10314 | 0x9107, |
10315 | 0x9108, |
10316 | 0x9200, |
10317 | 0x9201, |
10318 | 0x9202, |
10319 | 0x9203, |
10320 | 0x9204, |
10321 | 0x9205, |
10322 | 0x9206, |
10323 | 0x9207, |
10324 | 0x9208, |
10325 | 0x9209, |
10326 | 0x920a, |
10327 | 0x920b, |
10328 | 0x920c, |
10329 | 0x920d, |
10330 | 0x920e, |
10331 | 0x920f, |
10332 | 0x9212, |
10333 | 0x9213, |
10334 | 0x9214, |
10335 | 0x9215, |
10336 | 0x9216, |
10337 | 0x9217, |
10338 | 0x9301, |
10339 | 0x9302, |
10340 | 0x9303, |
10341 | 0x9304, |
10342 | 0x9305, |
10343 | 0x9306, |
10344 | 0x9311, |
10345 | 0x9312, |
10346 | 0x9313, |
10347 | 0x9314, |
10348 | 0x9315, |
10349 | 0x9316, |
10350 | 0x9800, |
10351 | 0x9801, |
10352 | 0x9802, |
10353 | 0x9803, |
10354 | 0x9804, |
10355 | 0x9805, |
10356 | 0x9806, |
10357 | 0x9808, |
10358 | 0x9980, |
10359 | 0x9981, |
10360 | 0x9b00, |
10361 | 0x9b01, |
10362 | 0x9b02, |
10363 | 0x9b03, |
10364 | 0x9b04, |
10365 | 0x9b05, |
10366 | 0x9b06, |
10367 | 0x9b07, |
10368 | 0x9b08, |
10369 | 0xa000, |
10370 | 0xa001, |
10371 | 0xa002, |
10372 | 0xa003, |
10373 | 0xa004, |
10374 | 0xa005, |
10375 | 0xa006, |
10376 | 0xa008, |
10377 | 0xa00e, |
10378 | 0xa00f, |
10379 | 0xa010, |
10380 | 0xa011, |
10381 | 0xa012, |
10382 | 0xa013, |
10383 | 0xa014, |
10384 | 0xa015, |
10385 | 0xa016, |
10386 | 0xa017, |
10387 | 0xa018, |
10388 | 0xa019, |
10389 | 0xa01a, |
10390 | 0xa01b, |
10391 | 0xa01c, |
10392 | 0xa01d, |
10393 | 0xa01e, |
10394 | 0xa01f, |
10395 | 0xa020, |
10396 | 0xa021, |
10397 | 0xa022, |
10398 | 0xa023, |
10399 | 0xa024, |
10400 | 0xa025, |
10401 | 0xa026, |
10402 | 0xa027, |
10403 | 0xa028, |
10404 | 0xa029, |
10405 | 0xa02a, |
10406 | 0xa02b, |
10407 | 0xa02c, |
10408 | 0xa02d, |
10409 | 0xa02e, |
10410 | 0xa02f, |
10411 | 0xa030, |
10412 | 0xa031, |
10413 | 0xa032, |
10414 | 0xa033, |
10415 | 0xa034, |
10416 | 0xa035, |
10417 | 0xa036, |
10418 | 0xa037, |
10419 | 0xa038, |
10420 | 0xa039, |
10421 | 0xa03a, |
10422 | 0xa03b, |
10423 | 0xa03c, |
10424 | 0xa03d, |
10425 | 0xa03e, |
10426 | 0xa03f, |
10427 | 0xa040, |
10428 | 0xa041, |
10429 | 0xa042, |
10430 | 0xa043, |
10431 | 0xa044, |
10432 | 0xa045, |
10433 | 0xa046, |
10434 | 0xa047, |
10435 | 0xa048, |
10436 | 0xa049, |
10437 | 0xa04a, |
10438 | 0xa04b, |
10439 | 0xa04c, |
10440 | 0xa04d, |
10441 | 0xa04e, |
10442 | 0xa04f, |
10443 | 0xa050, |
10444 | 0xa051, |
10445 | 0xa052, |
10446 | 0xa053, |
10447 | 0xa054, |
10448 | 0xa055, |
10449 | 0xa056, |
10450 | 0xa057, |
10451 | 0xa058, |
10452 | 0xa059, |
10453 | 0xa05a, |
10454 | 0xa05b, |
10455 | 0xa05c, |
10456 | 0xa05d, |
10457 | 0xa05e, |
10458 | 0xa05f, |
10459 | 0xa060, |
10460 | 0xa061, |
10461 | 0xa062, |
10462 | 0xa063, |
10463 | 0xa064, |
10464 | 0xa065, |
10465 | 0xa066, |
10466 | 0xa067, |
10467 | 0xa068, |
10468 | 0xa069, |
10469 | 0xa06a, |
10470 | 0xa06b, |
10471 | 0xa06c, |
10472 | 0xa06d, |
10473 | 0xa06e, |
10474 | 0xa06f, |
10475 | 0xa070, |
10476 | 0xa071, |
10477 | 0xa072, |
10478 | 0xa073, |
10479 | 0xa074, |
10480 | 0xa075, |
10481 | 0xa076, |
10482 | 0xa077, |
10483 | 0xa078, |
10484 | 0xa079, |
10485 | 0xa07a, |
10486 | 0xa07b, |
10487 | 0xa07c, |
10488 | 0xa07d, |
10489 | 0xa07e, |
10490 | 0xa07f, |
10491 | 0xa080, |
10492 | 0xa081, |
10493 | 0xa082, |
10494 | 0xa083, |
10495 | 0xa084, |
10496 | 0xa085, |
10497 | 0xa086, |
10498 | 0xa087, |
10499 | 0xa088, |
10500 | 0xa089, |
10501 | 0xa08a, |
10502 | 0xa08b, |
10503 | 0xa08c, |
10504 | 0xa08d, |
10505 | 0xa08e, |
10506 | 0xa08f, |
10507 | 0xa090, |
10508 | 0xa091, |
10509 | 0xa092, |
10510 | 0xa093, |
10511 | 0xa094, |
10512 | 0xa095, |
10513 | 0xa096, |
10514 | 0xa097, |
10515 | 0xa098, |
10516 | 0xa099, |
10517 | 0xa09a, |
10518 | 0xa09b, |
10519 | 0xa09c, |
10520 | 0xa09d, |
10521 | 0xa09e, |
10522 | 0xa09f, |
10523 | 0xa0a0, |
10524 | 0xa0a1, |
10525 | 0xa0a2, |
10526 | 0xa0a3, |
10527 | 0xa0a4, |
10528 | 0xa0a5, |
10529 | 0xa0a6, |
10530 | 0xa0a7, |
10531 | 0xa0a8, |
10532 | 0xa0a9, |
10533 | 0xa0aa, |
10534 | 0xa0ab, |
10535 | 0xa0ac, |
10536 | 0xa0ad, |
10537 | 0xa0ae, |
10538 | 0xa0af, |
10539 | 0xa0b0, |
10540 | 0xa0b1, |
10541 | 0xa0b2, |
10542 | 0xa0b3, |
10543 | 0xa0b4, |
10544 | 0xa0b5, |
10545 | 0xa0b6, |
10546 | 0xa0b7, |
10547 | 0xa0b8, |
10548 | 0xa0b9, |
10549 | 0xa0ba, |
10550 | 0xa0bb, |
10551 | 0xa0bc, |
10552 | 0xa0bd, |
10553 | 0xa0be, |
10554 | 0xa0bf, |
10555 | 0xa0c0, |
10556 | 0xa0c1, |
10557 | 0xa0c2, |
10558 | 0xa0c3, |
10559 | 0xa0c4, |
10560 | 0xa0c5, |
10561 | 0xa0c6, |
10562 | 0xa0c7, |
10563 | 0xa0c8, |
10564 | 0xa0c9, |
10565 | 0xa0ca, |
10566 | 0xa0cb, |
10567 | 0xa0cc, |
10568 | 0xa0cd, |
10569 | 0xa0ce, |
10570 | 0xa0cf, |
10571 | 0xa0d0, |
10572 | 0xa0d1, |
10573 | 0xa0d2, |
10574 | 0xa0d3, |
10575 | 0xa0d4, |
10576 | 0xa0d5, |
10577 | 0xa0d6, |
10578 | 0xa0d7, |
10579 | 0xa0d8, |
10580 | 0xa0d9, |
10581 | 0xa0da, |
10582 | 0xa0db, |
10583 | 0xa0dc, |
10584 | 0xa0dd, |
10585 | 0xa0de, |
10586 | 0xa0df, |
10587 | 0xa0e0, |
10588 | 0xa0e1, |
10589 | 0xa0e2, |
10590 | 0xa0e3, |
10591 | 0xa0e4, |
10592 | 0xa0e5, |
10593 | 0xa0e6, |
10594 | 0xa0e7, |
10595 | 0xa0e8, |
10596 | 0xa0e9, |
10597 | 0xa0ea, |
10598 | 0xa0eb, |
10599 | 0xa0ec, |
10600 | 0xa0ed, |
10601 | 0xa0ee, |
10602 | 0xa0ef, |
10603 | 0xa0f8, |
10604 | 0xa800, |
10605 | 0xa802, |
10606 | 0xa803, |
10607 | 0xa804, |
10608 | 0xa805, |
10609 | 0xa806, |
10610 | 0xa807, |
10611 | 0xa808, |
10612 | 0xa809, |
10613 | 0xa80a, |
10614 | 0xa80b, |
10615 | 0xa80c, |
10616 | 0xa80d, |
10617 | 0xa80e, |
10618 | 0xa80f, |
10619 | 0xa810, |
10620 | 0xa811, |
10621 | 0xa812, |
10622 | 0xa813, |
10623 | 0xa814, |
10624 | 0xa815, |
10625 | 0xa816, |
10626 | 0xa817, |
10627 | 0xa818, |
10628 | 0xa819, |
10629 | 0xa81a, |
10630 | 0xa81b, |
10631 | 0xa81c, |
10632 | 0xa81d, |
10633 | 0xa81e, |
10634 | 0xa81f, |
10635 | 0xa820, |
10636 | 0xa821, |
10637 | 0xa822, |
10638 | 0xa823, |
10639 | 0xa824, |
10640 | 0xa825, |
10641 | 0xa830, |
10642 | 0xa831, |
10643 | 0xa832, |
10644 | 0xa833, |
10645 | 0xa834, |
10646 | 0xa835, |
10647 | 0xa836, |
10648 | 0xa837, |
10649 | 0xa838, |
10650 | 0xa839, |
10651 | 0xa83a, |
10652 | 0xa83b, |
10653 | 0xa83c, |
10654 | 0xa83d, |
10655 | 0xa840, |
10656 | 0xa842, |
10657 | 0xa843, |
10658 | 0xa844, |
10659 | 0xa845, |
10660 | 0xa846, |
10661 | 0xa847, |
10662 | 0xa848, |
10663 | 0xa849, |
10664 | 0xa84a, |
10665 | 0xa84b, |
10666 | 0xa84c, |
10667 | 0xa84d, |
10668 | 0xa84e, |
10669 | 0xa84f, |
10670 | 0xa850, |
10671 | 0xa851, |
10672 | 0xa852, |
10673 | 0xa853, |
10674 | 0xa854, |
10675 | 0xa855, |
10676 | 0xa856, |
10677 | 0xa857, |
10678 | 0xa858, |
10679 | 0xa859, |
10680 | 0xa85a, |
10681 | 0xa85b, |
10682 | 0xa85c, |
10683 | 0xa85d, |
10684 | 0xa85e, |
10685 | 0xa85f, |
10686 | 0xa860, |
10687 | 0xa861, |
10688 | 0xa862, |
10689 | 0xa863, |
10690 | 0xa864, |
10691 | 0xa865, |
10692 | 0xa870, |
10693 | 0xa871, |
10694 | 0xa872, |
10695 | 0xa873, |
10696 | 0xa874, |
10697 | 0xa875, |
10698 | 0xa876, |
10699 | 0xa877, |
10700 | 0xa878, |
10701 | 0xa879, |
10702 | 0xa87a, |
10703 | 0xa87b, |
10704 | 0xa87c, |
10705 | 0xa87d, |
10706 | 0xa87e, |
10707 | 0xa87f, |
10708 | 0xa880, |
10709 | 0xa881, |
10710 | 0xa882, |
10711 | 0xa883, |
10712 | 0xa884, |
10713 | 0xa885, |
10714 | 0xa886, |
10715 | 0xa887, |
10716 | 0xa888, |
10717 | 0xa889, |
10718 | 0xa88a, |
10719 | 0xa88b, |
10720 | 0xa88c, |
10721 | 0xa88d, |
10722 | 0xa88e, |
10723 | 0xa88f, |
10724 | 0xa890, |
10725 | 0xa891, |
10726 | 0xa892, |
10727 | 0xa893, |
10728 | 0xa894, |
10729 | 0xa895, |
10730 | 0xa896, |
10731 | 0xa980, |
10732 | 0xa982, |
10733 | 0xa983, |
10734 | 0xa984, |
10735 | 0xa985, |
10736 | 0xa986, |
10737 | 0xa987, |
10738 | 0xa988, |
10739 | 0xa989, |
10740 | 0xa98a, |
10741 | 0xa98b, |
10742 | 0xa98c, |
10743 | 0xa98d, |
10744 | 0xa98e, |
10745 | 0xa98f, |
10746 | 0xa990, |
10747 | 0xa991, |
10748 | 0xa992, |
10749 | 0xa993, |
10750 | 0xa994, |
10751 | 0xa995, |
10752 | 0xa996, |
10753 | 0xa997, |
10754 | 0xa998, |
10755 | 0xa999, |
10756 | 0xa99a, |
10757 | 0xa99b, |
10758 | 0xa99c, |
10759 | 0xa99d, |
10760 | 0xa99e, |
10761 | 0xa99f, |
10762 | 0xa9a0, |
10763 | 0xa9a1, |
10764 | 0xa9a2, |
10765 | 0xa9a3, |
10766 | 0xa9a4, |
10767 | 0xa9a5, |
10768 | 0xa9a6, |
10769 | 0xa9a7, |
10770 | 0xa9a9, |
10771 | 0xa9e0, |
10772 | 0xa9e1, |
10773 | 0xa9e4, |
10774 | 0xa9e5, |
10775 | 0xab00, |
10776 | 0xab04, |
10777 | 0xab05, |
10778 | 0xab10, |
10779 | 0xab11, |
10780 | 0xab12, |
10781 | 0xab13, |
10782 | 0xab14, |
10783 | 0xab15, |
10784 | 0xab16, |
10785 | 0xab17, |
10786 | 0xab18, |
10787 | 0xab19, |
10788 | 0xacc0, |
10789 | 0xb300, |
10790 | 0xb301, |
10791 | 0xb304, |
10792 | 0xb305, |
10793 | 0xb306, |
10794 | 0xb307, |
10795 | 0xb4c0, |
10796 | 0xb4c1, |
10797 | 0xb4c2, |
10798 | 0xb4c3, |
10799 | 0xb4c4, |
10800 | 0xb4ca, |
10801 | 0xb4cb, |
10802 | 0xb4cc, |
10803 | 0xb4d1, |
10804 | 0xb800, |
10805 | 0xb801, |
10806 | 0xb802, |
10807 | 0xb803, |
10808 | 0xb980, |
10809 | 0xb982, |
10810 | 0xb983, |
10811 | 0xb984, |
10812 | 0xb985, |
10813 | 0xb986, |
10814 | 0xb990, |
10815 | 0xb991, |
10816 | 0xb992, |
10817 | 0xb993, |
10818 | 0xb994, |
10819 | 0xb995, |
10820 | 0xb996, |
10821 | 0xb997, |
10822 | 0xb998, |
10823 | 0xb999, |
10824 | 0xb99a, |
10825 | 0xb99b, |
10826 | 0xb9c0, |
10827 | 0xb9c1, |
10828 | 0xb9c2, |
10829 | 0xb9c3, |
10830 | 0xb9c4, |
10831 | 0xb9c5, |
10832 | 0xb9c6, |
10833 | 0xb9c7, |
10834 | 0xb9c8, |
10835 | 0xb9c9, |
10836 | 0xbb10, |
10837 | }; |
10838 | template<> constexpr inline uint16_t RP_BLIT_REGS<A7XX>[] = { |
10839 | 0xc02, |
10840 | 0xc06, |
10841 | 0xc10, |
10842 | 0xc11, |
10843 | 0xc12, |
10844 | 0xc13, |
10845 | 0xc14, |
10846 | 0xc15, |
10847 | 0xc16, |
10848 | 0xc17, |
10849 | 0xc18, |
10850 | 0xc19, |
10851 | 0xc1a, |
10852 | 0xc1b, |
10853 | 0xc1c, |
10854 | 0xc1d, |
10855 | 0xc1e, |
10856 | 0xc1f, |
10857 | 0xc20, |
10858 | 0xc21, |
10859 | 0xc22, |
10860 | 0xc23, |
10861 | 0xc24, |
10862 | 0xc25, |
10863 | 0xc26, |
10864 | 0xc27, |
10865 | 0xc28, |
10866 | 0xc29, |
10867 | 0xc2a, |
10868 | 0xc2b, |
10869 | 0xc2c, |
10870 | 0xc2d, |
10871 | 0xc2e, |
10872 | 0xc2f, |
10873 | 0xc38, |
10874 | 0xc39, |
10875 | 0xc3a, |
10876 | 0xc3b, |
10877 | 0xc3c, |
10878 | 0xc3d, |
10879 | 0xc3e, |
10880 | 0xc3f, |
10881 | 0xc40, |
10882 | 0xc41, |
10883 | 0xc42, |
10884 | 0xc43, |
10885 | 0xc44, |
10886 | 0xc45, |
10887 | 0xc46, |
10888 | 0xc47, |
10889 | 0xc48, |
10890 | 0xc49, |
10891 | 0xc4a, |
10892 | 0xc4b, |
10893 | 0xc4c, |
10894 | 0xc4d, |
10895 | 0xc4e, |
10896 | 0xc4f, |
10897 | 0xc50, |
10898 | 0xc51, |
10899 | 0xc52, |
10900 | 0xc53, |
10901 | 0xc54, |
10902 | 0xc55, |
10903 | 0xc56, |
10904 | 0xc57, |
10905 | 0x8000, |
10906 | 0x8001, |
10907 | 0x8002, |
10908 | 0x8003, |
10909 | 0x8004, |
10910 | 0x8005, |
10911 | 0x8006, |
10912 | 0x8007, |
10913 | 0x8010, |
10914 | 0x8011, |
10915 | 0x8012, |
10916 | 0x8013, |
10917 | 0x8014, |
10918 | 0x8015, |
10919 | 0x8016, |
10920 | 0x8017, |
10921 | 0x8018, |
10922 | 0x8019, |
10923 | 0x801a, |
10924 | 0x801b, |
10925 | 0x801c, |
10926 | 0x801d, |
10927 | 0x801e, |
10928 | 0x801f, |
10929 | 0x8020, |
10930 | 0x8021, |
10931 | 0x8022, |
10932 | 0x8023, |
10933 | 0x8024, |
10934 | 0x8025, |
10935 | 0x8026, |
10936 | 0x8027, |
10937 | 0x8028, |
10938 | 0x8029, |
10939 | 0x802a, |
10940 | 0x802b, |
10941 | 0x802c, |
10942 | 0x802d, |
10943 | 0x802e, |
10944 | 0x802f, |
10945 | 0x8030, |
10946 | 0x8031, |
10947 | 0x8032, |
10948 | 0x8033, |
10949 | 0x8034, |
10950 | 0x8035, |
10951 | 0x8036, |
10952 | 0x8037, |
10953 | 0x8038, |
10954 | 0x8039, |
10955 | 0x803a, |
10956 | 0x803b, |
10957 | 0x803c, |
10958 | 0x803d, |
10959 | 0x803e, |
10960 | 0x803f, |
10961 | 0x8040, |
10962 | 0x8041, |
10963 | 0x8042, |
10964 | 0x8043, |
10965 | 0x8044, |
10966 | 0x8045, |
10967 | 0x8046, |
10968 | 0x8047, |
10969 | 0x8048, |
10970 | 0x8049, |
10971 | 0x804a, |
10972 | 0x804b, |
10973 | 0x804c, |
10974 | 0x804d, |
10975 | 0x804e, |
10976 | 0x804f, |
10977 | 0x8050, |
10978 | 0x8051, |
10979 | 0x8052, |
10980 | 0x8053, |
10981 | 0x8054, |
10982 | 0x8055, |
10983 | 0x8056, |
10984 | 0x8057, |
10985 | 0x8058, |
10986 | 0x8059, |
10987 | 0x805a, |
10988 | 0x805b, |
10989 | 0x805c, |
10990 | 0x805d, |
10991 | 0x805e, |
10992 | 0x805f, |
10993 | 0x8060, |
10994 | 0x8061, |
10995 | 0x8062, |
10996 | 0x8063, |
10997 | 0x8064, |
10998 | 0x8065, |
10999 | 0x8066, |
11000 | 0x8067, |
11001 | 0x8068, |
11002 | 0x8069, |
11003 | 0x806a, |
11004 | 0x806b, |
11005 | 0x806c, |
11006 | 0x806d, |
11007 | 0x806e, |
11008 | 0x806f, |
11009 | 0x8070, |
11010 | 0x8071, |
11011 | 0x8072, |
11012 | 0x8073, |
11013 | 0x8074, |
11014 | 0x8075, |
11015 | 0x8076, |
11016 | 0x8077, |
11017 | 0x8078, |
11018 | 0x8079, |
11019 | 0x807a, |
11020 | 0x807b, |
11021 | 0x807c, |
11022 | 0x807d, |
11023 | 0x807e, |
11024 | 0x807f, |
11025 | 0x8080, |
11026 | 0x8081, |
11027 | 0x8082, |
11028 | 0x8083, |
11029 | 0x8084, |
11030 | 0x8085, |
11031 | 0x8086, |
11032 | 0x8087, |
11033 | 0x8088, |
11034 | 0x8089, |
11035 | 0x808a, |
11036 | 0x808b, |
11037 | 0x808c, |
11038 | 0x808d, |
11039 | 0x808e, |
11040 | 0x808f, |
11041 | 0x8090, |
11042 | 0x8091, |
11043 | 0x8092, |
11044 | 0x8094, |
11045 | 0x8095, |
11046 | 0x8096, |
11047 | 0x8097, |
11048 | 0x8098, |
11049 | 0x809b, |
11050 | 0x809c, |
11051 | 0x809d, |
11052 | 0x80a0, |
11053 | 0x80a1, |
11054 | 0x80a2, |
11055 | 0x80a3, |
11056 | 0x80a4, |
11057 | 0x80a5, |
11058 | 0x80a6, |
11059 | 0x80b0, |
11060 | 0x80b1, |
11061 | 0x80b2, |
11062 | 0x80b3, |
11063 | 0x80b4, |
11064 | 0x80b5, |
11065 | 0x80b6, |
11066 | 0x80b7, |
11067 | 0x80b8, |
11068 | 0x80b9, |
11069 | 0x80ba, |
11070 | 0x80bb, |
11071 | 0x80bc, |
11072 | 0x80bd, |
11073 | 0x80be, |
11074 | 0x80bf, |
11075 | 0x80c0, |
11076 | 0x80c1, |
11077 | 0x80c2, |
11078 | 0x80c3, |
11079 | 0x80c4, |
11080 | 0x80c5, |
11081 | 0x80c6, |
11082 | 0x80c7, |
11083 | 0x80c8, |
11084 | 0x80c9, |
11085 | 0x80ca, |
11086 | 0x80cb, |
11087 | 0x80cc, |
11088 | 0x80cd, |
11089 | 0x80ce, |
11090 | 0x80cf, |
11091 | 0x80d0, |
11092 | 0x80d1, |
11093 | 0x80d2, |
11094 | 0x80d3, |
11095 | 0x80d4, |
11096 | 0x80d5, |
11097 | 0x80d6, |
11098 | 0x80d7, |
11099 | 0x80d8, |
11100 | 0x80d9, |
11101 | 0x80da, |
11102 | 0x80db, |
11103 | 0x80dc, |
11104 | 0x80dd, |
11105 | 0x80de, |
11106 | 0x80df, |
11107 | 0x80e0, |
11108 | 0x80e1, |
11109 | 0x80e2, |
11110 | 0x80e3, |
11111 | 0x80e4, |
11112 | 0x80e5, |
11113 | 0x80e6, |
11114 | 0x80e7, |
11115 | 0x80e8, |
11116 | 0x80e9, |
11117 | 0x80ea, |
11118 | 0x80eb, |
11119 | 0x80ec, |
11120 | 0x80ed, |
11121 | 0x80ee, |
11122 | 0x80ef, |
11123 | 0x80f0, |
11124 | 0x80f1, |
11125 | 0x8100, |
11126 | 0x8101, |
11127 | 0x8102, |
11128 | 0x8103, |
11129 | 0x8104, |
11130 | 0x8105, |
11131 | 0x8106, |
11132 | 0x8107, |
11133 | 0x8109, |
11134 | 0x8113, |
11135 | 0x8114, |
11136 | 0x8115, |
11137 | 0x8116, |
11138 | 0x8400, |
11139 | 0x8401, |
11140 | 0x8402, |
11141 | 0x8403, |
11142 | 0x8404, |
11143 | 0x8405, |
11144 | 0x8406, |
11145 | 0x840a, |
11146 | 0x840b, |
11147 | 0x8800, |
11148 | 0x8801, |
11149 | 0x8802, |
11150 | 0x8803, |
11151 | 0x8804, |
11152 | 0x8805, |
11153 | 0x8806, |
11154 | 0x8809, |
11155 | 0x880a, |
11156 | 0x880b, |
11157 | 0x880c, |
11158 | 0x880d, |
11159 | 0x880f, |
11160 | 0x8810, |
11161 | 0x8812, |
11162 | 0x8820, |
11163 | 0x8821, |
11164 | 0x8822, |
11165 | 0x8823, |
11166 | 0x8824, |
11167 | 0x8825, |
11168 | 0x8826, |
11169 | 0x8827, |
11170 | 0x8828, |
11171 | 0x8829, |
11172 | 0x882a, |
11173 | 0x882b, |
11174 | 0x882c, |
11175 | 0x882d, |
11176 | 0x882e, |
11177 | 0x882f, |
11178 | 0x8830, |
11179 | 0x8831, |
11180 | 0x8832, |
11181 | 0x8833, |
11182 | 0x8834, |
11183 | 0x8835, |
11184 | 0x8836, |
11185 | 0x8837, |
11186 | 0x8838, |
11187 | 0x8839, |
11188 | 0x883a, |
11189 | 0x883b, |
11190 | 0x883c, |
11191 | 0x883d, |
11192 | 0x883e, |
11193 | 0x883f, |
11194 | 0x8840, |
11195 | 0x8841, |
11196 | 0x8842, |
11197 | 0x8843, |
11198 | 0x8844, |
11199 | 0x8845, |
11200 | 0x8846, |
11201 | 0x8847, |
11202 | 0x8848, |
11203 | 0x8849, |
11204 | 0x884a, |
11205 | 0x884b, |
11206 | 0x884c, |
11207 | 0x884d, |
11208 | 0x884e, |
11209 | 0x884f, |
11210 | 0x8850, |
11211 | 0x8851, |
11212 | 0x8852, |
11213 | 0x8853, |
11214 | 0x8854, |
11215 | 0x8855, |
11216 | 0x8856, |
11217 | 0x8857, |
11218 | 0x8858, |
11219 | 0x8859, |
11220 | 0x885a, |
11221 | 0x885b, |
11222 | 0x885c, |
11223 | 0x885d, |
11224 | 0x885e, |
11225 | 0x885f, |
11226 | 0x8860, |
11227 | 0x8861, |
11228 | 0x8862, |
11229 | 0x8863, |
11230 | 0x8865, |
11231 | 0x8870, |
11232 | 0x8871, |
11233 | 0x8872, |
11234 | 0x8873, |
11235 | 0x8874, |
11236 | 0x8875, |
11237 | 0x8876, |
11238 | 0x8877, |
11239 | 0x8878, |
11240 | 0x8879, |
11241 | 0x8880, |
11242 | 0x8881, |
11243 | 0x8882, |
11244 | 0x8883, |
11245 | 0x8884, |
11246 | 0x8885, |
11247 | 0x8886, |
11248 | 0x8887, |
11249 | 0x8888, |
11250 | 0x8889, |
11251 | 0x8890, |
11252 | 0x8898, |
11253 | 0x88c0, |
11254 | 0x88c1, |
11255 | 0x88d0, |
11256 | 0x88d1, |
11257 | 0x88d2, |
11258 | 0x88d3, |
11259 | 0x88d4, |
11260 | 0x88d5, |
11261 | 0x88d6, |
11262 | 0x88d7, |
11263 | 0x88d8, |
11264 | 0x88d9, |
11265 | 0x88da, |
11266 | 0x88db, |
11267 | 0x88dc, |
11268 | 0x88dd, |
11269 | 0x88de, |
11270 | 0x88df, |
11271 | 0x88e0, |
11272 | 0x88e1, |
11273 | 0x88e2, |
11274 | 0x88e3, |
11275 | 0x8900, |
11276 | 0x8901, |
11277 | 0x8902, |
11278 | 0x8903, |
11279 | 0x8904, |
11280 | 0x8905, |
11281 | 0x8906, |
11282 | 0x8907, |
11283 | 0x8908, |
11284 | 0x8909, |
11285 | 0x890a, |
11286 | 0x890b, |
11287 | 0x890c, |
11288 | 0x890d, |
11289 | 0x890e, |
11290 | 0x890f, |
11291 | 0x8910, |
11292 | 0x8911, |
11293 | 0x8912, |
11294 | 0x8913, |
11295 | 0x8914, |
11296 | 0x8915, |
11297 | 0x8916, |
11298 | 0x8917, |
11299 | 0x8918, |
11300 | 0x8919, |
11301 | 0x891a, |
11302 | 0x8c00, |
11303 | 0x8c01, |
11304 | 0x8c17, |
11305 | 0x8c18, |
11306 | 0x8c19, |
11307 | 0x8c1a, |
11308 | 0x8c1b, |
11309 | 0x8c1c, |
11310 | 0x8c1d, |
11311 | 0x8c1e, |
11312 | 0x8c1f, |
11313 | 0x8c20, |
11314 | 0x8c21, |
11315 | 0x8c22, |
11316 | 0x8c23, |
11317 | 0x8c24, |
11318 | 0x8c25, |
11319 | 0x8c2c, |
11320 | 0x8c2d, |
11321 | 0x8c2e, |
11322 | 0x8c2f, |
11323 | 0x9101, |
11324 | 0x9102, |
11325 | 0x9103, |
11326 | 0x9104, |
11327 | 0x9105, |
11328 | 0x9106, |
11329 | 0x9107, |
11330 | 0x9108, |
11331 | 0x9109, |
11332 | 0x910a, |
11333 | 0x910b, |
11334 | 0x910c, |
11335 | 0x9200, |
11336 | 0x9201, |
11337 | 0x9202, |
11338 | 0x9203, |
11339 | 0x9204, |
11340 | 0x9205, |
11341 | 0x9206, |
11342 | 0x9207, |
11343 | 0x9208, |
11344 | 0x9209, |
11345 | 0x920a, |
11346 | 0x920b, |
11347 | 0x920c, |
11348 | 0x920d, |
11349 | 0x920e, |
11350 | 0x920f, |
11351 | 0x9212, |
11352 | 0x9213, |
11353 | 0x9214, |
11354 | 0x9215, |
11355 | 0x9216, |
11356 | 0x9217, |
11357 | 0x9301, |
11358 | 0x9302, |
11359 | 0x9303, |
11360 | 0x9304, |
11361 | 0x9305, |
11362 | 0x9306, |
11363 | 0x9307, |
11364 | 0x9308, |
11365 | 0x9309, |
11366 | 0x9311, |
11367 | 0x9312, |
11368 | 0x9313, |
11369 | 0x9314, |
11370 | 0x9315, |
11371 | 0x9316, |
11372 | 0x9317, |
11373 | 0x9800, |
11374 | 0x9801, |
11375 | 0x9802, |
11376 | 0x9803, |
11377 | 0x9804, |
11378 | 0x9805, |
11379 | 0x9806, |
11380 | 0x9808, |
11381 | 0x9809, |
11382 | 0x9b00, |
11383 | 0x9b01, |
11384 | 0x9b02, |
11385 | 0x9b03, |
11386 | 0x9b04, |
11387 | 0x9b05, |
11388 | 0x9b07, |
11389 | 0x9b08, |
11390 | 0x9b09, |
11391 | 0xa000, |
11392 | 0xa001, |
11393 | 0xa002, |
11394 | 0xa003, |
11395 | 0xa004, |
11396 | 0xa005, |
11397 | 0xa006, |
11398 | 0xa008, |
11399 | 0xa00e, |
11400 | 0xa00f, |
11401 | 0xa010, |
11402 | 0xa011, |
11403 | 0xa012, |
11404 | 0xa013, |
11405 | 0xa014, |
11406 | 0xa015, |
11407 | 0xa016, |
11408 | 0xa017, |
11409 | 0xa018, |
11410 | 0xa019, |
11411 | 0xa01a, |
11412 | 0xa01b, |
11413 | 0xa01c, |
11414 | 0xa01d, |
11415 | 0xa01e, |
11416 | 0xa01f, |
11417 | 0xa020, |
11418 | 0xa021, |
11419 | 0xa022, |
11420 | 0xa023, |
11421 | 0xa024, |
11422 | 0xa025, |
11423 | 0xa026, |
11424 | 0xa027, |
11425 | 0xa028, |
11426 | 0xa029, |
11427 | 0xa02a, |
11428 | 0xa02b, |
11429 | 0xa02c, |
11430 | 0xa02d, |
11431 | 0xa02e, |
11432 | 0xa02f, |
11433 | 0xa030, |
11434 | 0xa031, |
11435 | 0xa032, |
11436 | 0xa033, |
11437 | 0xa034, |
11438 | 0xa035, |
11439 | 0xa036, |
11440 | 0xa037, |
11441 | 0xa038, |
11442 | 0xa039, |
11443 | 0xa03a, |
11444 | 0xa03b, |
11445 | 0xa03c, |
11446 | 0xa03d, |
11447 | 0xa03e, |
11448 | 0xa03f, |
11449 | 0xa040, |
11450 | 0xa041, |
11451 | 0xa042, |
11452 | 0xa043, |
11453 | 0xa044, |
11454 | 0xa045, |
11455 | 0xa046, |
11456 | 0xa047, |
11457 | 0xa048, |
11458 | 0xa049, |
11459 | 0xa04a, |
11460 | 0xa04b, |
11461 | 0xa04c, |
11462 | 0xa04d, |
11463 | 0xa04e, |
11464 | 0xa04f, |
11465 | 0xa050, |
11466 | 0xa051, |
11467 | 0xa052, |
11468 | 0xa053, |
11469 | 0xa054, |
11470 | 0xa055, |
11471 | 0xa056, |
11472 | 0xa057, |
11473 | 0xa058, |
11474 | 0xa059, |
11475 | 0xa05a, |
11476 | 0xa05b, |
11477 | 0xa05c, |
11478 | 0xa05d, |
11479 | 0xa05e, |
11480 | 0xa05f, |
11481 | 0xa060, |
11482 | 0xa061, |
11483 | 0xa062, |
11484 | 0xa063, |
11485 | 0xa064, |
11486 | 0xa065, |
11487 | 0xa066, |
11488 | 0xa067, |
11489 | 0xa068, |
11490 | 0xa069, |
11491 | 0xa06a, |
11492 | 0xa06b, |
11493 | 0xa06c, |
11494 | 0xa06d, |
11495 | 0xa06e, |
11496 | 0xa06f, |
11497 | 0xa070, |
11498 | 0xa071, |
11499 | 0xa072, |
11500 | 0xa073, |
11501 | 0xa074, |
11502 | 0xa075, |
11503 | 0xa076, |
11504 | 0xa077, |
11505 | 0xa078, |
11506 | 0xa079, |
11507 | 0xa07a, |
11508 | 0xa07b, |
11509 | 0xa07c, |
11510 | 0xa07d, |
11511 | 0xa07e, |
11512 | 0xa07f, |
11513 | 0xa080, |
11514 | 0xa081, |
11515 | 0xa082, |
11516 | 0xa083, |
11517 | 0xa084, |
11518 | 0xa085, |
11519 | 0xa086, |
11520 | 0xa087, |
11521 | 0xa088, |
11522 | 0xa089, |
11523 | 0xa08a, |
11524 | 0xa08b, |
11525 | 0xa08c, |
11526 | 0xa08d, |
11527 | 0xa08e, |
11528 | 0xa08f, |
11529 | 0xa090, |
11530 | 0xa091, |
11531 | 0xa092, |
11532 | 0xa093, |
11533 | 0xa094, |
11534 | 0xa095, |
11535 | 0xa096, |
11536 | 0xa097, |
11537 | 0xa098, |
11538 | 0xa099, |
11539 | 0xa09a, |
11540 | 0xa09b, |
11541 | 0xa09c, |
11542 | 0xa09d, |
11543 | 0xa09e, |
11544 | 0xa09f, |
11545 | 0xa0a0, |
11546 | 0xa0a1, |
11547 | 0xa0a2, |
11548 | 0xa0a3, |
11549 | 0xa0a4, |
11550 | 0xa0a5, |
11551 | 0xa0a6, |
11552 | 0xa0a7, |
11553 | 0xa0a8, |
11554 | 0xa0a9, |
11555 | 0xa0aa, |
11556 | 0xa0ab, |
11557 | 0xa0ac, |
11558 | 0xa0ad, |
11559 | 0xa0ae, |
11560 | 0xa0af, |
11561 | 0xa0b0, |
11562 | 0xa0b1, |
11563 | 0xa0b2, |
11564 | 0xa0b3, |
11565 | 0xa0b4, |
11566 | 0xa0b5, |
11567 | 0xa0b6, |
11568 | 0xa0b7, |
11569 | 0xa0b8, |
11570 | 0xa0b9, |
11571 | 0xa0ba, |
11572 | 0xa0bb, |
11573 | 0xa0bc, |
11574 | 0xa0bd, |
11575 | 0xa0be, |
11576 | 0xa0bf, |
11577 | 0xa0c0, |
11578 | 0xa0c1, |
11579 | 0xa0c2, |
11580 | 0xa0c3, |
11581 | 0xa0c4, |
11582 | 0xa0c5, |
11583 | 0xa0c6, |
11584 | 0xa0c7, |
11585 | 0xa0c8, |
11586 | 0xa0c9, |
11587 | 0xa0ca, |
11588 | 0xa0cb, |
11589 | 0xa0cc, |
11590 | 0xa0cd, |
11591 | 0xa0ce, |
11592 | 0xa0cf, |
11593 | 0xa0d0, |
11594 | 0xa0d1, |
11595 | 0xa0d2, |
11596 | 0xa0d3, |
11597 | 0xa0d4, |
11598 | 0xa0d5, |
11599 | 0xa0d6, |
11600 | 0xa0d7, |
11601 | 0xa0d8, |
11602 | 0xa0d9, |
11603 | 0xa0da, |
11604 | 0xa0db, |
11605 | 0xa0dc, |
11606 | 0xa0dd, |
11607 | 0xa0de, |
11608 | 0xa0df, |
11609 | 0xa0e0, |
11610 | 0xa0e1, |
11611 | 0xa0e2, |
11612 | 0xa0e3, |
11613 | 0xa0e4, |
11614 | 0xa0e5, |
11615 | 0xa0e6, |
11616 | 0xa0e7, |
11617 | 0xa0e8, |
11618 | 0xa0e9, |
11619 | 0xa0ea, |
11620 | 0xa0eb, |
11621 | 0xa0ec, |
11622 | 0xa0ed, |
11623 | 0xa0ee, |
11624 | 0xa0ef, |
11625 | 0xa0f8, |
11626 | 0xa800, |
11627 | 0xa802, |
11628 | 0xa803, |
11629 | 0xa804, |
11630 | 0xa805, |
11631 | 0xa806, |
11632 | 0xa807, |
11633 | 0xa808, |
11634 | 0xa809, |
11635 | 0xa80a, |
11636 | 0xa80b, |
11637 | 0xa80c, |
11638 | 0xa80d, |
11639 | 0xa80e, |
11640 | 0xa80f, |
11641 | 0xa810, |
11642 | 0xa811, |
11643 | 0xa812, |
11644 | 0xa813, |
11645 | 0xa814, |
11646 | 0xa815, |
11647 | 0xa816, |
11648 | 0xa817, |
11649 | 0xa818, |
11650 | 0xa819, |
11651 | 0xa81a, |
11652 | 0xa81b, |
11653 | 0xa81c, |
11654 | 0xa81d, |
11655 | 0xa81e, |
11656 | 0xa81f, |
11657 | 0xa820, |
11658 | 0xa821, |
11659 | 0xa822, |
11660 | 0xa823, |
11661 | 0xa824, |
11662 | 0xa825, |
11663 | 0xa827, |
11664 | 0xa830, |
11665 | 0xa831, |
11666 | 0xa832, |
11667 | 0xa833, |
11668 | 0xa834, |
11669 | 0xa835, |
11670 | 0xa836, |
11671 | 0xa837, |
11672 | 0xa838, |
11673 | 0xa839, |
11674 | 0xa83a, |
11675 | 0xa83b, |
11676 | 0xa83c, |
11677 | 0xa83d, |
11678 | 0xa83f, |
11679 | 0xa840, |
11680 | 0xa842, |
11681 | 0xa843, |
11682 | 0xa844, |
11683 | 0xa845, |
11684 | 0xa846, |
11685 | 0xa847, |
11686 | 0xa848, |
11687 | 0xa849, |
11688 | 0xa84a, |
11689 | 0xa84b, |
11690 | 0xa84c, |
11691 | 0xa84d, |
11692 | 0xa84e, |
11693 | 0xa84f, |
11694 | 0xa850, |
11695 | 0xa851, |
11696 | 0xa852, |
11697 | 0xa853, |
11698 | 0xa854, |
11699 | 0xa855, |
11700 | 0xa856, |
11701 | 0xa857, |
11702 | 0xa858, |
11703 | 0xa859, |
11704 | 0xa85a, |
11705 | 0xa85b, |
11706 | 0xa85c, |
11707 | 0xa85d, |
11708 | 0xa85e, |
11709 | 0xa85f, |
11710 | 0xa860, |
11711 | 0xa861, |
11712 | 0xa862, |
11713 | 0xa863, |
11714 | 0xa864, |
11715 | 0xa865, |
11716 | 0xa867, |
11717 | 0xa870, |
11718 | 0xa871, |
11719 | 0xa872, |
11720 | 0xa873, |
11721 | 0xa874, |
11722 | 0xa875, |
11723 | 0xa876, |
11724 | 0xa877, |
11725 | 0xa878, |
11726 | 0xa879, |
11727 | 0xa87a, |
11728 | 0xa87b, |
11729 | 0xa87c, |
11730 | 0xa87d, |
11731 | 0xa87e, |
11732 | 0xa87f, |
11733 | 0xa880, |
11734 | 0xa881, |
11735 | 0xa882, |
11736 | 0xa883, |
11737 | 0xa884, |
11738 | 0xa885, |
11739 | 0xa886, |
11740 | 0xa887, |
11741 | 0xa888, |
11742 | 0xa889, |
11743 | 0xa88a, |
11744 | 0xa88b, |
11745 | 0xa88c, |
11746 | 0xa88d, |
11747 | 0xa88e, |
11748 | 0xa88f, |
11749 | 0xa890, |
11750 | 0xa891, |
11751 | 0xa892, |
11752 | 0xa893, |
11753 | 0xa894, |
11754 | 0xa895, |
11755 | 0xa896, |
11756 | 0xa898, |
11757 | 0xa980, |
11758 | 0xa982, |
11759 | 0xa983, |
11760 | 0xa984, |
11761 | 0xa985, |
11762 | 0xa986, |
11763 | 0xa987, |
11764 | 0xa988, |
11765 | 0xa989, |
11766 | 0xa98a, |
11767 | 0xa98b, |
11768 | 0xa98c, |
11769 | 0xa98d, |
11770 | 0xa98e, |
11771 | 0xa98f, |
11772 | 0xa990, |
11773 | 0xa991, |
11774 | 0xa992, |
11775 | 0xa993, |
11776 | 0xa994, |
11777 | 0xa995, |
11778 | 0xa996, |
11779 | 0xa997, |
11780 | 0xa998, |
11781 | 0xa999, |
11782 | 0xa99a, |
11783 | 0xa99b, |
11784 | 0xa99c, |
11785 | 0xa99d, |
11786 | 0xa99e, |
11787 | 0xa99f, |
11788 | 0xa9a0, |
11789 | 0xa9a1, |
11790 | 0xa9a2, |
11791 | 0xa9a3, |
11792 | 0xa9a4, |
11793 | 0xa9a5, |
11794 | 0xa9a6, |
11795 | 0xa9a7, |
11796 | 0xa9a9, |
11797 | 0xa9aa, |
11798 | 0xa9ae, |
11799 | 0xa9bf, |
11800 | 0xa9c6, |
11801 | 0xa9c7, |
11802 | 0xa9c8, |
11803 | 0xa9c9, |
11804 | 0xa9ca, |
11805 | 0xa9cb, |
11806 | 0xa9d4, |
11807 | 0xa9d5, |
11808 | 0xa9d6, |
11809 | 0xa9d7, |
11810 | 0xa9d8, |
11811 | 0xa9d9, |
11812 | 0xa9da, |
11813 | 0xa9db, |
11814 | 0xa9dc, |
11815 | 0xa9dd, |
11816 | 0xa9de, |
11817 | 0xa9e0, |
11818 | 0xa9e1, |
11819 | 0xa9e4, |
11820 | 0xa9e5, |
11821 | 0xab00, |
11822 | 0xab03, |
11823 | 0xab04, |
11824 | 0xab05, |
11825 | 0xab0a, |
11826 | 0xab0b, |
11827 | 0xab0c, |
11828 | 0xab0d, |
11829 | 0xab0e, |
11830 | 0xab0f, |
11831 | 0xab10, |
11832 | 0xab11, |
11833 | 0xab12, |
11834 | 0xab13, |
11835 | 0xab14, |
11836 | 0xab15, |
11837 | 0xab16, |
11838 | 0xab17, |
11839 | 0xab18, |
11840 | 0xab19, |
11841 | 0xab21, |
11842 | 0xb2c0, |
11843 | 0xb2c2, |
11844 | 0xb2c3, |
11845 | 0xb2ca, |
11846 | 0xb2cb, |
11847 | 0xb2cc, |
11848 | 0xb2d2, |
11849 | 0xb300, |
11850 | 0xb301, |
11851 | 0xb304, |
11852 | 0xb305, |
11853 | 0xb306, |
11854 | 0xb307, |
11855 | }; |
11856 | #endif |
11857 | |
11858 | #endif /* A6XX_XML */ |
11859 | |