| 1 | #ifndef A6XX_GMU_XML |
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| 2 | #define A6XX_GMU_XML |
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| 3 | |
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| 4 | /* Autogenerated file, DO NOT EDIT manually! |
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| 5 | |
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| 6 | This file was generated by the rules-ng-ng gen_header.py tool in this git repository: |
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| 7 | http://gitlab.freedesktop.org/mesa/mesa/ |
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| 8 | git clone https://gitlab.freedesktop.org/mesa/mesa.git |
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| 9 | |
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| 10 | The rules-ng-ng source files this header was generated from are: |
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| 11 | |
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| 12 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11820 bytes, from Fri Jun 2 14:59:26 2023) |
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| 13 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023) |
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| 14 | - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023) |
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| 15 | |
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| 16 | Copyright (C) 2013-2024 by the following authors: |
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| 17 | - Rob Clark <robdclark@gmail.com> Rob Clark |
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| 18 | - Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin |
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| 19 | |
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| 20 | Permission is hereby granted, free of charge, to any person obtaining |
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| 21 | a copy of this software and associated documentation files (the |
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| 22 | "Software"), to deal in the Software without restriction, including |
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| 23 | without limitation the rights to use, copy, modify, merge, publish, |
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| 24 | distribute, sublicense, and/or sell copies of the Software, and to |
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| 25 | permit persons to whom the Software is furnished to do so, subject to |
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| 26 | the following conditions: |
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| 27 | |
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| 28 | The above copyright notice and this permission notice (including the |
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| 29 | next paragraph) shall be included in all copies or substantial |
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| 30 | portions of the Software. |
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| 31 | |
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| 32 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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| 33 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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| 34 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
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| 35 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
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| 36 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
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| 37 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
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| 38 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 39 | |
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| 40 | */ |
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| 41 | |
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| 42 | #ifdef __KERNEL__ |
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| 43 | #include <linux/bug.h> |
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| 44 | #define assert(x) BUG_ON(!(x)) |
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| 45 | #else |
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| 46 | #include <assert.h> |
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| 47 | #endif |
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| 48 | |
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| 49 | #ifdef __cplusplus |
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| 50 | #define __struct_cast(X) |
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| 51 | #else |
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| 52 | #define __struct_cast(X) (struct X) |
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| 53 | #endif |
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| 54 | |
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| 55 | #define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB 0x00800000 |
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| 56 | #define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB 0x40000000 |
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| 57 | |
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| 58 | #define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK 0x00400000 |
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| 59 | #define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK 0x40000000 |
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| 60 | #define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK 0x40000000 |
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| 61 | #define A6XX_GMU_OOB_DCVS_SET_MASK 0x00800000 |
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| 62 | #define A6XX_GMU_OOB_DCVS_CHECK_MASK 0x80000000 |
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| 63 | #define A6XX_GMU_OOB_DCVS_CLEAR_MASK 0x80000000 |
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| 64 | #define A6XX_GMU_OOB_GPU_SET_MASK 0x00040000 |
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| 65 | #define A6XX_GMU_OOB_GPU_CHECK_MASK 0x04000000 |
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| 66 | #define A6XX_GMU_OOB_GPU_CLEAR_MASK 0x04000000 |
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| 67 | #define A6XX_GMU_OOB_PERFCNTR_SET_MASK 0x00020000 |
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| 68 | #define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK 0x02000000 |
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| 69 | #define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK 0x02000000 |
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| 70 | |
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| 71 | #define A6XX_HFI_IRQ_MSGQ_MASK 0x00000001 |
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| 72 | #define A6XX_HFI_IRQ_DSGQ_MASK 0x00000002 |
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| 73 | #define A6XX_HFI_IRQ_BLOCKED_MSG_MASK 0x00000004 |
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| 74 | #define A6XX_HFI_IRQ_CM3_FAULT_MASK 0x00800000 |
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| 75 | #define A6XX_HFI_IRQ_GMU_ERR_MASK__MASK 0x007f0000 |
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| 76 | #define A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT 16 |
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| 77 | static inline uint32_t A6XX_HFI_IRQ_GMU_ERR_MASK(uint32_t val) |
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| 78 | { |
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| 79 | return ((val) << A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT) & A6XX_HFI_IRQ_GMU_ERR_MASK__MASK; |
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| 80 | } |
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| 81 | #define A6XX_HFI_IRQ_OOB_MASK__MASK 0xff000000 |
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| 82 | #define A6XX_HFI_IRQ_OOB_MASK__SHIFT 24 |
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| 83 | static inline uint32_t A6XX_HFI_IRQ_OOB_MASK(uint32_t val) |
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| 84 | { |
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| 85 | return ((val) << A6XX_HFI_IRQ_OOB_MASK__SHIFT) & A6XX_HFI_IRQ_OOB_MASK__MASK; |
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| 86 | } |
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| 87 | |
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| 88 | #define A6XX_HFI_H2F_IRQ_MASK_BIT 0x00000001 |
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| 89 | |
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| 90 | #define REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL 0x00000080 |
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| 91 | |
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| 92 | #define REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL 0x00000081 |
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| 93 | |
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| 94 | #define REG_A6XX_GMU_CM3_ITCM_START 0x00000c00 |
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| 95 | |
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| 96 | #define REG_A6XX_GMU_CM3_DTCM_START 0x00001c00 |
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| 97 | |
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| 98 | #define REG_A6XX_GMU_NMI_CONTROL_STATUS 0x000023f0 |
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| 99 | |
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| 100 | #define REG_A6XX_GMU_BOOT_SLUMBER_OPTION 0x000023f8 |
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| 101 | |
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| 102 | #define REG_A6XX_GMU_GX_VOTE_IDX 0x000023f9 |
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| 103 | |
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| 104 | #define REG_A6XX_GMU_MX_VOTE_IDX 0x000023fa |
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| 105 | |
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| 106 | #define REG_A6XX_GMU_DCVS_ACK_OPTION 0x000023fc |
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| 107 | |
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| 108 | #define REG_A6XX_GMU_DCVS_PERF_SETTING 0x000023fd |
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| 109 | |
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| 110 | #define REG_A6XX_GMU_DCVS_BW_SETTING 0x000023fe |
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| 111 | |
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| 112 | #define REG_A6XX_GMU_DCVS_RETURN 0x000023ff |
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| 113 | |
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| 114 | #define REG_A6XX_GMU_ICACHE_CONFIG 0x00004c00 |
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| 115 | |
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| 116 | #define REG_A6XX_GMU_DCACHE_CONFIG 0x00004c01 |
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| 117 | |
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| 118 | #define REG_A6XX_GMU_SYS_BUS_CONFIG 0x00004c0f |
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| 119 | |
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| 120 | #define REG_A6XX_GMU_CM3_SYSRESET 0x00005000 |
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| 121 | |
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| 122 | #define REG_A6XX_GMU_CM3_BOOT_CONFIG 0x00005001 |
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| 123 | |
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| 124 | #define REG_A6XX_GMU_CM3_FW_BUSY 0x0000501a |
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| 125 | |
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| 126 | #define REG_A6XX_GMU_CM3_FW_INIT_RESULT 0x0000501c |
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| 127 | |
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| 128 | #define REG_A6XX_GMU_CM3_CFG 0x0000502d |
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| 129 | |
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| 130 | #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE 0x00005040 |
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| 131 | |
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| 132 | #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0 0x00005041 |
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| 133 | |
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| 134 | #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1 0x00005042 |
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| 135 | |
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| 136 | #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L 0x00005044 |
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| 137 | |
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| 138 | #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H 0x00005045 |
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| 139 | |
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| 140 | #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L 0x00005046 |
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| 141 | |
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| 142 | #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H 0x00005047 |
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| 143 | |
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| 144 | #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L 0x00005048 |
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| 145 | |
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| 146 | #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H 0x00005049 |
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| 147 | |
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| 148 | #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L 0x0000504a |
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| 149 | |
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| 150 | #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H 0x0000504b |
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| 151 | |
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| 152 | #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L 0x0000504c |
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| 153 | |
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| 154 | #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H 0x0000504d |
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| 155 | |
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| 156 | #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L 0x0000504e |
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| 157 | |
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| 158 | #define REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H 0x0000504f |
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| 159 | |
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| 160 | #define REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL 0x000050c0 |
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| 161 | #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE 0x00000001 |
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| 162 | #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE 0x00000002 |
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| 163 | #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE 0x00000004 |
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| 164 | #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK 0x00003c00 |
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| 165 | #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT 10 |
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| 166 | static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS(uint32_t val) |
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| 167 | { |
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| 168 | return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_NUM_PASS_SKIPS__MASK; |
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| 169 | } |
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| 170 | #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK 0xffffc000 |
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| 171 | #define A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT 14 |
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| 172 | static inline uint32_t A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH(uint32_t val) |
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| 173 | { |
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| 174 | return ((val) << A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__SHIFT) & A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_MIN_PASS_LENGTH__MASK; |
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| 175 | } |
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| 176 | |
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| 177 | #define REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST 0x000050c1 |
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| 178 | |
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| 179 | #define REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST 0x000050c2 |
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| 180 | |
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| 181 | #define REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS 0x000050d0 |
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| 182 | #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_OFF 0x00000001 |
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| 183 | #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWERING_ON 0x00000002 |
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| 184 | #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF 0x00000004 |
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| 185 | #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_ON 0x00000008 |
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| 186 | #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF 0x00000010 |
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| 187 | #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GMU_UP_POWER_STATE 0x00000020 |
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| 188 | #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF 0x00000040 |
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| 189 | #define A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF 0x00000080 |
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| 190 | |
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| 191 | #define REG_A6XX_GMU_GPU_NAP_CTRL 0x000050e4 |
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| 192 | #define A6XX_GMU_GPU_NAP_CTRL_HW_NAP_ENABLE 0x00000001 |
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| 193 | #define A6XX_GMU_GPU_NAP_CTRL_SID__MASK 0x000001f0 |
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| 194 | #define A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT 4 |
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| 195 | static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) |
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| 196 | { |
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| 197 | return ((val) << A6XX_GMU_GPU_NAP_CTRL_SID__SHIFT) & A6XX_GMU_GPU_NAP_CTRL_SID__MASK; |
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| 198 | } |
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| 199 | |
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| 200 | #define REG_A6XX_GMU_RPMH_CTRL 0x000050e8 |
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| 201 | #define A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE 0x00000001 |
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| 202 | #define A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE 0x00000010 |
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| 203 | #define A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE 0x00000100 |
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| 204 | #define A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE 0x00000200 |
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| 205 | #define A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE 0x00000400 |
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| 206 | #define A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE 0x00000800 |
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| 207 | #define A6XX_GMU_RPMH_CTRL_DDR_MIN_VOTE_ENABLE 0x00001000 |
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| 208 | #define A6XX_GMU_RPMH_CTRL_MX_MIN_VOTE_ENABLE 0x00002000 |
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| 209 | #define A6XX_GMU_RPMH_CTRL_CX_MIN_VOTE_ENABLE 0x00004000 |
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| 210 | #define A6XX_GMU_RPMH_CTRL_GFX_MIN_VOTE_ENABLE 0x00008000 |
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| 211 | |
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| 212 | #define REG_A6XX_GMU_RPMH_HYST_CTRL 0x000050e9 |
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| 213 | |
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| 214 | #define REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE 0x000050ec |
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| 215 | |
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| 216 | #define REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF 0x000050f0 |
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| 217 | |
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| 218 | #define REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF 0x000050f1 |
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| 219 | |
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| 220 | #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG 0x00005100 |
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| 221 | |
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| 222 | #define REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP 0x00005101 |
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| 223 | |
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| 224 | #define REG_A6XX_GMU_BOOT_KMD_LM_HANDSHAKE 0x000051f0 |
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| 225 | |
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| 226 | #define REG_A6XX_GMU_LLM_GLM_SLEEP_CTRL 0x00005157 |
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| 227 | |
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| 228 | #define REG_A6XX_GMU_LLM_GLM_SLEEP_STATUS 0x00005158 |
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| 229 | |
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| 230 | #define REG_A6XX_GMU_ALWAYS_ON_COUNTER_L 0x00005088 |
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| 231 | |
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| 232 | #define REG_A6XX_GMU_ALWAYS_ON_COUNTER_H 0x00005089 |
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| 233 | |
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| 234 | #define REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE 0x000050c3 |
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| 235 | |
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| 236 | #define REG_A6XX_GMU_HFI_CTRL_STATUS 0x00005180 |
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| 237 | |
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| 238 | #define REG_A6XX_GMU_HFI_VERSION_INFO 0x00005181 |
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| 239 | |
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| 240 | #define REG_A6XX_GMU_HFI_SFR_ADDR 0x00005182 |
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| 241 | |
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| 242 | #define REG_A6XX_GMU_HFI_MMAP_ADDR 0x00005183 |
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| 243 | |
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| 244 | #define REG_A6XX_GMU_HFI_QTBL_INFO 0x00005184 |
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| 245 | |
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| 246 | #define REG_A6XX_GMU_HFI_QTBL_ADDR 0x00005185 |
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| 247 | |
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| 248 | #define REG_A6XX_GMU_HFI_CTRL_INIT 0x00005186 |
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| 249 | |
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| 250 | #define REG_A6XX_GMU_GMU2HOST_INTR_SET 0x00005190 |
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| 251 | |
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| 252 | #define REG_A6XX_GMU_GMU2HOST_INTR_CLR 0x00005191 |
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| 253 | |
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| 254 | #define REG_A6XX_GMU_GMU2HOST_INTR_INFO 0x00005192 |
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| 255 | #define A6XX_GMU_GMU2HOST_INTR_INFO_MSGQ 0x00000001 |
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| 256 | #define A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT 0x00800000 |
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| 257 | |
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| 258 | #define REG_A6XX_GMU_GMU2HOST_INTR_MASK 0x00005193 |
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| 259 | |
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| 260 | #define REG_A6XX_GMU_HOST2GMU_INTR_SET 0x00005194 |
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| 261 | |
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| 262 | #define REG_A6XX_GMU_HOST2GMU_INTR_CLR 0x00005195 |
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| 263 | |
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| 264 | #define REG_A6XX_GMU_HOST2GMU_INTR_RAW_INFO 0x00005196 |
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| 265 | |
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| 266 | #define REG_A6XX_GMU_HOST2GMU_INTR_EN_0 0x00005197 |
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| 267 | |
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| 268 | #define REG_A6XX_GMU_HOST2GMU_INTR_EN_1 0x00005198 |
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| 269 | |
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| 270 | #define REG_A6XX_GMU_HOST2GMU_INTR_EN_2 0x00005199 |
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| 271 | |
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| 272 | #define REG_A6XX_GMU_HOST2GMU_INTR_EN_3 0x0000519a |
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| 273 | |
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| 274 | #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_0 0x0000519b |
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| 275 | |
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| 276 | #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_1 0x0000519c |
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| 277 | |
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| 278 | #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_2 0x0000519d |
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| 279 | |
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| 280 | #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_3 0x0000519e |
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| 281 | |
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| 282 | #define REG_A6XX_GMU_GENERAL_0 0x000051c5 |
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| 283 | |
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| 284 | #define REG_A6XX_GMU_GENERAL_1 0x000051c6 |
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| 285 | |
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| 286 | #define REG_A6XX_GMU_GENERAL_6 0x000051cb |
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| 287 | |
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| 288 | #define REG_A6XX_GMU_GENERAL_7 0x000051cc |
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| 289 | |
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| 290 | #define REG_A7XX_GMU_GENERAL_8 0x000051cd |
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| 291 | |
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| 292 | #define REG_A7XX_GMU_GENERAL_9 0x000051ce |
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| 293 | |
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| 294 | #define REG_A7XX_GMU_GENERAL_10 0x000051cf |
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| 295 | |
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| 296 | #define REG_A6XX_GMU_ISENSE_CTRL 0x0000515d |
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| 297 | |
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| 298 | #define REG_A6XX_GPU_CS_ENABLE_REG 0x00008920 |
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| 299 | |
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| 300 | #define REG_A6XX_GPU_GMU_CX_GMU_ISENSE_CTRL 0x0000515d |
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| 301 | |
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| 302 | #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL3 0x00008578 |
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| 303 | |
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| 304 | #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL2 0x00008558 |
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| 305 | |
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| 306 | #define REG_A6XX_GPU_CS_A_SENSOR_CTRL_0 0x00008580 |
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| 307 | |
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| 308 | #define REG_A6XX_GPU_CS_A_SENSOR_CTRL_2 0x00027ada |
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| 309 | |
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| 310 | #define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000881a |
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| 311 | |
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| 312 | #define REG_A6XX_GPU_CS_AMP_CALIBRATION_CONTROL1 0x00008957 |
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| 313 | |
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| 314 | #define REG_A6XX_GPU_CS_SENSOR_GENERAL_STATUS 0x0000881a |
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| 315 | |
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| 316 | #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_0 0x0000881d |
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| 317 | |
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| 318 | #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_2 0x0000881f |
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| 319 | |
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| 320 | #define REG_A6XX_GPU_CS_AMP_CALIBRATION_STATUS1_4 0x00008821 |
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| 321 | |
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| 322 | #define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE 0x00008965 |
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| 323 | |
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| 324 | #define REG_A6XX_GPU_CS_AMP_PERIOD_CTRL 0x0000896d |
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| 325 | |
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| 326 | #define REG_A6XX_GPU_CS_AMP_CALIBRATION_DONE 0x00008965 |
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| 327 | |
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| 328 | #define REG_A6XX_GPU_GMU_CX_GMU_PWR_THRESHOLD 0x0000514d |
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| 329 | |
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| 330 | #define REG_A6XX_GMU_AO_INTERRUPT_EN 0x00009303 |
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| 331 | |
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| 332 | #define REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR 0x00009304 |
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| 333 | |
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| 334 | #define REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS 0x00009305 |
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| 335 | #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE 0x00000001 |
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| 336 | #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_RSCC_COMP 0x00000002 |
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| 337 | #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_VDROOP 0x00000004 |
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| 338 | #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR 0x00000008 |
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| 339 | #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_DBD_WAKEUP 0x00000010 |
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| 340 | #define A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR 0x00000020 |
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| 341 | |
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| 342 | #define REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK 0x00009306 |
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| 343 | |
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| 344 | #define REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL 0x00009309 |
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| 345 | |
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| 346 | #define REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL 0x0000930a |
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| 347 | |
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| 348 | #define REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL 0x0000930b |
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| 349 | |
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| 350 | #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS 0x0000930c |
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| 351 | #define A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB 0x00800000 |
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| 352 | |
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| 353 | #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2 0x0000930d |
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| 354 | |
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| 355 | #define REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK 0x0000930e |
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| 356 | |
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| 357 | #define REG_A6XX_GMU_AO_AHB_FENCE_CTRL 0x00009310 |
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| 358 | |
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| 359 | #define REG_A6XX_GMU_AHB_FENCE_STATUS 0x00009313 |
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| 360 | |
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| 361 | #define REG_A6XX_GMU_AHB_FENCE_STATUS_CLR 0x00009314 |
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| 362 | |
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| 363 | #define REG_A6XX_GMU_RBBM_INT_UNMASKED_STATUS 0x00009315 |
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| 364 | |
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| 365 | #define REG_A6XX_GMU_AO_SPARE_CNTL 0x00009316 |
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| 366 | |
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| 367 | #define REG_A6XX_GMU_RSCC_CONTROL_REQ 0x00009307 |
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| 368 | |
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| 369 | #define REG_A6XX_GMU_RSCC_CONTROL_ACK 0x00009308 |
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| 370 | |
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| 371 | #define REG_A6XX_GMU_AHB_FENCE_RANGE_0 0x00009311 |
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| 372 | |
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| 373 | #define REG_A6XX_GMU_AHB_FENCE_RANGE_1 0x00009312 |
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| 374 | |
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| 375 | #define REG_A6XX_GPU_CC_GX_GDSCR 0x00009c03 |
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| 376 | |
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| 377 | #define REG_A6XX_GPU_CC_GX_DOMAIN_MISC 0x00009d42 |
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| 378 | |
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| 379 | #define REG_A6XX_GPU_CPR_FSM_CTL 0x0000c001 |
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| 380 | |
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| 381 | #define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00000004 |
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| 382 | |
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| 383 | #define REG_A6XX_RSCC_PDC_SEQ_START_ADDR 0x00000008 |
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| 384 | |
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| 385 | #define REG_A6XX_RSCC_PDC_MATCH_VALUE_LO 0x00000009 |
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| 386 | |
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| 387 | #define REG_A6XX_RSCC_PDC_MATCH_VALUE_HI 0x0000000a |
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| 388 | |
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| 389 | #define REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0 0x0000000b |
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| 390 | |
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| 391 | #define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR 0x0000000d |
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| 392 | |
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| 393 | #define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA 0x0000000e |
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| 394 | |
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| 395 | #define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0 0x00000082 |
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| 396 | |
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| 397 | #define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0 0x00000083 |
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| 398 | |
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| 399 | #define REG_A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0 0x00000089 |
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| 400 | |
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| 401 | #define REG_A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0 0x0000008c |
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| 402 | |
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| 403 | #define REG_A6XX_RSCC_OVERRIDE_START_ADDR 0x00000100 |
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| 404 | |
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| 405 | #define REG_A6XX_RSCC_SEQ_BUSY_DRV0 0x00000101 |
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| 406 | |
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| 407 | #define REG_A7XX_RSCC_SEQ_MEM_0_DRV0_A740 0x00000154 |
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| 408 | |
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| 409 | #define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 0x00000180 |
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| 410 | |
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| 411 | #define REG_A6XX_RSCC_TCS0_DRV0_STATUS 0x00000346 |
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| 412 | |
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| 413 | #define REG_A6XX_RSCC_TCS1_DRV0_STATUS 0x000003ee |
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| 414 | |
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| 415 | #define REG_A6XX_RSCC_TCS2_DRV0_STATUS 0x00000496 |
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| 416 | |
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| 417 | #define REG_A6XX_RSCC_TCS3_DRV0_STATUS 0x0000053e |
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| 418 | |
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| 419 | #ifdef __cplusplus |
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| 420 | #endif |
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| 421 | |
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| 422 | #endif /* A6XX_GMU_XML */ |
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| 423 | |
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