1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. |
4 | */ |
5 | |
6 | #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__ |
7 | |
8 | #include <linux/types.h> |
9 | #include <linux/completion.h> |
10 | #include <linux/delay.h> |
11 | #include <linux/phy/phy.h> |
12 | #include <linux/phy/phy-dp.h> |
13 | #include <linux/pm_opp.h> |
14 | |
15 | #include <drm/display/drm_dp_helper.h> |
16 | #include <drm/drm_fixed.h> |
17 | #include <drm/drm_print.h> |
18 | |
19 | #include "dp_reg.h" |
20 | #include "dp_ctrl.h" |
21 | #include "dp_link.h" |
22 | |
23 | #define DP_KHZ_TO_HZ 1000 |
24 | #define IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES (30 * HZ / 1000) /* 30 ms */ |
25 | #define PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES (300 * HZ / 1000) /* 300 ms */ |
26 | #define WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES (HZ / 2) |
27 | |
28 | #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0) |
29 | #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3) |
30 | |
31 | #define MR_LINK_TRAINING1 0x8 |
32 | #define MR_LINK_SYMBOL_ERM 0x80 |
33 | #define MR_LINK_PRBS7 0x100 |
34 | #define MR_LINK_CUSTOM80 0x200 |
35 | #define MR_LINK_TRAINING4 0x40 |
36 | |
37 | enum { |
38 | DP_TRAINING_NONE, |
39 | DP_TRAINING_1, |
40 | DP_TRAINING_2, |
41 | }; |
42 | |
43 | struct dp_tu_calc_input { |
44 | u64 lclk; /* 162, 270, 540 and 810 */ |
45 | u64 pclk_khz; /* in KHz */ |
46 | u64 hactive; /* active h-width */ |
47 | u64 hporch; /* bp + fp + pulse */ |
48 | int nlanes; /* no.of.lanes */ |
49 | int bpp; /* bits */ |
50 | int pixel_enc; /* 444, 420, 422 */ |
51 | int dsc_en; /* dsc on/off */ |
52 | int async_en; /* async mode */ |
53 | int fec_en; /* fec */ |
54 | int compress_ratio; /* 2:1 = 200, 3:1 = 300, 3.75:1 = 375 */ |
55 | int num_of_dsc_slices; /* number of slices per line */ |
56 | }; |
57 | |
58 | struct dp_vc_tu_mapping_table { |
59 | u32 vic; |
60 | u8 lanes; |
61 | u8 lrate; /* DP_LINK_RATE -> 162(6), 270(10), 540(20), 810 (30) */ |
62 | u8 bpp; |
63 | u8 valid_boundary_link; |
64 | u16 delay_start_link; |
65 | bool boundary_moderation_en; |
66 | u8 valid_lower_boundary_link; |
67 | u8 upper_boundary_count; |
68 | u8 lower_boundary_count; |
69 | u8 tu_size_minus1; |
70 | }; |
71 | |
72 | struct dp_ctrl_private { |
73 | struct dp_ctrl dp_ctrl; |
74 | struct drm_device *drm_dev; |
75 | struct device *dev; |
76 | struct drm_dp_aux *aux; |
77 | struct dp_panel *panel; |
78 | struct dp_link *link; |
79 | struct dp_catalog *catalog; |
80 | |
81 | struct phy *phy; |
82 | |
83 | unsigned int num_core_clks; |
84 | struct clk_bulk_data *core_clks; |
85 | |
86 | unsigned int num_link_clks; |
87 | struct clk_bulk_data *link_clks; |
88 | |
89 | struct clk *pixel_clk; |
90 | |
91 | union phy_configure_opts phy_opts; |
92 | |
93 | struct completion idle_comp; |
94 | struct completion psr_op_comp; |
95 | struct completion video_comp; |
96 | |
97 | bool core_clks_on; |
98 | bool link_clks_on; |
99 | bool stream_clks_on; |
100 | }; |
101 | |
102 | static int dp_aux_link_configure(struct drm_dp_aux *aux, |
103 | struct dp_link_info *link) |
104 | { |
105 | u8 values[2]; |
106 | int err; |
107 | |
108 | values[0] = drm_dp_link_rate_to_bw_code(link_rate: link->rate); |
109 | values[1] = link->num_lanes; |
110 | |
111 | if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING) |
112 | values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
113 | |
114 | err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, buffer: values, size: sizeof(values)); |
115 | if (err < 0) |
116 | return err; |
117 | |
118 | return 0; |
119 | } |
120 | |
121 | void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl) |
122 | { |
123 | struct dp_ctrl_private *ctrl; |
124 | |
125 | ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); |
126 | |
127 | reinit_completion(x: &ctrl->idle_comp); |
128 | dp_catalog_ctrl_state_ctrl(dp_catalog: ctrl->catalog, DP_STATE_CTRL_PUSH_IDLE); |
129 | |
130 | if (!wait_for_completion_timeout(x: &ctrl->idle_comp, |
131 | IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) |
132 | pr_warn("PUSH_IDLE pattern timedout\n" ); |
133 | |
134 | drm_dbg_dp(ctrl->drm_dev, "mainlink off\n" ); |
135 | } |
136 | |
137 | static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl) |
138 | { |
139 | u32 config = 0, tbd; |
140 | const u8 *dpcd = ctrl->panel->dpcd; |
141 | |
142 | /* Default-> LSCLK DIV: 1/4 LCLK */ |
143 | config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); |
144 | |
145 | if (ctrl->panel->dp_mode.out_fmt_is_yuv_420) |
146 | config |= DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ |
147 | |
148 | /* Scrambler reset enable */ |
149 | if (drm_dp_alternate_scrambler_reset_cap(dpcd)) |
150 | config |= DP_CONFIGURATION_CTRL_ASSR; |
151 | |
152 | tbd = dp_link_get_test_bits_depth(dp_link: ctrl->link, |
153 | bpp: ctrl->panel->dp_mode.bpp); |
154 | |
155 | config |= tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; |
156 | |
157 | /* Num of Lanes */ |
158 | config |= ((ctrl->link->link_params.num_lanes - 1) |
159 | << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT); |
160 | |
161 | if (drm_dp_enhanced_frame_cap(dpcd)) |
162 | config |= DP_CONFIGURATION_CTRL_ENHANCED_FRAMING; |
163 | |
164 | config |= DP_CONFIGURATION_CTRL_P_INTERLACED; /* progressive video */ |
165 | |
166 | /* sync clock & static Mvid */ |
167 | config |= DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN; |
168 | config |= DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK; |
169 | |
170 | if (ctrl->panel->psr_cap.version) |
171 | config |= DP_CONFIGURATION_CTRL_SEND_VSC; |
172 | |
173 | dp_catalog_ctrl_config_ctrl(dp_catalog: ctrl->catalog, config); |
174 | } |
175 | |
176 | static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl) |
177 | { |
178 | u32 cc, tb; |
179 | |
180 | dp_catalog_ctrl_lane_mapping(dp_catalog: ctrl->catalog); |
181 | dp_catalog_ctrl_mainlink_ctrl(dp_catalog: ctrl->catalog, enable: true); |
182 | dp_catalog_setup_peripheral_flush(dp_catalog: ctrl->catalog); |
183 | |
184 | dp_ctrl_config_ctrl(ctrl); |
185 | |
186 | tb = dp_link_get_test_bits_depth(dp_link: ctrl->link, |
187 | bpp: ctrl->panel->dp_mode.bpp); |
188 | cc = dp_link_get_colorimetry_config(dp_link: ctrl->link); |
189 | dp_catalog_ctrl_config_misc(dp_catalog: ctrl->catalog, cc, tb); |
190 | dp_panel_timing_cfg(dp_panel: ctrl->panel); |
191 | } |
192 | |
193 | /* |
194 | * The structure and few functions present below are IP/Hardware |
195 | * specific implementation. Most of the implementation will not |
196 | * have coding comments |
197 | */ |
198 | struct tu_algo_data { |
199 | s64 lclk_fp; |
200 | s64 pclk_fp; |
201 | s64 lwidth; |
202 | s64 lwidth_fp; |
203 | s64 hbp_relative_to_pclk; |
204 | s64 hbp_relative_to_pclk_fp; |
205 | int nlanes; |
206 | int bpp; |
207 | int pixelEnc; |
208 | int dsc_en; |
209 | int async_en; |
210 | int bpc; |
211 | |
212 | uint ; |
213 | int ; |
214 | s64 ratio_fp; |
215 | s64 original_ratio_fp; |
216 | |
217 | s64 err_fp; |
218 | s64 n_err_fp; |
219 | s64 n_n_err_fp; |
220 | int tu_size; |
221 | int tu_size_desired; |
222 | int tu_size_minus1; |
223 | |
224 | int valid_boundary_link; |
225 | s64 resulting_valid_fp; |
226 | s64 total_valid_fp; |
227 | s64 effective_valid_fp; |
228 | s64 effective_valid_recorded_fp; |
229 | int n_tus; |
230 | int n_tus_per_lane; |
231 | int paired_tus; |
232 | int remainder_tus; |
233 | int remainder_tus_upper; |
234 | int remainder_tus_lower; |
235 | int ; |
236 | int filler_size; |
237 | int delay_start_link; |
238 | |
239 | int ; |
240 | int ; |
241 | s64 ratio_by_tu_fp; |
242 | s64 average_valid2_fp; |
243 | int new_valid_boundary_link; |
244 | int remainder_symbols_exist; |
245 | int n_symbols; |
246 | s64 n_remainder_symbols_per_lane_fp; |
247 | s64 last_partial_tu_fp; |
248 | s64 TU_ratio_err_fp; |
249 | |
250 | int n_tus_incl_last_incomplete_tu; |
251 | int ; |
252 | int ; |
253 | int ; |
254 | int filler_size_tmp; |
255 | int lower_filler_size_tmp; |
256 | int delay_start_link_tmp; |
257 | |
258 | bool boundary_moderation_en; |
259 | int boundary_mod_lower_err; |
260 | int upper_boundary_count; |
261 | int lower_boundary_count; |
262 | int i_upper_boundary_count; |
263 | int i_lower_boundary_count; |
264 | int valid_lower_boundary_link; |
265 | int even_distribution_BF; |
266 | int even_distribution_legacy; |
267 | int even_distribution; |
268 | int min_hblank_violated; |
269 | s64 delay_start_time_fp; |
270 | s64 hbp_time_fp; |
271 | s64 hactive_time_fp; |
272 | s64 diff_abs_fp; |
273 | |
274 | s64 ratio; |
275 | }; |
276 | |
277 | static int _tu_param_compare(s64 a, s64 b) |
278 | { |
279 | u32 a_sign; |
280 | u32 b_sign; |
281 | s64 a_temp, b_temp, minus_1; |
282 | |
283 | if (a == b) |
284 | return 0; |
285 | |
286 | minus_1 = drm_fixp_from_fraction(a: -1, b: 1); |
287 | |
288 | a_sign = (a >> 32) & 0x80000000 ? 1 : 0; |
289 | |
290 | b_sign = (b >> 32) & 0x80000000 ? 1 : 0; |
291 | |
292 | if (a_sign > b_sign) |
293 | return 2; |
294 | else if (b_sign > a_sign) |
295 | return 1; |
296 | |
297 | if (!a_sign && !b_sign) { /* positive */ |
298 | if (a > b) |
299 | return 1; |
300 | else |
301 | return 2; |
302 | } else { /* negative */ |
303 | a_temp = drm_fixp_mul(a, b: minus_1); |
304 | b_temp = drm_fixp_mul(a: b, b: minus_1); |
305 | |
306 | if (a_temp > b_temp) |
307 | return 2; |
308 | else |
309 | return 1; |
310 | } |
311 | } |
312 | |
313 | static void dp_panel_update_tu_timings(struct dp_tu_calc_input *in, |
314 | struct tu_algo_data *tu) |
315 | { |
316 | int nlanes = in->nlanes; |
317 | int dsc_num_slices = in->num_of_dsc_slices; |
318 | int dsc_num_bytes = 0; |
319 | int numerator; |
320 | s64 pclk_dsc_fp; |
321 | s64 dwidth_dsc_fp; |
322 | s64 hbp_dsc_fp; |
323 | |
324 | int tot_num_eoc_symbols = 0; |
325 | int tot_num_hor_bytes = 0; |
326 | int tot_num_dummy_bytes = 0; |
327 | int dwidth_dsc_bytes = 0; |
328 | int eoc_bytes = 0; |
329 | |
330 | s64 temp1_fp, temp2_fp, temp3_fp; |
331 | |
332 | tu->lclk_fp = drm_fixp_from_fraction(a: in->lclk, b: 1); |
333 | tu->pclk_fp = drm_fixp_from_fraction(a: in->pclk_khz, b: 1000); |
334 | tu->lwidth = in->hactive; |
335 | tu->hbp_relative_to_pclk = in->hporch; |
336 | tu->nlanes = in->nlanes; |
337 | tu->bpp = in->bpp; |
338 | tu->pixelEnc = in->pixel_enc; |
339 | tu->dsc_en = in->dsc_en; |
340 | tu->async_en = in->async_en; |
341 | tu->lwidth_fp = drm_fixp_from_fraction(a: in->hactive, b: 1); |
342 | tu->hbp_relative_to_pclk_fp = drm_fixp_from_fraction(a: in->hporch, b: 1); |
343 | |
344 | if (tu->pixelEnc == 420) { |
345 | temp1_fp = drm_fixp_from_fraction(a: 2, b: 1); |
346 | tu->pclk_fp = drm_fixp_div(a: tu->pclk_fp, b: temp1_fp); |
347 | tu->lwidth_fp = drm_fixp_div(a: tu->lwidth_fp, b: temp1_fp); |
348 | tu->hbp_relative_to_pclk_fp = |
349 | drm_fixp_div(a: tu->hbp_relative_to_pclk_fp, b: 2); |
350 | } |
351 | |
352 | if (tu->pixelEnc == 422) { |
353 | switch (tu->bpp) { |
354 | case 24: |
355 | tu->bpp = 16; |
356 | tu->bpc = 8; |
357 | break; |
358 | case 30: |
359 | tu->bpp = 20; |
360 | tu->bpc = 10; |
361 | break; |
362 | default: |
363 | tu->bpp = 16; |
364 | tu->bpc = 8; |
365 | break; |
366 | } |
367 | } else { |
368 | tu->bpc = tu->bpp/3; |
369 | } |
370 | |
371 | if (!in->dsc_en) |
372 | goto fec_check; |
373 | |
374 | temp1_fp = drm_fixp_from_fraction(a: in->compress_ratio, b: 100); |
375 | temp2_fp = drm_fixp_from_fraction(a: in->bpp, b: 1); |
376 | temp3_fp = drm_fixp_div(a: temp2_fp, b: temp1_fp); |
377 | temp2_fp = drm_fixp_mul(a: tu->lwidth_fp, b: temp3_fp); |
378 | |
379 | temp1_fp = drm_fixp_from_fraction(a: 8, b: 1); |
380 | temp3_fp = drm_fixp_div(a: temp2_fp, b: temp1_fp); |
381 | |
382 | numerator = drm_fixp2int(a: temp3_fp); |
383 | |
384 | dsc_num_bytes = numerator / dsc_num_slices; |
385 | eoc_bytes = dsc_num_bytes % nlanes; |
386 | tot_num_eoc_symbols = nlanes * dsc_num_slices; |
387 | tot_num_hor_bytes = dsc_num_bytes * dsc_num_slices; |
388 | tot_num_dummy_bytes = (nlanes - eoc_bytes) * dsc_num_slices; |
389 | |
390 | if (dsc_num_bytes == 0) |
391 | pr_info("incorrect no of bytes per slice=%d\n" , dsc_num_bytes); |
392 | |
393 | dwidth_dsc_bytes = (tot_num_hor_bytes + |
394 | tot_num_eoc_symbols + |
395 | (eoc_bytes == 0 ? 0 : tot_num_dummy_bytes)); |
396 | |
397 | dwidth_dsc_fp = drm_fixp_from_fraction(a: dwidth_dsc_bytes, b: 3); |
398 | |
399 | temp2_fp = drm_fixp_mul(a: tu->pclk_fp, b: dwidth_dsc_fp); |
400 | temp1_fp = drm_fixp_div(a: temp2_fp, b: tu->lwidth_fp); |
401 | pclk_dsc_fp = temp1_fp; |
402 | |
403 | temp1_fp = drm_fixp_div(a: pclk_dsc_fp, b: tu->pclk_fp); |
404 | temp2_fp = drm_fixp_mul(a: tu->hbp_relative_to_pclk_fp, b: temp1_fp); |
405 | hbp_dsc_fp = temp2_fp; |
406 | |
407 | /* output */ |
408 | tu->pclk_fp = pclk_dsc_fp; |
409 | tu->lwidth_fp = dwidth_dsc_fp; |
410 | tu->hbp_relative_to_pclk_fp = hbp_dsc_fp; |
411 | |
412 | fec_check: |
413 | if (in->fec_en) { |
414 | temp1_fp = drm_fixp_from_fraction(a: 976, b: 1000); /* 0.976 */ |
415 | tu->lclk_fp = drm_fixp_mul(a: tu->lclk_fp, b: temp1_fp); |
416 | } |
417 | } |
418 | |
419 | static void _tu_valid_boundary_calc(struct tu_algo_data *tu) |
420 | { |
421 | s64 temp1_fp, temp2_fp, temp, temp1, temp2; |
422 | int compare_result_1, compare_result_2, compare_result_3; |
423 | |
424 | temp1_fp = drm_fixp_from_fraction(a: tu->tu_size, b: 1); |
425 | temp2_fp = drm_fixp_mul(a: tu->ratio_fp, b: temp1_fp); |
426 | |
427 | tu->new_valid_boundary_link = drm_fixp2int_ceil(a: temp2_fp); |
428 | |
429 | temp = (tu->i_upper_boundary_count * |
430 | tu->new_valid_boundary_link + |
431 | tu->i_lower_boundary_count * |
432 | (tu->new_valid_boundary_link-1)); |
433 | tu->average_valid2_fp = drm_fixp_from_fraction(a: temp, |
434 | b: (tu->i_upper_boundary_count + |
435 | tu->i_lower_boundary_count)); |
436 | |
437 | temp1_fp = drm_fixp_from_fraction(a: tu->bpp, b: 8); |
438 | temp2_fp = tu->lwidth_fp; |
439 | temp1_fp = drm_fixp_mul(a: temp2_fp, b: temp1_fp); |
440 | temp2_fp = drm_fixp_div(a: temp1_fp, b: tu->average_valid2_fp); |
441 | tu->n_tus = drm_fixp2int(a: temp2_fp); |
442 | if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000) |
443 | tu->n_tus += 1; |
444 | |
445 | temp1_fp = drm_fixp_from_fraction(a: tu->n_tus, b: 1); |
446 | temp2_fp = drm_fixp_mul(a: temp1_fp, b: tu->average_valid2_fp); |
447 | temp1_fp = drm_fixp_from_fraction(a: tu->n_symbols, b: 1); |
448 | temp2_fp = temp1_fp - temp2_fp; |
449 | temp1_fp = drm_fixp_from_fraction(a: tu->nlanes, b: 1); |
450 | temp2_fp = drm_fixp_div(a: temp2_fp, b: temp1_fp); |
451 | tu->n_remainder_symbols_per_lane_fp = temp2_fp; |
452 | |
453 | temp1_fp = drm_fixp_from_fraction(a: tu->tu_size, b: 1); |
454 | tu->last_partial_tu_fp = |
455 | drm_fixp_div(a: tu->n_remainder_symbols_per_lane_fp, |
456 | b: temp1_fp); |
457 | |
458 | if (tu->n_remainder_symbols_per_lane_fp != 0) |
459 | tu->remainder_symbols_exist = 1; |
460 | else |
461 | tu->remainder_symbols_exist = 0; |
462 | |
463 | temp1_fp = drm_fixp_from_fraction(a: tu->n_tus, b: tu->nlanes); |
464 | tu->n_tus_per_lane = drm_fixp2int(a: temp1_fp); |
465 | |
466 | tu->paired_tus = (int)((tu->n_tus_per_lane) / |
467 | (tu->i_upper_boundary_count + |
468 | tu->i_lower_boundary_count)); |
469 | |
470 | tu->remainder_tus = tu->n_tus_per_lane - tu->paired_tus * |
471 | (tu->i_upper_boundary_count + |
472 | tu->i_lower_boundary_count); |
473 | |
474 | if ((tu->remainder_tus - tu->i_upper_boundary_count) > 0) { |
475 | tu->remainder_tus_upper = tu->i_upper_boundary_count; |
476 | tu->remainder_tus_lower = tu->remainder_tus - |
477 | tu->i_upper_boundary_count; |
478 | } else { |
479 | tu->remainder_tus_upper = tu->remainder_tus; |
480 | tu->remainder_tus_lower = 0; |
481 | } |
482 | |
483 | temp = tu->paired_tus * (tu->i_upper_boundary_count * |
484 | tu->new_valid_boundary_link + |
485 | tu->i_lower_boundary_count * |
486 | (tu->new_valid_boundary_link - 1)) + |
487 | (tu->remainder_tus_upper * |
488 | tu->new_valid_boundary_link) + |
489 | (tu->remainder_tus_lower * |
490 | (tu->new_valid_boundary_link - 1)); |
491 | tu->total_valid_fp = drm_fixp_from_fraction(a: temp, b: 1); |
492 | |
493 | if (tu->remainder_symbols_exist) { |
494 | temp1_fp = tu->total_valid_fp + |
495 | tu->n_remainder_symbols_per_lane_fp; |
496 | temp2_fp = drm_fixp_from_fraction(a: tu->n_tus_per_lane, b: 1); |
497 | temp2_fp = temp2_fp + tu->last_partial_tu_fp; |
498 | temp1_fp = drm_fixp_div(a: temp1_fp, b: temp2_fp); |
499 | } else { |
500 | temp2_fp = drm_fixp_from_fraction(a: tu->n_tus_per_lane, b: 1); |
501 | temp1_fp = drm_fixp_div(a: tu->total_valid_fp, b: temp2_fp); |
502 | } |
503 | tu->effective_valid_fp = temp1_fp; |
504 | |
505 | temp1_fp = drm_fixp_from_fraction(a: tu->tu_size, b: 1); |
506 | temp2_fp = drm_fixp_mul(a: tu->ratio_fp, b: temp1_fp); |
507 | tu->n_n_err_fp = tu->effective_valid_fp - temp2_fp; |
508 | |
509 | temp1_fp = drm_fixp_from_fraction(a: tu->tu_size, b: 1); |
510 | temp2_fp = drm_fixp_mul(a: tu->ratio_fp, b: temp1_fp); |
511 | tu->n_err_fp = tu->average_valid2_fp - temp2_fp; |
512 | |
513 | tu->even_distribution = tu->n_tus % tu->nlanes == 0 ? 1 : 0; |
514 | |
515 | temp1_fp = drm_fixp_from_fraction(a: tu->bpp, b: 8); |
516 | temp2_fp = tu->lwidth_fp; |
517 | temp1_fp = drm_fixp_mul(a: temp2_fp, b: temp1_fp); |
518 | temp2_fp = drm_fixp_div(a: temp1_fp, b: tu->average_valid2_fp); |
519 | |
520 | if (temp2_fp) |
521 | tu->n_tus_incl_last_incomplete_tu = drm_fixp2int_ceil(a: temp2_fp); |
522 | else |
523 | tu->n_tus_incl_last_incomplete_tu = 0; |
524 | |
525 | temp1 = 0; |
526 | temp1_fp = drm_fixp_from_fraction(a: tu->tu_size, b: 1); |
527 | temp2_fp = drm_fixp_mul(a: tu->original_ratio_fp, b: temp1_fp); |
528 | temp1_fp = tu->average_valid2_fp - temp2_fp; |
529 | temp2_fp = drm_fixp_from_fraction(a: tu->n_tus_incl_last_incomplete_tu, b: 1); |
530 | temp1_fp = drm_fixp_mul(a: temp2_fp, b: temp1_fp); |
531 | |
532 | if (temp1_fp) |
533 | temp1 = drm_fixp2int_ceil(a: temp1_fp); |
534 | |
535 | temp = tu->i_upper_boundary_count * tu->nlanes; |
536 | temp1_fp = drm_fixp_from_fraction(a: tu->tu_size, b: 1); |
537 | temp2_fp = drm_fixp_mul(a: tu->original_ratio_fp, b: temp1_fp); |
538 | temp1_fp = drm_fixp_from_fraction(a: tu->new_valid_boundary_link, b: 1); |
539 | temp2_fp = temp1_fp - temp2_fp; |
540 | temp1_fp = drm_fixp_from_fraction(a: temp, b: 1); |
541 | temp2_fp = drm_fixp_mul(a: temp1_fp, b: temp2_fp); |
542 | |
543 | if (temp2_fp) |
544 | temp2 = drm_fixp2int_ceil(a: temp2_fp); |
545 | else |
546 | temp2 = 0; |
547 | tu->extra_required_bytes_new_tmp = (int)(temp1 + temp2); |
548 | |
549 | temp1_fp = drm_fixp_from_fraction(a: 8, b: tu->bpp); |
550 | temp2_fp = drm_fixp_from_fraction( |
551 | a: tu->extra_required_bytes_new_tmp, b: 1); |
552 | temp1_fp = drm_fixp_mul(a: temp2_fp, b: temp1_fp); |
553 | |
554 | if (temp1_fp) |
555 | tu->extra_pclk_cycles_tmp = drm_fixp2int_ceil(a: temp1_fp); |
556 | else |
557 | tu->extra_pclk_cycles_tmp = 0; |
558 | |
559 | temp1_fp = drm_fixp_from_fraction(a: tu->extra_pclk_cycles_tmp, b: 1); |
560 | temp2_fp = drm_fixp_div(a: tu->lclk_fp, b: tu->pclk_fp); |
561 | temp1_fp = drm_fixp_mul(a: temp1_fp, b: temp2_fp); |
562 | |
563 | if (temp1_fp) |
564 | tu->extra_pclk_cycles_in_link_clk_tmp = |
565 | drm_fixp2int_ceil(a: temp1_fp); |
566 | else |
567 | tu->extra_pclk_cycles_in_link_clk_tmp = 0; |
568 | |
569 | tu->filler_size_tmp = tu->tu_size - tu->new_valid_boundary_link; |
570 | |
571 | tu->lower_filler_size_tmp = tu->filler_size_tmp + 1; |
572 | |
573 | tu->delay_start_link_tmp = tu->extra_pclk_cycles_in_link_clk_tmp + |
574 | tu->lower_filler_size_tmp + |
575 | tu->extra_buffer_margin; |
576 | |
577 | temp1_fp = drm_fixp_from_fraction(a: tu->delay_start_link_tmp, b: 1); |
578 | tu->delay_start_time_fp = drm_fixp_div(a: temp1_fp, b: tu->lclk_fp); |
579 | |
580 | compare_result_1 = _tu_param_compare(a: tu->n_n_err_fp, b: tu->diff_abs_fp); |
581 | if (compare_result_1 == 2) |
582 | compare_result_1 = 1; |
583 | else |
584 | compare_result_1 = 0; |
585 | |
586 | compare_result_2 = _tu_param_compare(a: tu->n_n_err_fp, b: tu->err_fp); |
587 | if (compare_result_2 == 2) |
588 | compare_result_2 = 1; |
589 | else |
590 | compare_result_2 = 0; |
591 | |
592 | compare_result_3 = _tu_param_compare(a: tu->hbp_time_fp, |
593 | b: tu->delay_start_time_fp); |
594 | if (compare_result_3 == 2) |
595 | compare_result_3 = 0; |
596 | else |
597 | compare_result_3 = 1; |
598 | |
599 | if (((tu->even_distribution == 1) || |
600 | ((tu->even_distribution_BF == 0) && |
601 | (tu->even_distribution_legacy == 0))) && |
602 | tu->n_err_fp >= 0 && tu->n_n_err_fp >= 0 && |
603 | compare_result_2 && |
604 | (compare_result_1 || (tu->min_hblank_violated == 1)) && |
605 | (tu->new_valid_boundary_link - 1) > 0 && |
606 | compare_result_3 && |
607 | (tu->delay_start_link_tmp <= 1023)) { |
608 | tu->upper_boundary_count = tu->i_upper_boundary_count; |
609 | tu->lower_boundary_count = tu->i_lower_boundary_count; |
610 | tu->err_fp = tu->n_n_err_fp; |
611 | tu->boundary_moderation_en = true; |
612 | tu->tu_size_desired = tu->tu_size; |
613 | tu->valid_boundary_link = tu->new_valid_boundary_link; |
614 | tu->effective_valid_recorded_fp = tu->effective_valid_fp; |
615 | tu->even_distribution_BF = 1; |
616 | tu->delay_start_link = tu->delay_start_link_tmp; |
617 | } else if (tu->boundary_mod_lower_err == 0) { |
618 | compare_result_1 = _tu_param_compare(a: tu->n_n_err_fp, |
619 | b: tu->diff_abs_fp); |
620 | if (compare_result_1 == 2) |
621 | tu->boundary_mod_lower_err = 1; |
622 | } |
623 | } |
624 | |
625 | static void _dp_ctrl_calc_tu(struct dp_ctrl_private *ctrl, |
626 | struct dp_tu_calc_input *in, |
627 | struct dp_vc_tu_mapping_table *tu_table) |
628 | { |
629 | struct tu_algo_data *tu; |
630 | int compare_result_1, compare_result_2; |
631 | u64 temp = 0; |
632 | s64 temp_fp = 0, temp1_fp = 0, temp2_fp = 0; |
633 | |
634 | s64 LCLK_FAST_SKEW_fp = drm_fixp_from_fraction(a: 6, b: 10000); /* 0.0006 */ |
635 | s64 const_p49_fp = drm_fixp_from_fraction(a: 49, b: 100); /* 0.49 */ |
636 | s64 const_p56_fp = drm_fixp_from_fraction(a: 56, b: 100); /* 0.56 */ |
637 | s64 RATIO_SCALE_fp = drm_fixp_from_fraction(a: 1001, b: 1000); |
638 | |
639 | u8 DP_BRUTE_FORCE = 1; |
640 | s64 BRUTE_FORCE_THRESHOLD_fp = drm_fixp_from_fraction(a: 1, b: 10); /* 0.1 */ |
641 | uint = 4; |
642 | uint HBLANK_MARGIN = 4; |
643 | |
644 | tu = kzalloc(size: sizeof(*tu), GFP_KERNEL); |
645 | if (!tu) |
646 | return; |
647 | |
648 | dp_panel_update_tu_timings(in, tu); |
649 | |
650 | tu->err_fp = drm_fixp_from_fraction(a: 1000, b: 1); /* 1000 */ |
651 | |
652 | temp1_fp = drm_fixp_from_fraction(a: 4, b: 1); |
653 | temp2_fp = drm_fixp_mul(a: temp1_fp, b: tu->lclk_fp); |
654 | temp_fp = drm_fixp_div(a: temp2_fp, b: tu->pclk_fp); |
655 | tu->extra_buffer_margin = drm_fixp2int_ceil(a: temp_fp); |
656 | |
657 | temp1_fp = drm_fixp_from_fraction(a: tu->bpp, b: 8); |
658 | temp2_fp = drm_fixp_mul(a: tu->pclk_fp, b: temp1_fp); |
659 | temp1_fp = drm_fixp_from_fraction(a: tu->nlanes, b: 1); |
660 | temp2_fp = drm_fixp_div(a: temp2_fp, b: temp1_fp); |
661 | tu->ratio_fp = drm_fixp_div(a: temp2_fp, b: tu->lclk_fp); |
662 | |
663 | tu->original_ratio_fp = tu->ratio_fp; |
664 | tu->boundary_moderation_en = false; |
665 | tu->upper_boundary_count = 0; |
666 | tu->lower_boundary_count = 0; |
667 | tu->i_upper_boundary_count = 0; |
668 | tu->i_lower_boundary_count = 0; |
669 | tu->valid_lower_boundary_link = 0; |
670 | tu->even_distribution_BF = 0; |
671 | tu->even_distribution_legacy = 0; |
672 | tu->even_distribution = 0; |
673 | tu->delay_start_time_fp = 0; |
674 | |
675 | tu->err_fp = drm_fixp_from_fraction(a: 1000, b: 1); |
676 | tu->n_err_fp = 0; |
677 | tu->n_n_err_fp = 0; |
678 | |
679 | tu->ratio = drm_fixp2int(a: tu->ratio_fp); |
680 | temp1_fp = drm_fixp_from_fraction(a: tu->nlanes, b: 1); |
681 | div64_u64_rem(dividend: tu->lwidth_fp, divisor: temp1_fp, remainder: &temp2_fp); |
682 | if (temp2_fp != 0 && |
683 | !tu->ratio && tu->dsc_en == 0) { |
684 | tu->ratio_fp = drm_fixp_mul(a: tu->ratio_fp, b: RATIO_SCALE_fp); |
685 | tu->ratio = drm_fixp2int(a: tu->ratio_fp); |
686 | if (tu->ratio) |
687 | tu->ratio_fp = drm_fixp_from_fraction(a: 1, b: 1); |
688 | } |
689 | |
690 | if (tu->ratio > 1) |
691 | tu->ratio = 1; |
692 | |
693 | if (tu->ratio == 1) |
694 | goto tu_size_calc; |
695 | |
696 | compare_result_1 = _tu_param_compare(a: tu->ratio_fp, b: const_p49_fp); |
697 | if (!compare_result_1 || compare_result_1 == 1) |
698 | compare_result_1 = 1; |
699 | else |
700 | compare_result_1 = 0; |
701 | |
702 | compare_result_2 = _tu_param_compare(a: tu->ratio_fp, b: const_p56_fp); |
703 | if (!compare_result_2 || compare_result_2 == 2) |
704 | compare_result_2 = 1; |
705 | else |
706 | compare_result_2 = 0; |
707 | |
708 | if (tu->dsc_en && compare_result_1 && compare_result_2) { |
709 | HBLANK_MARGIN += 4; |
710 | drm_dbg_dp(ctrl->drm_dev, |
711 | "increase HBLANK_MARGIN to %d\n" , HBLANK_MARGIN); |
712 | } |
713 | |
714 | tu_size_calc: |
715 | for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) { |
716 | temp1_fp = drm_fixp_from_fraction(a: tu->tu_size, b: 1); |
717 | temp2_fp = drm_fixp_mul(a: tu->ratio_fp, b: temp1_fp); |
718 | temp = drm_fixp2int_ceil(a: temp2_fp); |
719 | temp1_fp = drm_fixp_from_fraction(a: temp, b: 1); |
720 | tu->n_err_fp = temp1_fp - temp2_fp; |
721 | |
722 | if (tu->n_err_fp < tu->err_fp) { |
723 | tu->err_fp = tu->n_err_fp; |
724 | tu->tu_size_desired = tu->tu_size; |
725 | } |
726 | } |
727 | |
728 | tu->tu_size_minus1 = tu->tu_size_desired - 1; |
729 | |
730 | temp1_fp = drm_fixp_from_fraction(a: tu->tu_size_desired, b: 1); |
731 | temp2_fp = drm_fixp_mul(a: tu->ratio_fp, b: temp1_fp); |
732 | tu->valid_boundary_link = drm_fixp2int_ceil(a: temp2_fp); |
733 | |
734 | temp1_fp = drm_fixp_from_fraction(a: tu->bpp, b: 8); |
735 | temp2_fp = tu->lwidth_fp; |
736 | temp2_fp = drm_fixp_mul(a: temp2_fp, b: temp1_fp); |
737 | |
738 | temp1_fp = drm_fixp_from_fraction(a: tu->valid_boundary_link, b: 1); |
739 | temp2_fp = drm_fixp_div(a: temp2_fp, b: temp1_fp); |
740 | tu->n_tus = drm_fixp2int(a: temp2_fp); |
741 | if ((temp2_fp & 0xFFFFFFFF) > 0xFFFFF000) |
742 | tu->n_tus += 1; |
743 | |
744 | tu->even_distribution_legacy = tu->n_tus % tu->nlanes == 0 ? 1 : 0; |
745 | |
746 | drm_dbg_dp(ctrl->drm_dev, |
747 | "n_sym = %d, num_of_tus = %d\n" , |
748 | tu->valid_boundary_link, tu->n_tus); |
749 | |
750 | temp1_fp = drm_fixp_from_fraction(a: tu->tu_size_desired, b: 1); |
751 | temp2_fp = drm_fixp_mul(a: tu->original_ratio_fp, b: temp1_fp); |
752 | temp1_fp = drm_fixp_from_fraction(a: tu->valid_boundary_link, b: 1); |
753 | temp2_fp = temp1_fp - temp2_fp; |
754 | temp1_fp = drm_fixp_from_fraction(a: tu->n_tus + 1, b: 1); |
755 | temp2_fp = drm_fixp_mul(a: temp1_fp, b: temp2_fp); |
756 | |
757 | temp = drm_fixp2int(a: temp2_fp); |
758 | if (temp && temp2_fp) |
759 | tu->extra_bytes = drm_fixp2int_ceil(a: temp2_fp); |
760 | else |
761 | tu->extra_bytes = 0; |
762 | |
763 | temp1_fp = drm_fixp_from_fraction(a: tu->extra_bytes, b: 1); |
764 | temp2_fp = drm_fixp_from_fraction(a: 8, b: tu->bpp); |
765 | temp1_fp = drm_fixp_mul(a: temp1_fp, b: temp2_fp); |
766 | |
767 | if (temp && temp1_fp) |
768 | tu->extra_pclk_cycles = drm_fixp2int_ceil(a: temp1_fp); |
769 | else |
770 | tu->extra_pclk_cycles = drm_fixp2int(a: temp1_fp); |
771 | |
772 | temp1_fp = drm_fixp_div(a: tu->lclk_fp, b: tu->pclk_fp); |
773 | temp2_fp = drm_fixp_from_fraction(a: tu->extra_pclk_cycles, b: 1); |
774 | temp1_fp = drm_fixp_mul(a: temp2_fp, b: temp1_fp); |
775 | |
776 | if (temp1_fp) |
777 | tu->extra_pclk_cycles_in_link_clk = drm_fixp2int_ceil(a: temp1_fp); |
778 | else |
779 | tu->extra_pclk_cycles_in_link_clk = drm_fixp2int(a: temp1_fp); |
780 | |
781 | tu->filler_size = tu->tu_size_desired - tu->valid_boundary_link; |
782 | |
783 | temp1_fp = drm_fixp_from_fraction(a: tu->tu_size_desired, b: 1); |
784 | tu->ratio_by_tu_fp = drm_fixp_mul(a: tu->ratio_fp, b: temp1_fp); |
785 | |
786 | tu->delay_start_link = tu->extra_pclk_cycles_in_link_clk + |
787 | tu->filler_size + tu->extra_buffer_margin; |
788 | |
789 | tu->resulting_valid_fp = |
790 | drm_fixp_from_fraction(a: tu->valid_boundary_link, b: 1); |
791 | |
792 | temp1_fp = drm_fixp_from_fraction(a: tu->tu_size_desired, b: 1); |
793 | temp2_fp = drm_fixp_div(a: tu->resulting_valid_fp, b: temp1_fp); |
794 | tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp; |
795 | |
796 | temp1_fp = drm_fixp_from_fraction(a: HBLANK_MARGIN, b: 1); |
797 | temp1_fp = tu->hbp_relative_to_pclk_fp - temp1_fp; |
798 | tu->hbp_time_fp = drm_fixp_div(a: temp1_fp, b: tu->pclk_fp); |
799 | |
800 | temp1_fp = drm_fixp_from_fraction(a: tu->delay_start_link, b: 1); |
801 | tu->delay_start_time_fp = drm_fixp_div(a: temp1_fp, b: tu->lclk_fp); |
802 | |
803 | compare_result_1 = _tu_param_compare(a: tu->hbp_time_fp, |
804 | b: tu->delay_start_time_fp); |
805 | if (compare_result_1 == 2) /* if (hbp_time_fp < delay_start_time_fp) */ |
806 | tu->min_hblank_violated = 1; |
807 | |
808 | tu->hactive_time_fp = drm_fixp_div(a: tu->lwidth_fp, b: tu->pclk_fp); |
809 | |
810 | compare_result_2 = _tu_param_compare(a: tu->hactive_time_fp, |
811 | b: tu->delay_start_time_fp); |
812 | if (compare_result_2 == 2) |
813 | tu->min_hblank_violated = 1; |
814 | |
815 | tu->delay_start_time_fp = 0; |
816 | |
817 | /* brute force */ |
818 | |
819 | tu->delay_start_link_extra_pixclk = EXTRA_PIXCLK_CYCLE_DELAY; |
820 | tu->diff_abs_fp = tu->resulting_valid_fp - tu->ratio_by_tu_fp; |
821 | |
822 | temp = drm_fixp2int(a: tu->diff_abs_fp); |
823 | if (!temp && tu->diff_abs_fp <= 0xffff) |
824 | tu->diff_abs_fp = 0; |
825 | |
826 | /* if(diff_abs < 0) diff_abs *= -1 */ |
827 | if (tu->diff_abs_fp < 0) |
828 | tu->diff_abs_fp = drm_fixp_mul(a: tu->diff_abs_fp, b: -1); |
829 | |
830 | tu->boundary_mod_lower_err = 0; |
831 | if ((tu->diff_abs_fp != 0 && |
832 | ((tu->diff_abs_fp > BRUTE_FORCE_THRESHOLD_fp) || |
833 | (tu->even_distribution_legacy == 0) || |
834 | (DP_BRUTE_FORCE == 1))) || |
835 | (tu->min_hblank_violated == 1)) { |
836 | do { |
837 | tu->err_fp = drm_fixp_from_fraction(a: 1000, b: 1); |
838 | |
839 | temp1_fp = drm_fixp_div(a: tu->lclk_fp, b: tu->pclk_fp); |
840 | temp2_fp = drm_fixp_from_fraction( |
841 | a: tu->delay_start_link_extra_pixclk, b: 1); |
842 | temp1_fp = drm_fixp_mul(a: temp2_fp, b: temp1_fp); |
843 | |
844 | if (temp1_fp) |
845 | tu->extra_buffer_margin = |
846 | drm_fixp2int_ceil(a: temp1_fp); |
847 | else |
848 | tu->extra_buffer_margin = 0; |
849 | |
850 | temp1_fp = drm_fixp_from_fraction(a: tu->bpp, b: 8); |
851 | temp1_fp = drm_fixp_mul(a: tu->lwidth_fp, b: temp1_fp); |
852 | |
853 | if (temp1_fp) |
854 | tu->n_symbols = drm_fixp2int_ceil(a: temp1_fp); |
855 | else |
856 | tu->n_symbols = 0; |
857 | |
858 | for (tu->tu_size = 32; tu->tu_size <= 64; tu->tu_size++) { |
859 | for (tu->i_upper_boundary_count = 1; |
860 | tu->i_upper_boundary_count <= 15; |
861 | tu->i_upper_boundary_count++) { |
862 | for (tu->i_lower_boundary_count = 1; |
863 | tu->i_lower_boundary_count <= 15; |
864 | tu->i_lower_boundary_count++) { |
865 | _tu_valid_boundary_calc(tu); |
866 | } |
867 | } |
868 | } |
869 | tu->delay_start_link_extra_pixclk--; |
870 | } while (tu->boundary_moderation_en != true && |
871 | tu->boundary_mod_lower_err == 1 && |
872 | tu->delay_start_link_extra_pixclk != 0); |
873 | |
874 | if (tu->boundary_moderation_en == true) { |
875 | temp1_fp = drm_fixp_from_fraction( |
876 | a: (tu->upper_boundary_count * |
877 | tu->valid_boundary_link + |
878 | tu->lower_boundary_count * |
879 | (tu->valid_boundary_link - 1)), b: 1); |
880 | temp2_fp = drm_fixp_from_fraction( |
881 | a: (tu->upper_boundary_count + |
882 | tu->lower_boundary_count), b: 1); |
883 | tu->resulting_valid_fp = |
884 | drm_fixp_div(a: temp1_fp, b: temp2_fp); |
885 | |
886 | temp1_fp = drm_fixp_from_fraction( |
887 | a: tu->tu_size_desired, b: 1); |
888 | tu->ratio_by_tu_fp = |
889 | drm_fixp_mul(a: tu->original_ratio_fp, b: temp1_fp); |
890 | |
891 | tu->valid_lower_boundary_link = |
892 | tu->valid_boundary_link - 1; |
893 | |
894 | temp1_fp = drm_fixp_from_fraction(a: tu->bpp, b: 8); |
895 | temp1_fp = drm_fixp_mul(a: tu->lwidth_fp, b: temp1_fp); |
896 | temp2_fp = drm_fixp_div(a: temp1_fp, |
897 | b: tu->resulting_valid_fp); |
898 | tu->n_tus = drm_fixp2int(a: temp2_fp); |
899 | |
900 | tu->tu_size_minus1 = tu->tu_size_desired - 1; |
901 | tu->even_distribution_BF = 1; |
902 | |
903 | temp1_fp = |
904 | drm_fixp_from_fraction(a: tu->tu_size_desired, b: 1); |
905 | temp2_fp = |
906 | drm_fixp_div(a: tu->resulting_valid_fp, b: temp1_fp); |
907 | tu->TU_ratio_err_fp = temp2_fp - tu->original_ratio_fp; |
908 | } |
909 | } |
910 | |
911 | temp2_fp = drm_fixp_mul(a: LCLK_FAST_SKEW_fp, b: tu->lwidth_fp); |
912 | |
913 | if (temp2_fp) |
914 | temp = drm_fixp2int_ceil(a: temp2_fp); |
915 | else |
916 | temp = 0; |
917 | |
918 | temp1_fp = drm_fixp_from_fraction(a: tu->nlanes, b: 1); |
919 | temp2_fp = drm_fixp_mul(a: tu->original_ratio_fp, b: temp1_fp); |
920 | temp1_fp = drm_fixp_from_fraction(a: tu->bpp, b: 8); |
921 | temp2_fp = drm_fixp_div(a: temp1_fp, b: temp2_fp); |
922 | temp1_fp = drm_fixp_from_fraction(a: temp, b: 1); |
923 | temp2_fp = drm_fixp_mul(a: temp1_fp, b: temp2_fp); |
924 | temp = drm_fixp2int(a: temp2_fp); |
925 | |
926 | if (tu->async_en) |
927 | tu->delay_start_link += (int)temp; |
928 | |
929 | temp1_fp = drm_fixp_from_fraction(a: tu->delay_start_link, b: 1); |
930 | tu->delay_start_time_fp = drm_fixp_div(a: temp1_fp, b: tu->lclk_fp); |
931 | |
932 | /* OUTPUTS */ |
933 | tu_table->valid_boundary_link = tu->valid_boundary_link; |
934 | tu_table->delay_start_link = tu->delay_start_link; |
935 | tu_table->boundary_moderation_en = tu->boundary_moderation_en; |
936 | tu_table->valid_lower_boundary_link = tu->valid_lower_boundary_link; |
937 | tu_table->upper_boundary_count = tu->upper_boundary_count; |
938 | tu_table->lower_boundary_count = tu->lower_boundary_count; |
939 | tu_table->tu_size_minus1 = tu->tu_size_minus1; |
940 | |
941 | drm_dbg_dp(ctrl->drm_dev, "TU: valid_boundary_link: %d\n" , |
942 | tu_table->valid_boundary_link); |
943 | drm_dbg_dp(ctrl->drm_dev, "TU: delay_start_link: %d\n" , |
944 | tu_table->delay_start_link); |
945 | drm_dbg_dp(ctrl->drm_dev, "TU: boundary_moderation_en: %d\n" , |
946 | tu_table->boundary_moderation_en); |
947 | drm_dbg_dp(ctrl->drm_dev, "TU: valid_lower_boundary_link: %d\n" , |
948 | tu_table->valid_lower_boundary_link); |
949 | drm_dbg_dp(ctrl->drm_dev, "TU: upper_boundary_count: %d\n" , |
950 | tu_table->upper_boundary_count); |
951 | drm_dbg_dp(ctrl->drm_dev, "TU: lower_boundary_count: %d\n" , |
952 | tu_table->lower_boundary_count); |
953 | drm_dbg_dp(ctrl->drm_dev, "TU: tu_size_minus1: %d\n" , |
954 | tu_table->tu_size_minus1); |
955 | |
956 | kfree(objp: tu); |
957 | } |
958 | |
959 | static void dp_ctrl_calc_tu_parameters(struct dp_ctrl_private *ctrl, |
960 | struct dp_vc_tu_mapping_table *tu_table) |
961 | { |
962 | struct dp_tu_calc_input in; |
963 | struct drm_display_mode *drm_mode; |
964 | |
965 | drm_mode = &ctrl->panel->dp_mode.drm_mode; |
966 | |
967 | in.lclk = ctrl->link->link_params.rate / 1000; |
968 | in.pclk_khz = drm_mode->clock; |
969 | in.hactive = drm_mode->hdisplay; |
970 | in.hporch = drm_mode->htotal - drm_mode->hdisplay; |
971 | in.nlanes = ctrl->link->link_params.num_lanes; |
972 | in.bpp = ctrl->panel->dp_mode.bpp; |
973 | in.pixel_enc = ctrl->panel->dp_mode.out_fmt_is_yuv_420 ? 420 : 444; |
974 | in.dsc_en = 0; |
975 | in.async_en = 0; |
976 | in.fec_en = 0; |
977 | in.num_of_dsc_slices = 0; |
978 | in.compress_ratio = 100; |
979 | |
980 | _dp_ctrl_calc_tu(ctrl, in: &in, tu_table); |
981 | } |
982 | |
983 | static void dp_ctrl_setup_tr_unit(struct dp_ctrl_private *ctrl) |
984 | { |
985 | u32 dp_tu = 0x0; |
986 | u32 valid_boundary = 0x0; |
987 | u32 valid_boundary2 = 0x0; |
988 | struct dp_vc_tu_mapping_table tu_calc_table; |
989 | |
990 | dp_ctrl_calc_tu_parameters(ctrl, tu_table: &tu_calc_table); |
991 | |
992 | dp_tu |= tu_calc_table.tu_size_minus1; |
993 | valid_boundary |= tu_calc_table.valid_boundary_link; |
994 | valid_boundary |= (tu_calc_table.delay_start_link << 16); |
995 | |
996 | valid_boundary2 |= (tu_calc_table.valid_lower_boundary_link << 1); |
997 | valid_boundary2 |= (tu_calc_table.upper_boundary_count << 16); |
998 | valid_boundary2 |= (tu_calc_table.lower_boundary_count << 20); |
999 | |
1000 | if (tu_calc_table.boundary_moderation_en) |
1001 | valid_boundary2 |= BIT(0); |
1002 | |
1003 | pr_debug("dp_tu=0x%x, valid_boundary=0x%x, valid_boundary2=0x%x\n" , |
1004 | dp_tu, valid_boundary, valid_boundary2); |
1005 | |
1006 | dp_catalog_ctrl_update_transfer_unit(dp_catalog: ctrl->catalog, |
1007 | dp_tu, valid_boundary, valid_boundary2); |
1008 | } |
1009 | |
1010 | static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl) |
1011 | { |
1012 | int ret = 0; |
1013 | |
1014 | if (!wait_for_completion_timeout(x: &ctrl->video_comp, |
1015 | WAIT_FOR_VIDEO_READY_TIMEOUT_JIFFIES)) { |
1016 | DRM_ERROR("wait4video timedout\n" ); |
1017 | ret = -ETIMEDOUT; |
1018 | } |
1019 | return ret; |
1020 | } |
1021 | |
1022 | static int dp_ctrl_set_vx_px(struct dp_ctrl_private *ctrl, |
1023 | u8 v_level, u8 p_level) |
1024 | { |
1025 | union phy_configure_opts *phy_opts = &ctrl->phy_opts; |
1026 | |
1027 | /* TODO: Update for all lanes instead of just first one */ |
1028 | phy_opts->dp.voltage[0] = v_level; |
1029 | phy_opts->dp.pre[0] = p_level; |
1030 | phy_opts->dp.set_voltages = 1; |
1031 | phy_configure(phy: ctrl->phy, opts: phy_opts); |
1032 | phy_opts->dp.set_voltages = 0; |
1033 | |
1034 | return 0; |
1035 | } |
1036 | |
1037 | static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl) |
1038 | { |
1039 | struct dp_link *link = ctrl->link; |
1040 | int ret = 0, lane, lane_cnt; |
1041 | u8 buf[4]; |
1042 | u32 max_level_reached = 0; |
1043 | u32 voltage_swing_level = link->phy_params.v_level; |
1044 | u32 pre_emphasis_level = link->phy_params.p_level; |
1045 | |
1046 | drm_dbg_dp(ctrl->drm_dev, |
1047 | "voltage level: %d emphasis level: %d\n" , |
1048 | voltage_swing_level, pre_emphasis_level); |
1049 | ret = dp_ctrl_set_vx_px(ctrl, |
1050 | v_level: voltage_swing_level, p_level: pre_emphasis_level); |
1051 | |
1052 | if (ret) |
1053 | return ret; |
1054 | |
1055 | if (voltage_swing_level >= DP_TRAIN_VOLTAGE_SWING_MAX) { |
1056 | drm_dbg_dp(ctrl->drm_dev, |
1057 | "max. voltage swing level reached %d\n" , |
1058 | voltage_swing_level); |
1059 | max_level_reached |= DP_TRAIN_MAX_SWING_REACHED; |
1060 | } |
1061 | |
1062 | if (pre_emphasis_level >= DP_TRAIN_PRE_EMPHASIS_MAX) { |
1063 | drm_dbg_dp(ctrl->drm_dev, |
1064 | "max. pre-emphasis level reached %d\n" , |
1065 | pre_emphasis_level); |
1066 | max_level_reached |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
1067 | } |
1068 | |
1069 | pre_emphasis_level <<= DP_TRAIN_PRE_EMPHASIS_SHIFT; |
1070 | |
1071 | lane_cnt = ctrl->link->link_params.num_lanes; |
1072 | for (lane = 0; lane < lane_cnt; lane++) |
1073 | buf[lane] = voltage_swing_level | pre_emphasis_level |
1074 | | max_level_reached; |
1075 | |
1076 | drm_dbg_dp(ctrl->drm_dev, "sink: p|v=0x%x\n" , |
1077 | voltage_swing_level | pre_emphasis_level); |
1078 | ret = drm_dp_dpcd_write(aux: ctrl->aux, DP_TRAINING_LANE0_SET, |
1079 | buffer: buf, size: lane_cnt); |
1080 | if (ret == lane_cnt) |
1081 | ret = 0; |
1082 | |
1083 | return ret; |
1084 | } |
1085 | |
1086 | static bool dp_ctrl_train_pattern_set(struct dp_ctrl_private *ctrl, |
1087 | u8 pattern) |
1088 | { |
1089 | u8 buf; |
1090 | int ret = 0; |
1091 | |
1092 | drm_dbg_dp(ctrl->drm_dev, "sink: pattern=%x\n" , pattern); |
1093 | |
1094 | buf = pattern; |
1095 | |
1096 | if (pattern && pattern != DP_TRAINING_PATTERN_4) |
1097 | buf |= DP_LINK_SCRAMBLING_DISABLE; |
1098 | |
1099 | ret = drm_dp_dpcd_writeb(aux: ctrl->aux, DP_TRAINING_PATTERN_SET, value: buf); |
1100 | return ret == 1; |
1101 | } |
1102 | |
1103 | static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl, |
1104 | u8 *link_status) |
1105 | { |
1106 | int ret = 0, len; |
1107 | |
1108 | len = drm_dp_dpcd_read_link_status(aux: ctrl->aux, status: link_status); |
1109 | if (len != DP_LINK_STATUS_SIZE) { |
1110 | DRM_ERROR("DP link status read failed, err: %d\n" , len); |
1111 | ret = -EINVAL; |
1112 | } |
1113 | |
1114 | return ret; |
1115 | } |
1116 | |
1117 | static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl, |
1118 | int *training_step) |
1119 | { |
1120 | int tries, old_v_level, ret = 0; |
1121 | u8 link_status[DP_LINK_STATUS_SIZE]; |
1122 | int const maximum_retries = 4; |
1123 | |
1124 | dp_catalog_ctrl_state_ctrl(dp_catalog: ctrl->catalog, state: 0); |
1125 | |
1126 | *training_step = DP_TRAINING_1; |
1127 | |
1128 | ret = dp_catalog_ctrl_set_pattern_state_bit(dp_catalog: ctrl->catalog, pattern: 1); |
1129 | if (ret) |
1130 | return ret; |
1131 | dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_1 | |
1132 | DP_LINK_SCRAMBLING_DISABLE); |
1133 | |
1134 | ret = dp_ctrl_update_vx_px(ctrl); |
1135 | if (ret) |
1136 | return ret; |
1137 | |
1138 | tries = 0; |
1139 | old_v_level = ctrl->link->phy_params.v_level; |
1140 | for (tries = 0; tries < maximum_retries; tries++) { |
1141 | drm_dp_link_train_clock_recovery_delay(aux: ctrl->aux, dpcd: ctrl->panel->dpcd); |
1142 | |
1143 | ret = dp_ctrl_read_link_status(ctrl, link_status); |
1144 | if (ret) |
1145 | return ret; |
1146 | |
1147 | if (drm_dp_clock_recovery_ok(link_status, |
1148 | lane_count: ctrl->link->link_params.num_lanes)) { |
1149 | return 0; |
1150 | } |
1151 | |
1152 | if (ctrl->link->phy_params.v_level >= |
1153 | DP_TRAIN_VOLTAGE_SWING_MAX) { |
1154 | DRM_ERROR_RATELIMITED("max v_level reached\n" ); |
1155 | return -EAGAIN; |
1156 | } |
1157 | |
1158 | if (old_v_level != ctrl->link->phy_params.v_level) { |
1159 | tries = 0; |
1160 | old_v_level = ctrl->link->phy_params.v_level; |
1161 | } |
1162 | |
1163 | dp_link_adjust_levels(dp_link: ctrl->link, link_status); |
1164 | ret = dp_ctrl_update_vx_px(ctrl); |
1165 | if (ret) |
1166 | return ret; |
1167 | } |
1168 | |
1169 | DRM_ERROR("max tries reached\n" ); |
1170 | return -ETIMEDOUT; |
1171 | } |
1172 | |
1173 | static int dp_ctrl_link_rate_down_shift(struct dp_ctrl_private *ctrl) |
1174 | { |
1175 | int ret = 0; |
1176 | |
1177 | switch (ctrl->link->link_params.rate) { |
1178 | case 810000: |
1179 | ctrl->link->link_params.rate = 540000; |
1180 | break; |
1181 | case 540000: |
1182 | ctrl->link->link_params.rate = 270000; |
1183 | break; |
1184 | case 270000: |
1185 | ctrl->link->link_params.rate = 162000; |
1186 | break; |
1187 | case 162000: |
1188 | default: |
1189 | ret = -EINVAL; |
1190 | break; |
1191 | } |
1192 | |
1193 | if (!ret) { |
1194 | drm_dbg_dp(ctrl->drm_dev, "new rate=0x%x\n" , |
1195 | ctrl->link->link_params.rate); |
1196 | } |
1197 | |
1198 | return ret; |
1199 | } |
1200 | |
1201 | static int dp_ctrl_link_lane_down_shift(struct dp_ctrl_private *ctrl) |
1202 | { |
1203 | |
1204 | if (ctrl->link->link_params.num_lanes == 1) |
1205 | return -1; |
1206 | |
1207 | ctrl->link->link_params.num_lanes /= 2; |
1208 | ctrl->link->link_params.rate = ctrl->panel->link_info.rate; |
1209 | |
1210 | ctrl->link->phy_params.p_level = 0; |
1211 | ctrl->link->phy_params.v_level = 0; |
1212 | |
1213 | return 0; |
1214 | } |
1215 | |
1216 | static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl) |
1217 | { |
1218 | dp_ctrl_train_pattern_set(ctrl, DP_TRAINING_PATTERN_DISABLE); |
1219 | drm_dp_link_train_channel_eq_delay(aux: ctrl->aux, dpcd: ctrl->panel->dpcd); |
1220 | } |
1221 | |
1222 | static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, |
1223 | int *training_step) |
1224 | { |
1225 | int tries = 0, ret = 0; |
1226 | u8 pattern; |
1227 | u32 state_ctrl_bit; |
1228 | int const maximum_retries = 5; |
1229 | u8 link_status[DP_LINK_STATUS_SIZE]; |
1230 | |
1231 | dp_catalog_ctrl_state_ctrl(dp_catalog: ctrl->catalog, state: 0); |
1232 | |
1233 | *training_step = DP_TRAINING_2; |
1234 | |
1235 | if (drm_dp_tps4_supported(dpcd: ctrl->panel->dpcd)) { |
1236 | pattern = DP_TRAINING_PATTERN_4; |
1237 | state_ctrl_bit = 4; |
1238 | } else if (drm_dp_tps3_supported(dpcd: ctrl->panel->dpcd)) { |
1239 | pattern = DP_TRAINING_PATTERN_3; |
1240 | state_ctrl_bit = 3; |
1241 | } else { |
1242 | pattern = DP_TRAINING_PATTERN_2; |
1243 | state_ctrl_bit = 2; |
1244 | } |
1245 | |
1246 | ret = dp_catalog_ctrl_set_pattern_state_bit(dp_catalog: ctrl->catalog, pattern: state_ctrl_bit); |
1247 | if (ret) |
1248 | return ret; |
1249 | |
1250 | dp_ctrl_train_pattern_set(ctrl, pattern); |
1251 | |
1252 | for (tries = 0; tries <= maximum_retries; tries++) { |
1253 | drm_dp_link_train_channel_eq_delay(aux: ctrl->aux, dpcd: ctrl->panel->dpcd); |
1254 | |
1255 | ret = dp_ctrl_read_link_status(ctrl, link_status); |
1256 | if (ret) |
1257 | return ret; |
1258 | |
1259 | if (drm_dp_channel_eq_ok(link_status, |
1260 | lane_count: ctrl->link->link_params.num_lanes)) { |
1261 | return 0; |
1262 | } |
1263 | |
1264 | dp_link_adjust_levels(dp_link: ctrl->link, link_status); |
1265 | ret = dp_ctrl_update_vx_px(ctrl); |
1266 | if (ret) |
1267 | return ret; |
1268 | |
1269 | } |
1270 | |
1271 | return -ETIMEDOUT; |
1272 | } |
1273 | |
1274 | static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, |
1275 | int *training_step) |
1276 | { |
1277 | int ret = 0; |
1278 | const u8 *dpcd = ctrl->panel->dpcd; |
1279 | u8 encoding[] = { 0, DP_SET_ANSI_8B10B }; |
1280 | u8 assr; |
1281 | struct dp_link_info link_info = {0}; |
1282 | |
1283 | dp_ctrl_config_ctrl(ctrl); |
1284 | |
1285 | link_info.num_lanes = ctrl->link->link_params.num_lanes; |
1286 | link_info.rate = ctrl->link->link_params.rate; |
1287 | link_info.capabilities = DP_LINK_CAP_ENHANCED_FRAMING; |
1288 | |
1289 | dp_aux_link_configure(aux: ctrl->aux, link: &link_info); |
1290 | |
1291 | if (drm_dp_max_downspread(dpcd)) |
1292 | encoding[0] |= DP_SPREAD_AMP_0_5; |
1293 | |
1294 | /* config DOWNSPREAD_CTRL and MAIN_LINK_CHANNEL_CODING_SET */ |
1295 | drm_dp_dpcd_write(aux: ctrl->aux, DP_DOWNSPREAD_CTRL, buffer: encoding, size: 2); |
1296 | |
1297 | if (drm_dp_alternate_scrambler_reset_cap(dpcd)) { |
1298 | assr = DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; |
1299 | drm_dp_dpcd_write(aux: ctrl->aux, DP_EDP_CONFIGURATION_SET, |
1300 | buffer: &assr, size: 1); |
1301 | } |
1302 | |
1303 | ret = dp_ctrl_link_train_1(ctrl, training_step); |
1304 | if (ret) { |
1305 | DRM_ERROR("link training #1 failed. ret=%d\n" , ret); |
1306 | goto end; |
1307 | } |
1308 | |
1309 | /* print success info as this is a result of user initiated action */ |
1310 | drm_dbg_dp(ctrl->drm_dev, "link training #1 successful\n" ); |
1311 | |
1312 | ret = dp_ctrl_link_train_2(ctrl, training_step); |
1313 | if (ret) { |
1314 | DRM_ERROR("link training #2 failed. ret=%d\n" , ret); |
1315 | goto end; |
1316 | } |
1317 | |
1318 | /* print success info as this is a result of user initiated action */ |
1319 | drm_dbg_dp(ctrl->drm_dev, "link training #2 successful\n" ); |
1320 | |
1321 | end: |
1322 | dp_catalog_ctrl_state_ctrl(dp_catalog: ctrl->catalog, state: 0); |
1323 | |
1324 | return ret; |
1325 | } |
1326 | |
1327 | static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl, |
1328 | int *training_step) |
1329 | { |
1330 | int ret = 0; |
1331 | |
1332 | dp_catalog_ctrl_mainlink_ctrl(dp_catalog: ctrl->catalog, enable: true); |
1333 | |
1334 | if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) |
1335 | return ret; |
1336 | |
1337 | /* |
1338 | * As part of previous calls, DP controller state might have |
1339 | * transitioned to PUSH_IDLE. In order to start transmitting |
1340 | * a link training pattern, we have to first do soft reset. |
1341 | */ |
1342 | |
1343 | ret = dp_ctrl_link_train(ctrl, training_step); |
1344 | |
1345 | return ret; |
1346 | } |
1347 | |
1348 | int dp_ctrl_core_clk_enable(struct dp_ctrl *dp_ctrl) |
1349 | { |
1350 | struct dp_ctrl_private *ctrl; |
1351 | int ret = 0; |
1352 | |
1353 | ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); |
1354 | |
1355 | if (ctrl->core_clks_on) { |
1356 | drm_dbg_dp(ctrl->drm_dev, "core clks already enabled\n" ); |
1357 | return 0; |
1358 | } |
1359 | |
1360 | ret = clk_bulk_prepare_enable(ctrl->num_core_clks, ctrl->core_clks); |
1361 | if (ret) |
1362 | return ret; |
1363 | |
1364 | ctrl->core_clks_on = true; |
1365 | |
1366 | drm_dbg_dp(ctrl->drm_dev, "enable core clocks \n" ); |
1367 | drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n" , |
1368 | ctrl->stream_clks_on ? "on" : "off" , |
1369 | ctrl->link_clks_on ? "on" : "off" , |
1370 | ctrl->core_clks_on ? "on" : "off" ); |
1371 | |
1372 | return 0; |
1373 | } |
1374 | |
1375 | void dp_ctrl_core_clk_disable(struct dp_ctrl *dp_ctrl) |
1376 | { |
1377 | struct dp_ctrl_private *ctrl; |
1378 | |
1379 | ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); |
1380 | |
1381 | clk_bulk_disable_unprepare(ctrl->num_core_clks, ctrl->core_clks); |
1382 | |
1383 | ctrl->core_clks_on = false; |
1384 | |
1385 | drm_dbg_dp(ctrl->drm_dev, "disable core clocks \n" ); |
1386 | drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n" , |
1387 | ctrl->stream_clks_on ? "on" : "off" , |
1388 | ctrl->link_clks_on ? "on" : "off" , |
1389 | ctrl->core_clks_on ? "on" : "off" ); |
1390 | } |
1391 | |
1392 | static int dp_ctrl_link_clk_enable(struct dp_ctrl *dp_ctrl) |
1393 | { |
1394 | struct dp_ctrl_private *ctrl; |
1395 | int ret = 0; |
1396 | |
1397 | ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); |
1398 | |
1399 | if (ctrl->link_clks_on) { |
1400 | drm_dbg_dp(ctrl->drm_dev, "links clks already enabled\n" ); |
1401 | return 0; |
1402 | } |
1403 | |
1404 | if (!ctrl->core_clks_on) { |
1405 | drm_dbg_dp(ctrl->drm_dev, "Enable core clks before link clks\n" ); |
1406 | |
1407 | dp_ctrl_core_clk_enable(dp_ctrl); |
1408 | } |
1409 | |
1410 | ret = clk_bulk_prepare_enable(ctrl->num_link_clks, ctrl->link_clks); |
1411 | if (ret) |
1412 | return ret; |
1413 | |
1414 | ctrl->link_clks_on = true; |
1415 | |
1416 | drm_dbg_dp(ctrl->drm_dev, "enable link clocks\n" ); |
1417 | drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n" , |
1418 | ctrl->stream_clks_on ? "on" : "off" , |
1419 | ctrl->link_clks_on ? "on" : "off" , |
1420 | ctrl->core_clks_on ? "on" : "off" ); |
1421 | |
1422 | return 0; |
1423 | } |
1424 | |
1425 | static void dp_ctrl_link_clk_disable(struct dp_ctrl *dp_ctrl) |
1426 | { |
1427 | struct dp_ctrl_private *ctrl; |
1428 | |
1429 | ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); |
1430 | |
1431 | clk_bulk_disable_unprepare(ctrl->num_link_clks, ctrl->link_clks); |
1432 | |
1433 | ctrl->link_clks_on = false; |
1434 | |
1435 | drm_dbg_dp(ctrl->drm_dev, "disabled link clocks\n" ); |
1436 | drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n" , |
1437 | ctrl->stream_clks_on ? "on" : "off" , |
1438 | ctrl->link_clks_on ? "on" : "off" , |
1439 | ctrl->core_clks_on ? "on" : "off" ); |
1440 | } |
1441 | |
1442 | static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) |
1443 | { |
1444 | int ret = 0; |
1445 | struct phy *phy = ctrl->phy; |
1446 | const u8 *dpcd = ctrl->panel->dpcd; |
1447 | |
1448 | ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; |
1449 | ctrl->phy_opts.dp.link_rate = ctrl->link->link_params.rate / 100; |
1450 | ctrl->phy_opts.dp.ssc = drm_dp_max_downspread(dpcd); |
1451 | |
1452 | phy_configure(phy, opts: &ctrl->phy_opts); |
1453 | phy_power_on(phy); |
1454 | |
1455 | dev_pm_opp_set_rate(dev: ctrl->dev, target_freq: ctrl->link->link_params.rate * 1000); |
1456 | ret = dp_ctrl_link_clk_enable(dp_ctrl: &ctrl->dp_ctrl); |
1457 | if (ret) |
1458 | DRM_ERROR("Unable to start link clocks. ret=%d\n" , ret); |
1459 | |
1460 | drm_dbg_dp(ctrl->drm_dev, "link rate=%d\n" , ctrl->link->link_params.rate); |
1461 | |
1462 | return ret; |
1463 | } |
1464 | |
1465 | void dp_ctrl_reset_irq_ctrl(struct dp_ctrl *dp_ctrl, bool enable) |
1466 | { |
1467 | struct dp_ctrl_private *ctrl; |
1468 | |
1469 | ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); |
1470 | |
1471 | dp_catalog_ctrl_reset(dp_catalog: ctrl->catalog); |
1472 | |
1473 | /* |
1474 | * all dp controller programmable registers will not |
1475 | * be reset to default value after DP_SW_RESET |
1476 | * therefore interrupt mask bits have to be updated |
1477 | * to enable/disable interrupts |
1478 | */ |
1479 | dp_catalog_ctrl_enable_irq(dp_catalog: ctrl->catalog, enable); |
1480 | } |
1481 | |
1482 | void dp_ctrl_config_psr(struct dp_ctrl *dp_ctrl) |
1483 | { |
1484 | u8 cfg; |
1485 | struct dp_ctrl_private *ctrl = container_of(dp_ctrl, |
1486 | struct dp_ctrl_private, dp_ctrl); |
1487 | |
1488 | if (!ctrl->panel->psr_cap.version) |
1489 | return; |
1490 | |
1491 | dp_catalog_ctrl_config_psr(dp_catalog: ctrl->catalog); |
1492 | |
1493 | cfg = DP_PSR_ENABLE; |
1494 | drm_dp_dpcd_write(aux: ctrl->aux, DP_PSR_EN_CFG, buffer: &cfg, size: 1); |
1495 | } |
1496 | |
1497 | void dp_ctrl_set_psr(struct dp_ctrl *dp_ctrl, bool enter) |
1498 | { |
1499 | struct dp_ctrl_private *ctrl = container_of(dp_ctrl, |
1500 | struct dp_ctrl_private, dp_ctrl); |
1501 | |
1502 | if (!ctrl->panel->psr_cap.version) |
1503 | return; |
1504 | |
1505 | /* |
1506 | * When entering PSR, |
1507 | * 1. Send PSR enter SDP and wait for the PSR_UPDATE_INT |
1508 | * 2. Turn off video |
1509 | * 3. Disable the mainlink |
1510 | * |
1511 | * When exiting PSR, |
1512 | * 1. Enable the mainlink |
1513 | * 2. Send the PSR exit SDP |
1514 | */ |
1515 | if (enter) { |
1516 | reinit_completion(x: &ctrl->psr_op_comp); |
1517 | dp_catalog_ctrl_set_psr(dp_catalog: ctrl->catalog, enter: true); |
1518 | |
1519 | if (!wait_for_completion_timeout(x: &ctrl->psr_op_comp, |
1520 | PSR_OPERATION_COMPLETION_TIMEOUT_JIFFIES)) { |
1521 | DRM_ERROR("PSR_ENTRY timedout\n" ); |
1522 | dp_catalog_ctrl_set_psr(dp_catalog: ctrl->catalog, enter: false); |
1523 | return; |
1524 | } |
1525 | |
1526 | dp_ctrl_push_idle(dp_ctrl); |
1527 | dp_catalog_ctrl_state_ctrl(dp_catalog: ctrl->catalog, state: 0); |
1528 | |
1529 | dp_catalog_ctrl_psr_mainlink_enable(dp_catalog: ctrl->catalog, enable: false); |
1530 | } else { |
1531 | dp_catalog_ctrl_psr_mainlink_enable(dp_catalog: ctrl->catalog, enable: true); |
1532 | |
1533 | dp_catalog_ctrl_set_psr(dp_catalog: ctrl->catalog, enter: false); |
1534 | dp_catalog_ctrl_state_ctrl(dp_catalog: ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); |
1535 | dp_ctrl_wait4video_ready(ctrl); |
1536 | dp_catalog_ctrl_state_ctrl(dp_catalog: ctrl->catalog, state: 0); |
1537 | } |
1538 | } |
1539 | |
1540 | void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl) |
1541 | { |
1542 | struct dp_ctrl_private *ctrl; |
1543 | struct phy *phy; |
1544 | |
1545 | ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); |
1546 | phy = ctrl->phy; |
1547 | |
1548 | dp_catalog_ctrl_phy_reset(dp_catalog: ctrl->catalog); |
1549 | phy_init(phy); |
1550 | |
1551 | drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n" , |
1552 | phy, phy->init_count, phy->power_count); |
1553 | } |
1554 | |
1555 | void dp_ctrl_phy_exit(struct dp_ctrl *dp_ctrl) |
1556 | { |
1557 | struct dp_ctrl_private *ctrl; |
1558 | struct phy *phy; |
1559 | |
1560 | ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); |
1561 | phy = ctrl->phy; |
1562 | |
1563 | dp_catalog_ctrl_phy_reset(dp_catalog: ctrl->catalog); |
1564 | phy_exit(phy); |
1565 | drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n" , |
1566 | phy, phy->init_count, phy->power_count); |
1567 | } |
1568 | |
1569 | static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl) |
1570 | { |
1571 | const u8 *dpcd = ctrl->panel->dpcd; |
1572 | |
1573 | /* |
1574 | * For better interop experience, used a fixed NVID=0x8000 |
1575 | * whenever connected to a VGA dongle downstream. |
1576 | */ |
1577 | if (drm_dp_is_branch(dpcd)) |
1578 | return (drm_dp_has_quirk(desc: &ctrl->panel->desc, |
1579 | quirk: DP_DPCD_QUIRK_CONSTANT_N)); |
1580 | |
1581 | return false; |
1582 | } |
1583 | |
1584 | static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) |
1585 | { |
1586 | struct phy *phy = ctrl->phy; |
1587 | int ret = 0; |
1588 | |
1589 | dp_catalog_ctrl_mainlink_ctrl(dp_catalog: ctrl->catalog, enable: false); |
1590 | ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; |
1591 | phy_configure(phy, opts: &ctrl->phy_opts); |
1592 | /* |
1593 | * Disable and re-enable the mainlink clock since the |
1594 | * link clock might have been adjusted as part of the |
1595 | * link maintenance. |
1596 | */ |
1597 | dev_pm_opp_set_rate(dev: ctrl->dev, target_freq: 0); |
1598 | |
1599 | dp_ctrl_link_clk_disable(dp_ctrl: &ctrl->dp_ctrl); |
1600 | |
1601 | phy_power_off(phy); |
1602 | /* hw recommended delay before re-enabling clocks */ |
1603 | msleep(msecs: 20); |
1604 | |
1605 | ret = dp_ctrl_enable_mainlink_clocks(ctrl); |
1606 | if (ret) { |
1607 | DRM_ERROR("Failed to enable mainlink clks. ret=%d\n" , ret); |
1608 | return ret; |
1609 | } |
1610 | |
1611 | return ret; |
1612 | } |
1613 | |
1614 | static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl) |
1615 | { |
1616 | struct phy *phy; |
1617 | |
1618 | phy = ctrl->phy; |
1619 | |
1620 | dp_catalog_ctrl_mainlink_ctrl(dp_catalog: ctrl->catalog, enable: false); |
1621 | |
1622 | dp_catalog_ctrl_reset(dp_catalog: ctrl->catalog); |
1623 | |
1624 | dev_pm_opp_set_rate(dev: ctrl->dev, target_freq: 0); |
1625 | dp_ctrl_link_clk_disable(dp_ctrl: &ctrl->dp_ctrl); |
1626 | |
1627 | phy_power_off(phy); |
1628 | |
1629 | /* aux channel down, reinit phy */ |
1630 | phy_exit(phy); |
1631 | phy_init(phy); |
1632 | |
1633 | drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n" , |
1634 | phy, phy->init_count, phy->power_count); |
1635 | return 0; |
1636 | } |
1637 | |
1638 | static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl) |
1639 | { |
1640 | int ret = 0; |
1641 | int training_step = DP_TRAINING_NONE; |
1642 | |
1643 | dp_ctrl_push_idle(dp_ctrl: &ctrl->dp_ctrl); |
1644 | |
1645 | ctrl->link->phy_params.p_level = 0; |
1646 | ctrl->link->phy_params.v_level = 0; |
1647 | |
1648 | ret = dp_ctrl_setup_main_link(ctrl, training_step: &training_step); |
1649 | if (ret) |
1650 | goto end; |
1651 | |
1652 | dp_ctrl_clear_training_pattern(ctrl); |
1653 | |
1654 | dp_catalog_ctrl_state_ctrl(dp_catalog: ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); |
1655 | |
1656 | ret = dp_ctrl_wait4video_ready(ctrl); |
1657 | end: |
1658 | return ret; |
1659 | } |
1660 | |
1661 | static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl) |
1662 | { |
1663 | bool success = false; |
1664 | u32 pattern_sent = 0x0; |
1665 | u32 pattern_requested = ctrl->link->phy_params.phy_test_pattern_sel; |
1666 | |
1667 | drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n" , pattern_requested); |
1668 | |
1669 | if (dp_ctrl_set_vx_px(ctrl, |
1670 | v_level: ctrl->link->phy_params.v_level, |
1671 | p_level: ctrl->link->phy_params.p_level)) { |
1672 | DRM_ERROR("Failed to set v/p levels\n" ); |
1673 | return false; |
1674 | } |
1675 | dp_catalog_ctrl_send_phy_pattern(dp_catalog: ctrl->catalog, pattern: pattern_requested); |
1676 | dp_ctrl_update_vx_px(ctrl); |
1677 | dp_link_send_test_response(dp_link: ctrl->link); |
1678 | |
1679 | pattern_sent = dp_catalog_ctrl_read_phy_pattern(dp_catalog: ctrl->catalog); |
1680 | |
1681 | switch (pattern_sent) { |
1682 | case MR_LINK_TRAINING1: |
1683 | success = (pattern_requested == |
1684 | DP_PHY_TEST_PATTERN_D10_2); |
1685 | break; |
1686 | case MR_LINK_SYMBOL_ERM: |
1687 | success = ((pattern_requested == |
1688 | DP_PHY_TEST_PATTERN_ERROR_COUNT) || |
1689 | (pattern_requested == |
1690 | DP_PHY_TEST_PATTERN_CP2520)); |
1691 | break; |
1692 | case MR_LINK_PRBS7: |
1693 | success = (pattern_requested == |
1694 | DP_PHY_TEST_PATTERN_PRBS7); |
1695 | break; |
1696 | case MR_LINK_CUSTOM80: |
1697 | success = (pattern_requested == |
1698 | DP_PHY_TEST_PATTERN_80BIT_CUSTOM); |
1699 | break; |
1700 | case MR_LINK_TRAINING4: |
1701 | success = (pattern_requested == |
1702 | DP_PHY_TEST_PATTERN_SEL_MASK); |
1703 | break; |
1704 | default: |
1705 | success = false; |
1706 | } |
1707 | |
1708 | drm_dbg_dp(ctrl->drm_dev, "%s: test->0x%x\n" , |
1709 | success ? "success" : "failed" , pattern_requested); |
1710 | return success; |
1711 | } |
1712 | |
1713 | static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl) |
1714 | { |
1715 | int ret; |
1716 | unsigned long pixel_rate; |
1717 | |
1718 | if (!ctrl->link->phy_params.phy_test_pattern_sel) { |
1719 | drm_dbg_dp(ctrl->drm_dev, |
1720 | "no test pattern selected by sink\n" ); |
1721 | return 0; |
1722 | } |
1723 | |
1724 | /* |
1725 | * The global reset will need DP link related clocks to be |
1726 | * running. Add the global reset just before disabling the |
1727 | * link clocks and core clocks. |
1728 | */ |
1729 | dp_ctrl_off(dp_ctrl: &ctrl->dp_ctrl); |
1730 | |
1731 | ret = dp_ctrl_on_link(dp_ctrl: &ctrl->dp_ctrl); |
1732 | if (ret) { |
1733 | DRM_ERROR("failed to enable DP link controller\n" ); |
1734 | return ret; |
1735 | } |
1736 | |
1737 | pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; |
1738 | ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); |
1739 | if (ret) { |
1740 | DRM_ERROR("Failed to set pixel clock rate. ret=%d\n" , ret); |
1741 | return ret; |
1742 | } |
1743 | |
1744 | if (ctrl->stream_clks_on) { |
1745 | drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n" ); |
1746 | } else { |
1747 | ret = clk_prepare_enable(ctrl->pixel_clk); |
1748 | if (ret) { |
1749 | DRM_ERROR("Failed to start pixel clocks. ret=%d\n" , ret); |
1750 | return ret; |
1751 | } |
1752 | ctrl->stream_clks_on = true; |
1753 | } |
1754 | |
1755 | dp_ctrl_send_phy_test_pattern(ctrl); |
1756 | |
1757 | return 0; |
1758 | } |
1759 | |
1760 | void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl) |
1761 | { |
1762 | struct dp_ctrl_private *ctrl; |
1763 | u32 sink_request = 0x0; |
1764 | |
1765 | if (!dp_ctrl) { |
1766 | DRM_ERROR("invalid input\n" ); |
1767 | return; |
1768 | } |
1769 | |
1770 | ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); |
1771 | sink_request = ctrl->link->sink_request; |
1772 | |
1773 | if (sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { |
1774 | drm_dbg_dp(ctrl->drm_dev, "PHY_TEST_PATTERN request\n" ); |
1775 | if (dp_ctrl_process_phy_test_request(ctrl)) { |
1776 | DRM_ERROR("process phy_test_req failed\n" ); |
1777 | return; |
1778 | } |
1779 | } |
1780 | |
1781 | if (sink_request & DP_LINK_STATUS_UPDATED) { |
1782 | if (dp_ctrl_link_maintenance(ctrl)) { |
1783 | DRM_ERROR("LM failed: TEST_LINK_TRAINING\n" ); |
1784 | return; |
1785 | } |
1786 | } |
1787 | |
1788 | if (sink_request & DP_TEST_LINK_TRAINING) { |
1789 | dp_link_send_test_response(dp_link: ctrl->link); |
1790 | if (dp_ctrl_link_maintenance(ctrl)) { |
1791 | DRM_ERROR("LM failed: TEST_LINK_TRAINING\n" ); |
1792 | return; |
1793 | } |
1794 | } |
1795 | } |
1796 | |
1797 | static bool dp_ctrl_clock_recovery_any_ok( |
1798 | const u8 link_status[DP_LINK_STATUS_SIZE], |
1799 | int lane_count) |
1800 | { |
1801 | int reduced_cnt; |
1802 | |
1803 | if (lane_count <= 1) |
1804 | return false; |
1805 | |
1806 | /* |
1807 | * only interested in the lane number after reduced |
1808 | * lane_count = 4, then only interested in 2 lanes |
1809 | * lane_count = 2, then only interested in 1 lane |
1810 | */ |
1811 | reduced_cnt = lane_count >> 1; |
1812 | |
1813 | return drm_dp_clock_recovery_ok(link_status, lane_count: reduced_cnt); |
1814 | } |
1815 | |
1816 | static bool dp_ctrl_channel_eq_ok(struct dp_ctrl_private *ctrl) |
1817 | { |
1818 | u8 link_status[DP_LINK_STATUS_SIZE]; |
1819 | int num_lanes = ctrl->link->link_params.num_lanes; |
1820 | |
1821 | dp_ctrl_read_link_status(ctrl, link_status); |
1822 | |
1823 | return drm_dp_channel_eq_ok(link_status, lane_count: num_lanes); |
1824 | } |
1825 | |
1826 | int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl) |
1827 | { |
1828 | int rc = 0; |
1829 | struct dp_ctrl_private *ctrl; |
1830 | u32 rate; |
1831 | int link_train_max_retries = 5; |
1832 | u32 const phy_cts_pixel_clk_khz = 148500; |
1833 | u8 link_status[DP_LINK_STATUS_SIZE]; |
1834 | unsigned int training_step; |
1835 | unsigned long pixel_rate; |
1836 | |
1837 | if (!dp_ctrl) |
1838 | return -EINVAL; |
1839 | |
1840 | ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); |
1841 | |
1842 | rate = ctrl->panel->link_info.rate; |
1843 | pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; |
1844 | |
1845 | dp_ctrl_core_clk_enable(dp_ctrl: &ctrl->dp_ctrl); |
1846 | |
1847 | if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { |
1848 | drm_dbg_dp(ctrl->drm_dev, |
1849 | "using phy test link parameters\n" ); |
1850 | if (!pixel_rate) |
1851 | pixel_rate = phy_cts_pixel_clk_khz; |
1852 | } else { |
1853 | ctrl->link->link_params.rate = rate; |
1854 | ctrl->link->link_params.num_lanes = |
1855 | ctrl->panel->link_info.num_lanes; |
1856 | if (ctrl->panel->dp_mode.out_fmt_is_yuv_420) |
1857 | pixel_rate >>= 1; |
1858 | } |
1859 | |
1860 | drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n" , |
1861 | ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes, |
1862 | pixel_rate); |
1863 | |
1864 | rc = dp_ctrl_enable_mainlink_clocks(ctrl); |
1865 | if (rc) |
1866 | return rc; |
1867 | |
1868 | while (--link_train_max_retries) { |
1869 | training_step = DP_TRAINING_NONE; |
1870 | rc = dp_ctrl_setup_main_link(ctrl, training_step: &training_step); |
1871 | if (rc == 0) { |
1872 | /* training completed successfully */ |
1873 | break; |
1874 | } else if (training_step == DP_TRAINING_1) { |
1875 | /* link train_1 failed */ |
1876 | if (!dp_catalog_link_is_connected(dp_catalog: ctrl->catalog)) |
1877 | break; |
1878 | |
1879 | dp_ctrl_read_link_status(ctrl, link_status); |
1880 | |
1881 | rc = dp_ctrl_link_rate_down_shift(ctrl); |
1882 | if (rc < 0) { /* already in RBR = 1.6G */ |
1883 | if (dp_ctrl_clock_recovery_any_ok(link_status, |
1884 | lane_count: ctrl->link->link_params.num_lanes)) { |
1885 | /* |
1886 | * some lanes are ready, |
1887 | * reduce lane number |
1888 | */ |
1889 | rc = dp_ctrl_link_lane_down_shift(ctrl); |
1890 | if (rc < 0) { /* lane == 1 already */ |
1891 | /* end with failure */ |
1892 | break; |
1893 | } |
1894 | } else { |
1895 | /* end with failure */ |
1896 | break; /* lane == 1 already */ |
1897 | } |
1898 | } |
1899 | } else if (training_step == DP_TRAINING_2) { |
1900 | /* link train_2 failed */ |
1901 | if (!dp_catalog_link_is_connected(dp_catalog: ctrl->catalog)) |
1902 | break; |
1903 | |
1904 | dp_ctrl_read_link_status(ctrl, link_status); |
1905 | |
1906 | if (!drm_dp_clock_recovery_ok(link_status, |
1907 | lane_count: ctrl->link->link_params.num_lanes)) |
1908 | rc = dp_ctrl_link_rate_down_shift(ctrl); |
1909 | else |
1910 | rc = dp_ctrl_link_lane_down_shift(ctrl); |
1911 | |
1912 | if (rc < 0) { |
1913 | /* end with failure */ |
1914 | break; /* lane == 1 already */ |
1915 | } |
1916 | |
1917 | /* stop link training before start re training */ |
1918 | dp_ctrl_clear_training_pattern(ctrl); |
1919 | } |
1920 | |
1921 | rc = dp_ctrl_reinitialize_mainlink(ctrl); |
1922 | if (rc) { |
1923 | DRM_ERROR("Failed to reinitialize mainlink. rc=%d\n" , rc); |
1924 | break; |
1925 | } |
1926 | } |
1927 | |
1928 | if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) |
1929 | return rc; |
1930 | |
1931 | if (rc == 0) { /* link train successfully */ |
1932 | /* |
1933 | * do not stop train pattern here |
1934 | * stop link training at on_stream |
1935 | * to pass compliance test |
1936 | */ |
1937 | } else { |
1938 | /* |
1939 | * link training failed |
1940 | * end txing train pattern here |
1941 | */ |
1942 | dp_ctrl_clear_training_pattern(ctrl); |
1943 | |
1944 | dp_ctrl_deinitialize_mainlink(ctrl); |
1945 | rc = -ECONNRESET; |
1946 | } |
1947 | |
1948 | return rc; |
1949 | } |
1950 | |
1951 | static int dp_ctrl_link_retrain(struct dp_ctrl_private *ctrl) |
1952 | { |
1953 | int training_step = DP_TRAINING_NONE; |
1954 | |
1955 | return dp_ctrl_setup_main_link(ctrl, training_step: &training_step); |
1956 | } |
1957 | |
1958 | int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train) |
1959 | { |
1960 | int ret = 0; |
1961 | bool mainlink_ready = false; |
1962 | struct dp_ctrl_private *ctrl; |
1963 | unsigned long pixel_rate; |
1964 | unsigned long pixel_rate_orig; |
1965 | |
1966 | if (!dp_ctrl) |
1967 | return -EINVAL; |
1968 | |
1969 | ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); |
1970 | |
1971 | pixel_rate = pixel_rate_orig = ctrl->panel->dp_mode.drm_mode.clock; |
1972 | |
1973 | if (dp_ctrl->wide_bus_en || ctrl->panel->dp_mode.out_fmt_is_yuv_420) |
1974 | pixel_rate >>= 1; |
1975 | |
1976 | drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n" , |
1977 | ctrl->link->link_params.rate, |
1978 | ctrl->link->link_params.num_lanes, pixel_rate); |
1979 | |
1980 | drm_dbg_dp(ctrl->drm_dev, |
1981 | "core_clk_on=%d link_clk_on=%d stream_clk_on=%d\n" , |
1982 | ctrl->core_clks_on, ctrl->link_clks_on, ctrl->stream_clks_on); |
1983 | |
1984 | if (!ctrl->link_clks_on) { /* link clk is off */ |
1985 | ret = dp_ctrl_enable_mainlink_clocks(ctrl); |
1986 | if (ret) { |
1987 | DRM_ERROR("Failed to start link clocks. ret=%d\n" , ret); |
1988 | goto end; |
1989 | } |
1990 | } |
1991 | |
1992 | ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); |
1993 | if (ret) { |
1994 | DRM_ERROR("Failed to set pixel clock rate. ret=%d\n" , ret); |
1995 | goto end; |
1996 | } |
1997 | |
1998 | if (ctrl->stream_clks_on) { |
1999 | drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n" ); |
2000 | } else { |
2001 | ret = clk_prepare_enable(ctrl->pixel_clk); |
2002 | if (ret) { |
2003 | DRM_ERROR("Failed to start pixel clocks. ret=%d\n" , ret); |
2004 | goto end; |
2005 | } |
2006 | ctrl->stream_clks_on = true; |
2007 | } |
2008 | |
2009 | if (force_link_train || !dp_ctrl_channel_eq_ok(ctrl)) |
2010 | dp_ctrl_link_retrain(ctrl); |
2011 | |
2012 | /* stop txing train pattern to end link training */ |
2013 | dp_ctrl_clear_training_pattern(ctrl); |
2014 | |
2015 | /* |
2016 | * Set up transfer unit values and set controller state to send |
2017 | * video. |
2018 | */ |
2019 | reinit_completion(x: &ctrl->video_comp); |
2020 | |
2021 | dp_ctrl_configure_source_params(ctrl); |
2022 | |
2023 | dp_catalog_ctrl_config_msa(dp_catalog: ctrl->catalog, |
2024 | rate: ctrl->link->link_params.rate, |
2025 | stream_rate_khz: pixel_rate_orig, fixed_nvid: dp_ctrl_use_fixed_nvid(ctrl), |
2026 | is_ycbcr_420: ctrl->panel->dp_mode.out_fmt_is_yuv_420); |
2027 | |
2028 | dp_ctrl_setup_tr_unit(ctrl); |
2029 | |
2030 | dp_catalog_ctrl_state_ctrl(dp_catalog: ctrl->catalog, DP_STATE_CTRL_SEND_VIDEO); |
2031 | |
2032 | ret = dp_ctrl_wait4video_ready(ctrl); |
2033 | if (ret) |
2034 | return ret; |
2035 | |
2036 | mainlink_ready = dp_catalog_ctrl_mainlink_ready(dp_catalog: ctrl->catalog); |
2037 | drm_dbg_dp(ctrl->drm_dev, |
2038 | "mainlink %s\n" , mainlink_ready ? "READY" : "NOT READY" ); |
2039 | |
2040 | end: |
2041 | return ret; |
2042 | } |
2043 | |
2044 | void dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl) |
2045 | { |
2046 | struct dp_ctrl_private *ctrl; |
2047 | struct phy *phy; |
2048 | |
2049 | ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); |
2050 | phy = ctrl->phy; |
2051 | |
2052 | dp_catalog_panel_disable_vsc_sdp(dp_catalog: ctrl->catalog); |
2053 | |
2054 | /* set dongle to D3 (power off) mode */ |
2055 | dp_link_psm_config(dp_link: ctrl->link, link_info: &ctrl->panel->link_info, enable: true); |
2056 | |
2057 | dp_catalog_ctrl_mainlink_ctrl(dp_catalog: ctrl->catalog, enable: false); |
2058 | |
2059 | if (ctrl->stream_clks_on) { |
2060 | clk_disable_unprepare(ctrl->pixel_clk); |
2061 | ctrl->stream_clks_on = false; |
2062 | } |
2063 | |
2064 | dev_pm_opp_set_rate(dev: ctrl->dev, target_freq: 0); |
2065 | dp_ctrl_link_clk_disable(dp_ctrl: &ctrl->dp_ctrl); |
2066 | |
2067 | phy_power_off(phy); |
2068 | |
2069 | /* aux channel down, reinit phy */ |
2070 | phy_exit(phy); |
2071 | phy_init(phy); |
2072 | |
2073 | drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n" , |
2074 | phy, phy->init_count, phy->power_count); |
2075 | } |
2076 | |
2077 | void dp_ctrl_off_link(struct dp_ctrl *dp_ctrl) |
2078 | { |
2079 | struct dp_ctrl_private *ctrl; |
2080 | struct phy *phy; |
2081 | |
2082 | ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); |
2083 | phy = ctrl->phy; |
2084 | |
2085 | dp_catalog_ctrl_mainlink_ctrl(dp_catalog: ctrl->catalog, enable: false); |
2086 | |
2087 | dp_ctrl_link_clk_disable(dp_ctrl: &ctrl->dp_ctrl); |
2088 | |
2089 | DRM_DEBUG_DP("Before, phy=%p init_count=%d power_on=%d\n" , |
2090 | phy, phy->init_count, phy->power_count); |
2091 | |
2092 | phy_power_off(phy); |
2093 | |
2094 | DRM_DEBUG_DP("After, phy=%p init_count=%d power_on=%d\n" , |
2095 | phy, phy->init_count, phy->power_count); |
2096 | } |
2097 | |
2098 | void dp_ctrl_off(struct dp_ctrl *dp_ctrl) |
2099 | { |
2100 | struct dp_ctrl_private *ctrl; |
2101 | struct phy *phy; |
2102 | |
2103 | ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); |
2104 | phy = ctrl->phy; |
2105 | |
2106 | dp_catalog_panel_disable_vsc_sdp(dp_catalog: ctrl->catalog); |
2107 | |
2108 | dp_catalog_ctrl_mainlink_ctrl(dp_catalog: ctrl->catalog, enable: false); |
2109 | |
2110 | dp_catalog_ctrl_reset(dp_catalog: ctrl->catalog); |
2111 | |
2112 | if (ctrl->stream_clks_on) { |
2113 | clk_disable_unprepare(ctrl->pixel_clk); |
2114 | ctrl->stream_clks_on = false; |
2115 | } |
2116 | |
2117 | dev_pm_opp_set_rate(dev: ctrl->dev, target_freq: 0); |
2118 | dp_ctrl_link_clk_disable(dp_ctrl: &ctrl->dp_ctrl); |
2119 | |
2120 | phy_power_off(phy); |
2121 | drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n" , |
2122 | phy, phy->init_count, phy->power_count); |
2123 | } |
2124 | |
2125 | irqreturn_t dp_ctrl_isr(struct dp_ctrl *dp_ctrl) |
2126 | { |
2127 | struct dp_ctrl_private *ctrl; |
2128 | u32 isr; |
2129 | irqreturn_t ret = IRQ_NONE; |
2130 | |
2131 | if (!dp_ctrl) |
2132 | return IRQ_NONE; |
2133 | |
2134 | ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); |
2135 | |
2136 | if (ctrl->panel->psr_cap.version) { |
2137 | isr = dp_catalog_ctrl_read_psr_interrupt_status(dp_catalog: ctrl->catalog); |
2138 | |
2139 | if (isr) |
2140 | complete(&ctrl->psr_op_comp); |
2141 | |
2142 | if (isr & PSR_EXIT_INT) |
2143 | drm_dbg_dp(ctrl->drm_dev, "PSR exit done\n" ); |
2144 | |
2145 | if (isr & PSR_UPDATE_INT) |
2146 | drm_dbg_dp(ctrl->drm_dev, "PSR frame update done\n" ); |
2147 | |
2148 | if (isr & PSR_CAPTURE_INT) |
2149 | drm_dbg_dp(ctrl->drm_dev, "PSR frame capture done\n" ); |
2150 | } |
2151 | |
2152 | isr = dp_catalog_ctrl_get_interrupt(dp_catalog: ctrl->catalog); |
2153 | |
2154 | |
2155 | if (isr & DP_CTRL_INTR_READY_FOR_VIDEO) { |
2156 | drm_dbg_dp(ctrl->drm_dev, "dp_video_ready\n" ); |
2157 | complete(&ctrl->video_comp); |
2158 | ret = IRQ_HANDLED; |
2159 | } |
2160 | |
2161 | if (isr & DP_CTRL_INTR_IDLE_PATTERN_SENT) { |
2162 | drm_dbg_dp(ctrl->drm_dev, "idle_patterns_sent\n" ); |
2163 | complete(&ctrl->idle_comp); |
2164 | ret = IRQ_HANDLED; |
2165 | } |
2166 | |
2167 | return ret; |
2168 | } |
2169 | |
2170 | static const char *core_clks[] = { |
2171 | "core_iface" , |
2172 | "core_aux" , |
2173 | }; |
2174 | |
2175 | static const char *ctrl_clks[] = { |
2176 | "ctrl_link" , |
2177 | "ctrl_link_iface" , |
2178 | }; |
2179 | |
2180 | static int dp_ctrl_clk_init(struct dp_ctrl *dp_ctrl) |
2181 | { |
2182 | struct dp_ctrl_private *ctrl; |
2183 | struct device *dev; |
2184 | int i, rc; |
2185 | |
2186 | ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); |
2187 | dev = ctrl->dev; |
2188 | |
2189 | ctrl->num_core_clks = ARRAY_SIZE(core_clks); |
2190 | ctrl->core_clks = devm_kcalloc(dev, ctrl->num_core_clks, sizeof(*ctrl->core_clks), GFP_KERNEL); |
2191 | if (!ctrl->core_clks) |
2192 | return -ENOMEM; |
2193 | |
2194 | for (i = 0; i < ctrl->num_core_clks; i++) |
2195 | ctrl->core_clks[i].id = core_clks[i]; |
2196 | |
2197 | rc = devm_clk_bulk_get(dev, ctrl->num_core_clks, ctrl->core_clks); |
2198 | if (rc) |
2199 | return rc; |
2200 | |
2201 | ctrl->num_link_clks = ARRAY_SIZE(ctrl_clks); |
2202 | ctrl->link_clks = devm_kcalloc(dev, ctrl->num_link_clks, sizeof(*ctrl->link_clks), GFP_KERNEL); |
2203 | if (!ctrl->link_clks) |
2204 | return -ENOMEM; |
2205 | |
2206 | for (i = 0; i < ctrl->num_link_clks; i++) |
2207 | ctrl->link_clks[i].id = ctrl_clks[i]; |
2208 | |
2209 | rc = devm_clk_bulk_get(dev, ctrl->num_link_clks, ctrl->link_clks); |
2210 | if (rc) |
2211 | return rc; |
2212 | |
2213 | ctrl->pixel_clk = devm_clk_get(dev, "stream_pixel" ); |
2214 | if (IS_ERR(ptr: ctrl->pixel_clk)) |
2215 | return PTR_ERR(ptr: ctrl->pixel_clk); |
2216 | |
2217 | return 0; |
2218 | } |
2219 | |
2220 | struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, |
2221 | struct dp_panel *panel, struct drm_dp_aux *aux, |
2222 | struct dp_catalog *catalog, |
2223 | struct phy *phy) |
2224 | { |
2225 | struct dp_ctrl_private *ctrl; |
2226 | int ret; |
2227 | |
2228 | if (!dev || !panel || !aux || |
2229 | !link || !catalog) { |
2230 | DRM_ERROR("invalid input\n" ); |
2231 | return ERR_PTR(error: -EINVAL); |
2232 | } |
2233 | |
2234 | ctrl = devm_kzalloc(dev, size: sizeof(*ctrl), GFP_KERNEL); |
2235 | if (!ctrl) { |
2236 | DRM_ERROR("Mem allocation failure\n" ); |
2237 | return ERR_PTR(error: -ENOMEM); |
2238 | } |
2239 | |
2240 | ret = devm_pm_opp_set_clkname(dev, name: "ctrl_link" ); |
2241 | if (ret) { |
2242 | dev_err(dev, "invalid DP OPP table in device tree\n" ); |
2243 | /* caller do PTR_ERR(opp_table) */ |
2244 | return (struct dp_ctrl *)ERR_PTR(error: ret); |
2245 | } |
2246 | |
2247 | /* OPP table is optional */ |
2248 | ret = devm_pm_opp_of_add_table(dev); |
2249 | if (ret) |
2250 | dev_err(dev, "failed to add DP OPP table\n" ); |
2251 | |
2252 | init_completion(x: &ctrl->idle_comp); |
2253 | init_completion(x: &ctrl->psr_op_comp); |
2254 | init_completion(x: &ctrl->video_comp); |
2255 | |
2256 | /* in parameters */ |
2257 | ctrl->panel = panel; |
2258 | ctrl->aux = aux; |
2259 | ctrl->link = link; |
2260 | ctrl->catalog = catalog; |
2261 | ctrl->dev = dev; |
2262 | ctrl->phy = phy; |
2263 | |
2264 | ret = dp_ctrl_clk_init(dp_ctrl: &ctrl->dp_ctrl); |
2265 | if (ret) { |
2266 | dev_err(dev, "failed to init clocks\n" ); |
2267 | return ERR_PTR(error: ret); |
2268 | } |
2269 | |
2270 | return &ctrl->dp_ctrl; |
2271 | } |
2272 | |