1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * Copyright (c) 2015, The Linux Foundation. All rights reserved. |
4 | */ |
5 | |
6 | #include "dsi_cfg.h" |
7 | |
8 | static const char * const dsi_v2_bus_clk_names[] = { |
9 | "core_mmss" , "iface" , "bus" , |
10 | }; |
11 | |
12 | static const struct regulator_bulk_data apq8064_dsi_regulators[] = { |
13 | { .supply = "vdda" , .init_load_uA = 100000 }, /* 1.2 V */ |
14 | { .supply = "avdd" , .init_load_uA = 10000 }, /* 3.0 V */ |
15 | { .supply = "vddio" , .init_load_uA = 100000 }, /* 1.8 V */ |
16 | }; |
17 | |
18 | static const struct msm_dsi_config apq8064_dsi_cfg = { |
19 | .io_offset = 0, |
20 | .regulator_data = apq8064_dsi_regulators, |
21 | .num_regulators = ARRAY_SIZE(apq8064_dsi_regulators), |
22 | .bus_clk_names = dsi_v2_bus_clk_names, |
23 | .num_bus_clks = ARRAY_SIZE(dsi_v2_bus_clk_names), |
24 | .io_start = { |
25 | { 0x4700000, 0x5800000 }, |
26 | }, |
27 | }; |
28 | |
29 | static const char * const dsi_6g_bus_clk_names[] = { |
30 | "mdp_core" , "iface" , "bus" , "core_mmss" , |
31 | }; |
32 | |
33 | static const struct regulator_bulk_data msm8974_apq8084_regulators[] = { |
34 | { .supply = "vdd" , .init_load_uA = 150000 }, /* 3.0 V */ |
35 | { .supply = "vdda" , .init_load_uA = 100000 }, /* 1.2 V */ |
36 | { .supply = "vddio" , .init_load_uA = 100000 }, /* 1.8 V */ |
37 | }; |
38 | |
39 | static const struct msm_dsi_config msm8974_apq8084_dsi_cfg = { |
40 | .io_offset = DSI_6G_REG_SHIFT, |
41 | .regulator_data = msm8974_apq8084_regulators, |
42 | .num_regulators = ARRAY_SIZE(msm8974_apq8084_regulators), |
43 | .bus_clk_names = dsi_6g_bus_clk_names, |
44 | .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names), |
45 | .io_start = { |
46 | { 0xfd922800, 0xfd922b00 }, |
47 | }, |
48 | }; |
49 | |
50 | static const char * const dsi_v1_3_1_clk_names[] = { |
51 | "mdp_core" , "iface" , "bus" , |
52 | }; |
53 | |
54 | static const struct regulator_bulk_data dsi_v1_3_1_regulators[] = { |
55 | { .supply = "vdda" , .init_load_uA = 100000 }, /* 1.2 V */ |
56 | { .supply = "vddio" , .init_load_uA = 100000 }, /* 1.8 V */ |
57 | }; |
58 | |
59 | static const struct msm_dsi_config msm8916_dsi_cfg = { |
60 | .io_offset = DSI_6G_REG_SHIFT, |
61 | .regulator_data = dsi_v1_3_1_regulators, |
62 | .num_regulators = ARRAY_SIZE(dsi_v1_3_1_regulators), |
63 | .bus_clk_names = dsi_v1_3_1_clk_names, |
64 | .num_bus_clks = ARRAY_SIZE(dsi_v1_3_1_clk_names), |
65 | .io_start = { |
66 | { 0x1a98000 }, |
67 | }, |
68 | }; |
69 | |
70 | static const struct msm_dsi_config msm8976_dsi_cfg = { |
71 | .io_offset = DSI_6G_REG_SHIFT, |
72 | .regulator_data = dsi_v1_3_1_regulators, |
73 | .num_regulators = ARRAY_SIZE(dsi_v1_3_1_regulators), |
74 | .bus_clk_names = dsi_v1_3_1_clk_names, |
75 | .num_bus_clks = ARRAY_SIZE(dsi_v1_3_1_clk_names), |
76 | .io_start = { |
77 | { 0x1a94000, 0x1a96000 }, |
78 | }, |
79 | }; |
80 | |
81 | static const struct regulator_bulk_data msm8994_dsi_regulators[] = { |
82 | { .supply = "vdda" , .init_load_uA = 100000 }, /* 1.25 V */ |
83 | { .supply = "vddio" , .init_load_uA = 100000 }, /* 1.8 V */ |
84 | { .supply = "vcca" , .init_load_uA = 10000 }, /* 1.0 V */ |
85 | { .supply = "vdd" , .init_load_uA = 100000 }, /* 1.8 V */ |
86 | { .supply = "lab_reg" , .init_load_uA = -1 }, |
87 | { .supply = "ibb_reg" , .init_load_uA = -1 }, |
88 | }; |
89 | |
90 | static const struct msm_dsi_config msm8994_dsi_cfg = { |
91 | .io_offset = DSI_6G_REG_SHIFT, |
92 | .regulator_data = msm8994_dsi_regulators, |
93 | .num_regulators = ARRAY_SIZE(msm8994_dsi_regulators), |
94 | .bus_clk_names = dsi_6g_bus_clk_names, |
95 | .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names), |
96 | .io_start = { |
97 | { 0xfd998000, 0xfd9a0000 }, |
98 | }, |
99 | }; |
100 | |
101 | static const struct regulator_bulk_data msm8996_dsi_regulators[] = { |
102 | { .supply = "vdda" , .init_load_uA = 18160 }, /* 1.25 V */ |
103 | { .supply = "vcca" , .init_load_uA = 17000 }, /* 0.925 V */ |
104 | { .supply = "vddio" , .init_load_uA = 100000 }, /* 1.8 V */ |
105 | }; |
106 | |
107 | static const struct msm_dsi_config msm8996_dsi_cfg = { |
108 | .io_offset = DSI_6G_REG_SHIFT, |
109 | .regulator_data = msm8996_dsi_regulators, |
110 | .num_regulators = ARRAY_SIZE(msm8996_dsi_regulators), |
111 | .bus_clk_names = dsi_6g_bus_clk_names, |
112 | .num_bus_clks = ARRAY_SIZE(dsi_6g_bus_clk_names), |
113 | .io_start = { |
114 | { 0x994000, 0x996000 }, |
115 | }, |
116 | }; |
117 | |
118 | static const char * const dsi_msm8998_bus_clk_names[] = { |
119 | "iface" , "bus" , "core" , |
120 | }; |
121 | |
122 | static const struct regulator_bulk_data msm8998_dsi_regulators[] = { |
123 | { .supply = "vdd" , .init_load_uA = 367000 }, /* 0.9 V */ |
124 | { .supply = "vdda" , .init_load_uA = 62800 }, /* 1.2 V */ |
125 | }; |
126 | |
127 | static const struct msm_dsi_config msm8998_dsi_cfg = { |
128 | .io_offset = DSI_6G_REG_SHIFT, |
129 | .regulator_data = msm8998_dsi_regulators, |
130 | .num_regulators = ARRAY_SIZE(msm8998_dsi_regulators), |
131 | .bus_clk_names = dsi_msm8998_bus_clk_names, |
132 | .num_bus_clks = ARRAY_SIZE(dsi_msm8998_bus_clk_names), |
133 | .io_start = { |
134 | { 0xc994000, 0xc996000 }, |
135 | }, |
136 | }; |
137 | |
138 | static const char * const dsi_sdm660_bus_clk_names[] = { |
139 | "iface" , "bus" , "core" , "core_mmss" , |
140 | }; |
141 | |
142 | static const struct regulator_bulk_data sdm660_dsi_regulators[] = { |
143 | { .supply = "vdda" , .init_load_uA = 12560 }, /* 1.2 V */ |
144 | }; |
145 | |
146 | static const struct msm_dsi_config sdm660_dsi_cfg = { |
147 | .io_offset = DSI_6G_REG_SHIFT, |
148 | .regulator_data = sdm660_dsi_regulators, |
149 | .num_regulators = ARRAY_SIZE(sdm660_dsi_regulators), |
150 | .bus_clk_names = dsi_sdm660_bus_clk_names, |
151 | .num_bus_clks = ARRAY_SIZE(dsi_sdm660_bus_clk_names), |
152 | .io_start = { |
153 | { 0xc994000, 0xc996000 }, |
154 | }, |
155 | }; |
156 | |
157 | static const char * const dsi_v2_4_clk_names[] = { |
158 | "iface" , "bus" , |
159 | }; |
160 | |
161 | static const struct regulator_bulk_data dsi_v2_4_regulators[] = { |
162 | { .supply = "vdda" , .init_load_uA = 21800 }, /* 1.2 V */ |
163 | { .supply = "refgen" }, |
164 | }; |
165 | |
166 | static const struct msm_dsi_config sdm845_dsi_cfg = { |
167 | .io_offset = DSI_6G_REG_SHIFT, |
168 | .regulator_data = dsi_v2_4_regulators, |
169 | .num_regulators = ARRAY_SIZE(dsi_v2_4_regulators), |
170 | .bus_clk_names = dsi_v2_4_clk_names, |
171 | .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names), |
172 | .io_start = { |
173 | { 0xae94000, 0xae96000 }, /* SDM845 / SDM670 */ |
174 | { 0x5e94000 }, /* QCM2290 / SM6115 / SM6125 / SM6375 */ |
175 | }, |
176 | }; |
177 | |
178 | static const struct regulator_bulk_data sm8550_dsi_regulators[] = { |
179 | { .supply = "vdda" , .init_load_uA = 16800 }, /* 1.2 V */ |
180 | }; |
181 | |
182 | static const struct msm_dsi_config sm8550_dsi_cfg = { |
183 | .io_offset = DSI_6G_REG_SHIFT, |
184 | .regulator_data = sm8550_dsi_regulators, |
185 | .num_regulators = ARRAY_SIZE(sm8550_dsi_regulators), |
186 | .bus_clk_names = dsi_v2_4_clk_names, |
187 | .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names), |
188 | .io_start = { |
189 | { 0xae94000, 0xae96000 }, |
190 | }, |
191 | }; |
192 | |
193 | static const struct regulator_bulk_data sm8650_dsi_regulators[] = { |
194 | { .supply = "vdda" , .init_load_uA = 16600 }, /* 1.2 V */ |
195 | }; |
196 | |
197 | static const struct msm_dsi_config sm8650_dsi_cfg = { |
198 | .io_offset = DSI_6G_REG_SHIFT, |
199 | .regulator_data = sm8650_dsi_regulators, |
200 | .num_regulators = ARRAY_SIZE(sm8650_dsi_regulators), |
201 | .bus_clk_names = dsi_v2_4_clk_names, |
202 | .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names), |
203 | .io_start = { |
204 | { 0xae94000, 0xae96000 }, |
205 | }, |
206 | }; |
207 | |
208 | static const struct regulator_bulk_data sc7280_dsi_regulators[] = { |
209 | { .supply = "vdda" , .init_load_uA = 8350 }, /* 1.2 V */ |
210 | { .supply = "refgen" }, |
211 | }; |
212 | |
213 | static const struct msm_dsi_config sc7280_dsi_cfg = { |
214 | .io_offset = DSI_6G_REG_SHIFT, |
215 | .regulator_data = sc7280_dsi_regulators, |
216 | .num_regulators = ARRAY_SIZE(sc7280_dsi_regulators), |
217 | .bus_clk_names = dsi_v2_4_clk_names, |
218 | .num_bus_clks = ARRAY_SIZE(dsi_v2_4_clk_names), |
219 | .io_start = { |
220 | { 0xae94000, 0xae96000 }, |
221 | }, |
222 | }; |
223 | |
224 | static const struct msm_dsi_host_cfg_ops msm_dsi_v2_host_ops = { |
225 | .link_clk_set_rate = dsi_link_clk_set_rate_v2, |
226 | .link_clk_enable = dsi_link_clk_enable_v2, |
227 | .link_clk_disable = dsi_link_clk_disable_v2, |
228 | .clk_init_ver = dsi_clk_init_v2, |
229 | .tx_buf_alloc = dsi_tx_buf_alloc_v2, |
230 | .tx_buf_get = dsi_tx_buf_get_v2, |
231 | .tx_buf_put = NULL, |
232 | .dma_base_get = dsi_dma_base_get_v2, |
233 | .calc_clk_rate = dsi_calc_clk_rate_v2, |
234 | }; |
235 | |
236 | static const struct msm_dsi_host_cfg_ops msm_dsi_6g_host_ops = { |
237 | .link_clk_set_rate = dsi_link_clk_set_rate_6g, |
238 | .link_clk_enable = dsi_link_clk_enable_6g, |
239 | .link_clk_disable = dsi_link_clk_disable_6g, |
240 | .clk_init_ver = NULL, |
241 | .tx_buf_alloc = dsi_tx_buf_alloc_6g, |
242 | .tx_buf_get = dsi_tx_buf_get_6g, |
243 | .tx_buf_put = dsi_tx_buf_put_6g, |
244 | .dma_base_get = dsi_dma_base_get_6g, |
245 | .calc_clk_rate = dsi_calc_clk_rate_6g, |
246 | }; |
247 | |
248 | static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_host_ops = { |
249 | .link_clk_set_rate = dsi_link_clk_set_rate_6g, |
250 | .link_clk_enable = dsi_link_clk_enable_6g, |
251 | .link_clk_disable = dsi_link_clk_disable_6g, |
252 | .clk_init_ver = dsi_clk_init_6g_v2, |
253 | .tx_buf_alloc = dsi_tx_buf_alloc_6g, |
254 | .tx_buf_get = dsi_tx_buf_get_6g, |
255 | .tx_buf_put = dsi_tx_buf_put_6g, |
256 | .dma_base_get = dsi_dma_base_get_6g, |
257 | .calc_clk_rate = dsi_calc_clk_rate_6g, |
258 | }; |
259 | |
260 | static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { |
261 | {MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064, |
262 | &apq8064_dsi_cfg, &msm_dsi_v2_host_ops}, |
263 | {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0, |
264 | &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops}, |
265 | {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0_2, |
266 | &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops}, |
267 | {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1, |
268 | &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops}, |
269 | {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1_1, |
270 | &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops}, |
271 | {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_2, |
272 | &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops}, |
273 | {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3, |
274 | &msm8994_dsi_cfg, &msm_dsi_6g_host_ops}, |
275 | {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3_1, |
276 | &msm8916_dsi_cfg, &msm_dsi_6g_host_ops}, |
277 | {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_1, |
278 | &msm8996_dsi_cfg, &msm_dsi_6g_host_ops}, |
279 | {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_2, |
280 | &msm8976_dsi_cfg, &msm_dsi_6g_host_ops}, |
281 | {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_1_0, |
282 | &sdm660_dsi_cfg, &msm_dsi_6g_v2_host_ops}, |
283 | {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_0, |
284 | &msm8998_dsi_cfg, &msm_dsi_6g_v2_host_ops}, |
285 | {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1, |
286 | &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, |
287 | {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_0, |
288 | &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, |
289 | {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_0, |
290 | &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, |
291 | {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_1, |
292 | &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, |
293 | {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_5_0, |
294 | &sc7280_dsi_cfg, &msm_dsi_6g_v2_host_ops}, |
295 | {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_6_0, |
296 | &sdm845_dsi_cfg, &msm_dsi_6g_v2_host_ops}, |
297 | {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_7_0, |
298 | &sm8550_dsi_cfg, &msm_dsi_6g_v2_host_ops}, |
299 | {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_8_0, |
300 | &sm8650_dsi_cfg, &msm_dsi_6g_v2_host_ops}, |
301 | }; |
302 | |
303 | const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor) |
304 | { |
305 | const struct msm_dsi_cfg_handler *cfg_hnd = NULL; |
306 | int i; |
307 | |
308 | for (i = ARRAY_SIZE(dsi_cfg_handlers) - 1; i >= 0; i--) { |
309 | if ((dsi_cfg_handlers[i].major == major) && |
310 | (dsi_cfg_handlers[i].minor == minor)) { |
311 | cfg_hnd = &dsi_cfg_handlers[i]; |
312 | break; |
313 | } |
314 | } |
315 | |
316 | return cfg_hnd; |
317 | } |
318 | |