| 1 | // SPDX-License-Identifier: MIT |
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| 2 | #include <drm/drm_mode.h> |
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| 3 | #include "nouveau_drv.h" |
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| 4 | #include "nouveau_reg.h" |
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| 5 | #include "nouveau_crtc.h" |
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| 6 | #include "hw.h" |
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| 7 | |
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| 8 | static void |
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| 9 | nv04_cursor_show(struct nouveau_crtc *nv_crtc, bool update) |
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| 10 | { |
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| 11 | nv_show_cursor(dev: nv_crtc->base.dev, head: nv_crtc->index, show: true); |
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| 12 | } |
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| 13 | |
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| 14 | static void |
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| 15 | nv04_cursor_hide(struct nouveau_crtc *nv_crtc, bool update) |
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| 16 | { |
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| 17 | nv_show_cursor(dev: nv_crtc->base.dev, head: nv_crtc->index, show: false); |
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| 18 | } |
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| 19 | |
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| 20 | static void |
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| 21 | nv04_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y) |
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| 22 | { |
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| 23 | nv_crtc->cursor_saved_x = x; nv_crtc->cursor_saved_y = y; |
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| 24 | NVWriteRAMDAC(dev: nv_crtc->base.dev, head: nv_crtc->index, |
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| 25 | NV_PRAMDAC_CU_START_POS, |
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| 26 | XLATE(y, 0, NV_PRAMDAC_CU_START_POS_Y) | |
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| 27 | XLATE(x, 0, NV_PRAMDAC_CU_START_POS_X)); |
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| 28 | } |
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| 29 | |
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| 30 | static void |
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| 31 | crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) |
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| 32 | { |
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| 33 | NVWriteVgaCrtc(dev: crtc->dev, head: nouveau_crtc(crtc)->index, index, |
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| 34 | value: crtcstate->CRTC[index]); |
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| 35 | } |
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| 36 | |
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| 37 | static void |
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| 38 | nv04_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) |
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| 39 | { |
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| 40 | struct drm_device *dev = nv_crtc->base.dev; |
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| 41 | struct nouveau_drm *drm = nouveau_drm(dev); |
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| 42 | struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; |
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| 43 | struct drm_crtc *crtc = &nv_crtc->base; |
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| 44 | |
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| 45 | regp->CRTC[NV_CIO_CRE_HCUR_ADDR0_INDEX] = |
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| 46 | MASK(NV_CIO_CRE_HCUR_ASI) | |
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| 47 | XLATE(offset, 17, NV_CIO_CRE_HCUR_ADDR0_ADR); |
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| 48 | regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] = |
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| 49 | XLATE(offset, 11, NV_CIO_CRE_HCUR_ADDR1_ADR); |
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| 50 | if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) |
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| 51 | regp->CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX] |= |
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| 52 | MASK(NV_CIO_CRE_HCUR_ADDR1_CUR_DBL); |
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| 53 | regp->CRTC[NV_CIO_CRE_HCUR_ADDR2_INDEX] = offset >> 24; |
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| 54 | |
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| 55 | crtc_wr_cio_state(crtc, crtcstate: regp, NV_CIO_CRE_HCUR_ADDR0_INDEX); |
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| 56 | crtc_wr_cio_state(crtc, crtcstate: regp, NV_CIO_CRE_HCUR_ADDR1_INDEX); |
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| 57 | crtc_wr_cio_state(crtc, crtcstate: regp, NV_CIO_CRE_HCUR_ADDR2_INDEX); |
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| 58 | if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) |
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| 59 | nv_fix_nv40_hw_cursor(dev, head: nv_crtc->index); |
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| 60 | } |
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| 61 | |
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| 62 | int |
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| 63 | nv04_cursor_init(struct nouveau_crtc *crtc) |
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| 64 | { |
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| 65 | crtc->cursor.set_offset = nv04_cursor_set_offset; |
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| 66 | crtc->cursor.set_pos = nv04_cursor_set_pos; |
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| 67 | crtc->cursor.hide = nv04_cursor_hide; |
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| 68 | crtc->cursor.show = nv04_cursor_show; |
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| 69 | return 0; |
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| 70 | } |
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| 71 | |
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