1/*
2 * Copyright 2018 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22#include "base.h"
23
24#include <nvif/push507c.h>
25
26#include <nvhw/class/cl907c.h>
27
28static int
29base907c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
30{
31 struct nvif_push *push = wndw->wndw.push;
32 int ret;
33
34 if ((ret = PUSH_WAIT(push, 10)))
35 return ret;
36
37 PUSH_MTHD(push, NV907C, SET_PRESENT_CONTROL,
38 NVVAL(NV907C, SET_PRESENT_CONTROL, BEGIN_MODE, asyw->image.mode) |
39 NVDEF(NV907C, SET_PRESENT_CONTROL, TIMESTAMP_MODE, DISABLE) |
40 NVVAL(NV907C, SET_PRESENT_CONTROL, MIN_PRESENT_INTERVAL, asyw->image.interval));
41
42 PUSH_MTHD(push, NV907C, SET_CONTEXT_DMAS_ISO(0), asyw->image.handle, 1);
43
44 PUSH_MTHD(push, NV907C, SURFACE_SET_OFFSET(0, 0), asyw->image.offset[0] >> 8,
45 SURFACE_SET_OFFSET(0, 1), 0x00000000,
46
47 SURFACE_SET_SIZE(0),
48 NVVAL(NV907C, SURFACE_SET_SIZE, WIDTH, asyw->image.w) |
49 NVVAL(NV907C, SURFACE_SET_SIZE, HEIGHT, asyw->image.h),
50
51 SURFACE_SET_STORAGE(0),
52 NVVAL(NV907C, SURFACE_SET_STORAGE, BLOCK_HEIGHT, asyw->image.blockh) |
53 NVVAL(NV907C, SURFACE_SET_STORAGE, PITCH, asyw->image.pitch[0] >> 8) |
54 NVVAL(NV907C, SURFACE_SET_STORAGE, PITCH, asyw->image.blocks[0]) |
55 NVVAL(NV907C, SURFACE_SET_STORAGE, MEMORY_LAYOUT, asyw->image.layout),
56
57 SURFACE_SET_PARAMS(0),
58 NVVAL(NV907C, SURFACE_SET_PARAMS, FORMAT, asyw->image.format) |
59 NVDEF(NV907C, SURFACE_SET_PARAMS, SUPER_SAMPLE, X1_AA) |
60 NVDEF(NV907C, SURFACE_SET_PARAMS, GAMMA, LINEAR) |
61 NVDEF(NV907C, SURFACE_SET_PARAMS, LAYOUT, FRM));
62 return 0;
63}
64
65static int
66base907c_xlut_clr(struct nv50_wndw *wndw)
67{
68 struct nvif_push *push = wndw->wndw.push;
69 int ret;
70
71 if ((ret = PUSH_WAIT(push, 6)))
72 return ret;
73
74 PUSH_MTHD(push, NV907C, SET_BASE_LUT_LO,
75 NVDEF(NV907C, SET_BASE_LUT_LO, ENABLE, DISABLE));
76
77 PUSH_MTHD(push, NV907C, SET_OUTPUT_LUT_LO,
78 NVDEF(NV907C, SET_OUTPUT_LUT_LO, ENABLE, DISABLE));
79
80 PUSH_MTHD(push, NV907C, SET_CONTEXT_DMA_LUT, 0x00000000);
81 return 0;
82}
83
84static int
85base907c_xlut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
86{
87 struct nvif_push *push = wndw->wndw.push;
88 int ret;
89
90 if ((ret = PUSH_WAIT(push, 6)))
91 return ret;
92
93 PUSH_MTHD(push, NV907C, SET_BASE_LUT_LO,
94 NVVAL(NV907C, SET_BASE_LUT_LO, ENABLE, asyw->xlut.i.enable) |
95 NVVAL(NV907C, SET_BASE_LUT_LO, MODE, asyw->xlut.i.mode),
96
97 SET_BASE_LUT_HI, asyw->xlut.i.offset >> 8,
98
99 SET_OUTPUT_LUT_LO,
100 NVDEF(NV907C, SET_OUTPUT_LUT_LO, ENABLE, USE_CORE_LUT));
101
102 PUSH_MTHD(push, NV907C, SET_CONTEXT_DMA_LUT, asyw->xlut.handle);
103 return 0;
104}
105
106static void
107base907c_ilut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, int size)
108{
109 if (size == 1024)
110 asyw->xlut.i.mode = NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE;
111 else
112 asyw->xlut.i.mode = NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE;
113
114 asyw->xlut.i.enable = NV907C_SET_BASE_LUT_LO_ENABLE_ENABLE;
115 asyw->xlut.i.load = head907d_olut_load;
116}
117
118static inline u32
119csc_drm_to_base(u64 in)
120{
121 /* base takes a 19-bit 2's complement value in S3.16 format */
122 bool sign = in & BIT_ULL(63);
123 u32 integer = (in >> 32) & 0x7fffffff;
124 u32 fraction = in & 0xffffffff;
125
126 if (integer >= 4) {
127 return (1 << 18) - (sign ? 0 : 1);
128 } else {
129 u32 ret = (integer << 16) | (fraction >> 16);
130 if (sign)
131 ret = -ret;
132 return ret & GENMASK(18, 0);
133 }
134}
135
136void
137base907c_csc(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
138 const struct drm_color_ctm *ctm)
139{
140 int i, j;
141
142 for (j = 0; j < 3; j++) {
143 for (i = 0; i < 4; i++) {
144 u32 *val = &asyw->csc.matrix[j * 4 + i];
145 /* DRM does not support constant offset, while
146 * HW CSC does. Skip it. */
147 if (i == 3) {
148 *val = 0;
149 } else {
150 *val = csc_drm_to_base(in: ctm->matrix[j * 3 + i]);
151 }
152 }
153 }
154}
155
156static int
157base907c_csc_clr(struct nv50_wndw *wndw)
158{
159 struct nvif_push *push = wndw->wndw.push;
160 int ret;
161
162 if ((ret = PUSH_WAIT(push, 2)))
163 return ret;
164
165 PUSH_MTHD(push, NV907C, SET_CSC_RED2RED,
166 NVDEF(NV907C, SET_CSC_RED2RED, OWNER, CORE));
167 return 0;
168}
169
170static int
171base907c_csc_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
172{
173 struct nvif_push *push = wndw->wndw.push;
174 int ret;
175
176 if ((ret = PUSH_WAIT(push, 13)))
177 return ret;
178
179 PUSH_MTHD(push, NV907C, SET_CSC_RED2RED,
180 NVDEF(NV907C, SET_CSC_RED2RED, OWNER, BASE) |
181 NVVAL(NV907C, SET_CSC_RED2RED, COEFF, asyw->csc.matrix[0]),
182
183 SET_CSC_GRN2RED, &asyw->csc.matrix[1], 11);
184 return 0;
185}
186
187const struct nv50_wndw_func
188base907c = {
189 .acquire = base507c_acquire,
190 .release = base507c_release,
191 .sema_set = base507c_sema_set,
192 .sema_clr = base507c_sema_clr,
193 .ntfy_reset = base507c_ntfy_reset,
194 .ntfy_set = base507c_ntfy_set,
195 .ntfy_clr = base507c_ntfy_clr,
196 .ntfy_wait_begun = base507c_ntfy_wait_begun,
197 .ilut = base907c_ilut,
198 .csc = base907c_csc,
199 .csc_set = base907c_csc_set,
200 .csc_clr = base907c_csc_clr,
201 .olut_core = true,
202 .ilut_size = 1024,
203 .xlut_set = base907c_xlut_set,
204 .xlut_clr = base907c_xlut_clr,
205 .image_set = base907c_image_set,
206 .image_clr = base507c_image_clr,
207 .update = base507c_update,
208};
209
210int
211base907c_new(struct nouveau_drm *drm, int head, s32 oclass,
212 struct nv50_wndw **pwndw)
213{
214 return base507c_new_(&base907c, format: base507c_format, drm, head, oclass,
215 interlock_data: 0x00000002 << (head * 4), pwndw);
216}
217

source code of linux/drivers/gpu/drm/nouveau/dispnv50/base907c.c