1 | /* SPDX-License-Identifier: MIT */ |
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2 | #ifndef __NOUVEAU_ABI16_H__ |
3 | #define __NOUVEAU_ABI16_H__ |
4 | |
5 | #define ABI16_IOCTL_ARGS \ |
6 | struct drm_device *dev, void *data, struct drm_file *file_priv |
7 | |
8 | int nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS); |
9 | int nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS); |
10 | int nouveau_abi16_ioctl_channel_free(ABI16_IOCTL_ARGS); |
11 | int nouveau_abi16_ioctl_grobj_alloc(ABI16_IOCTL_ARGS); |
12 | int nouveau_abi16_ioctl_notifierobj_alloc(ABI16_IOCTL_ARGS); |
13 | int nouveau_abi16_ioctl_gpuobj_free(ABI16_IOCTL_ARGS); |
14 | |
15 | struct nouveau_abi16_ntfy { |
16 | struct nvif_object object; |
17 | struct list_head head; |
18 | struct nvkm_mm_node *node; |
19 | }; |
20 | |
21 | struct nouveau_abi16_chan { |
22 | struct list_head head; |
23 | struct nouveau_channel *chan; |
24 | struct nvif_object ce; |
25 | struct list_head notifiers; |
26 | struct nouveau_bo *ntfy; |
27 | struct nouveau_vma *ntfy_vma; |
28 | struct nvkm_mm heap; |
29 | struct nouveau_sched_entity sched_entity; |
30 | }; |
31 | |
32 | struct nouveau_abi16 { |
33 | struct nvif_device device; |
34 | struct list_head channels; |
35 | u64 handles; |
36 | }; |
37 | |
38 | struct nouveau_abi16 *nouveau_abi16_get(struct drm_file *); |
39 | int nouveau_abi16_put(struct nouveau_abi16 *, int); |
40 | void nouveau_abi16_fini(struct nouveau_abi16 *); |
41 | s32 nouveau_abi16_swclass(struct nouveau_drm *); |
42 | int nouveau_abi16_usif(struct drm_file *, void *data, u32 size); |
43 | |
44 | #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1) |
45 | #define NOUVEAU_GEM_DOMAIN_GART (1 << 2) |
46 | |
47 | struct drm_nouveau_grobj_alloc { |
48 | int channel; |
49 | uint32_t handle; |
50 | int class; |
51 | }; |
52 | |
53 | struct drm_nouveau_notifierobj_alloc { |
54 | uint32_t channel; |
55 | uint32_t handle; |
56 | uint32_t size; |
57 | uint32_t offset; |
58 | }; |
59 | |
60 | struct drm_nouveau_gpuobj_free { |
61 | int channel; |
62 | uint32_t handle; |
63 | }; |
64 | |
65 | struct drm_nouveau_setparam { |
66 | uint64_t param; |
67 | uint64_t value; |
68 | }; |
69 | |
70 | #define DRM_IOCTL_NOUVEAU_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SETPARAM, struct drm_nouveau_setparam) |
71 | #define DRM_IOCTL_NOUVEAU_GROBJ_ALLOC DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GROBJ_ALLOC, struct drm_nouveau_grobj_alloc) |
72 | #define DRM_IOCTL_NOUVEAU_NOTIFIEROBJ_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_NOTIFIEROBJ_ALLOC, struct drm_nouveau_notifierobj_alloc) |
73 | #define DRM_IOCTL_NOUVEAU_GPUOBJ_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GPUOBJ_FREE, struct drm_nouveau_gpuobj_free) |
74 | |
75 | #endif |
76 |