| 1 | /* SPDX-License-Identifier: MIT */ |
|---|---|
| 2 | |
| 3 | /* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */ |
| 4 | |
| 5 | #ifndef __NVRM_BAR_H__ |
| 6 | #define __NVRM_BAR_H__ |
| 7 | #include <nvrm/nvtypes.h> |
| 8 | |
| 9 | /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */ |
| 10 | |
| 11 | typedef enum |
| 12 | { |
| 13 | NV_RPC_UPDATE_PDE_BAR_1, |
| 14 | NV_RPC_UPDATE_PDE_BAR_2, |
| 15 | NV_RPC_UPDATE_PDE_BAR_INVALID, |
| 16 | } NV_RPC_UPDATE_PDE_BAR_TYPE; |
| 17 | |
| 18 | typedef struct UpdateBarPde_v15_00 |
| 19 | { |
| 20 | NV_RPC_UPDATE_PDE_BAR_TYPE barType; |
| 21 | NvU64 entryValue NV_ALIGN_BYTES(8); |
| 22 | NvU64 entryLevelShift NV_ALIGN_BYTES(8); |
| 23 | } UpdateBarPde_v15_00; |
| 24 | |
| 25 | typedef struct rpc_update_bar_pde_v15_00 |
| 26 | { |
| 27 | UpdateBarPde_v15_00 info; |
| 28 | } rpc_update_bar_pde_v15_00; |
| 29 | #endif |
| 30 |