| 1 | /* SPDX-License-Identifier: MIT */ |
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| 2 | |
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| 3 | /* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. */ |
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| 4 | |
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| 5 | #ifndef __NVRM_NVENC_H__ |
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| 6 | #define __NVRM_NVENC_H__ |
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| 7 | #include <nvrm/nvtypes.h> |
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| 8 | |
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| 9 | /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */ |
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| 10 | |
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| 11 | typedef struct |
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| 12 | { |
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| 13 | NvU32 size; |
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| 14 | NvU32 prohibitMultipleInstances; // Prohibit multiple allocations of MSENC? |
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| 15 | NvU32 engineInstance; // Select MSENC/NVENC0 or NVENC1 or NVENC2 |
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| 16 | } NV_MSENC_ALLOCATION_PARAMETERS; |
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| 17 | #endif |
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| 18 | |
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