1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) STMicroelectronics SA 2017
4 *
5 * Authors: Philippe Cornu <philippe.cornu@st.com>
6 * Yannick Fertre <yannick.fertre@st.com>
7 */
8
9#include <linux/backlight.h>
10#include <linux/delay.h>
11#include <linux/gpio/consumer.h>
12#include <linux/mod_devicetable.h>
13#include <linux/module.h>
14#include <linux/regulator/consumer.h>
15
16#include <video/mipi_display.h>
17
18#include <drm/drm_mipi_dsi.h>
19#include <drm/drm_modes.h>
20#include <drm/drm_panel.h>
21
22#define OTM8009A_BACKLIGHT_DEFAULT 240
23#define OTM8009A_BACKLIGHT_MAX 255
24
25/* Manufacturer Command Set */
26#define MCS_ADRSFT 0x0000 /* Address Shift Function */
27#define MCS_PANSET 0xB3A6 /* Panel Type Setting */
28#define MCS_SD_CTRL 0xC0A2 /* Source Driver Timing Setting */
29#define MCS_P_DRV_M 0xC0B4 /* Panel Driving Mode */
30#define MCS_OSC_ADJ 0xC181 /* Oscillator Adjustment for Idle/Normal mode */
31#define MCS_RGB_VID_SET 0xC1A1 /* RGB Video Mode Setting */
32#define MCS_SD_PCH_CTRL 0xC480 /* Source Driver Precharge Control */
33#define MCS_NO_DOC1 0xC48A /* Command not documented */
34#define MCS_PWR_CTRL1 0xC580 /* Power Control Setting 1 */
35#define MCS_PWR_CTRL2 0xC590 /* Power Control Setting 2 for Normal Mode */
36#define MCS_PWR_CTRL4 0xC5B0 /* Power Control Setting 4 for DC Voltage */
37#define MCS_PANCTRLSET1 0xCB80 /* Panel Control Setting 1 */
38#define MCS_PANCTRLSET2 0xCB90 /* Panel Control Setting 2 */
39#define MCS_PANCTRLSET3 0xCBA0 /* Panel Control Setting 3 */
40#define MCS_PANCTRLSET4 0xCBB0 /* Panel Control Setting 4 */
41#define MCS_PANCTRLSET5 0xCBC0 /* Panel Control Setting 5 */
42#define MCS_PANCTRLSET6 0xCBD0 /* Panel Control Setting 6 */
43#define MCS_PANCTRLSET7 0xCBE0 /* Panel Control Setting 7 */
44#define MCS_PANCTRLSET8 0xCBF0 /* Panel Control Setting 8 */
45#define MCS_PANU2D1 0xCC80 /* Panel U2D Setting 1 */
46#define MCS_PANU2D2 0xCC90 /* Panel U2D Setting 2 */
47#define MCS_PANU2D3 0xCCA0 /* Panel U2D Setting 3 */
48#define MCS_PAND2U1 0xCCB0 /* Panel D2U Setting 1 */
49#define MCS_PAND2U2 0xCCC0 /* Panel D2U Setting 2 */
50#define MCS_PAND2U3 0xCCD0 /* Panel D2U Setting 3 */
51#define MCS_GOAVST 0xCE80 /* GOA VST Setting */
52#define MCS_GOACLKA1 0xCEA0 /* GOA CLKA1 Setting */
53#define MCS_GOACLKA3 0xCEB0 /* GOA CLKA3 Setting */
54#define MCS_GOAECLK 0xCFC0 /* GOA ECLK Setting */
55#define MCS_NO_DOC2 0xCFD0 /* Command not documented */
56#define MCS_GVDDSET 0xD800 /* GVDD/NGVDD */
57#define MCS_VCOMDC 0xD900 /* VCOM Voltage Setting */
58#define MCS_GMCT2_2P 0xE100 /* Gamma Correction 2.2+ Setting */
59#define MCS_GMCT2_2N 0xE200 /* Gamma Correction 2.2- Setting */
60#define MCS_NO_DOC3 0xF5B6 /* Command not documented */
61#define MCS_CMD2_ENA1 0xFF00 /* Enable Access Command2 "CMD2" */
62#define MCS_CMD2_ENA2 0xFF80 /* Enable Access Orise Command2 */
63
64#define OTM8009A_HDISPLAY 480
65#define OTM8009A_VDISPLAY 800
66
67struct otm8009a {
68 struct device *dev;
69 struct drm_panel panel;
70 struct backlight_device *bl_dev;
71 struct gpio_desc *reset_gpio;
72 struct regulator *supply;
73 bool prepared;
74};
75
76static const struct drm_display_mode modes[] = {
77 { /* 50 Hz, preferred */
78 .clock = 29700,
79 .hdisplay = 480,
80 .hsync_start = 480 + 98,
81 .hsync_end = 480 + 98 + 32,
82 .htotal = 480 + 98 + 32 + 98,
83 .vdisplay = 800,
84 .vsync_start = 800 + 15,
85 .vsync_end = 800 + 15 + 10,
86 .vtotal = 800 + 15 + 10 + 14,
87 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
88 .width_mm = 52,
89 .height_mm = 86,
90 },
91 { /* 60 Hz */
92 .clock = 33000,
93 .hdisplay = 480,
94 .hsync_start = 480 + 70,
95 .hsync_end = 480 + 70 + 32,
96 .htotal = 480 + 70 + 32 + 72,
97 .vdisplay = 800,
98 .vsync_start = 800 + 15,
99 .vsync_end = 800 + 15 + 10,
100 .vtotal = 800 + 15 + 10 + 16,
101 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
102 .width_mm = 52,
103 .height_mm = 86,
104 },
105};
106
107static inline struct otm8009a *panel_to_otm8009a(struct drm_panel *panel)
108{
109 return container_of(panel, struct otm8009a, panel);
110}
111
112static void otm8009a_dcs_write_buf(struct otm8009a *ctx, const void *data,
113 size_t len)
114{
115 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
116
117 if (mipi_dsi_dcs_write_buffer(dsi, data, len) < 0)
118 dev_warn(ctx->dev, "mipi dsi dcs write buffer failed\n");
119}
120
121#define dcs_write_seq(ctx, seq...) \
122({ \
123 static const u8 d[] = { seq }; \
124 otm8009a_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \
125})
126
127#define dcs_write_cmd_at(ctx, cmd, seq...) \
128({ \
129 dcs_write_seq(ctx, MCS_ADRSFT, (cmd) & 0xFF); \
130 dcs_write_seq(ctx, (cmd) >> 8, seq); \
131})
132
133static int otm8009a_init_sequence(struct otm8009a *ctx)
134{
135 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
136 int ret;
137
138 /* Enter CMD2 */
139 dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0x80, 0x09, 0x01);
140
141 /* Enter Orise Command2 */
142 dcs_write_cmd_at(ctx, MCS_CMD2_ENA2, 0x80, 0x09);
143
144 dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL, 0x30);
145 mdelay(10);
146
147 dcs_write_cmd_at(ctx, MCS_NO_DOC1, 0x40);
148 mdelay(10);
149
150 dcs_write_cmd_at(ctx, MCS_PWR_CTRL4 + 1, 0xA9);
151 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 1, 0x34);
152 dcs_write_cmd_at(ctx, MCS_P_DRV_M, 0x50);
153 dcs_write_cmd_at(ctx, MCS_VCOMDC, 0x4E);
154 dcs_write_cmd_at(ctx, MCS_OSC_ADJ, 0x66); /* 65Hz */
155 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 2, 0x01);
156 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 5, 0x34);
157 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 4, 0x33);
158 dcs_write_cmd_at(ctx, MCS_GVDDSET, 0x79, 0x79);
159 dcs_write_cmd_at(ctx, MCS_SD_CTRL + 1, 0x1B);
160 dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 2, 0x83);
161 dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL + 1, 0x83);
162 dcs_write_cmd_at(ctx, MCS_RGB_VID_SET, 0x0E);
163 dcs_write_cmd_at(ctx, MCS_PANSET, 0x00, 0x01);
164
165 dcs_write_cmd_at(ctx, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00);
166 dcs_write_cmd_at(ctx, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00,
167 0x00, 0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00);
168 dcs_write_cmd_at(ctx, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00,
169 0x00, 0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00);
170 dcs_write_cmd_at(ctx, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00,
171 0x01, 0x02, 0x00, 0x00);
172
173 dcs_write_cmd_at(ctx, MCS_NO_DOC2, 0x00);
174
175 dcs_write_cmd_at(ctx, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
176 dcs_write_cmd_at(ctx, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
177 0, 0, 0, 0, 0);
178 dcs_write_cmd_at(ctx, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
179 0, 0, 0, 0, 0);
180 dcs_write_cmd_at(ctx, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
181 dcs_write_cmd_at(ctx, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0,
182 0, 0, 0, 0, 0);
183 dcs_write_cmd_at(ctx, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4,
184 4, 0, 0, 0, 0);
185 dcs_write_cmd_at(ctx, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
186 dcs_write_cmd_at(ctx, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
187 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
188
189 dcs_write_cmd_at(ctx, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25,
190 0x00, 0x00, 0x00, 0x00);
191 dcs_write_cmd_at(ctx, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
192 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C, 0x02);
193 dcs_write_cmd_at(ctx, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00,
194 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
195 dcs_write_cmd_at(ctx, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26,
196 0x00, 0x00, 0x00, 0x00);
197 dcs_write_cmd_at(ctx, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
198 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09, 0x01);
199 dcs_write_cmd_at(ctx, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00,
200 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
201
202 dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 1, 0x66);
203
204 dcs_write_cmd_at(ctx, MCS_NO_DOC3, 0x06);
205
206 dcs_write_cmd_at(ctx, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,
207 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,
208 0x01);
209 dcs_write_cmd_at(ctx, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,
210 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,
211 0x01);
212
213 /* Exit CMD2 */
214 dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF);
215
216 ret = mipi_dsi_dcs_nop(dsi);
217 if (ret)
218 return ret;
219
220 ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
221 if (ret)
222 return ret;
223
224 /* Wait for sleep out exit */
225 mdelay(120);
226
227 /* Default portrait 480x800 rgb24 */
228 dcs_write_seq(ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
229
230 ret = mipi_dsi_dcs_set_column_address(dsi, start: 0, OTM8009A_HDISPLAY - 1);
231 if (ret)
232 return ret;
233
234 ret = mipi_dsi_dcs_set_page_address(dsi, start: 0, OTM8009A_VDISPLAY - 1);
235 if (ret)
236 return ret;
237
238 /* See otm8009a driver documentation for pixel format descriptions */
239 ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT |
240 MIPI_DCS_PIXEL_FMT_24BIT << 4);
241 if (ret)
242 return ret;
243
244 /* Disable CABC feature */
245 dcs_write_seq(ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
246
247 ret = mipi_dsi_dcs_set_display_on(dsi);
248 if (ret)
249 return ret;
250
251 ret = mipi_dsi_dcs_nop(dsi);
252 if (ret)
253 return ret;
254
255 /* Send Command GRAM memory write (no parameters) */
256 dcs_write_seq(ctx, MIPI_DCS_WRITE_MEMORY_START);
257
258 /* Wait a short while to let the panel be ready before the 1st frame */
259 mdelay(10);
260
261 return 0;
262}
263
264static int otm8009a_disable(struct drm_panel *panel)
265{
266 struct otm8009a *ctx = panel_to_otm8009a(panel);
267 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
268 int ret;
269
270 backlight_disable(bd: ctx->bl_dev);
271
272 ret = mipi_dsi_dcs_set_display_off(dsi);
273 if (ret)
274 return ret;
275
276 ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
277 if (ret)
278 return ret;
279
280 msleep(msecs: 120);
281
282 return 0;
283}
284
285static int otm8009a_unprepare(struct drm_panel *panel)
286{
287 struct otm8009a *ctx = panel_to_otm8009a(panel);
288
289 if (ctx->reset_gpio) {
290 gpiod_set_value_cansleep(desc: ctx->reset_gpio, value: 1);
291 msleep(msecs: 20);
292 }
293
294 regulator_disable(regulator: ctx->supply);
295
296 ctx->prepared = false;
297
298 return 0;
299}
300
301static int otm8009a_prepare(struct drm_panel *panel)
302{
303 struct otm8009a *ctx = panel_to_otm8009a(panel);
304 int ret;
305
306 ret = regulator_enable(regulator: ctx->supply);
307 if (ret < 0) {
308 dev_err(panel->dev, "failed to enable supply: %d\n", ret);
309 return ret;
310 }
311
312 if (ctx->reset_gpio) {
313 gpiod_set_value_cansleep(desc: ctx->reset_gpio, value: 0);
314 gpiod_set_value_cansleep(desc: ctx->reset_gpio, value: 1);
315 msleep(msecs: 20);
316 gpiod_set_value_cansleep(desc: ctx->reset_gpio, value: 0);
317 msleep(msecs: 100);
318 }
319
320 ret = otm8009a_init_sequence(ctx);
321 if (ret)
322 return ret;
323
324 ctx->prepared = true;
325
326 return 0;
327}
328
329static int otm8009a_enable(struct drm_panel *panel)
330{
331 struct otm8009a *ctx = panel_to_otm8009a(panel);
332
333 backlight_enable(bd: ctx->bl_dev);
334
335 return 0;
336}
337
338static int otm8009a_get_modes(struct drm_panel *panel,
339 struct drm_connector *connector)
340{
341 struct drm_display_mode *mode;
342 unsigned int num_modes = ARRAY_SIZE(modes);
343 unsigned int i;
344
345 for (i = 0; i < num_modes; i++) {
346 mode = drm_mode_duplicate(dev: connector->dev, mode: &modes[i]);
347 if (!mode) {
348 dev_err(panel->dev, "failed to add mode %ux%u@%u\n",
349 modes[i].hdisplay,
350 modes[i].vdisplay,
351 drm_mode_vrefresh(&modes[i]));
352 return -ENOMEM;
353 }
354
355 mode->type = DRM_MODE_TYPE_DRIVER;
356
357 /* Setting first mode as preferred */
358 if (!i)
359 mode->type |= DRM_MODE_TYPE_PREFERRED;
360
361 drm_mode_set_name(mode);
362 drm_mode_probed_add(connector, mode);
363 }
364
365 connector->display_info.width_mm = mode->width_mm;
366 connector->display_info.height_mm = mode->height_mm;
367
368 return num_modes;
369}
370
371static const struct drm_panel_funcs otm8009a_drm_funcs = {
372 .disable = otm8009a_disable,
373 .unprepare = otm8009a_unprepare,
374 .prepare = otm8009a_prepare,
375 .enable = otm8009a_enable,
376 .get_modes = otm8009a_get_modes,
377};
378
379/*
380 * DSI-BASED BACKLIGHT
381 */
382
383static int otm8009a_backlight_update_status(struct backlight_device *bd)
384{
385 struct otm8009a *ctx = bl_get_data(bl_dev: bd);
386 u8 data[2];
387
388 if (!ctx->prepared) {
389 dev_dbg(&bd->dev, "lcd not ready yet for setting its backlight!\n");
390 return -ENXIO;
391 }
392
393 if (bd->props.power <= BACKLIGHT_POWER_REDUCED) {
394 /* Power on the backlight with the requested brightness
395 * Note We can not use mipi_dsi_dcs_set_display_brightness()
396 * as otm8009a driver support only 8-bit brightness (1 param).
397 */
398 data[0] = MIPI_DCS_SET_DISPLAY_BRIGHTNESS;
399 data[1] = bd->props.brightness;
400 otm8009a_dcs_write_buf(ctx, data, ARRAY_SIZE(data));
401
402 /* set Brightness Control & Backlight on */
403 data[1] = 0x24;
404
405 } else {
406 /* Power off the backlight: set Brightness Control & Bl off */
407 data[1] = 0;
408 }
409
410 /* Update Brightness Control & Backlight */
411 data[0] = MIPI_DCS_WRITE_CONTROL_DISPLAY;
412 otm8009a_dcs_write_buf(ctx, data, ARRAY_SIZE(data));
413
414 return 0;
415}
416
417static const struct backlight_ops otm8009a_backlight_ops = {
418 .update_status = otm8009a_backlight_update_status,
419};
420
421static int otm8009a_probe(struct mipi_dsi_device *dsi)
422{
423 struct device *dev = &dsi->dev;
424 struct otm8009a *ctx;
425 int ret;
426
427 ctx = devm_kzalloc(dev, size: sizeof(*ctx), GFP_KERNEL);
428 if (!ctx)
429 return -ENOMEM;
430
431 ctx->reset_gpio = devm_gpiod_get_optional(dev, con_id: "reset", flags: GPIOD_OUT_LOW);
432 if (IS_ERR(ptr: ctx->reset_gpio)) {
433 dev_err(dev, "cannot get reset-gpio\n");
434 return PTR_ERR(ptr: ctx->reset_gpio);
435 }
436
437 ctx->supply = devm_regulator_get(dev, id: "power");
438 if (IS_ERR(ptr: ctx->supply)) {
439 ret = PTR_ERR(ptr: ctx->supply);
440 if (ret != -EPROBE_DEFER)
441 dev_err(dev, "failed to request regulator: %d\n", ret);
442 return ret;
443 }
444
445 mipi_dsi_set_drvdata(dsi, data: ctx);
446
447 ctx->dev = dev;
448
449 dsi->lanes = 2;
450 dsi->format = MIPI_DSI_FMT_RGB888;
451 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
452 MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;
453
454 drm_panel_init(panel: &ctx->panel, dev, funcs: &otm8009a_drm_funcs,
455 DRM_MODE_CONNECTOR_DSI);
456
457 ctx->bl_dev = devm_backlight_device_register(dev, name: dev_name(dev),
458 parent: dev, devdata: ctx,
459 ops: &otm8009a_backlight_ops,
460 NULL);
461 if (IS_ERR(ptr: ctx->bl_dev)) {
462 ret = PTR_ERR(ptr: ctx->bl_dev);
463 dev_err(dev, "failed to register backlight: %d\n", ret);
464 return ret;
465 }
466
467 ctx->bl_dev->props.max_brightness = OTM8009A_BACKLIGHT_MAX;
468 ctx->bl_dev->props.brightness = OTM8009A_BACKLIGHT_DEFAULT;
469 ctx->bl_dev->props.power = BACKLIGHT_POWER_OFF;
470 ctx->bl_dev->props.type = BACKLIGHT_RAW;
471
472 drm_panel_add(panel: &ctx->panel);
473
474 ret = mipi_dsi_attach(dsi);
475 if (ret < 0) {
476 dev_err(dev, "mipi_dsi_attach failed. Is host ready?\n");
477 drm_panel_remove(panel: &ctx->panel);
478 return ret;
479 }
480
481 return 0;
482}
483
484static void otm8009a_remove(struct mipi_dsi_device *dsi)
485{
486 struct otm8009a *ctx = mipi_dsi_get_drvdata(dsi);
487
488 mipi_dsi_detach(dsi);
489 drm_panel_remove(panel: &ctx->panel);
490}
491
492static const struct of_device_id orisetech_otm8009a_of_match[] = {
493 { .compatible = "orisetech,otm8009a" },
494 { }
495};
496MODULE_DEVICE_TABLE(of, orisetech_otm8009a_of_match);
497
498static struct mipi_dsi_driver orisetech_otm8009a_driver = {
499 .probe = otm8009a_probe,
500 .remove = otm8009a_remove,
501 .driver = {
502 .name = "panel-orisetech-otm8009a",
503 .of_match_table = orisetech_otm8009a_of_match,
504 },
505};
506module_mipi_dsi_driver(orisetech_otm8009a_driver);
507
508MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
509MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
510MODULE_DESCRIPTION("DRM driver for Orise Tech OTM8009A MIPI DSI panel");
511MODULE_LICENSE("GPL v2");
512

source code of linux/drivers/gpu/drm/panel/panel-orisetech-otm8009a.c