1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), |
6 | * to deal in the Software without restriction, including without limitation |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
8 | * and/or sell copies of the Software, and to permit persons to whom the |
9 | * Software is furnished to do so, subject to the following conditions: |
10 | * |
11 | * The above copyright notice and this permission notice shall be included in |
12 | * all copies or substantial portions of the Software. |
13 | * |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
20 | * OTHER DEALINGS IN THE SOFTWARE. |
21 | */ |
22 | |
23 | #ifndef _PPTABLE_H |
24 | #define _PPTABLE_H |
25 | |
26 | #pragma pack(1) |
27 | |
28 | typedef struct _ATOM_PPLIB_THERMALCONTROLLER |
29 | |
30 | { |
31 | UCHAR ucType; // one of ATOM_PP_THERMALCONTROLLER_* |
32 | UCHAR ucI2cLine; // as interpreted by DAL I2C |
33 | UCHAR ucI2cAddress; |
34 | UCHAR ucFanParameters; // Fan Control Parameters. |
35 | UCHAR ucFanMinRPM; // Fan Minimum RPM (hundreds) -- for display purposes only. |
36 | UCHAR ucFanMaxRPM; // Fan Maximum RPM (hundreds) -- for display purposes only. |
37 | UCHAR ucReserved; // ---- |
38 | UCHAR ucFlags; // to be defined |
39 | } ATOM_PPLIB_THERMALCONTROLLER; |
40 | |
41 | #define ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK 0x0f |
42 | #define ATOM_PP_FANPARAMETERS_NOFAN 0x80 // No fan is connected to this controller. |
43 | |
44 | #define ATOM_PP_THERMALCONTROLLER_NONE 0 |
45 | #define ATOM_PP_THERMALCONTROLLER_LM63 1 // Not used by PPLib |
46 | #define ATOM_PP_THERMALCONTROLLER_ADM1032 2 // Not used by PPLib |
47 | #define ATOM_PP_THERMALCONTROLLER_ADM1030 3 // Not used by PPLib |
48 | #define ATOM_PP_THERMALCONTROLLER_MUA6649 4 // Not used by PPLib |
49 | #define ATOM_PP_THERMALCONTROLLER_LM64 5 |
50 | #define ATOM_PP_THERMALCONTROLLER_F75375 6 // Not used by PPLib |
51 | #define ATOM_PP_THERMALCONTROLLER_RV6xx 7 |
52 | #define ATOM_PP_THERMALCONTROLLER_RV770 8 |
53 | #define ATOM_PP_THERMALCONTROLLER_ADT7473 9 |
54 | #define ATOM_PP_THERMALCONTROLLER_KONG 10 |
55 | #define ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO 11 |
56 | #define ATOM_PP_THERMALCONTROLLER_EVERGREEN 12 |
57 | #define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen. |
58 | #define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally |
59 | #define ATOM_PP_THERMALCONTROLLER_NISLANDS 15 |
60 | #define ATOM_PP_THERMALCONTROLLER_SISLANDS 16 |
61 | #define ATOM_PP_THERMALCONTROLLER_LM96163 17 |
62 | #define ATOM_PP_THERMALCONTROLLER_CISLANDS 18 |
63 | #define ATOM_PP_THERMALCONTROLLER_KAVERI 19 |
64 | |
65 | |
66 | // Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal. |
67 | // We probably should reserve the bit 0x80 for this use. |
68 | // To keep the number of these types low we should also use the same code for all ASICs (i.e. do not distinguish RV6xx and RV7xx Internal here). |
69 | // The driver can pick the correct internal controller based on the ASIC. |
70 | |
71 | #define ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL 0x89 // ADT7473 Fan Control + Internal Thermal Controller |
72 | #define ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL 0x8D // EMC2103 Fan Control + Internal Thermal Controller |
73 | |
74 | typedef struct _ATOM_PPLIB_STATE |
75 | { |
76 | UCHAR ucNonClockStateIndex; |
77 | UCHAR ucClockStateIndices[]; // variable-sized |
78 | } ATOM_PPLIB_STATE; |
79 | |
80 | |
81 | typedef struct _ATOM_PPLIB_FANTABLE |
82 | { |
83 | UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same. |
84 | UCHAR ucTHyst; // Temperature hysteresis. Integer. |
85 | USHORT usTMin; // The temperature, in 0.01 centigrades, below which we just run at a minimal PWM. |
86 | USHORT usTMed; // The middle temperature where we change slopes. |
87 | USHORT usTHigh; // The high point above TMed for adjusting the second slope. |
88 | USHORT usPWMMin; // The minimum PWM value in percent (0.01% increments). |
89 | USHORT usPWMMed; // The PWM value (in percent) at TMed. |
90 | USHORT usPWMHigh; // The PWM value at THigh. |
91 | } ATOM_PPLIB_FANTABLE; |
92 | |
93 | typedef struct _ATOM_PPLIB_FANTABLE2 |
94 | { |
95 | ATOM_PPLIB_FANTABLE basicTable; |
96 | USHORT usTMax; // The max temperature |
97 | } ATOM_PPLIB_FANTABLE2; |
98 | |
99 | typedef struct _ATOM_PPLIB_FANTABLE3 |
100 | { |
101 | ATOM_PPLIB_FANTABLE2 basicTable2; |
102 | UCHAR ucFanControlMode; |
103 | USHORT usFanPWMMax; |
104 | USHORT usFanOutputSensitivity; |
105 | } ATOM_PPLIB_FANTABLE3; |
106 | |
107 | typedef struct |
108 | { |
109 | USHORT ; |
110 | ULONG ; // For Overdrive. |
111 | ULONG ; // For Overdrive. |
112 | // Add extra system parameters here, always adjust size to include all fields. |
113 | USHORT ; //points to ATOM_PPLIB_VCE_Table |
114 | USHORT ; //points to ATOM_PPLIB_UVD_Table |
115 | USHORT ; //points to ATOM_PPLIB_SAMU_Table |
116 | USHORT ; //points to ATOM_PPLIB_PPM_Table |
117 | USHORT ; //points to ATOM_PPLIB_ACP_Table |
118 | USHORT ; //points to ATOM_PPLIB_POWERTUNE_Table |
119 | } ; |
120 | |
121 | //// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps |
122 | #define ATOM_PP_PLATFORM_CAP_BACKBIAS 1 |
123 | #define ATOM_PP_PLATFORM_CAP_POWERPLAY 2 |
124 | #define ATOM_PP_PLATFORM_CAP_SBIOSPOWERSOURCE 4 |
125 | #define ATOM_PP_PLATFORM_CAP_ASPM_L0s 8 |
126 | #define ATOM_PP_PLATFORM_CAP_ASPM_L1 16 |
127 | #define ATOM_PP_PLATFORM_CAP_HARDWAREDC 32 |
128 | #define ATOM_PP_PLATFORM_CAP_GEMINIPRIMARY 64 |
129 | #define ATOM_PP_PLATFORM_CAP_STEPVDDC 128 |
130 | #define ATOM_PP_PLATFORM_CAP_VOLTAGECONTROL 256 |
131 | #define ATOM_PP_PLATFORM_CAP_SIDEPORTCONTROL 512 |
132 | #define ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1 1024 |
133 | #define ATOM_PP_PLATFORM_CAP_HTLINKCONTROL 2048 |
134 | #define ATOM_PP_PLATFORM_CAP_MVDDCONTROL 4096 |
135 | #define ATOM_PP_PLATFORM_CAP_GOTO_BOOT_ON_ALERT 0x2000 // Go to boot state on alerts, e.g. on an AC->DC transition. |
136 | #define ATOM_PP_PLATFORM_CAP_DONT_WAIT_FOR_VBLANK_ON_ALERT 0x4000 // Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). |
137 | #define ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL 0x8000 // Does the driver control VDDCI independently from VDDC. |
138 | #define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature. |
139 | #define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state. |
140 | #define ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE 0x00040000 // Does the driver supports new CAC voltage table. |
141 | #define ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY 0x00080000 // Does the driver supports revert GPIO5 polarity. |
142 | #define ATOM_PP_PLATFORM_CAP_OUTPUT_THERMAL2GPIO17 0x00100000 // Does the driver supports thermal2GPIO17. |
143 | #define ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE 0x00200000 // Does the driver supports VR HOT GPIO Configurable. |
144 | #define ATOM_PP_PLATFORM_CAP_TEMP_INVERSION 0x00400000 // Does the driver supports Temp Inversion feature. |
145 | #define ATOM_PP_PLATFORM_CAP_EVV 0x00800000 |
146 | |
147 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE |
148 | { |
149 | ATOM_COMMON_TABLE_HEADER ; |
150 | |
151 | UCHAR ucDataRevision; |
152 | |
153 | UCHAR ucNumStates; |
154 | UCHAR ucStateEntrySize; |
155 | UCHAR ucClockInfoSize; |
156 | UCHAR ucNonClockSize; |
157 | |
158 | // offset from start of this table to array of ucNumStates ATOM_PPLIB_STATE structures |
159 | USHORT usStateArrayOffset; |
160 | |
161 | // offset from start of this table to array of ASIC-specific structures, |
162 | // currently ATOM_PPLIB_CLOCK_INFO. |
163 | USHORT usClockInfoArrayOffset; |
164 | |
165 | // offset from start of this table to array of ATOM_PPLIB_NONCLOCK_INFO |
166 | USHORT usNonClockInfoArrayOffset; |
167 | |
168 | USHORT usBackbiasTime; // in microseconds |
169 | USHORT usVoltageTime; // in microseconds |
170 | USHORT usTableSize; //the size of this structure, or the extended structure |
171 | |
172 | ULONG ulPlatformCaps; // See ATOM_PPLIB_CAPS_* |
173 | |
174 | ATOM_PPLIB_THERMALCONTROLLER sThermalController; |
175 | |
176 | USHORT usBootClockInfoOffset; |
177 | USHORT usBootNonClockInfoOffset; |
178 | |
179 | } ATOM_PPLIB_POWERPLAYTABLE; |
180 | |
181 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE2 |
182 | { |
183 | ATOM_PPLIB_POWERPLAYTABLE basicTable; |
184 | UCHAR ucNumCustomThermalPolicy; |
185 | USHORT usCustomThermalPolicyArrayOffset; |
186 | }ATOM_PPLIB_POWERPLAYTABLE2, *LPATOM_PPLIB_POWERPLAYTABLE2; |
187 | |
188 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE3 |
189 | { |
190 | ATOM_PPLIB_POWERPLAYTABLE2 basicTable2; |
191 | USHORT usFormatID; // To be used ONLY by PPGen. |
192 | USHORT usFanTableOffset; |
193 | USHORT ; |
194 | } ATOM_PPLIB_POWERPLAYTABLE3, *LPATOM_PPLIB_POWERPLAYTABLE3; |
195 | |
196 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE4 |
197 | { |
198 | ATOM_PPLIB_POWERPLAYTABLE3 basicTable3; |
199 | ULONG ulGoldenPPID; // PPGen use only |
200 | ULONG ulGoldenRevision; // PPGen use only |
201 | USHORT usVddcDependencyOnSCLKOffset; |
202 | USHORT usVddciDependencyOnMCLKOffset; |
203 | USHORT usVddcDependencyOnMCLKOffset; |
204 | USHORT usMaxClockVoltageOnDCOffset; |
205 | USHORT usVddcPhaseShedLimitsTableOffset; // Points to ATOM_PPLIB_PhaseSheddingLimits_Table |
206 | USHORT usMvddDependencyOnMCLKOffset; |
207 | } ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4; |
208 | |
209 | typedef struct _ATOM_PPLIB_POWERPLAYTABLE5 |
210 | { |
211 | ATOM_PPLIB_POWERPLAYTABLE4 basicTable4; |
212 | ULONG ulTDPLimit; |
213 | ULONG ulNearTDPLimit; |
214 | ULONG ulSQRampingThreshold; |
215 | USHORT usCACLeakageTableOffset; // Points to ATOM_PPLIB_CAC_Leakage_Table |
216 | ULONG ulCACLeakage; // The iLeakage for driver calculated CAC leakage table |
217 | USHORT usTDPODLimit; |
218 | USHORT usLoadLineSlope; // in milliOhms * 100 |
219 | } ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5; |
220 | |
221 | //// ATOM_PPLIB_NONCLOCK_INFO::usClassification |
222 | #define ATOM_PPLIB_CLASSIFICATION_UI_MASK 0x0007 |
223 | #define ATOM_PPLIB_CLASSIFICATION_UI_SHIFT 0 |
224 | #define ATOM_PPLIB_CLASSIFICATION_UI_NONE 0 |
225 | #define ATOM_PPLIB_CLASSIFICATION_UI_BATTERY 1 |
226 | #define ATOM_PPLIB_CLASSIFICATION_UI_BALANCED 3 |
227 | #define ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE 5 |
228 | // 2, 4, 6, 7 are reserved |
229 | |
230 | #define ATOM_PPLIB_CLASSIFICATION_BOOT 0x0008 |
231 | #define ATOM_PPLIB_CLASSIFICATION_THERMAL 0x0010 |
232 | #define ATOM_PPLIB_CLASSIFICATION_LIMITEDPOWERSOURCE 0x0020 |
233 | #define ATOM_PPLIB_CLASSIFICATION_REST 0x0040 |
234 | #define ATOM_PPLIB_CLASSIFICATION_FORCED 0x0080 |
235 | #define ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE 0x0100 |
236 | #define ATOM_PPLIB_CLASSIFICATION_OVERDRIVETEMPLATE 0x0200 |
237 | #define ATOM_PPLIB_CLASSIFICATION_UVDSTATE 0x0400 |
238 | #define ATOM_PPLIB_CLASSIFICATION_3DLOW 0x0800 |
239 | #define ATOM_PPLIB_CLASSIFICATION_ACPI 0x1000 |
240 | #define ATOM_PPLIB_CLASSIFICATION_HD2STATE 0x2000 |
241 | #define ATOM_PPLIB_CLASSIFICATION_HDSTATE 0x4000 |
242 | #define ATOM_PPLIB_CLASSIFICATION_SDSTATE 0x8000 |
243 | |
244 | //// ATOM_PPLIB_NONCLOCK_INFO::usClassification2 |
245 | #define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001 |
246 | #define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002 |
247 | #define ATOM_PPLIB_CLASSIFICATION2_MVC 0x0004 //Multi-View Codec (BD-3D) |
248 | |
249 | //// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings |
250 | #define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001 |
251 | #define ATOM_PPLIB_SUPPORTS_VIDEO_PLAYBACK 0x00000002 |
252 | |
253 | // 0 is 2.5Gb/s, 1 is 5Gb/s |
254 | #define ATOM_PPLIB_PCIE_LINK_SPEED_MASK 0x00000004 |
255 | #define ATOM_PPLIB_PCIE_LINK_SPEED_SHIFT 2 |
256 | |
257 | // lanes - 1: 1, 2, 4, 8, 12, 16 permitted by PCIE spec |
258 | #define ATOM_PPLIB_PCIE_LINK_WIDTH_MASK 0x000000F8 |
259 | #define ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT 3 |
260 | |
261 | // lookup into reduced refresh-rate table |
262 | #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_MASK 0x00000F00 |
263 | #define ATOM_PPLIB_LIMITED_REFRESHRATE_VALUE_SHIFT 8 |
264 | |
265 | #define ATOM_PPLIB_LIMITED_REFRESHRATE_UNLIMITED 0 |
266 | #define ATOM_PPLIB_LIMITED_REFRESHRATE_50HZ 1 |
267 | // 2-15 TBD as needed. |
268 | |
269 | #define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000 |
270 | #define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000 |
271 | |
272 | #define ATOM_PPLIB_DISALLOW_ON_DC 0x00004000 |
273 | |
274 | #define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 |
275 | |
276 | //memory related flags |
277 | #define ATOM_PPLIB_SWSTATE_MEMORY_DLL_OFF 0x000010000 |
278 | |
279 | //M3 Arb //2bits, current 3 sets of parameters in total |
280 | #define ATOM_PPLIB_M3ARB_MASK 0x00060000 |
281 | #define ATOM_PPLIB_M3ARB_SHIFT 17 |
282 | |
283 | #define ATOM_PPLIB_ENABLE_DRR 0x00080000 |
284 | |
285 | // remaining 16 bits are reserved |
286 | typedef struct _ATOM_PPLIB_THERMAL_STATE |
287 | { |
288 | UCHAR ucMinTemperature; |
289 | UCHAR ucMaxTemperature; |
290 | UCHAR ucThermalAction; |
291 | }ATOM_PPLIB_THERMAL_STATE, *LPATOM_PPLIB_THERMAL_STATE; |
292 | |
293 | // Contained in an array starting at the offset |
294 | // in ATOM_PPLIB_POWERPLAYTABLE::usNonClockInfoArrayOffset. |
295 | // referenced from ATOM_PPLIB_STATE_INFO::ucNonClockStateIndex |
296 | #define ATOM_PPLIB_NONCLOCKINFO_VER1 12 |
297 | #define ATOM_PPLIB_NONCLOCKINFO_VER2 24 |
298 | typedef struct _ATOM_PPLIB_NONCLOCK_INFO |
299 | { |
300 | USHORT usClassification; |
301 | UCHAR ucMinTemperature; |
302 | UCHAR ucMaxTemperature; |
303 | ULONG ulCapsAndSettings; |
304 | UCHAR ucRequiredPower; |
305 | USHORT usClassification2; |
306 | ULONG ulVCLK; |
307 | ULONG ulDCLK; |
308 | UCHAR ucUnused[5]; |
309 | } ATOM_PPLIB_NONCLOCK_INFO; |
310 | |
311 | // Contained in an array starting at the offset |
312 | // in ATOM_PPLIB_POWERPLAYTABLE::usClockInfoArrayOffset. |
313 | // referenced from ATOM_PPLIB_STATE::ucClockStateIndices |
314 | typedef struct _ATOM_PPLIB_R600_CLOCK_INFO |
315 | { |
316 | USHORT usEngineClockLow; |
317 | UCHAR ucEngineClockHigh; |
318 | |
319 | USHORT usMemoryClockLow; |
320 | UCHAR ucMemoryClockHigh; |
321 | |
322 | USHORT usVDDC; |
323 | USHORT usUnused1; |
324 | USHORT usUnused2; |
325 | |
326 | ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* |
327 | |
328 | } ATOM_PPLIB_R600_CLOCK_INFO; |
329 | |
330 | // ulFlags in ATOM_PPLIB_R600_CLOCK_INFO |
331 | #define ATOM_PPLIB_R600_FLAGS_PCIEGEN2 1 |
332 | #define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2 |
333 | #define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4 |
334 | #define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8 |
335 | #define ATOM_PPLIB_R600_FLAGS_MEMORY_DLL_OFF 16 |
336 | #define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0). |
337 | |
338 | typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO |
339 | |
340 | { |
341 | USHORT usLowEngineClockLow; // Low Engine clock in MHz (the same way as on the R600). |
342 | UCHAR ucLowEngineClockHigh; |
343 | USHORT usHighEngineClockLow; // High Engine clock in MHz. |
344 | UCHAR ucHighEngineClockHigh; |
345 | USHORT usMemoryClockLow; // For now one of the ATOM_PPLIB_RS780_SPMCLK_XXXX constants. |
346 | UCHAR ucMemoryClockHigh; // Currentyl unused. |
347 | UCHAR ucPadding; // For proper alignment and size. |
348 | USHORT usVDDC; // For the 780, use: None, Low, High, Variable |
349 | UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} |
350 | UCHAR ucMinHTLinkWidth; // From SBIOS - {2, 4, 8, 16}. Effective only if CDLW enabled. Minimum down stream width could |
351 | USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). |
352 | ULONG ulFlags; |
353 | } ATOM_PPLIB_RS780_CLOCK_INFO; |
354 | |
355 | #define ATOM_PPLIB_RS780_VOLTAGE_NONE 0 |
356 | #define ATOM_PPLIB_RS780_VOLTAGE_LOW 1 |
357 | #define ATOM_PPLIB_RS780_VOLTAGE_HIGH 2 |
358 | #define ATOM_PPLIB_RS780_VOLTAGE_VARIABLE 3 |
359 | |
360 | #define ATOM_PPLIB_RS780_SPMCLK_NONE 0 // We cannot change the side port memory clock, leave it as it is. |
361 | #define ATOM_PPLIB_RS780_SPMCLK_LOW 1 |
362 | #define ATOM_PPLIB_RS780_SPMCLK_HIGH 2 |
363 | |
364 | #define ATOM_PPLIB_RS780_HTLINKFREQ_NONE 0 |
365 | #define ATOM_PPLIB_RS780_HTLINKFREQ_LOW 1 |
366 | #define ATOM_PPLIB_RS780_HTLINKFREQ_HIGH 2 |
367 | |
368 | typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO |
369 | { |
370 | USHORT usEngineClockLow; |
371 | UCHAR ucEngineClockHigh; |
372 | |
373 | USHORT usMemoryClockLow; |
374 | UCHAR ucMemoryClockHigh; |
375 | |
376 | USHORT usVDDC; |
377 | USHORT usVDDCI; |
378 | USHORT usUnused; |
379 | |
380 | ULONG ulFlags; // ATOM_PPLIB_R600_FLAGS_* |
381 | |
382 | } ATOM_PPLIB_EVERGREEN_CLOCK_INFO; |
383 | |
384 | typedef struct _ATOM_PPLIB_SI_CLOCK_INFO |
385 | { |
386 | USHORT usEngineClockLow; |
387 | UCHAR ucEngineClockHigh; |
388 | |
389 | USHORT usMemoryClockLow; |
390 | UCHAR ucMemoryClockHigh; |
391 | |
392 | USHORT usVDDC; |
393 | USHORT usVDDCI; |
394 | UCHAR ucPCIEGen; |
395 | UCHAR ucUnused1; |
396 | |
397 | ULONG ulFlags; // ATOM_PPLIB_SI_FLAGS_*, no flag is necessary for now |
398 | |
399 | } ATOM_PPLIB_SI_CLOCK_INFO; |
400 | |
401 | typedef struct _ATOM_PPLIB_CI_CLOCK_INFO |
402 | { |
403 | USHORT usEngineClockLow; |
404 | UCHAR ucEngineClockHigh; |
405 | |
406 | USHORT usMemoryClockLow; |
407 | UCHAR ucMemoryClockHigh; |
408 | |
409 | UCHAR ucPCIEGen; |
410 | USHORT usPCIELane; |
411 | } ATOM_PPLIB_CI_CLOCK_INFO; |
412 | |
413 | typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{ |
414 | USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz |
415 | UCHAR ucEngineClockHigh; //clockfrequency >> 16. |
416 | UCHAR vddcIndex; //2-bit vddc index; |
417 | USHORT tdpLimit; |
418 | //please initalize to 0 |
419 | USHORT rsv1; |
420 | //please initialize to 0s |
421 | ULONG rsv2[2]; |
422 | }ATOM_PPLIB_SUMO_CLOCK_INFO; |
423 | |
424 | typedef struct _ATOM_PPLIB_STATE_V2 |
425 | { |
426 | //number of valid dpm levels in this state; Driver uses it to calculate the whole |
427 | //size of the state: struct_size(ATOM_PPLIB_STATE_V2, clockInfoIndex, ucNumDPMLevels) |
428 | UCHAR ucNumDPMLevels; |
429 | |
430 | //a index to the array of nonClockInfos |
431 | UCHAR nonClockInfoIndex; |
432 | /** |
433 | * Driver will read the first ucNumDPMLevels in this array |
434 | */ |
435 | UCHAR clockInfoIndex[] __counted_by(ucNumDPMLevels); |
436 | } ATOM_PPLIB_STATE_V2; |
437 | |
438 | typedef struct _StateArray{ |
439 | //how many states we have |
440 | UCHAR ucNumEntries; |
441 | |
442 | ATOM_PPLIB_STATE_V2 states[] __counted_by(ucNumEntries); |
443 | }StateArray; |
444 | |
445 | |
446 | typedef struct _ClockInfoArray{ |
447 | //how many clock levels we have |
448 | UCHAR ucNumEntries; |
449 | |
450 | //sizeof(ATOM_PPLIB_CLOCK_INFO) |
451 | UCHAR ucEntrySize; |
452 | |
453 | UCHAR clockInfo[] __counted_by(ucNumEntries); |
454 | }ClockInfoArray; |
455 | |
456 | typedef struct _NonClockInfoArray{ |
457 | |
458 | //how many non-clock levels we have. normally should be same as number of states |
459 | UCHAR ucNumEntries; |
460 | //sizeof(ATOM_PPLIB_NONCLOCK_INFO) |
461 | UCHAR ucEntrySize; |
462 | |
463 | ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[] __counted_by(ucNumEntries); |
464 | }NonClockInfoArray; |
465 | |
466 | typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record |
467 | { |
468 | USHORT usClockLow; |
469 | UCHAR ucClockHigh; |
470 | USHORT usVoltage; |
471 | }ATOM_PPLIB_Clock_Voltage_Dependency_Record; |
472 | |
473 | typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table |
474 | { |
475 | UCHAR ucNumEntries; // Number of entries. |
476 | ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; // Dynamically allocate entries. |
477 | }ATOM_PPLIB_Clock_Voltage_Dependency_Table; |
478 | |
479 | typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record |
480 | { |
481 | USHORT usSclkLow; |
482 | UCHAR ucSclkHigh; |
483 | USHORT usMclkLow; |
484 | UCHAR ucMclkHigh; |
485 | USHORT usVddc; |
486 | USHORT usVddci; |
487 | }ATOM_PPLIB_Clock_Voltage_Limit_Record; |
488 | |
489 | typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table |
490 | { |
491 | UCHAR ucNumEntries; // Number of entries. |
492 | ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries. |
493 | }ATOM_PPLIB_Clock_Voltage_Limit_Table; |
494 | |
495 | union _ATOM_PPLIB_CAC_Leakage_Record |
496 | { |
497 | struct |
498 | { |
499 | USHORT usVddc; // We use this field for the "fake" standardized VDDC for power calculations; For CI and newer, we use this as the real VDDC value. in CI we read it as StdVoltageHiSidd |
500 | ULONG ulLeakageValue; // For CI and newer we use this as the "fake" standar VDDC value. in CI we read it as StdVoltageLoSidd |
501 | |
502 | }; |
503 | struct |
504 | { |
505 | USHORT usVddc1; |
506 | USHORT usVddc2; |
507 | USHORT usVddc3; |
508 | }; |
509 | }; |
510 | |
511 | typedef union _ATOM_PPLIB_CAC_Leakage_Record ATOM_PPLIB_CAC_Leakage_Record; |
512 | |
513 | typedef struct _ATOM_PPLIB_CAC_Leakage_Table |
514 | { |
515 | UCHAR ucNumEntries; // Number of entries. |
516 | ATOM_PPLIB_CAC_Leakage_Record entries[1]; // Dynamically allocate entries. |
517 | }ATOM_PPLIB_CAC_Leakage_Table; |
518 | |
519 | typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record |
520 | { |
521 | USHORT usVoltage; |
522 | USHORT usSclkLow; |
523 | UCHAR ucSclkHigh; |
524 | USHORT usMclkLow; |
525 | UCHAR ucMclkHigh; |
526 | }ATOM_PPLIB_PhaseSheddingLimits_Record; |
527 | |
528 | typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table |
529 | { |
530 | UCHAR ucNumEntries; // Number of entries. |
531 | ATOM_PPLIB_PhaseSheddingLimits_Record entries[1]; // Dynamically allocate entries. |
532 | }ATOM_PPLIB_PhaseSheddingLimits_Table; |
533 | |
534 | typedef struct _VCEClockInfo{ |
535 | USHORT usEVClkLow; |
536 | UCHAR ucEVClkHigh; |
537 | USHORT usECClkLow; |
538 | UCHAR ucECClkHigh; |
539 | }VCEClockInfo; |
540 | |
541 | typedef struct _VCEClockInfoArray{ |
542 | UCHAR ucNumEntries; |
543 | VCEClockInfo entries[1]; |
544 | }VCEClockInfoArray; |
545 | |
546 | typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record |
547 | { |
548 | USHORT usVoltage; |
549 | UCHAR ucVCEClockInfoIndex; |
550 | }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record; |
551 | |
552 | typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table |
553 | { |
554 | UCHAR numEntries; |
555 | ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1]; |
556 | }ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table; |
557 | |
558 | typedef struct _ATOM_PPLIB_VCE_State_Record |
559 | { |
560 | UCHAR ucVCEClockInfoIndex; |
561 | UCHAR ucClockInfoIndex; //highest 2 bits indicates memory p-states, lower 6bits indicates index to ClockInfoArrary |
562 | }ATOM_PPLIB_VCE_State_Record; |
563 | |
564 | typedef struct _ATOM_PPLIB_VCE_State_Table |
565 | { |
566 | UCHAR numEntries; |
567 | ATOM_PPLIB_VCE_State_Record entries[1]; |
568 | }ATOM_PPLIB_VCE_State_Table; |
569 | |
570 | |
571 | typedef struct _ATOM_PPLIB_VCE_Table |
572 | { |
573 | UCHAR revid; |
574 | // VCEClockInfoArray array; |
575 | // ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table limits; |
576 | // ATOM_PPLIB_VCE_State_Table states; |
577 | }ATOM_PPLIB_VCE_Table; |
578 | |
579 | |
580 | typedef struct _UVDClockInfo{ |
581 | USHORT usVClkLow; |
582 | UCHAR ucVClkHigh; |
583 | USHORT usDClkLow; |
584 | UCHAR ucDClkHigh; |
585 | }UVDClockInfo; |
586 | |
587 | typedef struct _UVDClockInfoArray{ |
588 | UCHAR ucNumEntries; |
589 | UVDClockInfo entries[1]; |
590 | }UVDClockInfoArray; |
591 | |
592 | typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record |
593 | { |
594 | USHORT usVoltage; |
595 | UCHAR ucUVDClockInfoIndex; |
596 | }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record; |
597 | |
598 | typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table |
599 | { |
600 | UCHAR numEntries; |
601 | ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1]; |
602 | }ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table; |
603 | |
604 | typedef struct _ATOM_PPLIB_UVD_Table |
605 | { |
606 | UCHAR revid; |
607 | // UVDClockInfoArray array; |
608 | // ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table limits; |
609 | }ATOM_PPLIB_UVD_Table; |
610 | |
611 | typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Record |
612 | { |
613 | USHORT usVoltage; |
614 | USHORT usSAMClockLow; |
615 | UCHAR ucSAMClockHigh; |
616 | }ATOM_PPLIB_SAMClk_Voltage_Limit_Record; |
617 | |
618 | typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Table{ |
619 | UCHAR numEntries; |
620 | ATOM_PPLIB_SAMClk_Voltage_Limit_Record entries[1]; |
621 | }ATOM_PPLIB_SAMClk_Voltage_Limit_Table; |
622 | |
623 | typedef struct _ATOM_PPLIB_SAMU_Table |
624 | { |
625 | UCHAR revid; |
626 | ATOM_PPLIB_SAMClk_Voltage_Limit_Table limits; |
627 | }ATOM_PPLIB_SAMU_Table; |
628 | |
629 | typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Record |
630 | { |
631 | USHORT usVoltage; |
632 | USHORT usACPClockLow; |
633 | UCHAR ucACPClockHigh; |
634 | }ATOM_PPLIB_ACPClk_Voltage_Limit_Record; |
635 | |
636 | typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Table{ |
637 | UCHAR numEntries; |
638 | ATOM_PPLIB_ACPClk_Voltage_Limit_Record entries[1]; |
639 | }ATOM_PPLIB_ACPClk_Voltage_Limit_Table; |
640 | |
641 | typedef struct _ATOM_PPLIB_ACP_Table |
642 | { |
643 | UCHAR revid; |
644 | ATOM_PPLIB_ACPClk_Voltage_Limit_Table limits; |
645 | }ATOM_PPLIB_ACP_Table; |
646 | |
647 | typedef struct _ATOM_PowerTune_Table{ |
648 | USHORT usTDP; |
649 | USHORT usConfigurableTDP; |
650 | USHORT usTDC; |
651 | USHORT usBatteryPowerLimit; |
652 | USHORT usSmallPowerLimit; |
653 | USHORT usLowCACLeakage; |
654 | USHORT usHighCACLeakage; |
655 | }ATOM_PowerTune_Table; |
656 | |
657 | typedef struct _ATOM_PPLIB_POWERTUNE_Table |
658 | { |
659 | UCHAR revid; |
660 | ATOM_PowerTune_Table power_tune_table; |
661 | }ATOM_PPLIB_POWERTUNE_Table; |
662 | |
663 | typedef struct _ATOM_PPLIB_POWERTUNE_Table_V1 |
664 | { |
665 | UCHAR revid; |
666 | ATOM_PowerTune_Table power_tune_table; |
667 | USHORT usMaximumPowerDeliveryLimit; |
668 | USHORT usReserve[7]; |
669 | } ATOM_PPLIB_POWERTUNE_Table_V1; |
670 | |
671 | #define ATOM_PPM_A_A 1 |
672 | #define ATOM_PPM_A_I 2 |
673 | typedef struct _ATOM_PPLIB_PPM_Table |
674 | { |
675 | UCHAR ucRevId; |
676 | UCHAR ucPpmDesign; //A+I or A+A |
677 | USHORT usCpuCoreNumber; |
678 | ULONG ulPlatformTDP; |
679 | ULONG ulSmallACPlatformTDP; |
680 | ULONG ulPlatformTDC; |
681 | ULONG ulSmallACPlatformTDC; |
682 | ULONG ulApuTDP; |
683 | ULONG ulDGpuTDP; |
684 | ULONG ulDGpuUlvPower; |
685 | ULONG ulTjmax; |
686 | } ATOM_PPLIB_PPM_Table; |
687 | |
688 | #pragma pack() |
689 | |
690 | #endif |
691 | |