| 1 | /* |
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| 2 | * Copyright 2011 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | */ |
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| 23 | #ifndef __RS780D_H__ |
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| 24 | #define __RS780D_H__ |
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| 25 | |
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| 26 | #define CG_SPLL_FUNC_CNTL 0x600 |
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| 27 | # define SPLL_RESET (1 << 0) |
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| 28 | # define SPLL_SLEEP (1 << 1) |
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| 29 | # define SPLL_REF_DIV(x) ((x) << 2) |
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| 30 | # define SPLL_REF_DIV_MASK (7 << 2) |
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| 31 | # define SPLL_REF_DIV_SHIFT 2 |
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| 32 | # define SPLL_FB_DIV(x) ((x) << 5) |
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| 33 | # define SPLL_FB_DIV_MASK (0xff << 2) |
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| 34 | # define SPLL_FB_DIV_SHIFT 2 |
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| 35 | # define SPLL_PULSEEN (1 << 13) |
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| 36 | # define SPLL_PULSENUM(x) ((x) << 14) |
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| 37 | # define SPLL_PULSENUM_MASK (3 << 14) |
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| 38 | # define SPLL_SW_HILEN(x) ((x) << 16) |
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| 39 | # define SPLL_SW_HILEN_MASK (0xf << 16) |
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| 40 | # define SPLL_SW_HILEN_SHIFT 16 |
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| 41 | # define SPLL_SW_LOLEN(x) ((x) << 20) |
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| 42 | # define SPLL_SW_LOLEN_MASK (0xf << 20) |
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| 43 | # define SPLL_SW_LOLEN_SHIFT 20 |
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| 44 | # define SPLL_DIVEN (1 << 24) |
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| 45 | # define SPLL_BYPASS_EN (1 << 25) |
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| 46 | # define SPLL_CHG_STATUS (1 << 29) |
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| 47 | # define SPLL_CTLREQ (1 << 30) |
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| 48 | # define SPLL_CTLACK (1 << 31) |
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| 49 | |
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| 50 | /* RS780/RS880 PM */ |
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| 51 | #define FVTHROT_CNTRL_REG 0x3000 |
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| 52 | #define DONT_WAIT_FOR_FBDIV_WRAP (1 << 0) |
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| 53 | #define MINIMUM_CIP(x) ((x) << 1) |
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| 54 | #define MINIMUM_CIP_SHIFT 1 |
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| 55 | #define MINIMUM_CIP_MASK 0x1fffffe |
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| 56 | #define REFRESH_RATE_DIVISOR(x) ((x) << 25) |
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| 57 | #define REFRESH_RATE_DIVISOR_SHIFT 25 |
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| 58 | #define REFRESH_RATE_DIVISOR_MASK (0x3 << 25) |
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| 59 | #define ENABLE_FV_THROT (1 << 27) |
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| 60 | #define ENABLE_FV_UPDATE (1 << 28) |
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| 61 | #define TREND_SEL_MODE (1 << 29) |
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| 62 | #define FORCE_TREND_SEL (1 << 30) |
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| 63 | #define ENABLE_FV_THROT_IO (1 << 31) |
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| 64 | #define FVTHROT_TARGET_REG 0x3004 |
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| 65 | #define TARGET_IDLE_COUNT(x) ((x) << 0) |
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| 66 | #define TARGET_IDLE_COUNT_MASK 0xffffff |
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| 67 | #define TARGET_IDLE_COUNT_SHIFT 0 |
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| 68 | #define FVTHROT_CB1 0x3008 |
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| 69 | #define FVTHROT_CB2 0x300c |
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| 70 | #define FVTHROT_CB3 0x3010 |
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| 71 | #define FVTHROT_CB4 0x3014 |
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| 72 | #define FVTHROT_UTC0 0x3018 |
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| 73 | #define FVTHROT_UTC1 0x301c |
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| 74 | #define FVTHROT_UTC2 0x3020 |
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| 75 | #define FVTHROT_UTC3 0x3024 |
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| 76 | #define FVTHROT_UTC4 0x3028 |
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| 77 | #define FVTHROT_DTC0 0x302c |
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| 78 | #define FVTHROT_DTC1 0x3030 |
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| 79 | #define FVTHROT_DTC2 0x3034 |
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| 80 | #define FVTHROT_DTC3 0x3038 |
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| 81 | #define FVTHROT_DTC4 0x303c |
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| 82 | #define FVTHROT_FBDIV_REG0 0x3040 |
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| 83 | #define MIN_FEEDBACK_DIV(x) ((x) << 0) |
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| 84 | #define MIN_FEEDBACK_DIV_MASK 0xfff |
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| 85 | #define MIN_FEEDBACK_DIV_SHIFT 0 |
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| 86 | #define MAX_FEEDBACK_DIV(x) ((x) << 12) |
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| 87 | #define MAX_FEEDBACK_DIV_MASK (0xfff << 12) |
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| 88 | #define MAX_FEEDBACK_DIV_SHIFT 12 |
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| 89 | #define FVTHROT_FBDIV_REG1 0x3044 |
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| 90 | #define MAX_FEEDBACK_STEP(x) ((x) << 0) |
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| 91 | #define MAX_FEEDBACK_STEP_MASK 0xfff |
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| 92 | #define MAX_FEEDBACK_STEP_SHIFT 0 |
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| 93 | #define STARTING_FEEDBACK_DIV(x) ((x) << 12) |
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| 94 | #define STARTING_FEEDBACK_DIV_MASK (0xfff << 12) |
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| 95 | #define STARTING_FEEDBACK_DIV_SHIFT 12 |
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| 96 | #define FORCE_FEEDBACK_DIV (1 << 24) |
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| 97 | #define FVTHROT_FBDIV_REG2 0x3048 |
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| 98 | #define FORCED_FEEDBACK_DIV(x) ((x) << 0) |
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| 99 | #define FORCED_FEEDBACK_DIV_MASK 0xfff |
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| 100 | #define FORCED_FEEDBACK_DIV_SHIFT 0 |
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| 101 | #define FB_DIV_TIMER_VAL(x) ((x) << 12) |
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| 102 | #define FB_DIV_TIMER_VAL_MASK (0xffff << 12) |
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| 103 | #define FB_DIV_TIMER_VAL_SHIFT 12 |
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| 104 | #define FVTHROT_FB_US_REG0 0x304c |
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| 105 | #define FVTHROT_FB_US_REG1 0x3050 |
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| 106 | #define FVTHROT_FB_DS_REG0 0x3054 |
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| 107 | #define FVTHROT_FB_DS_REG1 0x3058 |
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| 108 | #define FVTHROT_PWM_CTRL_REG0 0x305c |
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| 109 | #define STARTING_PWM_HIGHTIME(x) ((x) << 0) |
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| 110 | #define STARTING_PWM_HIGHTIME_MASK 0xfff |
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| 111 | #define STARTING_PWM_HIGHTIME_SHIFT 0 |
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| 112 | #define NUMBER_OF_CYCLES_IN_PERIOD(x) ((x) << 12) |
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| 113 | #define NUMBER_OF_CYCLES_IN_PERIOD_MASK (0xfff << 12) |
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| 114 | #define NUMBER_OF_CYCLES_IN_PERIOD_SHIFT 12 |
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| 115 | #define FORCE_STARTING_PWM_HIGHTIME (1 << 24) |
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| 116 | #define INVERT_PWM_WAVEFORM (1 << 25) |
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| 117 | #define FVTHROT_PWM_CTRL_REG1 0x3060 |
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| 118 | #define MIN_PWM_HIGHTIME(x) ((x) << 0) |
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| 119 | #define MIN_PWM_HIGHTIME_MASK 0xfff |
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| 120 | #define MIN_PWM_HIGHTIME_SHIFT 0 |
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| 121 | #define MAX_PWM_HIGHTIME(x) ((x) << 12) |
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| 122 | #define MAX_PWM_HIGHTIME_MASK (0xfff << 12) |
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| 123 | #define MAX_PWM_HIGHTIME_SHIFT 12 |
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| 124 | #define FVTHROT_PWM_US_REG0 0x3064 |
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| 125 | #define FVTHROT_PWM_US_REG1 0x3068 |
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| 126 | #define FVTHROT_PWM_DS_REG0 0x306c |
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| 127 | #define FVTHROT_PWM_DS_REG1 0x3070 |
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| 128 | #define FVTHROT_STATUS_REG0 0x3074 |
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| 129 | #define CURRENT_FEEDBACK_DIV_MASK 0xfff |
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| 130 | #define CURRENT_FEEDBACK_DIV_SHIFT 0 |
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| 131 | #define FVTHROT_STATUS_REG1 0x3078 |
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| 132 | #define FVTHROT_STATUS_REG2 0x307c |
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| 133 | #define CG_INTGFX_MISC 0x3080 |
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| 134 | #define FVTHROT_VBLANK_SEL (1 << 9) |
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| 135 | #define FVTHROT_PWM_FEEDBACK_DIV_REG1 0x308c |
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| 136 | #define RANGE0_PWM_FEEDBACK_DIV(x) ((x) << 0) |
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| 137 | #define RANGE0_PWM_FEEDBACK_DIV_MASK 0xfff |
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| 138 | #define RANGE0_PWM_FEEDBACK_DIV_SHIFT 0 |
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| 139 | #define RANGE_PWM_FEEDBACK_DIV_EN (1 << 12) |
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| 140 | #define FVTHROT_PWM_FEEDBACK_DIV_REG2 0x3090 |
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| 141 | #define RANGE1_PWM_FEEDBACK_DIV(x) ((x) << 0) |
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| 142 | #define RANGE1_PWM_FEEDBACK_DIV_MASK 0xfff |
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| 143 | #define RANGE1_PWM_FEEDBACK_DIV_SHIFT 0 |
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| 144 | #define RANGE2_PWM_FEEDBACK_DIV(x) ((x) << 12) |
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| 145 | #define RANGE2_PWM_FEEDBACK_DIV_MASK (0xfff << 12) |
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| 146 | #define RANGE2_PWM_FEEDBACK_DIV_SHIFT 12 |
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| 147 | #define FVTHROT_PWM_FEEDBACK_DIV_REG3 0x3094 |
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| 148 | #define RANGE0_PWM(x) ((x) << 0) |
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| 149 | #define RANGE0_PWM_MASK 0xfff |
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| 150 | #define RANGE0_PWM_SHIFT 0 |
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| 151 | #define RANGE1_PWM(x) ((x) << 12) |
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| 152 | #define RANGE1_PWM_MASK (0xfff << 12) |
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| 153 | #define RANGE1_PWM_SHIFT 12 |
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| 154 | #define FVTHROT_PWM_FEEDBACK_DIV_REG4 0x3098 |
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| 155 | #define RANGE2_PWM(x) ((x) << 0) |
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| 156 | #define RANGE2_PWM_MASK 0xfff |
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| 157 | #define RANGE2_PWM_SHIFT 0 |
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| 158 | #define RANGE3_PWM(x) ((x) << 12) |
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| 159 | #define RANGE3_PWM_MASK (0xfff << 12) |
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| 160 | #define RANGE3_PWM_SHIFT 12 |
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| 161 | #define FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1 0x30ac |
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| 162 | #define RANGE0_SLOW_CLK_FEEDBACK_DIV(x) ((x) << 0) |
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| 163 | #define RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK 0xfff |
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| 164 | #define RANGE0_SLOW_CLK_FEEDBACK_DIV_SHIFT 0 |
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| 165 | #define RANGE_SLOW_CLK_FEEDBACK_DIV_EN (1 << 12) |
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| 166 | |
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| 167 | #define GFX_MACRO_BYPASS_CNTL 0x30c0 |
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| 168 | #define SPLL_BYPASS_CNTL (1 << 0) |
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| 169 | #define UPLL_BYPASS_CNTL (1 << 1) |
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| 170 | |
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| 171 | #endif |
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| 172 | |
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