1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd |
4 | * Zheng Yang <zhengyang@rock-chips.com> |
5 | */ |
6 | |
7 | #ifndef __RK3066_HDMI_H__ |
8 | #define __RK3066_HDMI_H__ |
9 | |
10 | #define GRF_SOC_CON0 0x150 |
11 | #define HDMI_VIDEO_SEL BIT(14) |
12 | |
13 | #define DDC_SEGMENT_ADDR 0x30 |
14 | #define HDMI_SCL_RATE (50 * 1000) |
15 | #define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11 |
16 | |
17 | #define N_32K 0x1000 |
18 | #define N_441K 0x1880 |
19 | #define N_882K 0x3100 |
20 | #define N_1764K 0x6200 |
21 | #define N_48K 0x1800 |
22 | #define N_96K 0x3000 |
23 | #define N_192K 0x6000 |
24 | |
25 | #define HDMI_SYS_CTRL 0x000 |
26 | #define HDMI_LR_SWAP_N3 0x004 |
27 | #define HDMI_N2 0x008 |
28 | #define HDMI_N1 0x00c |
29 | #define HDMI_SPDIF_FS_CTS_INT3 0x010 |
30 | #define HDMI_CTS_INT2 0x014 |
31 | #define HDMI_CTS_INT1 0x018 |
32 | #define HDMI_CTS_EXT3 0x01c |
33 | #define HDMI_CTS_EXT2 0x020 |
34 | #define HDMI_CTS_EXT1 0x024 |
35 | #define HDMI_AUDIO_CTRL1 0x028 |
36 | #define HDMI_AUDIO_CTRL2 0x02c |
37 | #define HDMI_I2S_AUDIO_CTRL 0x030 |
38 | #define HDMI_I2S_SWAP 0x040 |
39 | #define HDMI_AUDIO_STA_BIT_CTRL1 0x044 |
40 | #define HDMI_AUDIO_STA_BIT_CTRL2 0x048 |
41 | #define HDMI_AUDIO_SRC_NUM_AND_LENGTH 0x050 |
42 | #define HDMI_AV_CTRL1 0x054 |
43 | #define HDMI_VIDEO_CTRL1 0x058 |
44 | #define HDMI_DEEP_COLOR_MODE 0x05c |
45 | |
46 | #define HDMI_EXT_VIDEO_PARA 0x0c0 |
47 | #define HDMI_EXT_HTOTAL_L 0x0c4 |
48 | #define HDMI_EXT_HTOTAL_H 0x0c8 |
49 | #define HDMI_EXT_HBLANK_L 0x0cc |
50 | #define HDMI_EXT_HBLANK_H 0x0d0 |
51 | #define HDMI_EXT_HDELAY_L 0x0d4 |
52 | #define HDMI_EXT_HDELAY_H 0x0d8 |
53 | #define HDMI_EXT_HDURATION_L 0x0dc |
54 | #define HDMI_EXT_HDURATION_H 0x0e0 |
55 | #define HDMI_EXT_VTOTAL_L 0x0e4 |
56 | #define HDMI_EXT_VTOTAL_H 0x0e8 |
57 | #define HDMI_AV_CTRL2 0x0ec |
58 | #define HDMI_EXT_VBLANK_L 0x0f4 |
59 | #define HDMI_EXT_VBLANK_H 0x10c |
60 | #define HDMI_EXT_VDELAY 0x0f8 |
61 | #define HDMI_EXT_VDURATION 0x0fc |
62 | |
63 | #define HDMI_CP_MANU_SEND_CTRL 0x100 |
64 | #define HDMI_CP_AUTO_SEND_CTRL 0x104 |
65 | #define HDMI_AUTO_CHECKSUM_OPT 0x108 |
66 | |
67 | #define HDMI_VIDEO_CTRL2 0x114 |
68 | |
69 | #define HDMI_PHY_OPTION 0x144 |
70 | |
71 | #define HDMI_CP_BUF_INDEX 0x17c |
72 | #define HDMI_CP_BUF_ACC_HB0 0x180 |
73 | #define HDMI_CP_BUF_ACC_HB1 0x184 |
74 | #define HDMI_CP_BUF_ACC_HB2 0x188 |
75 | #define HDMI_CP_BUF_ACC_PB0 0x18c |
76 | |
77 | #define HDMI_DDC_READ_FIFO_ADDR 0x200 |
78 | #define HDMI_DDC_BUS_FREQ_L 0x204 |
79 | #define HDMI_DDC_BUS_FREQ_H 0x208 |
80 | #define HDMI_DDC_BUS_CTRL 0x2dc |
81 | #define HDMI_DDC_I2C_LEN 0x278 |
82 | #define HDMI_DDC_I2C_OFFSET 0x280 |
83 | #define HDMI_DDC_I2C_CTRL 0x284 |
84 | #define HDMI_DDC_I2C_READ_BUF0 0x288 |
85 | #define HDMI_DDC_I2C_READ_BUF1 0x28c |
86 | #define HDMI_DDC_I2C_READ_BUF2 0x290 |
87 | #define HDMI_DDC_I2C_READ_BUF3 0x294 |
88 | #define HDMI_DDC_I2C_WRITE_BUF0 0x298 |
89 | #define HDMI_DDC_I2C_WRITE_BUF1 0x29c |
90 | #define HDMI_DDC_I2C_WRITE_BUF2 0x2a0 |
91 | #define HDMI_DDC_I2C_WRITE_BUF3 0x2a4 |
92 | #define HDMI_DDC_I2C_WRITE_BUF4 0x2ac |
93 | #define HDMI_DDC_I2C_WRITE_BUF5 0x2b0 |
94 | #define HDMI_DDC_I2C_WRITE_BUF6 0x2b4 |
95 | |
96 | #define HDMI_INTR_MASK1 0x248 |
97 | #define HDMI_INTR_MASK2 0x24c |
98 | #define HDMI_INTR_STATUS1 0x250 |
99 | #define HDMI_INTR_STATUS2 0x254 |
100 | #define HDMI_INTR_MASK3 0x258 |
101 | #define HDMI_INTR_MASK4 0x25c |
102 | #define HDMI_INTR_STATUS3 0x260 |
103 | #define HDMI_INTR_STATUS4 0x264 |
104 | |
105 | #define HDMI_HDCP_CTRL 0x2bc |
106 | |
107 | #define HDMI_EDID_SEGMENT_POINTER 0x310 |
108 | #define HDMI_EDID_WORD_ADDR 0x314 |
109 | #define HDMI_EDID_FIFO_ADDR 0x318 |
110 | |
111 | #define HDMI_HPG_MENS_STA 0x37c |
112 | |
113 | #define HDMI_INTERNAL_CLK_DIVIDER 0x800 |
114 | |
115 | enum { |
116 | /* HDMI_SYS_CTRL */ |
117 | HDMI_SYS_POWER_MODE_MASK = 0xf0, |
118 | HDMI_SYS_POWER_MODE_A = 0x10, |
119 | HDMI_SYS_POWER_MODE_B = 0x20, |
120 | HDMI_SYS_POWER_MODE_D = 0x40, |
121 | HDMI_SYS_POWER_MODE_E = 0x80, |
122 | HDMI_SYS_PLL_RESET_MASK = 0x0c, |
123 | HDMI_SYS_PLL_RESET = 0x0c, |
124 | HDMI_SYS_PLLB_RESET = 0x08, |
125 | |
126 | /* HDMI_LR_SWAP_N3 */ |
127 | HDMI_AUDIO_LR_SWAP_MASK = 0xf0, |
128 | HDMI_AUDIO_LR_SWAP_SUBPACKET0 = 0x10, |
129 | HDMI_AUDIO_LR_SWAP_SUBPACKET1 = 0x20, |
130 | HDMI_AUDIO_LR_SWAP_SUBPACKET2 = 0x40, |
131 | HDMI_AUDIO_LR_SWAP_SUBPACKET3 = 0x80, |
132 | HDMI_AUDIO_N_19_16_MASK = 0x0f, |
133 | |
134 | /* HDMI_AUDIO_CTRL1 */ |
135 | HDMI_AUDIO_EXTERNAL_CTS = BIT(7), |
136 | HDMI_AUDIO_INPUT_IIS = 0, |
137 | HDMI_AUDIO_INPUT_SPDIF = 0x08, |
138 | HDMI_AUDIO_INPUT_MCLK_ACTIVE = 0x04, |
139 | HDMI_AUDIO_INPUT_MCLK_DEACTIVE = 0, |
140 | HDMI_AUDIO_INPUT_MCLK_RATE_128X = 0, |
141 | HDMI_AUDIO_INPUT_MCLK_RATE_256X = 1, |
142 | HDMI_AUDIO_INPUT_MCLK_RATE_384X = 2, |
143 | HDMI_AUDIO_INPUT_MCLK_RATE_512X = 3, |
144 | |
145 | /* HDMI_I2S_AUDIO_CTRL */ |
146 | HDMI_AUDIO_I2S_FORMAT_STANDARD = 0, |
147 | HDMI_AUDIO_I2S_CHANNEL_1_2 = 0x04, |
148 | HDMI_AUDIO_I2S_CHANNEL_3_4 = 0x0c, |
149 | HDMI_AUDIO_I2S_CHANNEL_5_6 = 0x1c, |
150 | HDMI_AUDIO_I2S_CHANNEL_7_8 = 0x3c, |
151 | |
152 | /* HDMI_AV_CTRL1 */ |
153 | HDMI_AUDIO_SAMPLE_FRE_MASK = 0xf0, |
154 | HDMI_AUDIO_SAMPLE_FRE_32000 = 0x30, |
155 | HDMI_AUDIO_SAMPLE_FRE_44100 = 0, |
156 | HDMI_AUDIO_SAMPLE_FRE_48000 = 0x20, |
157 | HDMI_AUDIO_SAMPLE_FRE_88200 = 0x80, |
158 | HDMI_AUDIO_SAMPLE_FRE_96000 = 0xa0, |
159 | HDMI_AUDIO_SAMPLE_FRE_176400 = 0xc0, |
160 | HDMI_AUDIO_SAMPLE_FRE_192000 = 0xe0, |
161 | HDMI_AUDIO_SAMPLE_FRE_768000 = 0x90, |
162 | |
163 | HDMI_VIDEO_INPUT_FORMAT_MASK = 0x0e, |
164 | HDMI_VIDEO_INPUT_RGB_YCBCR444 = 0, |
165 | HDMI_VIDEO_INPUT_YCBCR422 = 0x02, |
166 | HDMI_VIDEO_DE_MASK = 0x1, |
167 | HDMI_VIDEO_INTERNAL_DE = 0, |
168 | HDMI_VIDEO_EXTERNAL_DE = 0x01, |
169 | |
170 | /* HDMI_VIDEO_CTRL1 */ |
171 | HDMI_VIDEO_OUTPUT_FORMAT_MASK = 0xc0, |
172 | HDMI_VIDEO_OUTPUT_RGB444 = 0, |
173 | HDMI_VIDEO_OUTPUT_YCBCR444 = 0x40, |
174 | HDMI_VIDEO_OUTPUT_YCBCR422 = 0x80, |
175 | HDMI_VIDEO_INPUT_DATA_DEPTH_MASK = 0x30, |
176 | HDMI_VIDEO_INPUT_DATA_DEPTH_12BIT = 0, |
177 | HDMI_VIDEO_INPUT_DATA_DEPTH_10BIT = 0x10, |
178 | HDMI_VIDEO_INPUT_DATA_DEPTH_8BIT = 0x30, |
179 | HDMI_VIDEO_INPUT_COLOR_MASK = 1, |
180 | HDMI_VIDEO_INPUT_COLOR_RGB = 0, |
181 | HDMI_VIDEO_INPUT_COLOR_YCBCR = 1, |
182 | |
183 | /* HDMI_EXT_VIDEO_PARA */ |
184 | HDMI_VIDEO_VSYNC_OFFSET_SHIFT = 4, |
185 | HDMI_VIDEO_VSYNC_ACTIVE_HIGH = BIT(3), |
186 | HDMI_VIDEO_VSYNC_ACTIVE_LOW = 0, |
187 | HDMI_VIDEO_HSYNC_ACTIVE_HIGH = BIT(2), |
188 | HDMI_VIDEO_HSYNC_ACTIVE_LOW = 0, |
189 | HDMI_VIDEO_MODE_INTERLACE = BIT(1), |
190 | HDMI_VIDEO_MODE_PROGRESSIVE = 0, |
191 | HDMI_EXT_VIDEO_SET_EN = BIT(0), |
192 | |
193 | /* HDMI_CP_AUTO_SEND_CTRL */ |
194 | |
195 | /* HDMI_VIDEO_CTRL2 */ |
196 | HDMI_VIDEO_AV_MUTE_MASK = 0xc0, |
197 | HDMI_VIDEO_CLR_AV_MUTE = BIT(7), |
198 | HDMI_VIDEO_SET_AV_MUTE = BIT(6), |
199 | HDMI_AUDIO_CP_LOGIC_RESET_MASK = BIT(2), |
200 | HDMI_AUDIO_CP_LOGIC_RESET = BIT(2), |
201 | HDMI_VIDEO_AUDIO_DISABLE_MASK = 0x3, |
202 | HDMI_AUDIO_DISABLE = BIT(1), |
203 | HDMI_VIDEO_DISABLE = BIT(0), |
204 | |
205 | /* HDMI_CP_BUF_INDEX */ |
206 | HDMI_INFOFRAME_VSI = 0x05, |
207 | HDMI_INFOFRAME_AVI = 0x06, |
208 | HDMI_INFOFRAME_AAI = 0x08, |
209 | |
210 | /* HDMI_INTR_MASK1 */ |
211 | /* HDMI_INTR_STATUS1 */ |
212 | HDMI_INTR_HOTPLUG = BIT(7), |
213 | HDMI_INTR_MSENS = BIT(6), |
214 | HDMI_INTR_VSYNC = BIT(5), |
215 | HDMI_INTR_AUDIO_FIFO_FULL = BIT(4), |
216 | HDMI_INTR_EDID_MASK = 0x6, |
217 | HDMI_INTR_EDID_READY = BIT(2), |
218 | HDMI_INTR_EDID_ERR = BIT(1), |
219 | |
220 | /* HDMI_HDCP_CTRL */ |
221 | HDMI_VIDEO_MODE_MASK = BIT(1), |
222 | HDMI_VIDEO_MODE_HDMI = BIT(1), |
223 | |
224 | /* HDMI_HPG_MENS_STA */ |
225 | HDMI_HPG_IN_STATUS_HIGH = BIT(7), |
226 | HDMI_MSENS_IN_STATUS_HIGH = BIT(6), |
227 | }; |
228 | |
229 | #endif /* __RK3066_HDMI_H__ */ |
230 | |