| 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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| 2 | /* |
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| 3 | * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd |
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| 4 | * Author: |
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| 5 | * Sandy Huang <hjc@rock-chips.com> |
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| 6 | * Mark Yao <mark.yao@rock-chips.com> |
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| 7 | */ |
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| 8 | |
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| 9 | #ifndef _ROCKCHIP_LVDS_ |
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| 10 | #define _ROCKCHIP_LVDS_ |
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| 11 | |
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| 12 | #define RK3288_LVDS_CH0_REG0 0x00 |
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| 13 | #define RK3288_LVDS_CH0_REG0_LVDS_EN BIT(7) |
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| 14 | #define RK3288_LVDS_CH0_REG0_TTL_EN BIT(6) |
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| 15 | #define RK3288_LVDS_CH0_REG0_LANECK_EN BIT(5) |
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| 16 | #define RK3288_LVDS_CH0_REG0_LANE4_EN BIT(4) |
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| 17 | #define RK3288_LVDS_CH0_REG0_LANE3_EN BIT(3) |
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| 18 | #define RK3288_LVDS_CH0_REG0_LANE2_EN BIT(2) |
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| 19 | #define RK3288_LVDS_CH0_REG0_LANE1_EN BIT(1) |
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| 20 | #define RK3288_LVDS_CH0_REG0_LANE0_EN BIT(0) |
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| 21 | |
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| 22 | #define RK3288_LVDS_CH0_REG1 0x04 |
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| 23 | #define RK3288_LVDS_CH0_REG1_LANECK_BIAS BIT(5) |
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| 24 | #define RK3288_LVDS_CH0_REG1_LANE4_BIAS BIT(4) |
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| 25 | #define RK3288_LVDS_CH0_REG1_LANE3_BIAS BIT(3) |
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| 26 | #define RK3288_LVDS_CH0_REG1_LANE2_BIAS BIT(2) |
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| 27 | #define RK3288_LVDS_CH0_REG1_LANE1_BIAS BIT(1) |
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| 28 | #define RK3288_LVDS_CH0_REG1_LANE0_BIAS BIT(0) |
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| 29 | |
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| 30 | #define RK3288_LVDS_CH0_REG2 0x08 |
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| 31 | #define RK3288_LVDS_CH0_REG2_RESERVE_ON BIT(7) |
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| 32 | #define RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE BIT(6) |
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| 33 | #define RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE BIT(5) |
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| 34 | #define RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE BIT(4) |
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| 35 | #define RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE BIT(3) |
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| 36 | #define RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE BIT(2) |
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| 37 | #define RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE BIT(1) |
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| 38 | #define RK3288_LVDS_CH0_REG2_PLL_FBDIV8 BIT(0) |
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| 39 | |
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| 40 | #define RK3288_LVDS_CH0_REG3 0x0c |
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| 41 | #define RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK 0xff |
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| 42 | |
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| 43 | #define RK3288_LVDS_CH0_REG4 0x10 |
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| 44 | #define RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE BIT(5) |
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| 45 | #define RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE BIT(4) |
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| 46 | #define RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE BIT(3) |
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| 47 | #define RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE BIT(2) |
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| 48 | #define RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE BIT(1) |
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| 49 | #define RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE BIT(0) |
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| 50 | |
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| 51 | #define RK3288_LVDS_CH0_REG5 0x14 |
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| 52 | #define RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA BIT(5) |
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| 53 | #define RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA BIT(4) |
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| 54 | #define RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA BIT(3) |
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| 55 | #define RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA BIT(2) |
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| 56 | #define RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA BIT(1) |
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| 57 | #define RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA BIT(0) |
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| 58 | |
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| 59 | #define RK3288_LVDS_CFG_REGC 0x30 |
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| 60 | #define RK3288_LVDS_CFG_REGC_PLL_ENABLE 0x00 |
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| 61 | #define RK3288_LVDS_CFG_REGC_PLL_DISABLE 0xff |
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| 62 | |
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| 63 | #define RK3288_LVDS_CH0_REGD 0x34 |
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| 64 | #define RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK 0x1f |
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| 65 | |
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| 66 | #define RK3288_LVDS_CH0_REG20 0x80 |
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| 67 | #define RK3288_LVDS_CH0_REG20_MSB 0x45 |
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| 68 | #define RK3288_LVDS_CH0_REG20_LSB 0x44 |
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| 69 | |
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| 70 | #define RK3288_LVDS_CFG_REG21 0x84 |
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| 71 | #define RK3288_LVDS_CFG_REG21_TX_ENABLE 0x92 |
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| 72 | #define RK3288_LVDS_CFG_REG21_TX_DISABLE 0x00 |
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| 73 | #define RK3288_LVDS_CH1_OFFSET 0x100 |
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| 74 | |
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| 75 | #define RK3288_LVDS_GRF_SOC_CON6 0x025C |
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| 76 | #define RK3288_LVDS_GRF_SOC_CON7 0x0260 |
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| 77 | |
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| 78 | /* fbdiv value is split over 2 registers, with bit8 in reg2 */ |
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| 79 | #define RK3288_LVDS_PLL_FBDIV_REG2(_fbd) \ |
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| 80 | (_fbd & BIT(8) ? RK3288_LVDS_CH0_REG2_PLL_FBDIV8 : 0) |
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| 81 | #define RK3288_LVDS_PLL_FBDIV_REG3(_fbd) \ |
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| 82 | (_fbd & RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK) |
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| 83 | #define RK3288_LVDS_PLL_PREDIV_REGD(_pd) \ |
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| 84 | (_pd & RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK) |
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| 85 | |
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| 86 | #define RK3288_LVDS_SOC_CON6_SEL_VOP_LIT BIT(3) |
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| 87 | |
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| 88 | #define LVDS_FMT_MASK (0x07 << 16) |
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| 89 | #define LVDS_MSB BIT(3) |
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| 90 | #define LVDS_DUAL BIT(4) |
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| 91 | #define LVDS_FMT_1 BIT(5) |
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| 92 | #define LVDS_TTL_EN BIT(6) |
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| 93 | #define LVDS_START_PHASE_RST_1 BIT(7) |
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| 94 | #define LVDS_DCLK_INV BIT(8) |
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| 95 | #define LVDS_CH0_EN BIT(11) |
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| 96 | #define LVDS_CH1_EN BIT(12) |
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| 97 | #define LVDS_PWRDN BIT(15) |
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| 98 | |
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| 99 | #define LVDS_24BIT (0 << 1) |
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| 100 | #define LVDS_18BIT (1 << 1) |
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| 101 | #define LVDS_FORMAT_VESA (0 << 0) |
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| 102 | #define LVDS_FORMAT_JEIDA (1 << 0) |
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| 103 | |
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| 104 | #define LVDS_VESA_24 0 |
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| 105 | #define LVDS_JEIDA_24 1 |
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| 106 | #define LVDS_VESA_18 2 |
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| 107 | #define LVDS_JEIDA_18 3 |
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| 108 | |
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| 109 | #define HIWORD_UPDATE(v, h, l) ((GENMASK(h, l) << 16) | ((v) << (l))) |
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| 110 | |
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| 111 | #define PX30_LVDS_GRF_PD_VO_CON0 0x434 |
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| 112 | #define PX30_LVDS_TIE_CLKS(val) HIWORD_UPDATE(val, 8, 8) |
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| 113 | #define PX30_LVDS_INVERT_CLKS(val) HIWORD_UPDATE(val, 9, 9) |
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| 114 | #define PX30_LVDS_INVERT_DCLK(val) HIWORD_UPDATE(val, 5, 5) |
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| 115 | |
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| 116 | #define PX30_LVDS_GRF_PD_VO_CON1 0x438 |
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| 117 | #define PX30_LVDS_FORMAT(val) HIWORD_UPDATE(val, 14, 13) |
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| 118 | #define PX30_LVDS_MODE_EN(val) HIWORD_UPDATE(val, 12, 12) |
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| 119 | #define PX30_LVDS_MSBSEL(val) HIWORD_UPDATE(val, 11, 11) |
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| 120 | #define PX30_LVDS_P2S_EN(val) HIWORD_UPDATE(val, 6, 6) |
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| 121 | #define PX30_LVDS_VOP_SEL(val) HIWORD_UPDATE(val, 1, 1) |
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| 122 | |
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| 123 | #endif /* _ROCKCHIP_LVDS_ */ |
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| 124 | |
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