1 | /* SPDX-License-Identifier: GPL-2.0 */ |
2 | /* |
3 | * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/ |
4 | * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> |
5 | */ |
6 | |
7 | #ifndef __TIDSS_DISPC_H__ |
8 | #define __TIDSS_DISPC_H__ |
9 | |
10 | #include "tidss_drv.h" |
11 | |
12 | struct dispc_device; |
13 | |
14 | struct drm_crtc_state; |
15 | |
16 | enum tidss_gamma_type { TIDSS_GAMMA_8BIT, TIDSS_GAMMA_10BIT }; |
17 | |
18 | struct tidss_vp_feat { |
19 | struct tidss_vp_color_feat { |
20 | u32 gamma_size; |
21 | enum tidss_gamma_type gamma_type; |
22 | bool has_ctm; |
23 | } color; |
24 | }; |
25 | |
26 | struct tidss_plane_feat { |
27 | struct tidss_plane_color_feat { |
28 | u32 encodings; |
29 | u32 ranges; |
30 | enum drm_color_encoding default_encoding; |
31 | enum drm_color_range default_range; |
32 | } color; |
33 | struct tidss_plane_blend_feat { |
34 | bool global_alpha; |
35 | } blend; |
36 | }; |
37 | |
38 | struct dispc_features_scaling { |
39 | u32 in_width_max_5tap_rgb; |
40 | u32 in_width_max_3tap_rgb; |
41 | u32 in_width_max_5tap_yuv; |
42 | u32 in_width_max_3tap_yuv; |
43 | u32 upscale_limit; |
44 | u32 downscale_limit_5tap; |
45 | u32 downscale_limit_3tap; |
46 | u32 xinc_max; |
47 | }; |
48 | |
49 | struct dispc_errata { |
50 | bool i2000; /* DSS Does Not Support YUV Pixel Data Formats */ |
51 | }; |
52 | |
53 | enum dispc_vp_bus_type { |
54 | DISPC_VP_DPI, /* DPI output */ |
55 | DISPC_VP_OLDI, /* OLDI (LVDS) output */ |
56 | DISPC_VP_INTERNAL, /* SoC internal routing */ |
57 | DISPC_VP_TIED_OFF, /* Tied off / Unavailable */ |
58 | DISPC_VP_MAX_BUS_TYPE, |
59 | }; |
60 | |
61 | enum dispc_dss_subrevision { |
62 | DISPC_K2G, |
63 | DISPC_AM625, |
64 | DISPC_AM62A7, |
65 | DISPC_AM65X, |
66 | DISPC_J721E, |
67 | }; |
68 | |
69 | struct dispc_features { |
70 | int min_pclk_khz; |
71 | int max_pclk_khz[DISPC_VP_MAX_BUS_TYPE]; |
72 | |
73 | struct dispc_features_scaling scaling; |
74 | |
75 | enum dispc_dss_subrevision subrev; |
76 | |
77 | const char *common; |
78 | const u16 *common_regs; |
79 | u32 num_vps; |
80 | const char *vp_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */ |
81 | const char *ovr_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */ |
82 | const char *vpclk_name[TIDSS_MAX_PORTS]; /* Should match dt clk names */ |
83 | const enum dispc_vp_bus_type vp_bus_type[TIDSS_MAX_PORTS]; |
84 | struct tidss_vp_feat vp_feat; |
85 | u32 num_planes; |
86 | const char *vid_name[TIDSS_MAX_PLANES]; /* Should match dt reg names */ |
87 | bool vid_lite[TIDSS_MAX_PLANES]; |
88 | u32 vid_order[TIDSS_MAX_PLANES]; |
89 | }; |
90 | |
91 | extern const struct dispc_features dispc_k2g_feats; |
92 | extern const struct dispc_features dispc_am625_feats; |
93 | extern const struct dispc_features dispc_am62a7_feats; |
94 | extern const struct dispc_features dispc_am65x_feats; |
95 | extern const struct dispc_features dispc_j721e_feats; |
96 | |
97 | void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask); |
98 | dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc); |
99 | |
100 | void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, |
101 | u32 hw_videoport, u32 x, u32 y, u32 layer); |
102 | void dispc_ovr_enable_layer(struct dispc_device *dispc, |
103 | u32 hw_videoport, u32 layer, bool enable); |
104 | |
105 | void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport, |
106 | const struct drm_crtc_state *state); |
107 | void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport, |
108 | const struct drm_crtc_state *state); |
109 | void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport); |
110 | void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport); |
111 | bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport); |
112 | void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport); |
113 | int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport, |
114 | const struct drm_crtc_state *state); |
115 | enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc, |
116 | u32 hw_videoport, |
117 | const struct drm_display_mode *mode); |
118 | int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport); |
119 | void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport); |
120 | int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport, |
121 | unsigned long rate); |
122 | void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport, |
123 | const struct drm_crtc_state *state, bool newmodeset); |
124 | |
125 | int dispc_runtime_suspend(struct dispc_device *dispc); |
126 | int dispc_runtime_resume(struct dispc_device *dispc); |
127 | |
128 | int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane, |
129 | const struct drm_plane_state *state, |
130 | u32 hw_videoport); |
131 | void dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane, |
132 | const struct drm_plane_state *state, |
133 | u32 hw_videoport); |
134 | void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable); |
135 | const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len); |
136 | |
137 | int dispc_init(struct tidss_device *tidss); |
138 | void dispc_remove(struct tidss_device *tidss); |
139 | |
140 | #endif |
141 | |