| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ |
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| 4 | * Author: Jyri Sarha <jsarha@ti.com> |
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| 5 | */ |
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| 6 | |
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| 7 | #ifndef __TIDSS_DISPC_REGS_H |
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| 8 | #define __TIDSS_DISPC_REGS_H |
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| 9 | |
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| 10 | enum dispc_common_regs { |
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| 11 | NOT_APPLICABLE_OFF = 0, |
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| 12 | DSS_REVISION_OFF, |
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| 13 | DSS_SYSCONFIG_OFF, |
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| 14 | DSS_SYSSTATUS_OFF, |
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| 15 | DISPC_IRQ_EOI_OFF, |
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| 16 | DISPC_IRQSTATUS_RAW_OFF, |
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| 17 | DISPC_IRQSTATUS_OFF, |
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| 18 | DISPC_IRQENABLE_SET_OFF, |
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| 19 | DISPC_IRQENABLE_CLR_OFF, |
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| 20 | DISPC_VID_IRQENABLE_OFF, |
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| 21 | DISPC_VID_IRQSTATUS_OFF, |
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| 22 | DISPC_VP_IRQENABLE_OFF, |
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| 23 | DISPC_VP_IRQSTATUS_OFF, |
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| 24 | WB_IRQENABLE_OFF, |
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| 25 | WB_IRQSTATUS_OFF, |
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| 26 | DISPC_GLOBAL_MFLAG_ATTRIBUTE_OFF, |
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| 27 | DISPC_GLOBAL_OUTPUT_ENABLE_OFF, |
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| 28 | DISPC_GLOBAL_BUFFER_OFF, |
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| 29 | DSS_CBA_CFG_OFF, |
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| 30 | DISPC_DBG_CONTROL_OFF, |
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| 31 | DISPC_DBG_STATUS_OFF, |
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| 32 | DISPC_CLKGATING_DISABLE_OFF, |
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| 33 | DISPC_SECURE_DISABLE_OFF, |
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| 34 | FBDC_REVISION_1_OFF, |
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| 35 | FBDC_REVISION_2_OFF, |
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| 36 | FBDC_REVISION_3_OFF, |
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| 37 | FBDC_REVISION_4_OFF, |
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| 38 | FBDC_REVISION_5_OFF, |
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| 39 | FBDC_REVISION_6_OFF, |
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| 40 | FBDC_COMMON_CONTROL_OFF, |
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| 41 | FBDC_CONSTANT_COLOR_0_OFF, |
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| 42 | FBDC_CONSTANT_COLOR_1_OFF, |
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| 43 | DISPC_CONNECTIONS_OFF, |
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| 44 | DISPC_MSS_VP1_OFF, |
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| 45 | DISPC_MSS_VP3_OFF, |
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| 46 | DISPC_COMMON_REG_TABLE_LEN, |
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| 47 | }; |
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| 48 | |
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| 49 | /* |
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| 50 | * dispc_common_regmap should be defined as const u16 * and pointing |
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| 51 | * to a valid dss common register map for the platform, before the |
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| 52 | * macros bellow can be used. |
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| 53 | */ |
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| 54 | |
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| 55 | #define REG(r) (dispc_common_regmap[r ## _OFF]) |
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| 56 | |
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| 57 | #define DSS_REVISION REG(DSS_REVISION) |
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| 58 | #define DSS_SYSCONFIG REG(DSS_SYSCONFIG) |
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| 59 | #define DSS_SYSSTATUS REG(DSS_SYSSTATUS) |
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| 60 | #define DISPC_IRQ_EOI REG(DISPC_IRQ_EOI) |
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| 61 | #define DISPC_IRQSTATUS_RAW REG(DISPC_IRQSTATUS_RAW) |
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| 62 | #define DISPC_IRQSTATUS REG(DISPC_IRQSTATUS) |
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| 63 | #define DISPC_IRQENABLE_SET REG(DISPC_IRQENABLE_SET) |
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| 64 | #define DISPC_IRQENABLE_CLR REG(DISPC_IRQENABLE_CLR) |
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| 65 | #define DISPC_VID_IRQENABLE(n) (REG(DISPC_VID_IRQENABLE) + (n) * 4) |
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| 66 | #define DISPC_VID_IRQSTATUS(n) (REG(DISPC_VID_IRQSTATUS) + (n) * 4) |
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| 67 | #define DISPC_VP_IRQENABLE(n) (REG(DISPC_VP_IRQENABLE) + (n) * 4) |
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| 68 | #define DISPC_VP_IRQSTATUS(n) (REG(DISPC_VP_IRQSTATUS) + (n) * 4) |
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| 69 | #define WB_IRQENABLE REG(WB_IRQENABLE) |
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| 70 | #define WB_IRQSTATUS REG(WB_IRQSTATUS) |
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| 71 | |
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| 72 | #define DISPC_GLOBAL_MFLAG_ATTRIBUTE REG(DISPC_GLOBAL_MFLAG_ATTRIBUTE) |
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| 73 | #define DISPC_GLOBAL_OUTPUT_ENABLE REG(DISPC_GLOBAL_OUTPUT_ENABLE) |
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| 74 | #define DISPC_GLOBAL_BUFFER REG(DISPC_GLOBAL_BUFFER) |
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| 75 | #define DSS_CBA_CFG REG(DSS_CBA_CFG) |
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| 76 | #define DISPC_DBG_CONTROL REG(DISPC_DBG_CONTROL) |
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| 77 | #define DISPC_DBG_STATUS REG(DISPC_DBG_STATUS) |
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| 78 | #define DISPC_CLKGATING_DISABLE REG(DISPC_CLKGATING_DISABLE) |
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| 79 | #define DISPC_SECURE_DISABLE REG(DISPC_SECURE_DISABLE) |
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| 80 | |
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| 81 | #define FBDC_REVISION_1 REG(FBDC_REVISION_1) |
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| 82 | #define FBDC_REVISION_2 REG(FBDC_REVISION_2) |
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| 83 | #define FBDC_REVISION_3 REG(FBDC_REVISION_3) |
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| 84 | #define FBDC_REVISION_4 REG(FBDC_REVISION_4) |
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| 85 | #define FBDC_REVISION_5 REG(FBDC_REVISION_5) |
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| 86 | #define FBDC_REVISION_6 REG(FBDC_REVISION_6) |
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| 87 | #define FBDC_COMMON_CONTROL REG(FBDC_COMMON_CONTROL) |
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| 88 | #define FBDC_CONSTANT_COLOR_0 REG(FBDC_CONSTANT_COLOR_0) |
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| 89 | #define FBDC_CONSTANT_COLOR_1 REG(FBDC_CONSTANT_COLOR_1) |
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| 90 | #define DISPC_CONNECTIONS REG(DISPC_CONNECTIONS) |
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| 91 | #define DISPC_MSS_VP1 REG(DISPC_MSS_VP1) |
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| 92 | #define DISPC_MSS_VP3 REG(DISPC_MSS_VP3) |
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| 93 | |
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| 94 | /* VID */ |
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| 95 | |
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| 96 | #define DISPC_VID_ACCUH_0 0x0 |
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| 97 | #define DISPC_VID_ACCUH_1 0x4 |
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| 98 | #define DISPC_VID_ACCUH2_0 0x8 |
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| 99 | #define DISPC_VID_ACCUH2_1 0xc |
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| 100 | #define DISPC_VID_ACCUV_0 0x10 |
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| 101 | #define DISPC_VID_ACCUV_1 0x14 |
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| 102 | #define DISPC_VID_ACCUV2_0 0x18 |
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| 103 | #define DISPC_VID_ACCUV2_1 0x1c |
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| 104 | #define DISPC_VID_ATTRIBUTES 0x20 |
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| 105 | #define DISPC_VID_ATTRIBUTES2 0x24 |
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| 106 | #define DISPC_VID_BA_0 0x28 |
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| 107 | #define DISPC_VID_BA_1 0x2c |
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| 108 | #define DISPC_VID_BA_UV_0 0x30 |
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| 109 | #define DISPC_VID_BA_UV_1 0x34 |
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| 110 | #define DISPC_VID_BUF_SIZE_STATUS 0x38 |
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| 111 | #define DISPC_VID_BUF_THRESHOLD 0x3c |
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| 112 | #define DISPC_VID_CSC_COEF(n) (0x40 + (n) * 4) |
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| 113 | |
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| 114 | #define DISPC_VID_FIRH 0x5c |
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| 115 | #define DISPC_VID_FIRH2 0x60 |
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| 116 | #define DISPC_VID_FIRV 0x64 |
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| 117 | #define DISPC_VID_FIRV2 0x68 |
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| 118 | |
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| 119 | #define DISPC_VID_FIR_COEFS_H0 0x6c |
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| 120 | #define DISPC_VID_FIR_COEF_H0(phase) (0x6c + (phase) * 4) |
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| 121 | #define DISPC_VID_FIR_COEFS_H0_C 0x90 |
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| 122 | #define DISPC_VID_FIR_COEF_H0_C(phase) (0x90 + (phase) * 4) |
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| 123 | |
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| 124 | #define DISPC_VID_FIR_COEFS_H12 0xb4 |
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| 125 | #define DISPC_VID_FIR_COEF_H12(phase) (0xb4 + (phase) * 4) |
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| 126 | #define DISPC_VID_FIR_COEFS_H12_C 0xf4 |
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| 127 | #define DISPC_VID_FIR_COEF_H12_C(phase) (0xf4 + (phase) * 4) |
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| 128 | |
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| 129 | #define DISPC_VID_FIR_COEFS_V0 0x134 |
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| 130 | #define DISPC_VID_FIR_COEF_V0(phase) (0x134 + (phase) * 4) |
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| 131 | #define DISPC_VID_FIR_COEFS_V0_C 0x158 |
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| 132 | #define DISPC_VID_FIR_COEF_V0_C(phase) (0x158 + (phase) * 4) |
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| 133 | |
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| 134 | #define DISPC_VID_FIR_COEFS_V12 0x17c |
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| 135 | #define DISPC_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4) |
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| 136 | #define DISPC_VID_FIR_COEFS_V12_C 0x1bc |
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| 137 | #define DISPC_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4) |
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| 138 | |
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| 139 | #define DISPC_VID_GLOBAL_ALPHA 0x1fc |
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| 140 | #define DISPC_VID_K2G_IRQENABLE 0x200 /* K2G */ |
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| 141 | #define DISPC_VID_K2G_IRQSTATUS 0x204 /* K2G */ |
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| 142 | #define DISPC_VID_MFLAG_THRESHOLD 0x208 |
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| 143 | #define DISPC_VID_PICTURE_SIZE 0x20c |
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| 144 | #define DISPC_VID_PIXEL_INC 0x210 |
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| 145 | #define DISPC_VID_K2G_POSITION 0x214 /* K2G */ |
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| 146 | #define DISPC_VID_PRELOAD 0x218 |
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| 147 | #define DISPC_VID_ROW_INC 0x21c |
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| 148 | #define DISPC_VID_SIZE 0x220 |
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| 149 | #define DISPC_VID_BA_EXT_0 0x22c |
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| 150 | #define DISPC_VID_BA_EXT_1 0x230 |
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| 151 | #define DISPC_VID_BA_UV_EXT_0 0x234 |
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| 152 | #define DISPC_VID_BA_UV_EXT_1 0x238 |
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| 153 | #define DISPC_VID_CSC_COEF7 0x23c |
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| 154 | #define DISPC_VID_ROW_INC_UV 0x248 |
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| 155 | #define DISPC_VID_CLUT 0x260 |
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| 156 | #define DISPC_VID_SAFETY_ATTRIBUTES 0x2a0 |
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| 157 | #define DISPC_VID_SAFETY_CAPT_SIGNATURE 0x2a4 |
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| 158 | #define DISPC_VID_SAFETY_POSITION 0x2a8 |
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| 159 | #define DISPC_VID_SAFETY_REF_SIGNATURE 0x2ac |
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| 160 | #define DISPC_VID_SAFETY_SIZE 0x2b0 |
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| 161 | #define DISPC_VID_SAFETY_LFSR_SEED 0x2b4 |
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| 162 | #define DISPC_VID_LUMAKEY 0x2b8 |
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| 163 | #define DISPC_VID_DMA_BUFSIZE 0x2bc /* J721E */ |
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| 164 | |
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| 165 | /* OVR */ |
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| 166 | |
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| 167 | #define DISPC_OVR_CONFIG 0x0 |
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| 168 | #define DISPC_OVR_VIRTVP 0x4 /* J721E */ |
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| 169 | #define DISPC_OVR_DEFAULT_COLOR 0x8 |
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| 170 | #define DISPC_OVR_DEFAULT_COLOR2 0xc |
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| 171 | #define DISPC_OVR_TRANS_COLOR_MAX 0x10 |
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| 172 | #define DISPC_OVR_TRANS_COLOR_MAX2 0x14 |
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| 173 | #define DISPC_OVR_TRANS_COLOR_MIN 0x18 |
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| 174 | #define DISPC_OVR_TRANS_COLOR_MIN2 0x1c |
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| 175 | #define DISPC_OVR_ATTRIBUTES(n) (0x20 + (n) * 4) |
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| 176 | #define DISPC_OVR_ATTRIBUTES2(n) (0x34 + (n) * 4) /* J721E */ |
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| 177 | /* VP */ |
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| 178 | |
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| 179 | #define DISPC_VP_CONFIG 0x0 |
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| 180 | #define DISPC_VP_CONTROL 0x4 |
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| 181 | #define DISPC_VP_CSC_COEF0 0x8 |
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| 182 | #define DISPC_VP_CSC_COEF1 0xc |
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| 183 | #define DISPC_VP_CSC_COEF2 0x10 |
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| 184 | #define DISPC_VP_DATA_CYCLE_0 0x14 |
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| 185 | #define DISPC_VP_DATA_CYCLE_1 0x18 |
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| 186 | #define DISPC_VP_K2G_GAMMA_TABLE 0x20 /* K2G */ |
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| 187 | #define DISPC_VP_K2G_IRQENABLE 0x3c /* K2G */ |
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| 188 | #define DISPC_VP_K2G_IRQSTATUS 0x40 /* K2G */ |
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| 189 | #define DISPC_VP_DATA_CYCLE_2 0x1c |
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| 190 | #define DISPC_VP_LINE_NUMBER 0x44 |
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| 191 | #define DISPC_VP_POL_FREQ 0x4c |
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| 192 | #define DISPC_VP_SIZE_SCREEN 0x50 |
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| 193 | #define DISPC_VP_TIMING_H 0x54 |
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| 194 | #define DISPC_VP_TIMING_V 0x58 |
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| 195 | #define DISPC_VP_CSC_COEF3 0x5c |
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| 196 | #define DISPC_VP_CSC_COEF4 0x60 |
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| 197 | #define DISPC_VP_CSC_COEF5 0x64 |
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| 198 | #define DISPC_VP_CSC_COEF6 0x68 |
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| 199 | #define DISPC_VP_CSC_COEF7 0x6c |
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| 200 | #define DISPC_VP_SAFETY_ATTRIBUTES_0 0x70 |
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| 201 | #define DISPC_VP_SAFETY_ATTRIBUTES_1 0x74 |
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| 202 | #define DISPC_VP_SAFETY_ATTRIBUTES_2 0x78 |
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| 203 | #define DISPC_VP_SAFETY_ATTRIBUTES_3 0x7c |
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| 204 | #define DISPC_VP_SAFETY_CAPT_SIGNATURE_0 0x90 |
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| 205 | #define DISPC_VP_SAFETY_CAPT_SIGNATURE_1 0x94 |
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| 206 | #define DISPC_VP_SAFETY_CAPT_SIGNATURE_2 0x98 |
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| 207 | #define DISPC_VP_SAFETY_CAPT_SIGNATURE_3 0x9c |
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| 208 | #define DISPC_VP_SAFETY_POSITION_0 0xb0 |
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| 209 | #define DISPC_VP_SAFETY_POSITION_1 0xb4 |
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| 210 | #define DISPC_VP_SAFETY_POSITION_2 0xb8 |
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| 211 | #define DISPC_VP_SAFETY_POSITION_3 0xbc |
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| 212 | #define DISPC_VP_SAFETY_REF_SIGNATURE_0 0xd0 |
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| 213 | #define DISPC_VP_SAFETY_REF_SIGNATURE_1 0xd4 |
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| 214 | #define DISPC_VP_SAFETY_REF_SIGNATURE_2 0xd8 |
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| 215 | #define DISPC_VP_SAFETY_REF_SIGNATURE_3 0xdc |
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| 216 | #define DISPC_VP_SAFETY_SIZE_0 0xf0 |
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| 217 | #define DISPC_VP_SAFETY_SIZE_1 0xf4 |
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| 218 | #define DISPC_VP_SAFETY_SIZE_2 0xf8 |
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| 219 | #define DISPC_VP_SAFETY_SIZE_3 0xfc |
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| 220 | #define DISPC_VP_SAFETY_LFSR_SEED 0x110 |
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| 221 | #define DISPC_VP_GAMMA_TABLE 0x120 |
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| 222 | #define DISPC_VP_DSS_OLDI_CFG 0x160 |
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| 223 | #define DISPC_VP_DSS_OLDI_STATUS 0x164 |
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| 224 | #define DISPC_VP_DSS_OLDI_LB 0x168 |
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| 225 | #define DISPC_VP_DSS_MERGE_SPLIT 0x16c /* J721E */ |
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| 226 | #define DISPC_VP_DSS_DMA_THREADSIZE 0x170 /* J721E */ |
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| 227 | #define DISPC_VP_DSS_DMA_THREADSIZE_STATUS 0x174 /* J721E */ |
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| 228 | |
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| 229 | /* |
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| 230 | * OLDI IO_CTRL register offsets. On AM654 the registers are found |
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| 231 | * from CTRL_MMR0, there the syscon regmap should map 0x14 bytes from |
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| 232 | * CTRLMMR0P1_OLDI_DAT0_IO_CTRL to CTRLMMR0P1_OLDI_CLK_IO_CTRL |
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| 233 | * register range. |
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| 234 | */ |
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| 235 | #define OLDI_DAT0_IO_CTRL 0x00 |
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| 236 | #define OLDI_DAT1_IO_CTRL 0x04 |
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| 237 | #define OLDI_DAT2_IO_CTRL 0x08 |
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| 238 | #define OLDI_DAT3_IO_CTRL 0x0C |
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| 239 | #define OLDI_CLK_IO_CTRL 0x10 |
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| 240 | |
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| 241 | #define OLDI_PWRDN_TX BIT(8) |
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| 242 | |
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| 243 | #endif /* __TIDSS_DISPC_REGS_H */ |
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| 244 | |
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