| 1 | // SPDX-License-Identifier: GPL-2.0+ |
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| 2 | /* Copyright (C) 2017-2018 Broadcom */ |
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| 3 | |
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| 4 | #ifndef V3D_REGS_H |
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| 5 | #define V3D_REGS_H |
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| 6 | |
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| 7 | #include <linux/bitops.h> |
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| 8 | |
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| 9 | #define V3D_MASK(high, low) ((u32)GENMASK(high, low)) |
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| 10 | /* Using the GNU statement expression extension */ |
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| 11 | #define V3D_SET_FIELD(value, field) \ |
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| 12 | ({ \ |
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| 13 | u32 fieldval = (value) << field##_SHIFT; \ |
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| 14 | WARN_ON((fieldval & ~field##_MASK) != 0); \ |
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| 15 | fieldval & field##_MASK; \ |
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| 16 | }) |
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| 17 | |
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| 18 | #define V3D_GET_FIELD(word, field) (((word) & field##_MASK) >> \ |
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| 19 | field##_SHIFT) |
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| 20 | |
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| 21 | /* Hub registers for shared hardware between V3D cores. */ |
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| 22 | |
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| 23 | #define V3D_HUB_AXICFG 0x00000 |
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| 24 | # define V3D_HUB_AXICFG_MAX_LEN_MASK V3D_MASK(3, 0) |
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| 25 | # define V3D_HUB_AXICFG_MAX_LEN_SHIFT 0 |
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| 26 | #define V3D_HUB_UIFCFG 0x00004 |
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| 27 | #define V3D_HUB_IDENT0 0x00008 |
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| 28 | |
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| 29 | #define V3D_HUB_IDENT1 0x0000c |
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| 30 | # define V3D_HUB_IDENT1_WITH_MSO BIT(19) |
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| 31 | # define V3D_HUB_IDENT1_WITH_TSY BIT(18) |
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| 32 | # define V3D_HUB_IDENT1_WITH_TFU BIT(17) |
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| 33 | # define V3D_HUB_IDENT1_WITH_L3C BIT(16) |
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| 34 | # define V3D_HUB_IDENT1_NHOSTS_MASK V3D_MASK(15, 12) |
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| 35 | # define V3D_HUB_IDENT1_NHOSTS_SHIFT 12 |
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| 36 | # define V3D_HUB_IDENT1_NCORES_MASK V3D_MASK(11, 8) |
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| 37 | # define V3D_HUB_IDENT1_NCORES_SHIFT 8 |
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| 38 | # define V3D_HUB_IDENT1_REV_MASK V3D_MASK(7, 4) |
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| 39 | # define V3D_HUB_IDENT1_REV_SHIFT 4 |
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| 40 | # define V3D_HUB_IDENT1_TVER_MASK V3D_MASK(3, 0) |
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| 41 | # define V3D_HUB_IDENT1_TVER_SHIFT 0 |
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| 42 | |
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| 43 | #define V3D_HUB_IDENT2 0x00010 |
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| 44 | # define V3D_HUB_IDENT2_WITH_MMU BIT(8) |
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| 45 | # define V3D_HUB_IDENT2_L3C_NKB_MASK V3D_MASK(7, 0) |
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| 46 | # define V3D_HUB_IDENT2_L3C_NKB_SHIFT 0 |
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| 47 | |
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| 48 | #define V3D_HUB_IDENT3 0x00014 |
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| 49 | # define V3D_HUB_IDENT3_IPREV_MASK V3D_MASK(15, 8) |
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| 50 | # define V3D_HUB_IDENT3_IPREV_SHIFT 8 |
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| 51 | # define V3D_HUB_IDENT3_IPIDX_MASK V3D_MASK(7, 0) |
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| 52 | # define V3D_HUB_IDENT3_IPIDX_SHIFT 0 |
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| 53 | |
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| 54 | #define V3D_HUB_INT_STS 0x00050 |
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| 55 | #define V3D_HUB_INT_SET 0x00054 |
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| 56 | #define V3D_HUB_INT_CLR 0x00058 |
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| 57 | #define V3D_HUB_INT_MSK_STS 0x0005c |
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| 58 | #define V3D_HUB_INT_MSK_SET 0x00060 |
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| 59 | #define V3D_HUB_INT_MSK_CLR 0x00064 |
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| 60 | # define V3D_HUB_INT_MMU_WRV BIT(5) |
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| 61 | # define V3D_HUB_INT_MMU_PTI BIT(4) |
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| 62 | # define V3D_HUB_INT_MMU_CAP BIT(3) |
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| 63 | # define V3D_HUB_INT_MSO BIT(2) |
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| 64 | # define V3D_HUB_INT_TFUC BIT(1) |
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| 65 | # define V3D_HUB_INT_TFUF BIT(0) |
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| 66 | |
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| 67 | #define V3D_GCA_CACHE_CTRL 0x0000c |
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| 68 | # define V3D_GCA_CACHE_CTRL_FLUSH BIT(0) |
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| 69 | |
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| 70 | #define V3D_GCA_SAFE_SHUTDOWN 0x000b0 |
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| 71 | # define V3D_GCA_SAFE_SHUTDOWN_EN BIT(0) |
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| 72 | |
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| 73 | #define V3D_GCA_SAFE_SHUTDOWN_ACK 0x000b4 |
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| 74 | # define V3D_GCA_SAFE_SHUTDOWN_ACK_ACKED 3 |
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| 75 | |
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| 76 | # define V3D_TOP_GR_BRIDGE_REVISION 0x00000 |
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| 77 | # define V3D_TOP_GR_BRIDGE_MAJOR_MASK V3D_MASK(15, 8) |
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| 78 | # define V3D_TOP_GR_BRIDGE_MAJOR_SHIFT 8 |
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| 79 | # define V3D_TOP_GR_BRIDGE_MINOR_MASK V3D_MASK(7, 0) |
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| 80 | # define V3D_TOP_GR_BRIDGE_MINOR_SHIFT 0 |
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| 81 | |
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| 82 | /* 7268 reset reg */ |
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| 83 | # define V3D_TOP_GR_BRIDGE_SW_INIT_0 0x00008 |
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| 84 | # define V3D_TOP_GR_BRIDGE_SW_INIT_0_V3D_CLK_108_SW_INIT BIT(0) |
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| 85 | /* 7278 reset reg */ |
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| 86 | # define V3D_TOP_GR_BRIDGE_SW_INIT_1 0x0000c |
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| 87 | # define V3D_TOP_GR_BRIDGE_SW_INIT_1_V3D_CLK_108_SW_INIT BIT(0) |
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| 88 | |
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| 89 | #define V3D_TFU_CS 0x00400 |
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| 90 | /* Stops current job, empties input fifo. */ |
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| 91 | # define V3D_TFU_CS_TFURST BIT(31) |
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| 92 | # define V3D_TFU_CS_CVTCT_MASK V3D_MASK(23, 16) |
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| 93 | # define V3D_TFU_CS_CVTCT_SHIFT 16 |
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| 94 | # define V3D_TFU_CS_NFREE_MASK V3D_MASK(13, 8) |
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| 95 | # define V3D_TFU_CS_NFREE_SHIFT 8 |
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| 96 | # define V3D_TFU_CS_BUSY BIT(0) |
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| 97 | |
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| 98 | #define V3D_TFU_SU 0x00404 |
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| 99 | /* Interrupt when FINTTHR input slots are free (0 = disabled) */ |
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| 100 | # define V3D_TFU_SU_FINTTHR_MASK V3D_MASK(13, 8) |
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| 101 | # define V3D_TFU_SU_FINTTHR_SHIFT 8 |
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| 102 | /* Skips resetting the CRC at the start of CRC generation. */ |
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| 103 | # define V3D_TFU_SU_CRCCHAIN BIT(4) |
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| 104 | /* skips writes, computes CRC of the image. miplevels must be 0. */ |
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| 105 | # define V3D_TFU_SU_CRC BIT(3) |
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| 106 | # define V3D_TFU_SU_THROTTLE_MASK V3D_MASK(1, 0) |
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| 107 | # define V3D_TFU_SU_THROTTLE_SHIFT 0 |
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| 108 | |
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| 109 | #define V3D_TFU_ICFG 0x00408 |
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| 110 | /* Interrupt when the conversion is complete. */ |
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| 111 | # define V3D_TFU_ICFG_IOC BIT(0) |
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| 112 | |
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| 113 | /* Input Image Address */ |
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| 114 | #define V3D_TFU_IIA 0x0040c |
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| 115 | /* Input Chroma Address */ |
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| 116 | #define V3D_TFU_ICA 0x00410 |
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| 117 | /* Input Image Stride */ |
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| 118 | #define V3D_TFU_IIS 0x00414 |
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| 119 | /* Input Image U-Plane Address */ |
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| 120 | #define V3D_TFU_IUA 0x00418 |
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| 121 | /* Output Image Address */ |
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| 122 | #define V3D_TFU_IOA 0x0041c |
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| 123 | /* Image Output Size */ |
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| 124 | #define V3D_TFU_IOS 0x00420 |
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| 125 | /* TFU YUV Coefficient 0 */ |
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| 126 | #define V3D_TFU_COEF0 0x00424 |
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| 127 | /* Use these regs instead of the defaults. */ |
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| 128 | # define V3D_TFU_COEF0_USECOEF BIT(31) |
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| 129 | /* TFU YUV Coefficient 1 */ |
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| 130 | #define V3D_TFU_COEF1 0x00428 |
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| 131 | /* TFU YUV Coefficient 2 */ |
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| 132 | #define V3D_TFU_COEF2 0x0042c |
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| 133 | /* TFU YUV Coefficient 3 */ |
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| 134 | #define V3D_TFU_COEF3 0x00430 |
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| 135 | |
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| 136 | #define V3D_TFU_CRC 0x00434 |
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| 137 | |
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| 138 | /* Per-MMU registers. */ |
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| 139 | |
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| 140 | #define V3D_MMUC_CONTROL 0x01000 |
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| 141 | # define V3D_MMUC_CONTROL_CLEAR BIT(3) |
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| 142 | # define V3D_MMUC_CONTROL_FLUSHING BIT(2) |
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| 143 | # define V3D_MMUC_CONTROL_FLUSH BIT(1) |
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| 144 | # define V3D_MMUC_CONTROL_ENABLE BIT(0) |
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| 145 | |
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| 146 | #define V3D_MMU_CTL 0x01200 |
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| 147 | # define V3D_MMU_CTL_CAP_EXCEEDED BIT(27) |
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| 148 | # define V3D_MMU_CTL_CAP_EXCEEDED_ABORT BIT(26) |
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| 149 | # define V3D_MMU_CTL_CAP_EXCEEDED_INT BIT(25) |
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| 150 | # define V3D_MMU_CTL_CAP_EXCEEDED_EXCEPTION BIT(24) |
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| 151 | # define V3D_MMU_CTL_PT_INVALID BIT(20) |
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| 152 | # define V3D_MMU_CTL_PT_INVALID_ABORT BIT(19) |
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| 153 | # define V3D_MMU_CTL_PT_INVALID_INT BIT(18) |
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| 154 | # define V3D_MMU_CTL_PT_INVALID_EXCEPTION BIT(17) |
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| 155 | # define V3D_MMU_CTL_PT_INVALID_ENABLE BIT(16) |
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| 156 | # define V3D_MMU_CTL_WRITE_VIOLATION BIT(12) |
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| 157 | # define V3D_MMU_CTL_WRITE_VIOLATION_ABORT BIT(11) |
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| 158 | # define V3D_MMU_CTL_WRITE_VIOLATION_INT BIT(10) |
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| 159 | # define V3D_MMU_CTL_WRITE_VIOLATION_EXCEPTION BIT(9) |
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| 160 | # define V3D_MMU_CTL_TLB_CLEARING BIT(7) |
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| 161 | # define V3D_MMU_CTL_TLB_STATS_CLEAR BIT(3) |
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| 162 | # define V3D_MMU_CTL_TLB_CLEAR BIT(2) |
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| 163 | # define V3D_MMU_CTL_TLB_STATS_ENABLE BIT(1) |
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| 164 | # define V3D_MMU_CTL_ENABLE BIT(0) |
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| 165 | |
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| 166 | #define V3D_MMU_PT_PA_BASE 0x01204 |
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| 167 | #define V3D_MMU_HIT 0x01208 |
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| 168 | #define V3D_MMU_MISSES 0x0120c |
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| 169 | #define V3D_MMU_STALLS 0x01210 |
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| 170 | |
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| 171 | #define V3D_MMU_ADDR_CAP 0x01214 |
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| 172 | # define V3D_MMU_ADDR_CAP_ENABLE BIT(31) |
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| 173 | # define V3D_MMU_ADDR_CAP_MPAGE_MASK V3D_MASK(11, 0) |
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| 174 | # define V3D_MMU_ADDR_CAP_MPAGE_SHIFT 0 |
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| 175 | |
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| 176 | #define V3D_MMU_SHOOT_DOWN 0x01218 |
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| 177 | # define V3D_MMU_SHOOT_DOWN_SHOOTING BIT(29) |
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| 178 | # define V3D_MMU_SHOOT_DOWN_SHOOT BIT(28) |
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| 179 | # define V3D_MMU_SHOOT_DOWN_PAGE_MASK V3D_MASK(27, 0) |
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| 180 | # define V3D_MMU_SHOOT_DOWN_PAGE_SHIFT 0 |
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| 181 | |
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| 182 | #define V3D_MMU_BYPASS_START 0x0121c |
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| 183 | #define V3D_MMU_BYPASS_END 0x01220 |
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| 184 | |
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| 185 | /* AXI ID of the access that faulted */ |
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| 186 | #define V3D_MMU_VIO_ID 0x0122c |
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| 187 | |
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| 188 | /* Address for illegal PTEs to return */ |
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| 189 | #define V3D_MMU_ILLEGAL_ADDR 0x01230 |
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| 190 | # define V3D_MMU_ILLEGAL_ADDR_ENABLE BIT(31) |
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| 191 | |
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| 192 | /* Address that faulted */ |
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| 193 | #define V3D_MMU_VIO_ADDR 0x01234 |
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| 194 | |
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| 195 | #define V3D_MMU_DEBUG_INFO 0x01238 |
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| 196 | # define V3D_MMU_PA_WIDTH_MASK V3D_MASK(11, 8) |
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| 197 | # define V3D_MMU_PA_WIDTH_SHIFT 8 |
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| 198 | # define V3D_MMU_VA_WIDTH_MASK V3D_MASK(7, 4) |
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| 199 | # define V3D_MMU_VA_WIDTH_SHIFT 4 |
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| 200 | # define V3D_MMU_VERSION_MASK V3D_MASK(3, 0) |
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| 201 | # define V3D_MMU_VERSION_SHIFT 0 |
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| 202 | |
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| 203 | /* Per-V3D-core registers */ |
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| 204 | |
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| 205 | #define V3D_CTL_IDENT0 0x00000 |
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| 206 | # define V3D_IDENT0_VER_MASK V3D_MASK(31, 24) |
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| 207 | # define V3D_IDENT0_VER_SHIFT 24 |
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| 208 | |
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| 209 | #define V3D_CTL_IDENT1 0x00004 |
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| 210 | /* Multiples of 1kb */ |
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| 211 | # define V3D_IDENT1_VPM_SIZE_MASK V3D_MASK(31, 28) |
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| 212 | # define V3D_IDENT1_VPM_SIZE_SHIFT 28 |
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| 213 | # define V3D_IDENT1_NSEM_MASK V3D_MASK(23, 16) |
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| 214 | # define V3D_IDENT1_NSEM_SHIFT 16 |
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| 215 | # define V3D_IDENT1_NTMU_MASK V3D_MASK(15, 12) |
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| 216 | # define V3D_IDENT1_NTMU_SHIFT 12 |
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| 217 | # define V3D_IDENT1_QUPS_MASK V3D_MASK(11, 8) |
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| 218 | # define V3D_IDENT1_QUPS_SHIFT 8 |
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| 219 | # define V3D_IDENT1_NSLC_MASK V3D_MASK(7, 4) |
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| 220 | # define V3D_IDENT1_NSLC_SHIFT 4 |
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| 221 | # define V3D_IDENT1_REV_MASK V3D_MASK(3, 0) |
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| 222 | # define V3D_IDENT1_REV_SHIFT 0 |
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| 223 | |
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| 224 | #define V3D_CTL_IDENT2 0x00008 |
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| 225 | # define V3D_IDENT2_BCG_INT BIT(28) |
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| 226 | |
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| 227 | #define V3D_CTL_MISCCFG 0x00018 |
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| 228 | # define V3D_CTL_MISCCFG_QRMAXCNT_MASK V3D_MASK(3, 1) |
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| 229 | # define V3D_CTL_MISCCFG_QRMAXCNT_SHIFT 1 |
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| 230 | # define V3D_MISCCFG_OVRTMUOUT BIT(0) |
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| 231 | |
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| 232 | #define V3D_CTL_L2CACTL 0x00020 |
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| 233 | # define V3D_L2CACTL_L2CCLR BIT(2) |
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| 234 | # define V3D_L2CACTL_L2CDIS BIT(1) |
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| 235 | # define V3D_L2CACTL_L2CENA BIT(0) |
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| 236 | |
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| 237 | #define V3D_CTL_SLCACTL 0x00024 |
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| 238 | # define V3D_SLCACTL_TVCCS_MASK V3D_MASK(27, 24) |
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| 239 | # define V3D_SLCACTL_TVCCS_SHIFT 24 |
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| 240 | # define V3D_SLCACTL_TDCCS_MASK V3D_MASK(19, 16) |
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| 241 | # define V3D_SLCACTL_TDCCS_SHIFT 16 |
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| 242 | # define V3D_SLCACTL_UCC_MASK V3D_MASK(11, 8) |
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| 243 | # define V3D_SLCACTL_UCC_SHIFT 8 |
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| 244 | # define V3D_SLCACTL_ICC_MASK V3D_MASK(3, 0) |
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| 245 | # define V3D_SLCACTL_ICC_SHIFT 0 |
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| 246 | |
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| 247 | #define V3D_CTL_L2TCACTL 0x00030 |
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| 248 | # define V3D_L2TCACTL_TMUWCF BIT(8) |
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| 249 | # define V3D_L2TCACTL_L2T_NO_WM BIT(4) |
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| 250 | /* Invalidates cache lines. */ |
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| 251 | # define V3D_L2TCACTL_FLM_FLUSH 0 |
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| 252 | /* Removes cachelines without writing dirty lines back. */ |
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| 253 | # define V3D_L2TCACTL_FLM_CLEAR 1 |
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| 254 | /* Writes out dirty cachelines and marks them clean, but doesn't invalidate. */ |
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| 255 | # define V3D_L2TCACTL_FLM_CLEAN 2 |
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| 256 | # define V3D_L2TCACTL_FLM_MASK V3D_MASK(2, 1) |
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| 257 | # define V3D_L2TCACTL_FLM_SHIFT 1 |
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| 258 | # define V3D_L2TCACTL_L2TFLS BIT(0) |
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| 259 | #define V3D_CTL_L2TFLSTA 0x00034 |
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| 260 | #define V3D_CTL_L2TFLEND 0x00038 |
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| 261 | |
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| 262 | #define V3D_CTL_INT_STS 0x00050 |
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| 263 | #define V3D_CTL_INT_SET 0x00054 |
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| 264 | #define V3D_CTL_INT_CLR 0x00058 |
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| 265 | #define V3D_CTL_INT_MSK_STS 0x0005c |
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| 266 | #define V3D_CTL_INT_MSK_SET 0x00060 |
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| 267 | #define V3D_CTL_INT_MSK_CLR 0x00064 |
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| 268 | # define V3D_INT_QPU_MASK V3D_MASK(27, 16) |
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| 269 | # define V3D_INT_QPU_SHIFT 16 |
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| 270 | # define V3D_INT_CSDDONE BIT(7) |
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| 271 | # define V3D_INT_PCTR BIT(6) |
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| 272 | # define V3D_INT_GMPV BIT(5) |
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| 273 | # define V3D_INT_TRFB BIT(4) |
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| 274 | # define V3D_INT_SPILLUSE BIT(3) |
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| 275 | # define V3D_INT_OUTOMEM BIT(2) |
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| 276 | # define V3D_INT_FLDONE BIT(1) |
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| 277 | # define V3D_INT_FRDONE BIT(0) |
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| 278 | |
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| 279 | #define V3D_CLE_CT0CS 0x00100 |
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| 280 | #define V3D_CLE_CT1CS 0x00104 |
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| 281 | #define V3D_CLE_CTNCS(n) (V3D_CLE_CT0CS + 4 * n) |
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| 282 | #define V3D_CLE_CT0EA 0x00108 |
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| 283 | #define V3D_CLE_CT1EA 0x0010c |
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| 284 | #define V3D_CLE_CTNEA(n) (V3D_CLE_CT0EA + 4 * n) |
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| 285 | #define V3D_CLE_CT0CA 0x00110 |
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| 286 | #define V3D_CLE_CT1CA 0x00114 |
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| 287 | #define V3D_CLE_CTNCA(n) (V3D_CLE_CT0CA + 4 * n) |
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| 288 | #define V3D_CLE_CT0RA 0x00118 |
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| 289 | #define V3D_CLE_CT1RA 0x0011c |
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| 290 | #define V3D_CLE_CTNRA(n) (V3D_CLE_CT0RA + 4 * n) |
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| 291 | #define V3D_CLE_CT0LC 0x00120 |
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| 292 | #define V3D_CLE_CT1LC 0x00124 |
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| 293 | #define V3D_CLE_CT0PC 0x00128 |
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| 294 | #define V3D_CLE_CT1PC 0x0012c |
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| 295 | #define V3D_CLE_PCS 0x00130 |
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| 296 | #define V3D_CLE_BFC 0x00134 |
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| 297 | #define V3D_CLE_RFC 0x00138 |
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| 298 | #define V3D_CLE_TFBC 0x0013c |
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| 299 | #define V3D_CLE_TFIT 0x00140 |
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| 300 | #define V3D_CLE_CT1CFG 0x00144 |
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| 301 | #define V3D_CLE_CT1TILECT 0x00148 |
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| 302 | #define V3D_CLE_CT1TSKIP 0x0014c |
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| 303 | #define V3D_CLE_CT1PTCT 0x00150 |
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| 304 | #define V3D_CLE_CT0SYNC 0x00154 |
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| 305 | #define V3D_CLE_CT1SYNC 0x00158 |
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| 306 | #define V3D_CLE_CT0QTS 0x0015c |
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| 307 | # define V3D_CLE_CT0QTS_ENABLE BIT(1) |
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| 308 | #define V3D_CLE_CT0QBA 0x00160 |
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| 309 | #define V3D_CLE_CT1QBA 0x00164 |
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| 310 | #define V3D_CLE_CTNQBA(n) (V3D_CLE_CT0QBA + 4 * n) |
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| 311 | #define V3D_CLE_CT0QEA 0x00168 |
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| 312 | #define V3D_CLE_CT1QEA 0x0016c |
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| 313 | #define V3D_CLE_CTNQEA(n) (V3D_CLE_CT0QEA + 4 * n) |
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| 314 | #define V3D_CLE_CT0QMA 0x00170 |
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| 315 | #define V3D_CLE_CT0QMS 0x00174 |
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| 316 | #define V3D_CLE_CT1QCFG 0x00178 |
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| 317 | /* If set without ETPROC, entirely skip tiles with no primitives. */ |
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| 318 | # define V3D_CLE_QCFG_ETFILT BIT(7) |
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| 319 | /* If set with ETFILT, just write the clear color to tiles with no |
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| 320 | * primitives. |
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| 321 | */ |
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| 322 | # define V3D_CLE_QCFG_ETPROC BIT(6) |
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| 323 | # define V3D_CLE_QCFG_ETSFLUSH BIT(1) |
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| 324 | # define V3D_CLE_QCFG_MCDIS BIT(0) |
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| 325 | |
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| 326 | #define V3D_PTB_BPCA 0x00300 |
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| 327 | #define V3D_PTB_BPCS 0x00304 |
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| 328 | #define V3D_PTB_BPOA 0x00308 |
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| 329 | #define V3D_PTB_BPOS 0x0030c |
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| 330 | |
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| 331 | #define V3D_PTB_BXCF 0x00310 |
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| 332 | # define V3D_PTB_BXCF_RWORDERDISA BIT(1) |
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| 333 | # define V3D_PTB_BXCF_CLIPDISA BIT(0) |
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| 334 | |
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| 335 | #define V3D_V3_PCTR_0_EN 0x00674 |
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| 336 | #define V3D_V3_PCTR_0_EN_ENABLE BIT(31) |
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| 337 | #define V3D_V4_PCTR_0_EN 0x00650 |
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| 338 | /* When a bit is set, resets the counter to 0. */ |
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| 339 | #define V3D_V3_PCTR_0_CLR 0x00670 |
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| 340 | #define V3D_V4_PCTR_0_CLR 0x00654 |
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| 341 | #define V3D_PCTR_0_OVERFLOW 0x00658 |
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| 342 | |
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| 343 | #define V3D_V3_PCTR_0_PCTRS0 0x00684 |
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| 344 | #define V3D_V3_PCTR_0_PCTRS15 0x00660 |
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| 345 | #define V3D_V3_PCTR_0_PCTRSX(x) (V3D_V3_PCTR_0_PCTRS0 + \ |
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| 346 | 4 * (x)) |
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| 347 | /* Each src reg muxes four counters each. */ |
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| 348 | #define V3D_V4_PCTR_0_SRC_0_3 0x00660 |
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| 349 | #define V3D_V4_PCTR_0_SRC_28_31 0x0067c |
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| 350 | #define V3D_V4_PCTR_0_SRC_X(x) (V3D_V4_PCTR_0_SRC_0_3 + \ |
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| 351 | 4 * (x)) |
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| 352 | # define V3D_PCTR_S0_MASK V3D_MASK(6, 0) |
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| 353 | # define V3D_PCTR_S0_SHIFT 0 |
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| 354 | # define V3D_PCTR_S1_MASK V3D_MASK(14, 8) |
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| 355 | # define V3D_PCTR_S1_SHIFT 8 |
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| 356 | # define V3D_PCTR_S2_MASK V3D_MASK(22, 16) |
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| 357 | # define V3D_PCTR_S2_SHIFT 16 |
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| 358 | # define V3D_PCTR_S3_MASK V3D_MASK(30, 24) |
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| 359 | # define V3D_PCTR_S3_SHIFT 24 |
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| 360 | # define V3D_PCTR_CYCLE_COUNT 32 |
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| 361 | |
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| 362 | /* Output values of the counters. */ |
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| 363 | #define V3D_PCTR_0_PCTR0 0x00680 |
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| 364 | #define V3D_PCTR_0_PCTR31 0x006fc |
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| 365 | #define V3D_PCTR_0_PCTRX(x) (V3D_PCTR_0_PCTR0 + \ |
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| 366 | 4 * (x)) |
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| 367 | #define V3D_GMP_STATUS 0x00800 |
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| 368 | # define V3D_GMP_STATUS_GMPRST BIT(31) |
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| 369 | # define V3D_GMP_STATUS_WR_COUNT_MASK V3D_MASK(30, 24) |
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| 370 | # define V3D_GMP_STATUS_WR_COUNT_SHIFT 24 |
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| 371 | # define V3D_GMP_STATUS_RD_COUNT_MASK V3D_MASK(22, 16) |
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| 372 | # define V3D_GMP_STATUS_RD_COUNT_SHIFT 16 |
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| 373 | # define V3D_GMP_STATUS_WR_ACTIVE BIT(5) |
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| 374 | # define V3D_GMP_STATUS_RD_ACTIVE BIT(4) |
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| 375 | # define V3D_GMP_STATUS_CFG_BUSY BIT(3) |
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| 376 | # define V3D_GMP_STATUS_CNTOVF BIT(2) |
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| 377 | # define V3D_GMP_STATUS_INVPROT BIT(1) |
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| 378 | # define V3D_GMP_STATUS_VIO BIT(0) |
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| 379 | |
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| 380 | #define V3D_GMP_CFG 0x00804 |
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| 381 | # define V3D_GMP_CFG_LBURSTEN BIT(3) |
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| 382 | # define V3D_GMP_CFG_PGCRSEN BIT() |
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| 383 | # define V3D_GMP_CFG_STOP_REQ BIT(1) |
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| 384 | # define V3D_GMP_CFG_PROT_ENABLE BIT(0) |
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| 385 | |
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| 386 | #define V3D_GMP_VIO_ADDR 0x00808 |
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| 387 | #define V3D_GMP_VIO_TYPE 0x0080c |
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| 388 | #define V3D_GMP_TABLE_ADDR 0x00810 |
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| 389 | #define V3D_GMP_CLEAR_LOAD 0x00814 |
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| 390 | #define V3D_GMP_PRESERVE_LOAD 0x00818 |
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| 391 | #define V3D_GMP_VALID_LINES 0x00820 |
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| 392 | |
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| 393 | #define V3D_CSD_STATUS 0x00900 |
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| 394 | # define V3D_CSD_STATUS_NUM_COMPLETED_MASK V3D_MASK(11, 4) |
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| 395 | # define V3D_CSD_STATUS_NUM_COMPLETED_SHIFT 4 |
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| 396 | # define V3D_CSD_STATUS_NUM_ACTIVE_MASK V3D_MASK(3, 2) |
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| 397 | # define V3D_CSD_STATUS_NUM_ACTIVE_SHIFT 2 |
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| 398 | # define V3D_CSD_STATUS_HAVE_CURRENT_DISPATCH BIT(1) |
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| 399 | # define V3D_CSD_STATUS_HAVE_QUEUED_DISPATCH BIT(0) |
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| 400 | |
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| 401 | #define V3D_CSD_QUEUED_CFG0 0x00904 |
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| 402 | # define V3D_CSD_QUEUED_CFG0_NUM_WGS_X_MASK V3D_MASK(31, 16) |
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| 403 | # define V3D_CSD_QUEUED_CFG0_NUM_WGS_X_SHIFT 16 |
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| 404 | # define V3D_CSD_QUEUED_CFG0_WG_X_OFFSET_MASK V3D_MASK(15, 0) |
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| 405 | # define V3D_CSD_QUEUED_CFG0_WG_X_OFFSET_SHIFT 0 |
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| 406 | |
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| 407 | #define V3D_CSD_QUEUED_CFG1 0x00908 |
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| 408 | # define V3D_CSD_QUEUED_CFG1_NUM_WGS_Y_MASK V3D_MASK(31, 16) |
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| 409 | # define V3D_CSD_QUEUED_CFG1_NUM_WGS_Y_SHIFT 16 |
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| 410 | # define V3D_CSD_QUEUED_CFG1_WG_Y_OFFSET_MASK V3D_MASK(15, 0) |
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| 411 | # define V3D_CSD_QUEUED_CFG1_WG_Y_OFFSET_SHIFT 0 |
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| 412 | |
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| 413 | #define V3D_CSD_QUEUED_CFG2 0x0090c |
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| 414 | # define V3D_CSD_QUEUED_CFG2_NUM_WGS_Z_MASK V3D_MASK(31, 16) |
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| 415 | # define V3D_CSD_QUEUED_CFG2_NUM_WGS_Z_SHIFT 16 |
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| 416 | # define V3D_CSD_QUEUED_CFG2_WG_Z_OFFSET_MASK V3D_MASK(15, 0) |
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| 417 | # define V3D_CSD_QUEUED_CFG2_WG_Z_OFFSET_SHIFT 0 |
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| 418 | |
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| 419 | #define V3D_CSD_QUEUED_CFG3 0x00910 |
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| 420 | # define V3D_CSD_QUEUED_CFG3_OVERLAP_WITH_PREV BIT(26) |
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| 421 | # define V3D_CSD_QUEUED_CFG3_MAX_SG_ID_MASK V3D_MASK(25, 20) |
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| 422 | # define V3D_CSD_QUEUED_CFG3_MAX_SG_ID_SHIFT 20 |
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| 423 | # define V3D_CSD_QUEUED_CFG3_BATCHES_PER_SG_M1_MASK V3D_MASK(19, 12) |
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| 424 | # define V3D_CSD_QUEUED_CFG3_BATCHES_PER_SG_M1_SHIFT 12 |
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| 425 | # define V3D_CSD_QUEUED_CFG3_WGS_PER_SG_MASK V3D_MASK(11, 8) |
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| 426 | # define V3D_CSD_QUEUED_CFG3_WGS_PER_SG_SHIFT 8 |
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| 427 | # define V3D_CSD_QUEUED_CFG3_WG_SIZE_MASK V3D_MASK(7, 0) |
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| 428 | # define V3D_CSD_QUEUED_CFG3_WG_SIZE_SHIFT 0 |
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| 429 | |
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| 430 | /* Number of batches, minus 1 */ |
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| 431 | #define V3D_CSD_QUEUED_CFG4 0x00914 |
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| 432 | |
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| 433 | /* Shader address, pnan, singleseg, threading, like a shader record. */ |
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| 434 | #define V3D_CSD_QUEUED_CFG5 0x00918 |
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| 435 | |
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| 436 | /* Uniforms address (4 byte aligned) */ |
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| 437 | #define V3D_CSD_QUEUED_CFG6 0x0091c |
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| 438 | |
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| 439 | #define V3D_CSD_CURRENT_CFG0 0x00920 |
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| 440 | #define V3D_CSD_CURRENT_CFG1 0x00924 |
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| 441 | #define V3D_CSD_CURRENT_CFG2 0x00928 |
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| 442 | #define V3D_CSD_CURRENT_CFG3 0x0092c |
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| 443 | #define V3D_CSD_CURRENT_CFG4 0x00930 |
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| 444 | #define V3D_CSD_CURRENT_CFG5 0x00934 |
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| 445 | #define V3D_CSD_CURRENT_CFG6 0x00938 |
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| 446 | |
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| 447 | #define V3D_CSD_CURRENT_ID0 0x0093c |
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| 448 | # define V3D_CSD_CURRENT_ID0_WG_X_MASK V3D_MASK(31, 16) |
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| 449 | # define V3D_CSD_CURRENT_ID0_WG_X_SHIFT 16 |
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| 450 | # define V3D_CSD_CURRENT_ID0_WG_IN_SG_MASK V3D_MASK(11, 8) |
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| 451 | # define V3D_CSD_CURRENT_ID0_WG_IN_SG_SHIFT 8 |
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| 452 | # define V3D_CSD_CURRENT_ID0_L_IDX_MASK V3D_MASK(7, 0) |
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| 453 | # define V3D_CSD_CURRENT_ID0_L_IDX_SHIFT 0 |
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| 454 | |
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| 455 | #define V3D_CSD_CURRENT_ID1 0x00940 |
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| 456 | # define V3D_CSD_CURRENT_ID0_WG_Z_MASK V3D_MASK(31, 16) |
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| 457 | # define V3D_CSD_CURRENT_ID0_WG_Z_SHIFT 16 |
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| 458 | # define V3D_CSD_CURRENT_ID0_WG_Y_MASK V3D_MASK(15, 0) |
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| 459 | # define V3D_CSD_CURRENT_ID0_WG_Y_SHIFT 0 |
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| 460 | |
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| 461 | #define V3D_ERR_FDBGO 0x00f04 |
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| 462 | #define V3D_ERR_FDBGB 0x00f08 |
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| 463 | #define V3D_ERR_FDBGR 0x00f0c |
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| 464 | |
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| 465 | #define V3D_ERR_FDBGS 0x00f10 |
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| 466 | # define V3D_ERR_FDBGS_INTERPZ_IP_STALL BIT(17) |
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| 467 | # define V3D_ERR_FDBGS_DEPTHO_FIFO_IP_STALL BIT(16) |
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| 468 | # define V3D_ERR_FDBGS_XYNRM_IP_STALL BIT(14) |
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| 469 | # define V3D_ERR_FDBGS_EZREQ_FIFO_OP_VALID BIT(13) |
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| 470 | # define V3D_ERR_FDBGS_QXYF_FIFO_OP_VALID BIT(12) |
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| 471 | # define V3D_ERR_FDBGS_QXYF_FIFO_OP_LAST BIT(11) |
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| 472 | # define V3D_ERR_FDBGS_EZTEST_ANYQVALID BIT(7) |
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| 473 | # define V3D_ERR_FDBGS_EZTEST_PASS BIT(6) |
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| 474 | # define V3D_ERR_FDBGS_EZTEST_QREADY BIT(5) |
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| 475 | # define V3D_ERR_FDBGS_EZTEST_VLF_OKNOVALID BIT(4) |
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| 476 | # define V3D_ERR_FDBGS_EZTEST_QSTALL BIT(3) |
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| 477 | # define V3D_ERR_FDBGS_EZTEST_IP_VLFSTALL BIT(2) |
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| 478 | # define V3D_ERR_FDBGS_EZTEST_IP_PRSTALL BIT(1) |
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| 479 | # define V3D_ERR_FDBGS_EZTEST_IP_QSTALL BIT(0) |
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| 480 | |
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| 481 | #define V3D_ERR_STAT 0x00f20 |
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| 482 | # define V3D_ERR_L2CARE BIT(15) |
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| 483 | # define V3D_ERR_VCMBE BIT(14) |
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| 484 | # define V3D_ERR_VCMRE BIT(13) |
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| 485 | # define V3D_ERR_VCDI BIT(12) |
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| 486 | # define V3D_ERR_VCDE BIT(11) |
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| 487 | # define V3D_ERR_VDWE BIT(10) |
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| 488 | # define V3D_ERR_VPMEAS BIT(9) |
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| 489 | # define V3D_ERR_VPMEFNA BIT(8) |
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| 490 | # define V3D_ERR_VPMEWNA BIT(7) |
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| 491 | # define V3D_ERR_VPMERNA BIT(6) |
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| 492 | # define V3D_ERR_VPMERR BIT(5) |
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| 493 | # define V3D_ERR_VPMEWR BIT(4) |
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| 494 | # define V3D_ERR_VPAERRGL BIT(3) |
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| 495 | # define V3D_ERR_VPAEBRGL BIT(2) |
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| 496 | # define V3D_ERR_VPAERGS BIT(1) |
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| 497 | # define V3D_ERR_VPAEABB BIT(0) |
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| 498 | |
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| 499 | #endif /* V3D_REGS_H */ |
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| 500 | |
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