| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * ZynqMP Display Controller Driver - Register Definitions |
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| 4 | * |
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| 5 | * Copyright (C) 2017 - 2020 Xilinx, Inc. |
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| 6 | * |
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| 7 | * Authors: |
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| 8 | * - Hyun Woo Kwon <hyun.kwon@xilinx.com> |
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| 9 | * - Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
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| 10 | */ |
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| 11 | |
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| 12 | #ifndef _ZYNQMP_DISP_REGS_H_ |
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| 13 | #define _ZYNQMP_DISP_REGS_H_ |
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| 14 | |
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| 15 | #include <linux/bits.h> |
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| 16 | |
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| 17 | /* Blender registers */ |
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| 18 | #define ZYNQMP_DISP_V_BLEND_BG_CLR_0 0x0 |
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| 19 | #define ZYNQMP_DISP_V_BLEND_BG_CLR_1 0x4 |
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| 20 | #define ZYNQMP_DISP_V_BLEND_BG_CLR_2 0x8 |
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| 21 | #define ZYNQMP_DISP_V_BLEND_BG_MAX 0xfff |
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| 22 | #define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA 0xc |
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| 23 | #define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_VALUE(n) ((n) << 1) |
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| 24 | #define ZYNQMP_DISP_V_BLEND_SET_GLOBAL_ALPHA_EN BIT(0) |
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| 25 | #define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT 0x14 |
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| 26 | #define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_RGB 0x0 |
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| 27 | #define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR444 0x1 |
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| 28 | #define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YCBCR422 0x2 |
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| 29 | #define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_YONLY 0x3 |
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| 30 | #define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_XVYCC 0x4 |
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| 31 | #define ZYNQMP_DISP_V_BLEND_OUTPUT_VID_FMT_EN_DOWNSAMPLE BIT(4) |
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| 32 | #define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(n) (0x18 + ((n) * 4)) |
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| 33 | #define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_EN_US BIT(0) |
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| 34 | #define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_RGB BIT(1) |
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| 35 | #define ZYNQMP_DISP_V_BLEND_LAYER_CONTROL_BYPASS BIT(8) |
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| 36 | #define ZYNQMP_DISP_V_BLEND_NUM_COEFF 9 |
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| 37 | #define ZYNQMP_DISP_V_BLEND_NUM_OFFSET 3 |
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| 38 | #define ZYNQMP_DISP_V_BLEND_RGB2YCBCR_COEFF(n) (0x20 + ((n) * 4)) |
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| 39 | #define ZYNQMP_DISP_V_BLEND_IN1CSC_COEFF(n) (0x44 + ((n) * 4)) |
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| 40 | #define ZYNQMP_DISP_V_BLEND_IN1CSC_OFFSET(n) (0x68 + ((n) * 4)) |
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| 41 | #define ZYNQMP_DISP_V_BLEND_OUTCSC_OFFSET(n) (0x74 + ((n) * 4)) |
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| 42 | #define ZYNQMP_DISP_V_BLEND_IN2CSC_COEFF(n) (0x80 + ((n) * 4)) |
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| 43 | #define ZYNQMP_DISP_V_BLEND_IN2CSC_OFFSET(n) (0xa4 + ((n) * 4)) |
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| 44 | #define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_ENABLE 0x1d0 |
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| 45 | #define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP1 0x1d4 |
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| 46 | #define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP2 0x1d8 |
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| 47 | #define ZYNQMP_DISP_V_BLEND_CHROMA_KEY_COMP3 0x1dc |
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| 48 | |
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| 49 | /* AV buffer manager registers */ |
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| 50 | #define ZYNQMP_DISP_AV_BUF_FMT 0x0 |
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| 51 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_SHIFT 0 |
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| 52 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MASK (0x1f << 0) |
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| 53 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_UYVY (0 << 0) |
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| 54 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_VYUY (1 << 0) |
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| 55 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YVYU (2 << 0) |
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| 56 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUYV (3 << 0) |
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| 57 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16 (4 << 0) |
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| 58 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24 (5 << 0) |
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| 59 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI (6 << 0) |
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| 60 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MONO (7 << 0) |
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| 61 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2 (8 << 0) |
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| 62 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUV444 (9 << 0) |
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| 63 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888 (10 << 0) |
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| 64 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGBA8880 (11 << 0) |
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| 65 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_RGB888_10 (12 << 0) |
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| 66 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUV444_10 (13 << 0) |
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| 67 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_10 (14 << 0) |
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| 68 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_10 (15 << 0) |
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| 69 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_10 (16 << 0) |
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| 70 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24_10 (17 << 0) |
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| 71 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YONLY_10 (18 << 0) |
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| 72 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420 (19 << 0) |
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| 73 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420 (20 << 0) |
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| 74 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_420 (21 << 0) |
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| 75 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16_420_10 (22 << 0) |
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| 76 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420_10 (23 << 0) |
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| 77 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI2_420_10 (24 << 0) |
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| 78 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_SHIFT 8 |
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| 79 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_MASK (0xf << 8) |
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| 80 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA8888 (0 << 8) |
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| 81 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_ABGR8888 (1 << 8) |
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| 82 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB888 (2 << 8) |
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| 83 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_BGR888 (3 << 8) |
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| 84 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA5551 (4 << 8) |
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| 85 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGBA4444 (5 << 8) |
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| 86 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_RGB565 (6 << 8) |
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| 87 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_8BPP (7 << 8) |
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| 88 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_4BPP (8 << 8) |
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| 89 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_2BPP (9 << 8) |
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| 90 | #define ZYNQMP_DISP_AV_BUF_FMT_NL_GFX_1BPP (10 << 8) |
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| 91 | #define ZYNQMP_DISP_AV_BUF_NON_LIVE_LATENCY 0x8 |
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| 92 | #define ZYNQMP_DISP_AV_BUF_CHBUF(n) (0x10 + ((n) * 4)) |
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| 93 | #define ZYNQMP_DISP_AV_BUF_CHBUF_EN BIT(0) |
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| 94 | #define ZYNQMP_DISP_AV_BUF_CHBUF_FLUSH BIT(1) |
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| 95 | #define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_SHIFT 2 |
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| 96 | #define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MASK (0xf << 2) |
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| 97 | #define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_MAX 0xf |
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| 98 | #define ZYNQMP_DISP_AV_BUF_CHBUF_BURST_LEN_AUD_MAX 0x3 |
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| 99 | #define ZYNQMP_DISP_AV_BUF_STATUS 0x28 |
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| 100 | #define ZYNQMP_DISP_AV_BUF_STC_CTRL 0x2c |
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| 101 | #define ZYNQMP_DISP_AV_BUF_STC_CTRL_EN BIT(0) |
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| 102 | #define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_SHIFT 1 |
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| 103 | #define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_EX_VSYNC 0 |
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| 104 | #define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_EX_VID 1 |
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| 105 | #define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_EX_AUD 2 |
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| 106 | #define ZYNQMP_DISP_AV_BUF_STC_CTRL_EVENT_INT_VSYNC 3 |
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| 107 | #define ZYNQMP_DISP_AV_BUF_STC_INIT_VALUE0 0x30 |
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| 108 | #define ZYNQMP_DISP_AV_BUF_STC_INIT_VALUE1 0x34 |
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| 109 | #define ZYNQMP_DISP_AV_BUF_STC_ADJ 0x38 |
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| 110 | #define ZYNQMP_DISP_AV_BUF_STC_VID_VSYNC_TS0 0x3c |
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| 111 | #define ZYNQMP_DISP_AV_BUF_STC_VID_VSYNC_TS1 0x40 |
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| 112 | #define ZYNQMP_DISP_AV_BUF_STC_EXT_VSYNC_TS0 0x44 |
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| 113 | #define ZYNQMP_DISP_AV_BUF_STC_EXT_VSYNC_TS1 0x48 |
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| 114 | #define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT_TS0 0x4c |
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| 115 | #define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT_TS1 0x50 |
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| 116 | #define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT2_TS0 0x54 |
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| 117 | #define ZYNQMP_DISP_AV_BUF_STC_CUSTOM_EVENT2_TS1 0x58 |
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| 118 | #define ZYNQMP_DISP_AV_BUF_STC_SNAPSHOT0 0x60 |
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| 119 | #define ZYNQMP_DISP_AV_BUF_STC_SNAPSHOT1 0x64 |
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| 120 | #define ZYNQMP_DISP_AV_BUF_OUTPUT 0x70 |
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| 121 | #define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_SHIFT 0 |
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| 122 | #define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MASK (0x3 << 0) |
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| 123 | #define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_LIVE (0 << 0) |
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| 124 | #define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_MEM (1 << 0) |
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| 125 | #define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_PATTERN (2 << 0) |
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| 126 | #define ZYNQMP_DISP_AV_BUF_OUTPUT_VID1_NONE (3 << 0) |
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| 127 | #define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_SHIFT 2 |
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| 128 | #define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MASK (0x3 << 2) |
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| 129 | #define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_DISABLE (0 << 2) |
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| 130 | #define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_MEM (1 << 2) |
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| 131 | #define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_LIVE (2 << 2) |
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| 132 | #define ZYNQMP_DISP_AV_BUF_OUTPUT_VID2_NONE (3 << 2) |
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| 133 | #define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_SHIFT 4 |
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| 134 | #define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MASK (0x3 << 4) |
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| 135 | #define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_PL (0 << 4) |
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| 136 | #define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_MEM (1 << 4) |
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| 137 | #define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_PATTERN (2 << 4) |
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| 138 | #define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD1_DISABLE (3 << 4) |
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| 139 | #define ZYNQMP_DISP_AV_BUF_OUTPUT_AUD2_EN BIT(6) |
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| 140 | #define ZYNQMP_DISP_AV_BUF_HCOUNT_VCOUNT_INT0 0x74 |
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| 141 | #define ZYNQMP_DISP_AV_BUF_HCOUNT_VCOUNT_INT1 0x78 |
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| 142 | #define ZYNQMP_DISP_AV_BUF_PATTERN_GEN_SELECT 0x100 |
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| 143 | #define ZYNQMP_DISP_AV_BUF_CLK_SRC 0x120 |
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| 144 | #define ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_FROM_PS BIT(0) |
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| 145 | #define ZYNQMP_DISP_AV_BUF_CLK_SRC_AUD_FROM_PS BIT(1) |
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| 146 | #define ZYNQMP_DISP_AV_BUF_CLK_SRC_VID_INTERNAL_TIMING BIT(2) |
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| 147 | #define ZYNQMP_DISP_AV_BUF_SRST_REG 0x124 |
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| 148 | #define ZYNQMP_DISP_AV_BUF_SRST_REG_VID_RST BIT(1) |
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| 149 | #define ZYNQMP_DISP_AV_BUF_AUDIO_CH_CONFIG 0x12c |
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| 150 | #define ZYNQMP_DISP_AV_BUF_GFX_COMP_SF(n) (0x200 + ((n) * 4)) |
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| 151 | #define ZYNQMP_DISP_AV_BUF_VID_COMP_SF(n) (0x20c + ((n) * 4)) |
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| 152 | #define ZYNQMP_DISP_AV_BUF_LIVD_VID_COMP_SF(n) (0x218 + ((n) * 4)) |
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| 153 | #define ZYNQMP_DISP_AV_BUF_LIVE_VID_CONFIG 0x224 |
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| 154 | #define ZYNQMP_DISP_AV_BUF_LIVD_GFX_COMP_SF(n) (0x228 + ((n) * 4)) |
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| 155 | #define ZYNQMP_DISP_AV_BUF_LIVE_GFX_CONFIG 0x234 |
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| 156 | #define ZYNQMP_DISP_AV_BUF_4BIT_SF 0x11111 |
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| 157 | #define ZYNQMP_DISP_AV_BUF_5BIT_SF 0x10842 |
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| 158 | #define ZYNQMP_DISP_AV_BUF_6BIT_SF 0x10410 |
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| 159 | #define ZYNQMP_DISP_AV_BUF_8BIT_SF 0x10101 |
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| 160 | #define ZYNQMP_DISP_AV_BUF_10BIT_SF 0x10040 |
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| 161 | #define ZYNQMP_DISP_AV_BUF_NULL_SF 0 |
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| 162 | #define ZYNQMP_DISP_AV_BUF_NUM_SF 3 |
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| 163 | #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_6 0x0 |
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| 164 | #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_8 0x1 |
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| 165 | #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_10 0x2 |
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| 166 | #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_12 0x3 |
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| 167 | #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_BPC_MASK GENMASK(2, 0) |
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| 168 | #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_RGB 0x0 |
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| 169 | #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV444 0x1 |
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| 170 | #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YUV422 0x2 |
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| 171 | #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_YONLY 0x3 |
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| 172 | #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_FMT_MASK GENMASK(5, 4) |
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| 173 | #define ZYNQMP_DISP_AV_BUF_LIVE_CONFIG_CB_FIRST BIT(8) |
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| 174 | #define ZYNQMP_DISP_AV_BUF_PALETTE_MEMORY 0x400 |
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| 175 | |
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| 176 | /* Audio registers */ |
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| 177 | #define ZYNQMP_DISP_AUD_MIXER_VOLUME 0x0 |
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| 178 | #define ZYNQMP_DISP_AUD_MIXER_VOLUME_NO_SCALE 0x20002000 |
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| 179 | #define ZYNQMP_DISP_AUD_MIXER_META_DATA 0x4 |
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| 180 | #define ZYNQMP_DISP_AUD_CH_STATUS0 0x8 |
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| 181 | #define ZYNQMP_DISP_AUD_CH_STATUS1 0xc |
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| 182 | #define ZYNQMP_DISP_AUD_CH_STATUS2 0x10 |
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| 183 | #define ZYNQMP_DISP_AUD_CH_STATUS3 0x14 |
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| 184 | #define ZYNQMP_DISP_AUD_CH_STATUS4 0x18 |
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| 185 | #define ZYNQMP_DISP_AUD_CH_STATUS5 0x1c |
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| 186 | #define ZYNQMP_DISP_AUD_CH_A_DATA0 0x20 |
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| 187 | #define ZYNQMP_DISP_AUD_CH_A_DATA1 0x24 |
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| 188 | #define ZYNQMP_DISP_AUD_CH_A_DATA2 0x28 |
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| 189 | #define ZYNQMP_DISP_AUD_CH_A_DATA3 0x2c |
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| 190 | #define ZYNQMP_DISP_AUD_CH_A_DATA4 0x30 |
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| 191 | #define ZYNQMP_DISP_AUD_CH_A_DATA5 0x34 |
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| 192 | #define ZYNQMP_DISP_AUD_CH_B_DATA0 0x38 |
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| 193 | #define ZYNQMP_DISP_AUD_CH_B_DATA1 0x3c |
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| 194 | #define ZYNQMP_DISP_AUD_CH_B_DATA2 0x40 |
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| 195 | #define ZYNQMP_DISP_AUD_CH_B_DATA3 0x44 |
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| 196 | #define ZYNQMP_DISP_AUD_CH_B_DATA4 0x48 |
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| 197 | #define ZYNQMP_DISP_AUD_CH_B_DATA5 0x4c |
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| 198 | #define ZYNQMP_DISP_AUD_SOFT_RESET 0xc00 |
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| 199 | #define ZYNQMP_DISP_AUD_SOFT_RESET_AUD_SRST BIT(0) |
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| 200 | |
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| 201 | #endif /* _ZYNQMP_DISP_REGS_H_ */ |
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| 202 | |
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