| 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
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| 2 | /* |
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| 3 | * ZynqMP DPSUB Subsystem Driver |
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| 4 | * |
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| 5 | * Copyright (C) 2017 - 2020 Xilinx, Inc. |
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| 6 | * |
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| 7 | * Authors: |
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| 8 | * - Hyun Woo Kwon <hyun.kwon@xilinx.com> |
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| 9 | * - Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
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| 10 | */ |
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| 11 | |
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| 12 | #ifndef _ZYNQMP_DPSUB_H_ |
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| 13 | #define _ZYNQMP_DPSUB_H_ |
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| 14 | |
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| 15 | struct clk; |
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| 16 | struct device; |
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| 17 | struct drm_bridge; |
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| 18 | struct zynqmp_disp; |
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| 19 | struct zynqmp_disp_layer; |
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| 20 | struct zynqmp_dp; |
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| 21 | struct zynqmp_dpsub_drm; |
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| 22 | |
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| 23 | #define ZYNQMP_DPSUB_NUM_LAYERS 2 |
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| 24 | |
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| 25 | enum zynqmp_dpsub_port { |
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| 26 | ZYNQMP_DPSUB_PORT_LIVE_VIDEO, |
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| 27 | ZYNQMP_DPSUB_PORT_LIVE_GFX, |
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| 28 | ZYNQMP_DPSUB_PORT_LIVE_AUDIO, |
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| 29 | ZYNQMP_DPSUB_PORT_OUT_VIDEO, |
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| 30 | ZYNQMP_DPSUB_PORT_OUT_AUDIO, |
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| 31 | ZYNQMP_DPSUB_PORT_OUT_DP, |
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| 32 | ZYNQMP_DPSUB_NUM_PORTS, |
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| 33 | }; |
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| 34 | |
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| 35 | enum zynqmp_dpsub_format { |
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| 36 | ZYNQMP_DPSUB_FORMAT_RGB, |
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| 37 | ZYNQMP_DPSUB_FORMAT_YCRCB444, |
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| 38 | ZYNQMP_DPSUB_FORMAT_YCRCB422, |
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| 39 | ZYNQMP_DPSUB_FORMAT_YONLY, |
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| 40 | }; |
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| 41 | |
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| 42 | /** |
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| 43 | * struct zynqmp_dpsub - ZynqMP DisplayPort Subsystem |
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| 44 | * @dev: The physical device |
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| 45 | * @apb_clk: The APB clock |
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| 46 | * @vid_clk: Video clock |
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| 47 | * @vid_clk_from_ps: True of the video clock comes from PS, false from PL |
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| 48 | * @aud_clk: Audio clock |
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| 49 | * @aud_clk_from_ps: True of the audio clock comes from PS, false from PL |
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| 50 | * @connected_ports: Bitmask of connected ports in the device tree |
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| 51 | * @dma_enabled: True if the DMA interface is enabled, false if the DPSUB is |
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| 52 | * driven by the live input |
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| 53 | * @drm: The DRM/KMS device data |
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| 54 | * @bridge: The DP encoder bridge |
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| 55 | * @disp: The display controller |
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| 56 | * @dp: The DisplayPort controller |
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| 57 | * @dma_align: DMA alignment constraint (must be a power of 2) |
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| 58 | */ |
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| 59 | struct zynqmp_dpsub { |
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| 60 | struct device *dev; |
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| 61 | |
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| 62 | struct clk *apb_clk; |
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| 63 | struct clk *vid_clk; |
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| 64 | bool vid_clk_from_ps; |
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| 65 | struct clk *aud_clk; |
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| 66 | bool aud_clk_from_ps; |
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| 67 | |
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| 68 | unsigned int connected_ports; |
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| 69 | bool dma_enabled; |
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| 70 | |
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| 71 | struct zynqmp_dpsub_drm *drm; |
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| 72 | struct drm_bridge *bridge; |
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| 73 | |
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| 74 | struct zynqmp_disp *disp; |
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| 75 | struct zynqmp_disp_layer *layers[ZYNQMP_DPSUB_NUM_LAYERS]; |
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| 76 | struct zynqmp_dp *dp; |
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| 77 | |
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| 78 | unsigned int dma_align; |
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| 79 | }; |
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| 80 | |
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| 81 | bool zynqmp_dpsub_audio_enabled(struct zynqmp_dpsub *dpsub); |
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| 82 | unsigned int zynqmp_dpsub_get_audio_clk_rate(struct zynqmp_dpsub *dpsub); |
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| 83 | |
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| 84 | void zynqmp_dpsub_release(struct zynqmp_dpsub *dpsub); |
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| 85 | |
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| 86 | #endif /* _ZYNQMP_DPSUB_H_ */ |
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| 87 | |
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