1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Synopsys DesignWare I2C adapter driver.
4 *
5 * Based on the TI DAVINCI I2C adapter driver.
6 *
7 * Copyright (C) 2006 Texas Instruments.
8 * Copyright (C) 2007 MontaVista Software Inc.
9 * Copyright (C) 2009 Provigent Ltd.
10 */
11
12#include <linux/bits.h>
13#include <linux/completion.h>
14#include <linux/errno.h>
15#include <linux/i2c.h>
16#include <linux/pm.h>
17#include <linux/regmap.h>
18#include <linux/types.h>
19
20#define DW_IC_DEFAULT_FUNCTIONALITY (I2C_FUNC_I2C | \
21 I2C_FUNC_SMBUS_BYTE | \
22 I2C_FUNC_SMBUS_BYTE_DATA | \
23 I2C_FUNC_SMBUS_WORD_DATA | \
24 I2C_FUNC_SMBUS_BLOCK_DATA | \
25 I2C_FUNC_SMBUS_I2C_BLOCK)
26
27#define DW_IC_CON_MASTER BIT(0)
28#define DW_IC_CON_SPEED_STD (1 << 1)
29#define DW_IC_CON_SPEED_FAST (2 << 1)
30#define DW_IC_CON_SPEED_HIGH (3 << 1)
31#define DW_IC_CON_SPEED_MASK GENMASK(2, 1)
32#define DW_IC_CON_10BITADDR_SLAVE BIT(3)
33#define DW_IC_CON_10BITADDR_MASTER BIT(4)
34#define DW_IC_CON_RESTART_EN BIT(5)
35#define DW_IC_CON_SLAVE_DISABLE BIT(6)
36#define DW_IC_CON_STOP_DET_IFADDRESSED BIT(7)
37#define DW_IC_CON_TX_EMPTY_CTRL BIT(8)
38#define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL BIT(9)
39#define DW_IC_CON_BUS_CLEAR_CTRL BIT(11)
40
41#define DW_IC_DATA_CMD_DAT GENMASK(7, 0)
42#define DW_IC_DATA_CMD_FIRST_DATA_BYTE BIT(11)
43
44/*
45 * Registers offset
46 */
47#define DW_IC_CON 0x00
48#define DW_IC_TAR 0x04
49#define DW_IC_SAR 0x08
50#define DW_IC_DATA_CMD 0x10
51#define DW_IC_SS_SCL_HCNT 0x14
52#define DW_IC_SS_SCL_LCNT 0x18
53#define DW_IC_FS_SCL_HCNT 0x1c
54#define DW_IC_FS_SCL_LCNT 0x20
55#define DW_IC_HS_SCL_HCNT 0x24
56#define DW_IC_HS_SCL_LCNT 0x28
57#define DW_IC_INTR_STAT 0x2c
58#define DW_IC_INTR_MASK 0x30
59#define DW_IC_RAW_INTR_STAT 0x34
60#define DW_IC_RX_TL 0x38
61#define DW_IC_TX_TL 0x3c
62#define DW_IC_CLR_INTR 0x40
63#define DW_IC_CLR_RX_UNDER 0x44
64#define DW_IC_CLR_RX_OVER 0x48
65#define DW_IC_CLR_TX_OVER 0x4c
66#define DW_IC_CLR_RD_REQ 0x50
67#define DW_IC_CLR_TX_ABRT 0x54
68#define DW_IC_CLR_RX_DONE 0x58
69#define DW_IC_CLR_ACTIVITY 0x5c
70#define DW_IC_CLR_STOP_DET 0x60
71#define DW_IC_CLR_START_DET 0x64
72#define DW_IC_CLR_GEN_CALL 0x68
73#define DW_IC_ENABLE 0x6c
74#define DW_IC_STATUS 0x70
75#define DW_IC_TXFLR 0x74
76#define DW_IC_RXFLR 0x78
77#define DW_IC_SDA_HOLD 0x7c
78#define DW_IC_TX_ABRT_SOURCE 0x80
79#define DW_IC_ENABLE_STATUS 0x9c
80#define DW_IC_CLR_RESTART_DET 0xa8
81#define DW_IC_COMP_PARAM_1 0xf4
82#define DW_IC_COMP_VERSION 0xf8
83#define DW_IC_SDA_HOLD_MIN_VERS 0x3131312A /* "111*" == v1.11* */
84#define DW_IC_COMP_TYPE 0xfc
85#define DW_IC_COMP_TYPE_VALUE 0x44570140 /* "DW" + 0x0140 */
86
87#define DW_IC_INTR_RX_UNDER BIT(0)
88#define DW_IC_INTR_RX_OVER BIT(1)
89#define DW_IC_INTR_RX_FULL BIT(2)
90#define DW_IC_INTR_TX_OVER BIT(3)
91#define DW_IC_INTR_TX_EMPTY BIT(4)
92#define DW_IC_INTR_RD_REQ BIT(5)
93#define DW_IC_INTR_TX_ABRT BIT(6)
94#define DW_IC_INTR_RX_DONE BIT(7)
95#define DW_IC_INTR_ACTIVITY BIT(8)
96#define DW_IC_INTR_STOP_DET BIT(9)
97#define DW_IC_INTR_START_DET BIT(10)
98#define DW_IC_INTR_GEN_CALL BIT(11)
99#define DW_IC_INTR_RESTART_DET BIT(12)
100#define DW_IC_INTR_MST_ON_HOLD BIT(13)
101
102#define DW_IC_INTR_DEFAULT_MASK (DW_IC_INTR_RX_FULL | \
103 DW_IC_INTR_TX_ABRT | \
104 DW_IC_INTR_STOP_DET)
105#define DW_IC_INTR_MASTER_MASK (DW_IC_INTR_DEFAULT_MASK | \
106 DW_IC_INTR_TX_EMPTY)
107#define DW_IC_INTR_SLAVE_MASK (DW_IC_INTR_DEFAULT_MASK | \
108 DW_IC_INTR_RX_UNDER | \
109 DW_IC_INTR_RD_REQ)
110
111#define DW_IC_ENABLE_ENABLE BIT(0)
112#define DW_IC_ENABLE_ABORT BIT(1)
113
114#define DW_IC_STATUS_ACTIVITY BIT(0)
115#define DW_IC_STATUS_TFE BIT(2)
116#define DW_IC_STATUS_RFNE BIT(3)
117#define DW_IC_STATUS_MASTER_ACTIVITY BIT(5)
118#define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6)
119#define DW_IC_STATUS_MASTER_HOLD_TX_FIFO_EMPTY BIT(7)
120
121#define DW_IC_SDA_HOLD_RX_SHIFT 16
122#define DW_IC_SDA_HOLD_RX_MASK GENMASK(23, 16)
123
124#define DW_IC_ERR_TX_ABRT 0x1
125
126#define DW_IC_TAR_10BITADDR_MASTER BIT(12)
127
128#define DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH (BIT(2) | BIT(3))
129#define DW_IC_COMP_PARAM_1_SPEED_MODE_MASK GENMASK(3, 2)
130
131/*
132 * Sofware status flags
133 */
134#define STATUS_ACTIVE BIT(0)
135#define STATUS_WRITE_IN_PROGRESS BIT(1)
136#define STATUS_READ_IN_PROGRESS BIT(2)
137#define STATUS_MASK GENMASK(2, 0)
138
139/*
140 * operation modes
141 */
142#define DW_IC_MASTER 0
143#define DW_IC_SLAVE 1
144
145/*
146 * Hardware abort codes from the DW_IC_TX_ABRT_SOURCE register.
147 *
148 * Only expected abort codes are listed here,
149 * refer to the datasheet for the full list.
150 */
151#define ABRT_7B_ADDR_NOACK 0
152#define ABRT_10ADDR1_NOACK 1
153#define ABRT_10ADDR2_NOACK 2
154#define ABRT_TXDATA_NOACK 3
155#define ABRT_GCALL_NOACK 4
156#define ABRT_GCALL_READ 5
157#define ABRT_SBYTE_ACKDET 7
158#define ABRT_SBYTE_NORSTRT 9
159#define ABRT_10B_RD_NORSTRT 10
160#define ABRT_MASTER_DIS 11
161#define ARB_LOST 12
162#define ABRT_SLAVE_FLUSH_TXFIFO 13
163#define ABRT_SLAVE_ARBLOST 14
164#define ABRT_SLAVE_RD_INTX 15
165
166#define DW_IC_TX_ABRT_7B_ADDR_NOACK BIT(ABRT_7B_ADDR_NOACK)
167#define DW_IC_TX_ABRT_10ADDR1_NOACK BIT(ABRT_10ADDR1_NOACK)
168#define DW_IC_TX_ABRT_10ADDR2_NOACK BIT(ABRT_10ADDR2_NOACK)
169#define DW_IC_TX_ABRT_TXDATA_NOACK BIT(ABRT_TXDATA_NOACK)
170#define DW_IC_TX_ABRT_GCALL_NOACK BIT(ABRT_GCALL_NOACK)
171#define DW_IC_TX_ABRT_GCALL_READ BIT(ABRT_GCALL_READ)
172#define DW_IC_TX_ABRT_SBYTE_ACKDET BIT(ABRT_SBYTE_ACKDET)
173#define DW_IC_TX_ABRT_SBYTE_NORSTRT BIT(ABRT_SBYTE_NORSTRT)
174#define DW_IC_TX_ABRT_10B_RD_NORSTRT BIT(ABRT_10B_RD_NORSTRT)
175#define DW_IC_TX_ABRT_MASTER_DIS BIT(ABRT_MASTER_DIS)
176#define DW_IC_TX_ARB_LOST BIT(ARB_LOST)
177#define DW_IC_RX_ABRT_SLAVE_RD_INTX BIT(ABRT_SLAVE_RD_INTX)
178#define DW_IC_RX_ABRT_SLAVE_ARBLOST BIT(ABRT_SLAVE_ARBLOST)
179#define DW_IC_RX_ABRT_SLAVE_FLUSH_TXFIFO BIT(ABRT_SLAVE_FLUSH_TXFIFO)
180
181#define DW_IC_TX_ABRT_NOACK (DW_IC_TX_ABRT_7B_ADDR_NOACK | \
182 DW_IC_TX_ABRT_10ADDR1_NOACK | \
183 DW_IC_TX_ABRT_10ADDR2_NOACK | \
184 DW_IC_TX_ABRT_TXDATA_NOACK | \
185 DW_IC_TX_ABRT_GCALL_NOACK)
186
187struct clk;
188struct device;
189struct reset_control;
190
191/**
192 * struct dw_i2c_dev - private i2c-designware data
193 * @dev: driver model device node
194 * @map: IO registers map
195 * @sysmap: System controller registers map
196 * @base: IO registers pointer
197 * @ext: Extended IO registers pointer
198 * @cmd_complete: tx completion indicator
199 * @clk: input reference clock
200 * @pclk: clock required to access the registers
201 * @rst: optional reset for the controller
202 * @slave: represent an I2C slave device
203 * @get_clk_rate_khz: callback to retrieve IP specific bus speed
204 * @cmd_err: run time hardware error code
205 * @msgs: points to an array of messages currently being transferred
206 * @msgs_num: the number of elements in msgs
207 * @msg_write_idx: the element index of the current tx message in the msgs array
208 * @tx_buf_len: the length of the current tx buffer
209 * @tx_buf: the current tx buffer
210 * @msg_read_idx: the element index of the current rx message in the msgs array
211 * @rx_buf_len: the length of the current rx buffer
212 * @rx_buf: the current rx buffer
213 * @msg_err: error status of the current transfer
214 * @status: i2c master status, one of STATUS_*
215 * @abort_source: copy of the TX_ABRT_SOURCE register
216 * @sw_mask: SW mask of DW_IC_INTR_MASK used in polling mode
217 * @irq: interrupt number for the i2c master
218 * @flags: platform specific flags like type of IO accessors or model
219 * @adapter: i2c subsystem adapter node
220 * @functionality: I2C_FUNC_* ORed bits to reflect what controller does support
221 * @master_cfg: configuration for the master device
222 * @slave_cfg: configuration for the slave device
223 * @tx_fifo_depth: depth of the hardware tx fifo
224 * @rx_fifo_depth: depth of the hardware rx fifo
225 * @rx_outstanding: current master-rx elements in tx fifo
226 * @timings: bus clock frequency, SDA hold and other timings
227 * @sda_hold_time: SDA hold value
228 * @ss_hcnt: standard speed HCNT value
229 * @ss_lcnt: standard speed LCNT value
230 * @fs_hcnt: fast speed HCNT value
231 * @fs_lcnt: fast speed LCNT value
232 * @fp_hcnt: fast plus HCNT value
233 * @fp_lcnt: fast plus LCNT value
234 * @hs_hcnt: high speed HCNT value
235 * @hs_lcnt: high speed LCNT value
236 * @acquire_lock: function to acquire a hardware lock on the bus
237 * @release_lock: function to release a hardware lock on the bus
238 * @semaphore_idx: Index of table with semaphore type attached to the bus. It's
239 * -1 if there is no semaphore.
240 * @shared_with_punit: true if this bus is shared with the SoC's PUNIT
241 * @init: function to initialize the I2C hardware
242 * @set_sda_hold_time: callback to retrieve IP specific SDA hold timing
243 * @mode: operation mode - DW_IC_MASTER or DW_IC_SLAVE
244 * @rinfo: I²C GPIO recovery information
245 * @bus_capacitance_pF: bus capacitance in picofarads
246 * @clk_freq_optimized: if this value is true, it means the hardware reduces
247 * its internal clock frequency by reducing the internal latency required
248 * to generate the high period and low period of SCL line.
249 *
250 * HCNT and LCNT parameters can be used if the platform knows more accurate
251 * values than the one computed based only on the input clock frequency.
252 * Leave them to be %0 if not used.
253 */
254struct dw_i2c_dev {
255 struct device *dev;
256 struct regmap *map;
257 struct regmap *sysmap;
258 void __iomem *base;
259 void __iomem *ext;
260 struct completion cmd_complete;
261 struct clk *clk;
262 struct clk *pclk;
263 struct reset_control *rst;
264 struct i2c_client *slave;
265 u32 (*get_clk_rate_khz) (struct dw_i2c_dev *dev);
266 int cmd_err;
267 struct i2c_msg *msgs;
268 int msgs_num;
269 int msg_write_idx;
270 u32 tx_buf_len;
271 u8 *tx_buf;
272 int msg_read_idx;
273 u32 rx_buf_len;
274 u8 *rx_buf;
275 int msg_err;
276 unsigned int status;
277 unsigned int abort_source;
278 unsigned int sw_mask;
279 int irq;
280 u32 flags;
281 struct i2c_adapter adapter;
282 u32 functionality;
283 u32 master_cfg;
284 u32 slave_cfg;
285 unsigned int tx_fifo_depth;
286 unsigned int rx_fifo_depth;
287 int rx_outstanding;
288 struct i2c_timings timings;
289 u32 sda_hold_time;
290 u16 ss_hcnt;
291 u16 ss_lcnt;
292 u16 fs_hcnt;
293 u16 fs_lcnt;
294 u16 fp_hcnt;
295 u16 fp_lcnt;
296 u16 hs_hcnt;
297 u16 hs_lcnt;
298 int (*acquire_lock)(void);
299 void (*release_lock)(void);
300 int semaphore_idx;
301 bool shared_with_punit;
302 int (*init)(struct dw_i2c_dev *dev);
303 int (*set_sda_hold_time)(struct dw_i2c_dev *dev);
304 int mode;
305 struct i2c_bus_recovery_info rinfo;
306 u32 bus_capacitance_pF;
307 bool clk_freq_optimized;
308};
309
310#define ACCESS_INTR_MASK BIT(0)
311#define ACCESS_NO_IRQ_SUSPEND BIT(1)
312#define ARBITRATION_SEMAPHORE BIT(2)
313#define ACCESS_POLLING BIT(3)
314
315#define MODEL_MSCC_OCELOT BIT(8)
316#define MODEL_BAIKAL_BT1 BIT(9)
317#define MODEL_AMD_NAVI_GPU BIT(10)
318#define MODEL_WANGXUN_SP BIT(11)
319#define MODEL_MASK GENMASK(11, 8)
320
321/*
322 * Enable UCSI interrupt by writing 0xd at register
323 * offset 0x474 specified in hardware specification.
324 */
325#define AMD_UCSI_INTR_REG 0x474
326#define AMD_UCSI_INTR_EN 0xd
327
328#define TXGBE_TX_FIFO_DEPTH 4
329#define TXGBE_RX_FIFO_DEPTH 1
330
331struct i2c_dw_semaphore_callbacks {
332 int (*probe)(struct dw_i2c_dev *dev);
333 void (*remove)(struct dw_i2c_dev *dev);
334};
335
336int i2c_dw_init_regmap(struct dw_i2c_dev *dev);
337u32 i2c_dw_scl_hcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk,
338 u32 tSYMBOL, u32 tf, int offset);
339u32 i2c_dw_scl_lcnt(struct dw_i2c_dev *dev, unsigned int reg, u32 ic_clk,
340 u32 tLOW, u32 tf, int offset);
341int i2c_dw_set_sda_hold(struct dw_i2c_dev *dev);
342u32 i2c_dw_clk_rate(struct dw_i2c_dev *dev);
343int i2c_dw_prepare_clk(struct dw_i2c_dev *dev, bool prepare);
344int i2c_dw_acquire_lock(struct dw_i2c_dev *dev);
345void i2c_dw_release_lock(struct dw_i2c_dev *dev);
346int i2c_dw_wait_bus_not_busy(struct dw_i2c_dev *dev);
347int i2c_dw_handle_tx_abort(struct dw_i2c_dev *dev);
348int i2c_dw_set_fifo_size(struct dw_i2c_dev *dev);
349u32 i2c_dw_func(struct i2c_adapter *adap);
350
351extern const struct dev_pm_ops i2c_dw_dev_pm_ops;
352
353static inline void __i2c_dw_enable(struct dw_i2c_dev *dev)
354{
355 dev->status |= STATUS_ACTIVE;
356 regmap_write(map: dev->map, DW_IC_ENABLE, val: 1);
357}
358
359static inline void __i2c_dw_disable_nowait(struct dw_i2c_dev *dev)
360{
361 regmap_write(map: dev->map, DW_IC_ENABLE, val: 0);
362 dev->status &= ~STATUS_ACTIVE;
363}
364
365static inline void __i2c_dw_write_intr_mask(struct dw_i2c_dev *dev,
366 unsigned int intr_mask)
367{
368 unsigned int val = dev->flags & ACCESS_POLLING ? 0 : intr_mask;
369
370 regmap_write(map: dev->map, DW_IC_INTR_MASK, val);
371 dev->sw_mask = intr_mask;
372}
373
374static inline void __i2c_dw_read_intr_mask(struct dw_i2c_dev *dev,
375 unsigned int *intr_mask)
376{
377 if (!(dev->flags & ACCESS_POLLING))
378 regmap_read(map: dev->map, DW_IC_INTR_MASK, val: intr_mask);
379 else
380 *intr_mask = dev->sw_mask;
381}
382
383void __i2c_dw_disable(struct dw_i2c_dev *dev);
384void i2c_dw_disable(struct dw_i2c_dev *dev);
385
386extern void i2c_dw_configure_master(struct dw_i2c_dev *dev);
387extern int i2c_dw_probe_master(struct dw_i2c_dev *dev);
388
389#if IS_ENABLED(CONFIG_I2C_DESIGNWARE_SLAVE)
390extern void i2c_dw_configure_slave(struct dw_i2c_dev *dev);
391extern int i2c_dw_probe_slave(struct dw_i2c_dev *dev);
392#else
393static inline void i2c_dw_configure_slave(struct dw_i2c_dev *dev) { }
394static inline int i2c_dw_probe_slave(struct dw_i2c_dev *dev) { return -EINVAL; }
395#endif
396
397static inline void i2c_dw_configure(struct dw_i2c_dev *dev)
398{
399 if (i2c_detect_slave_mode(dev: dev->dev))
400 i2c_dw_configure_slave(dev);
401 else
402 i2c_dw_configure_master(dev);
403}
404
405int i2c_dw_probe(struct dw_i2c_dev *dev);
406
407#if IS_ENABLED(CONFIG_I2C_DESIGNWARE_BAYTRAIL)
408int i2c_dw_baytrail_probe_lock_support(struct dw_i2c_dev *dev);
409#endif
410
411#if IS_ENABLED(CONFIG_I2C_DESIGNWARE_AMDPSP)
412int i2c_dw_amdpsp_probe_lock_support(struct dw_i2c_dev *dev);
413#endif
414
415int i2c_dw_fw_parse_and_configure(struct dw_i2c_dev *dev);
416

source code of linux/drivers/i2c/busses/i2c-designware-core.h