1/*
2 * Broadcom NetXtreme-E RoCE driver.
3 *
4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5 * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 *
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the
22 * distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 * Description: RoCE HSI File - Autogenerated
37 */
38
39#ifndef __BNXT_RE_HSI_H__
40#define __BNXT_RE_HSI_H__
41
42/* include linux/bnxt/hsi.h */
43#include <linux/bnxt/hsi.h>
44
45/* tx_doorbell (size:32b/4B) */
46struct tx_doorbell {
47 __le32 key_idx;
48 #define TX_DOORBELL_IDX_MASK 0xffffffUL
49 #define TX_DOORBELL_IDX_SFT 0
50 #define TX_DOORBELL_KEY_MASK 0xf0000000UL
51 #define TX_DOORBELL_KEY_SFT 28
52 #define TX_DOORBELL_KEY_TX (0x0UL << 28)
53 #define TX_DOORBELL_KEY_LAST TX_DOORBELL_KEY_TX
54};
55
56/* rx_doorbell (size:32b/4B) */
57struct rx_doorbell {
58 __le32 key_idx;
59 #define RX_DOORBELL_IDX_MASK 0xffffffUL
60 #define RX_DOORBELL_IDX_SFT 0
61 #define RX_DOORBELL_KEY_MASK 0xf0000000UL
62 #define RX_DOORBELL_KEY_SFT 28
63 #define RX_DOORBELL_KEY_RX (0x1UL << 28)
64 #define RX_DOORBELL_KEY_LAST RX_DOORBELL_KEY_RX
65};
66
67/* cmpl_doorbell (size:32b/4B) */
68struct cmpl_doorbell {
69 __le32 key_mask_valid_idx;
70 #define CMPL_DOORBELL_IDX_MASK 0xffffffUL
71 #define CMPL_DOORBELL_IDX_SFT 0
72 #define CMPL_DOORBELL_IDX_VALID 0x4000000UL
73 #define CMPL_DOORBELL_MASK 0x8000000UL
74 #define CMPL_DOORBELL_KEY_MASK 0xf0000000UL
75 #define CMPL_DOORBELL_KEY_SFT 28
76 #define CMPL_DOORBELL_KEY_CMPL (0x2UL << 28)
77 #define CMPL_DOORBELL_KEY_LAST CMPL_DOORBELL_KEY_CMPL
78};
79
80/* status_doorbell (size:32b/4B) */
81struct status_doorbell {
82 __le32 key_idx;
83 #define STATUS_DOORBELL_IDX_MASK 0xffffffUL
84 #define STATUS_DOORBELL_IDX_SFT 0
85 #define STATUS_DOORBELL_KEY_MASK 0xf0000000UL
86 #define STATUS_DOORBELL_KEY_SFT 28
87 #define STATUS_DOORBELL_KEY_STAT (0x3UL << 28)
88 #define STATUS_DOORBELL_KEY_LAST STATUS_DOORBELL_KEY_STAT
89};
90
91/* cmdq_init (size:128b/16B) */
92struct cmdq_init {
93 __le64 cmdq_pbl;
94 __le16 cmdq_size_cmdq_lvl;
95 #define CMDQ_INIT_CMDQ_LVL_MASK 0x3UL
96 #define CMDQ_INIT_CMDQ_LVL_SFT 0
97 #define CMDQ_INIT_CMDQ_SIZE_MASK 0xfffcUL
98 #define CMDQ_INIT_CMDQ_SIZE_SFT 2
99 __le16 creq_ring_id;
100 __le32 prod_idx;
101};
102
103/* cmdq_base (size:128b/16B) */
104struct cmdq_base {
105 u8 opcode;
106 #define CMDQ_BASE_OPCODE_CREATE_QP 0x1UL
107 #define CMDQ_BASE_OPCODE_DESTROY_QP 0x2UL
108 #define CMDQ_BASE_OPCODE_MODIFY_QP 0x3UL
109 #define CMDQ_BASE_OPCODE_QUERY_QP 0x4UL
110 #define CMDQ_BASE_OPCODE_CREATE_SRQ 0x5UL
111 #define CMDQ_BASE_OPCODE_DESTROY_SRQ 0x6UL
112 #define CMDQ_BASE_OPCODE_QUERY_SRQ 0x8UL
113 #define CMDQ_BASE_OPCODE_CREATE_CQ 0x9UL
114 #define CMDQ_BASE_OPCODE_DESTROY_CQ 0xaUL
115 #define CMDQ_BASE_OPCODE_RESIZE_CQ 0xcUL
116 #define CMDQ_BASE_OPCODE_ALLOCATE_MRW 0xdUL
117 #define CMDQ_BASE_OPCODE_DEALLOCATE_KEY 0xeUL
118 #define CMDQ_BASE_OPCODE_REGISTER_MR 0xfUL
119 #define CMDQ_BASE_OPCODE_DEREGISTER_MR 0x10UL
120 #define CMDQ_BASE_OPCODE_ADD_GID 0x11UL
121 #define CMDQ_BASE_OPCODE_DELETE_GID 0x12UL
122 #define CMDQ_BASE_OPCODE_MODIFY_GID 0x17UL
123 #define CMDQ_BASE_OPCODE_QUERY_GID 0x18UL
124 #define CMDQ_BASE_OPCODE_CREATE_QP1 0x13UL
125 #define CMDQ_BASE_OPCODE_DESTROY_QP1 0x14UL
126 #define CMDQ_BASE_OPCODE_CREATE_AH 0x15UL
127 #define CMDQ_BASE_OPCODE_DESTROY_AH 0x16UL
128 #define CMDQ_BASE_OPCODE_INITIALIZE_FW 0x80UL
129 #define CMDQ_BASE_OPCODE_DEINITIALIZE_FW 0x81UL
130 #define CMDQ_BASE_OPCODE_STOP_FUNC 0x82UL
131 #define CMDQ_BASE_OPCODE_QUERY_FUNC 0x83UL
132 #define CMDQ_BASE_OPCODE_SET_FUNC_RESOURCES 0x84UL
133 #define CMDQ_BASE_OPCODE_READ_CONTEXT 0x85UL
134 #define CMDQ_BASE_OPCODE_VF_BACKCHANNEL_REQUEST 0x86UL
135 #define CMDQ_BASE_OPCODE_READ_VF_MEMORY 0x87UL
136 #define CMDQ_BASE_OPCODE_COMPLETE_VF_REQUEST 0x88UL
137 #define CMDQ_BASE_OPCODE_EXTEND_CONTEXT_ARRRAY 0x89UL
138 #define CMDQ_BASE_OPCODE_MAP_TC_TO_COS 0x8aUL
139 #define CMDQ_BASE_OPCODE_QUERY_VERSION 0x8bUL
140 #define CMDQ_BASE_OPCODE_MODIFY_ROCE_CC 0x8cUL
141 #define CMDQ_BASE_OPCODE_QUERY_ROCE_CC 0x8dUL
142 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS 0x8eUL
143 #define CMDQ_BASE_OPCODE_SET_LINK_AGGR_MODE 0x8fUL
144 #define CMDQ_BASE_OPCODE_MODIFY_CQ 0x90UL
145 #define CMDQ_BASE_OPCODE_QUERY_QP_EXTEND 0x91UL
146 #define CMDQ_BASE_OPCODE_QUERY_ROCE_STATS_EXT 0x92UL
147 #define CMDQ_BASE_OPCODE_ROCE_MIRROR_CFG 0x99UL
148 #define CMDQ_BASE_OPCODE_LAST CMDQ_BASE_OPCODE_ROCE_MIRROR_CFG
149 u8 cmd_size;
150 __le16 flags;
151 __le16 cookie;
152 u8 resp_size;
153 u8 reserved8;
154 __le64 resp_addr;
155};
156
157/* creq_base (size:128b/16B) */
158struct creq_base {
159 u8 type;
160 #define CREQ_BASE_TYPE_MASK 0x3fUL
161 #define CREQ_BASE_TYPE_SFT 0
162 #define CREQ_BASE_TYPE_QP_EVENT 0x38UL
163 #define CREQ_BASE_TYPE_FUNC_EVENT 0x3aUL
164 #define CREQ_BASE_TYPE_LAST CREQ_BASE_TYPE_FUNC_EVENT
165 u8 reserved56[7];
166 u8 v;
167 #define CREQ_BASE_V 0x1UL
168 u8 event;
169 u8 reserved48[6];
170};
171
172/* cmdq_query_version (size:128b/16B) */
173struct cmdq_query_version {
174 u8 opcode;
175 #define CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION 0x8bUL
176 #define CMDQ_QUERY_VERSION_OPCODE_LAST CMDQ_QUERY_VERSION_OPCODE_QUERY_VERSION
177 u8 cmd_size;
178 __le16 flags;
179 __le16 cookie;
180 u8 resp_size;
181 u8 reserved8;
182 __le64 resp_addr;
183};
184
185/* creq_query_version_resp (size:128b/16B) */
186struct creq_query_version_resp {
187 u8 type;
188 #define CREQ_QUERY_VERSION_RESP_TYPE_MASK 0x3fUL
189 #define CREQ_QUERY_VERSION_RESP_TYPE_SFT 0
190 #define CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT 0x38UL
191 #define CREQ_QUERY_VERSION_RESP_TYPE_LAST CREQ_QUERY_VERSION_RESP_TYPE_QP_EVENT
192 u8 status;
193 __le16 cookie;
194 u8 fw_maj;
195 u8 fw_minor;
196 u8 fw_bld;
197 u8 fw_rsvd;
198 u8 v;
199 #define CREQ_QUERY_VERSION_RESP_V 0x1UL
200 u8 event;
201 #define CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION 0x8bUL
202 #define CREQ_QUERY_VERSION_RESP_EVENT_LAST \
203 CREQ_QUERY_VERSION_RESP_EVENT_QUERY_VERSION
204 __le16 reserved16;
205 u8 intf_maj;
206 u8 intf_minor;
207 u8 intf_bld;
208 u8 intf_rsvd;
209};
210
211/* cmdq_initialize_fw (size:896b/112B) */
212struct cmdq_initialize_fw {
213 u8 opcode;
214 #define CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW 0x80UL
215 #define CMDQ_INITIALIZE_FW_OPCODE_LAST CMDQ_INITIALIZE_FW_OPCODE_INITIALIZE_FW
216 u8 cmd_size;
217 __le16 flags;
218 #define CMDQ_INITIALIZE_FW_FLAGS_MRAV_RESERVATION_SPLIT 0x1UL
219 #define CMDQ_INITIALIZE_FW_FLAGS_HW_REQUESTER_RETX_SUPPORTED 0x2UL
220 #define CMDQ_INITIALIZE_FW_FLAGS_OPTIMIZE_MODIFY_QP_SUPPORTED 0x8UL
221 #define CMDQ_INITIALIZE_FW_FLAGS_L2_VF_RESOURCE_MGMT 0x10UL
222 #define CMDQ_INITIALIZE_FW_FLAGS_MIRROR_ON_ROCE_SUPPORTED 0x80UL
223 __le16 cookie;
224 u8 resp_size;
225 u8 reserved8;
226 __le64 resp_addr;
227 u8 qpc_pg_size_qpc_lvl;
228 #define CMDQ_INITIALIZE_FW_QPC_LVL_MASK 0xfUL
229 #define CMDQ_INITIALIZE_FW_QPC_LVL_SFT 0
230 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_0 0x0UL
231 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_1 0x1UL
232 #define CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2 0x2UL
233 #define CMDQ_INITIALIZE_FW_QPC_LVL_LAST CMDQ_INITIALIZE_FW_QPC_LVL_LVL_2
234 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_MASK 0xf0UL
235 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_SFT 4
236 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_4K (0x0UL << 4)
237 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8K (0x1UL << 4)
238 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_64K (0x2UL << 4)
239 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_2M (0x3UL << 4)
240 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_8M (0x4UL << 4)
241 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G (0x5UL << 4)
242 #define CMDQ_INITIALIZE_FW_QPC_PG_SIZE_LAST CMDQ_INITIALIZE_FW_QPC_PG_SIZE_PG_1G
243 u8 mrw_pg_size_mrw_lvl;
244 #define CMDQ_INITIALIZE_FW_MRW_LVL_MASK 0xfUL
245 #define CMDQ_INITIALIZE_FW_MRW_LVL_SFT 0
246 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_0 0x0UL
247 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_1 0x1UL
248 #define CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2 0x2UL
249 #define CMDQ_INITIALIZE_FW_MRW_LVL_LAST CMDQ_INITIALIZE_FW_MRW_LVL_LVL_2
250 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_MASK 0xf0UL
251 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_SFT 4
252 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_4K (0x0UL << 4)
253 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8K (0x1UL << 4)
254 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_64K (0x2UL << 4)
255 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_2M (0x3UL << 4)
256 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_8M (0x4UL << 4)
257 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G (0x5UL << 4)
258 #define CMDQ_INITIALIZE_FW_MRW_PG_SIZE_LAST CMDQ_INITIALIZE_FW_MRW_PG_SIZE_PG_1G
259 u8 srq_pg_size_srq_lvl;
260 #define CMDQ_INITIALIZE_FW_SRQ_LVL_MASK 0xfUL
261 #define CMDQ_INITIALIZE_FW_SRQ_LVL_SFT 0
262 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_0 0x0UL
263 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_1 0x1UL
264 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2 0x2UL
265 #define CMDQ_INITIALIZE_FW_SRQ_LVL_LAST CMDQ_INITIALIZE_FW_SRQ_LVL_LVL_2
266 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_MASK 0xf0UL
267 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_SFT 4
268 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_4K (0x0UL << 4)
269 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8K (0x1UL << 4)
270 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_64K (0x2UL << 4)
271 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_2M (0x3UL << 4)
272 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_8M (0x4UL << 4)
273 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G (0x5UL << 4)
274 #define CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_SRQ_PG_SIZE_PG_1G
275 u8 cq_pg_size_cq_lvl;
276 #define CMDQ_INITIALIZE_FW_CQ_LVL_MASK 0xfUL
277 #define CMDQ_INITIALIZE_FW_CQ_LVL_SFT 0
278 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_0 0x0UL
279 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_1 0x1UL
280 #define CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2 0x2UL
281 #define CMDQ_INITIALIZE_FW_CQ_LVL_LAST CMDQ_INITIALIZE_FW_CQ_LVL_LVL_2
282 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_MASK 0xf0UL
283 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_SFT 4
284 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_4K (0x0UL << 4)
285 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8K (0x1UL << 4)
286 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_64K (0x2UL << 4)
287 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_2M (0x3UL << 4)
288 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_8M (0x4UL << 4)
289 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G (0x5UL << 4)
290 #define CMDQ_INITIALIZE_FW_CQ_PG_SIZE_LAST CMDQ_INITIALIZE_FW_CQ_PG_SIZE_PG_1G
291 u8 tqm_pg_size_tqm_lvl;
292 #define CMDQ_INITIALIZE_FW_TQM_LVL_MASK 0xfUL
293 #define CMDQ_INITIALIZE_FW_TQM_LVL_SFT 0
294 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_0 0x0UL
295 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_1 0x1UL
296 #define CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2 0x2UL
297 #define CMDQ_INITIALIZE_FW_TQM_LVL_LAST CMDQ_INITIALIZE_FW_TQM_LVL_LVL_2
298 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_MASK 0xf0UL
299 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_SFT 4
300 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_4K (0x0UL << 4)
301 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8K (0x1UL << 4)
302 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_64K (0x2UL << 4)
303 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_2M (0x3UL << 4)
304 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_8M (0x4UL << 4)
305 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G (0x5UL << 4)
306 #define CMDQ_INITIALIZE_FW_TQM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TQM_PG_SIZE_PG_1G
307 u8 tim_pg_size_tim_lvl;
308 #define CMDQ_INITIALIZE_FW_TIM_LVL_MASK 0xfUL
309 #define CMDQ_INITIALIZE_FW_TIM_LVL_SFT 0
310 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_0 0x0UL
311 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_1 0x1UL
312 #define CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2 0x2UL
313 #define CMDQ_INITIALIZE_FW_TIM_LVL_LAST CMDQ_INITIALIZE_FW_TIM_LVL_LVL_2
314 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_MASK 0xf0UL
315 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_SFT 4
316 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_4K (0x0UL << 4)
317 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8K (0x1UL << 4)
318 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_64K (0x2UL << 4)
319 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_2M (0x3UL << 4)
320 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_8M (0x4UL << 4)
321 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G (0x5UL << 4)
322 #define CMDQ_INITIALIZE_FW_TIM_PG_SIZE_LAST CMDQ_INITIALIZE_FW_TIM_PG_SIZE_PG_1G
323 __le16 log2_dbr_pg_size;
324 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_MASK 0xfUL
325 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_SFT 0
326 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4K 0x0UL
327 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8K 0x1UL
328 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16K 0x2UL
329 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32K 0x3UL
330 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64K 0x4UL
331 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128K 0x5UL
332 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_256K 0x6UL
333 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_512K 0x7UL
334 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_1M 0x8UL
335 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_2M 0x9UL
336 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_4M 0xaUL
337 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_8M 0xbUL
338 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_16M 0xcUL
339 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_32M 0xdUL
340 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_64M 0xeUL
341 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M 0xfUL
342 #define CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_LAST \
343 CMDQ_INITIALIZE_FW_LOG2_DBR_PG_SIZE_PG_128M
344 #define CMDQ_INITIALIZE_FW_RSVD_MASK 0xfff0UL
345 #define CMDQ_INITIALIZE_FW_RSVD_SFT 4
346 __le64 qpc_page_dir;
347 __le64 mrw_page_dir;
348 __le64 srq_page_dir;
349 __le64 cq_page_dir;
350 __le64 tqm_page_dir;
351 __le64 tim_page_dir;
352 __le32 number_of_qp;
353 __le32 number_of_mrw;
354 __le32 number_of_srq;
355 __le32 number_of_cq;
356 __le32 max_qp_per_vf;
357 __le32 max_mrw_per_vf;
358 __le32 max_srq_per_vf;
359 __le32 max_cq_per_vf;
360 __le32 max_gid_per_vf;
361 __le32 stat_ctx_id;
362};
363
364/* creq_initialize_fw_resp (size:128b/16B) */
365struct creq_initialize_fw_resp {
366 u8 type;
367 #define CREQ_INITIALIZE_FW_RESP_TYPE_MASK 0x3fUL
368 #define CREQ_INITIALIZE_FW_RESP_TYPE_SFT 0
369 #define CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL
370 #define CREQ_INITIALIZE_FW_RESP_TYPE_LAST CREQ_INITIALIZE_FW_RESP_TYPE_QP_EVENT
371 u8 status;
372 __le16 cookie;
373 __le32 reserved32;
374 u8 v;
375 #define CREQ_INITIALIZE_FW_RESP_V 0x1UL
376 u8 event;
377 #define CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW 0x80UL
378 #define CREQ_INITIALIZE_FW_RESP_EVENT_LAST \
379 CREQ_INITIALIZE_FW_RESP_EVENT_INITIALIZE_FW
380 u8 reserved48[6];
381};
382
383/* cmdq_deinitialize_fw (size:128b/16B) */
384struct cmdq_deinitialize_fw {
385 u8 opcode;
386 #define CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW 0x81UL
387 #define CMDQ_DEINITIALIZE_FW_OPCODE_LAST \
388 CMDQ_DEINITIALIZE_FW_OPCODE_DEINITIALIZE_FW
389 u8 cmd_size;
390 __le16 flags;
391 __le16 cookie;
392 u8 resp_size;
393 u8 reserved8;
394 __le64 resp_addr;
395};
396
397/* creq_deinitialize_fw_resp (size:128b/16B) */
398struct creq_deinitialize_fw_resp {
399 u8 type;
400 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_MASK 0x3fUL
401 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_SFT 0
402 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT 0x38UL
403 #define CREQ_DEINITIALIZE_FW_RESP_TYPE_LAST CREQ_DEINITIALIZE_FW_RESP_TYPE_QP_EVENT
404 u8 status;
405 __le16 cookie;
406 __le32 reserved32;
407 u8 v;
408 #define CREQ_DEINITIALIZE_FW_RESP_V 0x1UL
409 u8 event;
410 #define CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW 0x81UL
411 #define CREQ_DEINITIALIZE_FW_RESP_EVENT_LAST \
412 CREQ_DEINITIALIZE_FW_RESP_EVENT_DEINITIALIZE_FW
413 u8 reserved48[6];
414};
415
416/* cmdq_create_qp (size:832b/104B) */
417struct cmdq_create_qp {
418 u8 opcode;
419 #define CMDQ_CREATE_QP_OPCODE_CREATE_QP 0x1UL
420 #define CMDQ_CREATE_QP_OPCODE_LAST CMDQ_CREATE_QP_OPCODE_CREATE_QP
421 u8 cmd_size;
422 __le16 flags;
423 __le16 cookie;
424 u8 resp_size;
425 u8 reserved8;
426 __le64 resp_addr;
427 __le64 qp_handle;
428 __le32 qp_flags;
429 #define CMDQ_CREATE_QP_QP_FLAGS_SRQ_USED 0x1UL
430 #define CMDQ_CREATE_QP_QP_FLAGS_FORCE_COMPLETION 0x2UL
431 #define CMDQ_CREATE_QP_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL
432 #define CMDQ_CREATE_QP_QP_FLAGS_FR_PMR_ENABLED 0x8UL
433 #define CMDQ_CREATE_QP_QP_FLAGS_VARIABLE_SIZED_WQE_ENABLED 0x10UL
434 #define CMDQ_CREATE_QP_QP_FLAGS_OPTIMIZED_TRANSMIT_ENABLED 0x20UL
435 #define CMDQ_CREATE_QP_QP_FLAGS_RESPONDER_UD_CQE_WITH_CFA 0x40UL
436 #define CMDQ_CREATE_QP_QP_FLAGS_EXT_STATS_ENABLED 0x80UL
437 #define CMDQ_CREATE_QP_QP_FLAGS_EXPRESS_MODE_ENABLED 0x100UL
438 #define CMDQ_CREATE_QP_QP_FLAGS_STEERING_TAG_VALID 0x200UL
439 #define CMDQ_CREATE_QP_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED 0x400UL
440 #define CMDQ_CREATE_QP_QP_FLAGS_LAST \
441 CMDQ_CREATE_QP_QP_FLAGS_RDMA_READ_OR_ATOMICS_USED
442 u8 type;
443 #define CMDQ_CREATE_QP_TYPE_RC 0x2UL
444 #define CMDQ_CREATE_QP_TYPE_UD 0x4UL
445 #define CMDQ_CREATE_QP_TYPE_RAW_ETHERTYPE 0x6UL
446 #define CMDQ_CREATE_QP_TYPE_GSI 0x7UL
447 #define CMDQ_CREATE_QP_TYPE_LAST CMDQ_CREATE_QP_TYPE_GSI
448 u8 sq_pg_size_sq_lvl;
449 #define CMDQ_CREATE_QP_SQ_LVL_MASK 0xfUL
450 #define CMDQ_CREATE_QP_SQ_LVL_SFT 0
451 #define CMDQ_CREATE_QP_SQ_LVL_LVL_0 0x0UL
452 #define CMDQ_CREATE_QP_SQ_LVL_LVL_1 0x1UL
453 #define CMDQ_CREATE_QP_SQ_LVL_LVL_2 0x2UL
454 #define CMDQ_CREATE_QP_SQ_LVL_LAST CMDQ_CREATE_QP_SQ_LVL_LVL_2
455 #define CMDQ_CREATE_QP_SQ_PG_SIZE_MASK 0xf0UL
456 #define CMDQ_CREATE_QP_SQ_PG_SIZE_SFT 4
457 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_4K (0x0UL << 4)
458 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8K (0x1UL << 4)
459 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_64K (0x2UL << 4)
460 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_2M (0x3UL << 4)
461 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_8M (0x4UL << 4)
462 #define CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G (0x5UL << 4)
463 #define CMDQ_CREATE_QP_SQ_PG_SIZE_LAST CMDQ_CREATE_QP_SQ_PG_SIZE_PG_1G
464 u8 rq_pg_size_rq_lvl;
465 #define CMDQ_CREATE_QP_RQ_LVL_MASK 0xfUL
466 #define CMDQ_CREATE_QP_RQ_LVL_SFT 0
467 #define CMDQ_CREATE_QP_RQ_LVL_LVL_0 0x0UL
468 #define CMDQ_CREATE_QP_RQ_LVL_LVL_1 0x1UL
469 #define CMDQ_CREATE_QP_RQ_LVL_LVL_2 0x2UL
470 #define CMDQ_CREATE_QP_RQ_LVL_LAST CMDQ_CREATE_QP_RQ_LVL_LVL_2
471 #define CMDQ_CREATE_QP_RQ_PG_SIZE_MASK 0xf0UL
472 #define CMDQ_CREATE_QP_RQ_PG_SIZE_SFT 4
473 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_4K (0x0UL << 4)
474 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8K (0x1UL << 4)
475 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_64K (0x2UL << 4)
476 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_2M (0x3UL << 4)
477 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_8M (0x4UL << 4)
478 #define CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G (0x5UL << 4)
479 #define CMDQ_CREATE_QP_RQ_PG_SIZE_LAST CMDQ_CREATE_QP_RQ_PG_SIZE_PG_1G
480 u8 unused_0;
481 __le32 dpi;
482 __le32 sq_size;
483 __le32 rq_size;
484 __le16 sq_fwo_sq_sge;
485 #define CMDQ_CREATE_QP_SQ_SGE_MASK 0xfUL
486 #define CMDQ_CREATE_QP_SQ_SGE_SFT 0
487 #define CMDQ_CREATE_QP_SQ_FWO_MASK 0xfff0UL
488 #define CMDQ_CREATE_QP_SQ_FWO_SFT 4
489 __le16 rq_fwo_rq_sge;
490 #define CMDQ_CREATE_QP_RQ_SGE_MASK 0xfUL
491 #define CMDQ_CREATE_QP_RQ_SGE_SFT 0
492 #define CMDQ_CREATE_QP_RQ_FWO_MASK 0xfff0UL
493 #define CMDQ_CREATE_QP_RQ_FWO_SFT 4
494 __le32 scq_cid;
495 __le32 rcq_cid;
496 __le32 srq_cid;
497 __le32 pd_id;
498 __le64 sq_pbl;
499 __le64 rq_pbl;
500 __le64 irrq_addr;
501 __le64 orrq_addr;
502 __le32 request_xid;
503 __le16 steering_tag;
504 __le16 reserved16;
505};
506
507/* creq_create_qp_resp (size:128b/16B) */
508struct creq_create_qp_resp {
509 u8 type;
510 #define CREQ_CREATE_QP_RESP_TYPE_MASK 0x3fUL
511 #define CREQ_CREATE_QP_RESP_TYPE_SFT 0
512 #define CREQ_CREATE_QP_RESP_TYPE_QP_EVENT 0x38UL
513 #define CREQ_CREATE_QP_RESP_TYPE_LAST CREQ_CREATE_QP_RESP_TYPE_QP_EVENT
514 u8 status;
515 __le16 cookie;
516 __le32 xid;
517 u8 v;
518 #define CREQ_CREATE_QP_RESP_V 0x1UL
519 u8 event;
520 #define CREQ_CREATE_QP_RESP_EVENT_CREATE_QP 0x1UL
521 #define CREQ_CREATE_QP_RESP_EVENT_LAST CREQ_CREATE_QP_RESP_EVENT_CREATE_QP
522 u8 optimized_transmit_enabled;
523 u8 reserved48[5];
524};
525
526/* cmdq_destroy_qp (size:192b/24B) */
527struct cmdq_destroy_qp {
528 u8 opcode;
529 #define CMDQ_DESTROY_QP_OPCODE_DESTROY_QP 0x2UL
530 #define CMDQ_DESTROY_QP_OPCODE_LAST CMDQ_DESTROY_QP_OPCODE_DESTROY_QP
531 u8 cmd_size;
532 __le16 flags;
533 __le16 cookie;
534 u8 resp_size;
535 u8 reserved8;
536 __le64 resp_addr;
537 __le32 qp_cid;
538 __le32 unused_0;
539};
540
541/* creq_destroy_qp_resp (size:128b/16B) */
542struct creq_destroy_qp_resp {
543 u8 type;
544 #define CREQ_DESTROY_QP_RESP_TYPE_MASK 0x3fUL
545 #define CREQ_DESTROY_QP_RESP_TYPE_SFT 0
546 #define CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT 0x38UL
547 #define CREQ_DESTROY_QP_RESP_TYPE_LAST CREQ_DESTROY_QP_RESP_TYPE_QP_EVENT
548 u8 status;
549 __le16 cookie;
550 __le32 xid;
551 u8 v;
552 #define CREQ_DESTROY_QP_RESP_V 0x1UL
553 u8 event;
554 #define CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP 0x2UL
555 #define CREQ_DESTROY_QP_RESP_EVENT_LAST CREQ_DESTROY_QP_RESP_EVENT_DESTROY_QP
556 u8 reserved48[6];
557};
558
559/* cmdq_modify_qp (size:1024b/128B) */
560struct cmdq_modify_qp {
561 u8 opcode;
562 #define CMDQ_MODIFY_QP_OPCODE_MODIFY_QP 0x3UL
563 #define CMDQ_MODIFY_QP_OPCODE_LAST CMDQ_MODIFY_QP_OPCODE_MODIFY_QP
564 u8 cmd_size;
565 __le16 flags;
566 #define CMDQ_MODIFY_QP_FLAGS_SRQ_USED 0x1UL
567 __le16 cookie;
568 u8 resp_size;
569 u8 qp_type;
570 #define CMDQ_MODIFY_QP_QP_TYPE_RC 0x2UL
571 #define CMDQ_MODIFY_QP_QP_TYPE_UD 0x4UL
572 #define CMDQ_MODIFY_QP_QP_TYPE_RAW_ETHERTYPE 0x6UL
573 #define CMDQ_MODIFY_QP_QP_TYPE_GSI 0x7UL
574 #define CMDQ_MODIFY_QP_QP_TYPE_LAST CMDQ_MODIFY_QP_QP_TYPE_GSI
575 __le64 resp_addr;
576 __le32 modify_mask;
577 #define CMDQ_MODIFY_QP_MODIFY_MASK_STATE 0x1UL
578 #define CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY 0x2UL
579 #define CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS 0x4UL
580 #define CMDQ_MODIFY_QP_MODIFY_MASK_PKEY 0x8UL
581 #define CMDQ_MODIFY_QP_MODIFY_MASK_QKEY 0x10UL
582 #define CMDQ_MODIFY_QP_MODIFY_MASK_DGID 0x20UL
583 #define CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL 0x40UL
584 #define CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX 0x80UL
585 #define CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT 0x100UL
586 #define CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS 0x200UL
587 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC 0x400UL
588 #define CMDQ_MODIFY_QP_MODIFY_MASK_PINGPONG_PUSH_MODE 0x800UL
589 #define CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU 0x1000UL
590 #define CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT 0x2000UL
591 #define CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT 0x4000UL
592 #define CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY 0x8000UL
593 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN 0x10000UL
594 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC 0x20000UL
595 #define CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER 0x40000UL
596 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN 0x80000UL
597 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC 0x100000UL
598 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE 0x200000UL
599 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE 0x400000UL
600 #define CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE 0x800000UL
601 #define CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE 0x1000000UL
602 #define CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA 0x2000000UL
603 #define CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID 0x4000000UL
604 #define CMDQ_MODIFY_QP_MODIFY_MASK_SRC_MAC 0x8000000UL
605 #define CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID 0x10000000UL
606 #define CMDQ_MODIFY_QP_MODIFY_MASK_ENABLE_CC 0x20000000UL
607 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_ECN 0x40000000UL
608 #define CMDQ_MODIFY_QP_MODIFY_MASK_TOS_DSCP 0x80000000UL
609 __le32 qp_cid;
610 u8 network_type_en_sqd_async_notify_new_state;
611 #define CMDQ_MODIFY_QP_NEW_STATE_MASK 0xfUL
612 #define CMDQ_MODIFY_QP_NEW_STATE_SFT 0
613 #define CMDQ_MODIFY_QP_NEW_STATE_RESET 0x0UL
614 #define CMDQ_MODIFY_QP_NEW_STATE_INIT 0x1UL
615 #define CMDQ_MODIFY_QP_NEW_STATE_RTR 0x2UL
616 #define CMDQ_MODIFY_QP_NEW_STATE_RTS 0x3UL
617 #define CMDQ_MODIFY_QP_NEW_STATE_SQD 0x4UL
618 #define CMDQ_MODIFY_QP_NEW_STATE_SQE 0x5UL
619 #define CMDQ_MODIFY_QP_NEW_STATE_ERR 0x6UL
620 #define CMDQ_MODIFY_QP_NEW_STATE_LAST CMDQ_MODIFY_QP_NEW_STATE_ERR
621 #define CMDQ_MODIFY_QP_EN_SQD_ASYNC_NOTIFY 0x10UL
622 #define CMDQ_MODIFY_QP_UNUSED1 0x20UL
623 #define CMDQ_MODIFY_QP_NETWORK_TYPE_MASK 0xc0UL
624 #define CMDQ_MODIFY_QP_NETWORK_TYPE_SFT 6
625 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1 (0x0UL << 6)
626 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4 (0x2UL << 6)
627 #define CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6 (0x3UL << 6)
628 #define CMDQ_MODIFY_QP_NETWORK_TYPE_LAST CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6
629 u8 access;
630 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK 0xffUL
631 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT 0
632 #define CMDQ_MODIFY_QP_ACCESS_LOCAL_WRITE 0x1UL
633 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE 0x2UL
634 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_READ 0x4UL
635 #define CMDQ_MODIFY_QP_ACCESS_REMOTE_ATOMIC 0x8UL
636 __le16 pkey;
637 __le32 qkey;
638 __le32 dgid[4];
639 __le32 flow_label;
640 __le16 sgid_index;
641 u8 hop_limit;
642 u8 traffic_class;
643 __le16 dest_mac[3];
644 u8 tos_dscp_tos_ecn;
645 #define CMDQ_MODIFY_QP_TOS_ECN_MASK 0x3UL
646 #define CMDQ_MODIFY_QP_TOS_ECN_SFT 0
647 #define CMDQ_MODIFY_QP_TOS_DSCP_MASK 0xfcUL
648 #define CMDQ_MODIFY_QP_TOS_DSCP_SFT 2
649 u8 path_mtu_pingpong_push_enable;
650 #define CMDQ_MODIFY_QP_PINGPONG_PUSH_ENABLE 0x1UL
651 #define CMDQ_MODIFY_QP_UNUSED3_MASK 0xeUL
652 #define CMDQ_MODIFY_QP_UNUSED3_SFT 1
653 #define CMDQ_MODIFY_QP_PATH_MTU_MASK 0xf0UL
654 #define CMDQ_MODIFY_QP_PATH_MTU_SFT 4
655 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_256 (0x0UL << 4)
656 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_512 (0x1UL << 4)
657 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_1024 (0x2UL << 4)
658 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_2048 (0x3UL << 4)
659 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_4096 (0x4UL << 4)
660 #define CMDQ_MODIFY_QP_PATH_MTU_MTU_8192 (0x5UL << 4)
661 #define CMDQ_MODIFY_QP_PATH_MTU_LAST CMDQ_MODIFY_QP_PATH_MTU_MTU_8192
662 u8 timeout;
663 u8 retry_cnt;
664 u8 rnr_retry;
665 u8 min_rnr_timer;
666 __le32 rq_psn;
667 __le32 sq_psn;
668 u8 max_rd_atomic;
669 u8 max_dest_rd_atomic;
670 __le16 enable_cc;
671 #define CMDQ_MODIFY_QP_ENABLE_CC 0x1UL
672 #define CMDQ_MODIFY_QP_UNUSED15_MASK 0xfffeUL
673 #define CMDQ_MODIFY_QP_UNUSED15_SFT 1
674 __le32 sq_size;
675 __le32 rq_size;
676 __le16 sq_sge;
677 __le16 rq_sge;
678 __le32 max_inline_data;
679 __le32 dest_qp_id;
680 __le32 pingpong_push_dpi;
681 __le16 src_mac[3];
682 __le16 vlan_pcp_vlan_dei_vlan_id;
683 #define CMDQ_MODIFY_QP_VLAN_ID_MASK 0xfffUL
684 #define CMDQ_MODIFY_QP_VLAN_ID_SFT 0
685 #define CMDQ_MODIFY_QP_VLAN_DEI 0x1000UL
686 #define CMDQ_MODIFY_QP_VLAN_PCP_MASK 0xe000UL
687 #define CMDQ_MODIFY_QP_VLAN_PCP_SFT 13
688 __le64 irrq_addr;
689 __le64 orrq_addr;
690 __le32 ext_modify_mask;
691 #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_EXT_STATS_CTX 0x1UL
692 #define CMDQ_MODIFY_QP_EXT_MODIFY_MASK_SCHQ_ID_VALID 0x2UL
693 __le32 ext_stats_ctx_id;
694 __le16 schq_id;
695 __le16 unused_0;
696 __le32 reserved32;
697};
698
699/* creq_modify_qp_resp (size:128b/16B) */
700struct creq_modify_qp_resp {
701 u8 type;
702 #define CREQ_MODIFY_QP_RESP_TYPE_MASK 0x3fUL
703 #define CREQ_MODIFY_QP_RESP_TYPE_SFT 0
704 #define CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT 0x38UL
705 #define CREQ_MODIFY_QP_RESP_TYPE_LAST CREQ_MODIFY_QP_RESP_TYPE_QP_EVENT
706 u8 status;
707 __le16 cookie;
708 __le32 xid;
709 u8 v;
710 #define CREQ_MODIFY_QP_RESP_V 0x1UL
711 u8 event;
712 #define CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP 0x3UL
713 #define CREQ_MODIFY_QP_RESP_EVENT_LAST CREQ_MODIFY_QP_RESP_EVENT_MODIFY_QP
714 u8 pingpong_push_state_index_enabled;
715 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_ENABLED 0x1UL
716 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_MASK 0xeUL
717 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_INDEX_SFT 1
718 #define CREQ_MODIFY_QP_RESP_PINGPONG_PUSH_STATE 0x10UL
719 u8 reserved8;
720 __le32 lag_src_mac;
721};
722
723/* cmdq_query_qp (size:192b/24B) */
724struct cmdq_query_qp {
725 u8 opcode;
726 #define CMDQ_QUERY_QP_OPCODE_QUERY_QP 0x4UL
727 #define CMDQ_QUERY_QP_OPCODE_LAST CMDQ_QUERY_QP_OPCODE_QUERY_QP
728 u8 cmd_size;
729 __le16 flags;
730 __le16 cookie;
731 u8 resp_size;
732 u8 reserved8;
733 __le64 resp_addr;
734 __le32 qp_cid;
735 __le32 unused_0;
736};
737
738/* creq_query_qp_resp (size:128b/16B) */
739struct creq_query_qp_resp {
740 u8 type;
741 #define CREQ_QUERY_QP_RESP_TYPE_MASK 0x3fUL
742 #define CREQ_QUERY_QP_RESP_TYPE_SFT 0
743 #define CREQ_QUERY_QP_RESP_TYPE_QP_EVENT 0x38UL
744 #define CREQ_QUERY_QP_RESP_TYPE_LAST CREQ_QUERY_QP_RESP_TYPE_QP_EVENT
745 u8 status;
746 __le16 cookie;
747 __le32 size;
748 u8 v;
749 #define CREQ_QUERY_QP_RESP_V 0x1UL
750 u8 event;
751 #define CREQ_QUERY_QP_RESP_EVENT_QUERY_QP 0x4UL
752 #define CREQ_QUERY_QP_RESP_EVENT_LAST CREQ_QUERY_QP_RESP_EVENT_QUERY_QP
753 u8 reserved48[6];
754};
755
756/* creq_query_qp_resp_sb (size:832b/104B) */
757struct creq_query_qp_resp_sb {
758 u8 opcode;
759 #define CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP 0x4UL
760 #define CREQ_QUERY_QP_RESP_SB_OPCODE_LAST CREQ_QUERY_QP_RESP_SB_OPCODE_QUERY_QP
761 u8 status;
762 __le16 cookie;
763 __le16 flags;
764 u8 resp_size;
765 u8 reserved8;
766 __le32 xid;
767 u8 en_sqd_async_notify_state;
768 #define CREQ_QUERY_QP_RESP_SB_STATE_MASK 0xfUL
769 #define CREQ_QUERY_QP_RESP_SB_STATE_SFT 0
770 #define CREQ_QUERY_QP_RESP_SB_STATE_RESET 0x0UL
771 #define CREQ_QUERY_QP_RESP_SB_STATE_INIT 0x1UL
772 #define CREQ_QUERY_QP_RESP_SB_STATE_RTR 0x2UL
773 #define CREQ_QUERY_QP_RESP_SB_STATE_RTS 0x3UL
774 #define CREQ_QUERY_QP_RESP_SB_STATE_SQD 0x4UL
775 #define CREQ_QUERY_QP_RESP_SB_STATE_SQE 0x5UL
776 #define CREQ_QUERY_QP_RESP_SB_STATE_ERR 0x6UL
777 #define CREQ_QUERY_QP_RESP_SB_STATE_LAST CREQ_QUERY_QP_RESP_SB_STATE_ERR
778 #define CREQ_QUERY_QP_RESP_SB_EN_SQD_ASYNC_NOTIFY 0x10UL
779 #define CREQ_QUERY_QP_RESP_SB_UNUSED3_MASK 0xe0UL
780 #define CREQ_QUERY_QP_RESP_SB_UNUSED3_SFT 5
781 u8 access;
782 #define \
783 CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_MASK\
784 0xffUL
785 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC_REMOTE_READ_REMOTE_WRITE_LOCAL_WRITE_SFT\
786 0
787 #define CREQ_QUERY_QP_RESP_SB_ACCESS_LOCAL_WRITE 0x1UL
788 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_WRITE 0x2UL
789 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_READ 0x4UL
790 #define CREQ_QUERY_QP_RESP_SB_ACCESS_REMOTE_ATOMIC 0x8UL
791 __le16 pkey;
792 __le32 qkey;
793 __le16 udp_src_port;
794 __le16 reserved16;
795 __le32 dgid[4];
796 __le32 flow_label;
797 __le16 sgid_index;
798 u8 hop_limit;
799 u8 traffic_class;
800 __le16 dest_mac[3];
801 __le16 path_mtu_dest_vlan_id;
802 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_MASK 0xfffUL
803 #define CREQ_QUERY_QP_RESP_SB_DEST_VLAN_ID_SFT 0
804 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK 0xf000UL
805 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_SFT 12
806 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_256 (0x0UL << 12)
807 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_512 (0x1UL << 12)
808 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_1024 (0x2UL << 12)
809 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_2048 (0x3UL << 12)
810 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_4096 (0x4UL << 12)
811 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192 (0x5UL << 12)
812 #define CREQ_QUERY_QP_RESP_SB_PATH_MTU_LAST CREQ_QUERY_QP_RESP_SB_PATH_MTU_MTU_8192
813 u8 timeout;
814 u8 retry_cnt;
815 u8 rnr_retry;
816 u8 min_rnr_timer;
817 __le32 rq_psn;
818 __le32 sq_psn;
819 u8 max_rd_atomic;
820 u8 max_dest_rd_atomic;
821 u8 tos_dscp_tos_ecn;
822 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_MASK 0x3UL
823 #define CREQ_QUERY_QP_RESP_SB_TOS_ECN_SFT 0
824 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_MASK 0xfcUL
825 #define CREQ_QUERY_QP_RESP_SB_TOS_DSCP_SFT 2
826 u8 enable_cc;
827 #define CREQ_QUERY_QP_RESP_SB_ENABLE_CC 0x1UL
828 __le32 sq_size;
829 __le32 rq_size;
830 __le16 sq_sge;
831 __le16 rq_sge;
832 __le32 max_inline_data;
833 __le32 dest_qp_id;
834 __le16 port_id;
835 u8 unused_0;
836 u8 stat_collection_id;
837 __le16 src_mac[3];
838 __le16 vlan_pcp_vlan_dei_vlan_id;
839 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_MASK 0xfffUL
840 #define CREQ_QUERY_QP_RESP_SB_VLAN_ID_SFT 0
841 #define CREQ_QUERY_QP_RESP_SB_VLAN_DEI 0x1000UL
842 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_MASK 0xe000UL
843 #define CREQ_QUERY_QP_RESP_SB_VLAN_PCP_SFT 13
844};
845
846/* cmdq_query_qp_extend (size:192b/24B) */
847struct cmdq_query_qp_extend {
848 u8 opcode;
849 #define CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND 0x91UL
850 #define CMDQ_QUERY_QP_EXTEND_OPCODE_LAST CMDQ_QUERY_QP_EXTEND_OPCODE_QUERY_QP_EXTEND
851 u8 cmd_size;
852 __le16 flags;
853 __le16 cookie;
854 u8 resp_size;
855 u8 num_qps;
856 __le64 resp_addr;
857 __le32 function_id;
858 #define CMDQ_QUERY_QP_EXTEND_PF_NUM_MASK 0xffUL
859 #define CMDQ_QUERY_QP_EXTEND_PF_NUM_SFT 0
860 #define CMDQ_QUERY_QP_EXTEND_VF_NUM_MASK 0xffff00UL
861 #define CMDQ_QUERY_QP_EXTEND_VF_NUM_SFT 8
862 #define CMDQ_QUERY_QP_EXTEND_VF_VALID 0x1000000UL
863 __le32 current_index;
864};
865
866/* creq_query_qp_extend_resp (size:128b/16B) */
867struct creq_query_qp_extend_resp {
868 u8 type;
869 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_MASK 0x3fUL
870 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_SFT 0
871 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT 0x38UL
872 #define CREQ_QUERY_QP_EXTEND_RESP_TYPE_LAST CREQ_QUERY_QP_EXTEND_RESP_TYPE_QP_EVENT
873 u8 status;
874 __le16 cookie;
875 __le32 size;
876 u8 v;
877 #define CREQ_QUERY_QP_EXTEND_RESP_V 0x1UL
878 u8 event;
879 #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND 0x91UL
880 #define CREQ_QUERY_QP_EXTEND_RESP_EVENT_LAST CREQ_QUERY_QP_EXTEND_RESP_EVENT_QUERY_QP_EXTEND
881 __le16 reserved16;
882 __le32 current_index;
883};
884
885/* creq_query_qp_extend_resp_sb (size:384b/48B) */
886struct creq_query_qp_extend_resp_sb {
887 u8 opcode;
888 #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND 0x91UL
889 #define CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_LAST \
890 CREQ_QUERY_QP_EXTEND_RESP_SB_OPCODE_QUERY_QP_EXTEND
891 u8 status;
892 __le16 cookie;
893 __le16 flags;
894 u8 resp_size;
895 u8 reserved8;
896 __le32 xid;
897 u8 state;
898 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_MASK 0xfUL
899 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SFT 0
900 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RESET 0x0UL
901 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_INIT 0x1UL
902 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTR 0x2UL
903 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_RTS 0x3UL
904 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQD 0x4UL
905 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_SQE 0x5UL
906 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR 0x6UL
907 #define CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_LAST CREQ_QUERY_QP_EXTEND_RESP_SB_STATE_ERR
908 #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_MASK 0xf0UL
909 #define CREQ_QUERY_QP_EXTEND_RESP_SB_UNUSED4_SFT 4
910 u8 reserved_8;
911 __le16 port_id;
912 __le32 qkey;
913 __le16 sgid_index;
914 u8 network_type;
915 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV1 0x0UL
916 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV4 0x2UL
917 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6 0x3UL
918 #define CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_LAST \
919 CREQ_QUERY_QP_EXTEND_RESP_SB_NETWORK_TYPE_ROCEV2_IPV6
920 u8 unused_0;
921 __le32 dgid[4];
922 __le32 dest_qp_id;
923 u8 stat_collection_id;
924 u8 reservred_8;
925 __le16 reserved_16;
926};
927
928/* creq_query_qp_extend_resp_sb_tlv (size:512b/64B) */
929struct creq_query_qp_extend_resp_sb_tlv {
930 __le16 cmd_discr;
931 u8 reserved_8b;
932 u8 tlv_flags;
933 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL
934 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL
935 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
936 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL
937 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
938 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
939 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \
940 CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES
941 __le16 tlv_type;
942 __le16 length;
943 u8 total_size;
944 u8 reserved56[7];
945 u8 opcode;
946 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND 0x91UL
947 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_LAST \
948 CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_OPCODE_QUERY_QP_EXTEND
949 u8 status;
950 __le16 cookie;
951 __le16 flags;
952 u8 resp_size;
953 u8 reserved8;
954 __le32 xid;
955 u8 state;
956 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_MASK 0xfUL
957 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SFT 0
958 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RESET 0x0UL
959 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_INIT 0x1UL
960 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTR 0x2UL
961 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_RTS 0x3UL
962 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQD 0x4UL
963 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_SQE 0x5UL
964 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR 0x6UL
965 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_LAST \
966 CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_STATE_ERR
967 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_MASK 0xf0UL
968 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_UNUSED4_SFT 4
969 u8 reserved_8;
970 __le16 port_id;
971 __le32 qkey;
972 __le16 sgid_index;
973 u8 network_type;
974 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV1 0x0UL
975 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV4 0x2UL
976 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6 0x3UL
977 #define CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_LAST \
978 CREQ_QUERY_QP_EXTEND_RESP_SB_TLV_NETWORK_TYPE_ROCEV2_IPV6
979 u8 unused_0;
980 __le32 dgid[4];
981 __le32 dest_qp_id;
982 u8 stat_collection_id;
983 u8 reservred_8;
984 __le16 reserved_16;
985};
986
987/* cmdq_create_srq (size:448b/56B) */
988struct cmdq_create_srq {
989 u8 opcode;
990 #define CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ 0x5UL
991 #define CMDQ_CREATE_SRQ_OPCODE_LAST CMDQ_CREATE_SRQ_OPCODE_CREATE_SRQ
992 u8 cmd_size;
993 __le16 flags;
994 #define CMDQ_CREATE_SRQ_FLAGS_STEERING_TAG_VALID 0x1UL
995 __le16 cookie;
996 u8 resp_size;
997 u8 reserved8;
998 __le64 resp_addr;
999 __le64 srq_handle;
1000 __le16 pg_size_lvl;
1001 #define CMDQ_CREATE_SRQ_LVL_MASK 0x3UL
1002 #define CMDQ_CREATE_SRQ_LVL_SFT 0
1003 #define CMDQ_CREATE_SRQ_LVL_LVL_0 0x0UL
1004 #define CMDQ_CREATE_SRQ_LVL_LVL_1 0x1UL
1005 #define CMDQ_CREATE_SRQ_LVL_LVL_2 0x2UL
1006 #define CMDQ_CREATE_SRQ_LVL_LAST CMDQ_CREATE_SRQ_LVL_LVL_2
1007 #define CMDQ_CREATE_SRQ_PG_SIZE_MASK 0x1cUL
1008 #define CMDQ_CREATE_SRQ_PG_SIZE_SFT 2
1009 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_4K (0x0UL << 2)
1010 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8K (0x1UL << 2)
1011 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_64K (0x2UL << 2)
1012 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_2M (0x3UL << 2)
1013 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_8M (0x4UL << 2)
1014 #define CMDQ_CREATE_SRQ_PG_SIZE_PG_1G (0x5UL << 2)
1015 #define CMDQ_CREATE_SRQ_PG_SIZE_LAST CMDQ_CREATE_SRQ_PG_SIZE_PG_1G
1016 #define CMDQ_CREATE_SRQ_UNUSED11_MASK 0xffe0UL
1017 #define CMDQ_CREATE_SRQ_UNUSED11_SFT 5
1018 __le16 eventq_id;
1019 #define CMDQ_CREATE_SRQ_EVENTQ_ID_MASK 0xfffUL
1020 #define CMDQ_CREATE_SRQ_EVENTQ_ID_SFT 0
1021 #define CMDQ_CREATE_SRQ_UNUSED4_MASK 0xf000UL
1022 #define CMDQ_CREATE_SRQ_UNUSED4_SFT 12
1023 __le16 srq_size;
1024 __le16 srq_fwo;
1025 __le32 dpi;
1026 __le32 pd_id;
1027 __le64 pbl;
1028 __le16 steering_tag;
1029 u8 reserved48[6];
1030};
1031
1032/* creq_create_srq_resp (size:128b/16B) */
1033struct creq_create_srq_resp {
1034 u8 type;
1035 #define CREQ_CREATE_SRQ_RESP_TYPE_MASK 0x3fUL
1036 #define CREQ_CREATE_SRQ_RESP_TYPE_SFT 0
1037 #define CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT 0x38UL
1038 #define CREQ_CREATE_SRQ_RESP_TYPE_LAST CREQ_CREATE_SRQ_RESP_TYPE_QP_EVENT
1039 u8 status;
1040 __le16 cookie;
1041 __le32 xid;
1042 u8 v;
1043 #define CREQ_CREATE_SRQ_RESP_V 0x1UL
1044 u8 event;
1045 #define CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ 0x5UL
1046 #define CREQ_CREATE_SRQ_RESP_EVENT_LAST CREQ_CREATE_SRQ_RESP_EVENT_CREATE_SRQ
1047 u8 reserved48[6];
1048};
1049
1050/* cmdq_destroy_srq (size:192b/24B) */
1051struct cmdq_destroy_srq {
1052 u8 opcode;
1053 #define CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ 0x6UL
1054 #define CMDQ_DESTROY_SRQ_OPCODE_LAST CMDQ_DESTROY_SRQ_OPCODE_DESTROY_SRQ
1055 u8 cmd_size;
1056 __le16 flags;
1057 __le16 cookie;
1058 u8 resp_size;
1059 u8 reserved8;
1060 __le64 resp_addr;
1061 __le32 srq_cid;
1062 __le32 unused_0;
1063};
1064
1065/* creq_destroy_srq_resp (size:128b/16B) */
1066struct creq_destroy_srq_resp {
1067 u8 type;
1068 #define CREQ_DESTROY_SRQ_RESP_TYPE_MASK 0x3fUL
1069 #define CREQ_DESTROY_SRQ_RESP_TYPE_SFT 0
1070 #define CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT 0x38UL
1071 #define CREQ_DESTROY_SRQ_RESP_TYPE_LAST CREQ_DESTROY_SRQ_RESP_TYPE_QP_EVENT
1072 u8 status;
1073 __le16 cookie;
1074 __le32 xid;
1075 u8 v;
1076 #define CREQ_DESTROY_SRQ_RESP_V 0x1UL
1077 u8 event;
1078 #define CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ 0x6UL
1079 #define CREQ_DESTROY_SRQ_RESP_EVENT_LAST CREQ_DESTROY_SRQ_RESP_EVENT_DESTROY_SRQ
1080 __le16 enable_for_arm[3];
1081 #define CREQ_DESTROY_SRQ_RESP_UNUSED0_MASK 0xffffUL
1082 #define CREQ_DESTROY_SRQ_RESP_UNUSED0_SFT 0
1083 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_MASK 0x30000UL
1084 #define CREQ_DESTROY_SRQ_RESP_ENABLE_FOR_ARM_SFT 16
1085};
1086
1087/* cmdq_query_srq (size:192b/24B) */
1088struct cmdq_query_srq {
1089 u8 opcode;
1090 #define CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ 0x8UL
1091 #define CMDQ_QUERY_SRQ_OPCODE_LAST CMDQ_QUERY_SRQ_OPCODE_QUERY_SRQ
1092 u8 cmd_size;
1093 __le16 flags;
1094 __le16 cookie;
1095 u8 resp_size;
1096 u8 reserved8;
1097 __le64 resp_addr;
1098 __le32 srq_cid;
1099 __le32 unused_0;
1100};
1101
1102/* creq_query_srq_resp (size:128b/16B) */
1103struct creq_query_srq_resp {
1104 u8 type;
1105 #define CREQ_QUERY_SRQ_RESP_TYPE_MASK 0x3fUL
1106 #define CREQ_QUERY_SRQ_RESP_TYPE_SFT 0
1107 #define CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT 0x38UL
1108 #define CREQ_QUERY_SRQ_RESP_TYPE_LAST CREQ_QUERY_SRQ_RESP_TYPE_QP_EVENT
1109 u8 status;
1110 __le16 cookie;
1111 __le32 size;
1112 u8 v;
1113 #define CREQ_QUERY_SRQ_RESP_V 0x1UL
1114 u8 event;
1115 #define CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ 0x8UL
1116 #define CREQ_QUERY_SRQ_RESP_EVENT_LAST CREQ_QUERY_SRQ_RESP_EVENT_QUERY_SRQ
1117 u8 reserved48[6];
1118};
1119
1120/* creq_query_srq_resp_sb (size:256b/32B) */
1121struct creq_query_srq_resp_sb {
1122 u8 opcode;
1123 #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ 0x8UL
1124 #define CREQ_QUERY_SRQ_RESP_SB_OPCODE_LAST CREQ_QUERY_SRQ_RESP_SB_OPCODE_QUERY_SRQ
1125 u8 status;
1126 __le16 cookie;
1127 __le16 flags;
1128 u8 resp_size;
1129 u8 reserved8;
1130 __le32 xid;
1131 __le16 srq_limit;
1132 __le16 reserved16;
1133 __le32 data[4];
1134};
1135
1136/* cmdq_create_cq (size:448b/56B) */
1137struct cmdq_create_cq {
1138 u8 opcode;
1139 #define CMDQ_CREATE_CQ_OPCODE_CREATE_CQ 0x9UL
1140 #define CMDQ_CREATE_CQ_OPCODE_LAST CMDQ_CREATE_CQ_OPCODE_CREATE_CQ
1141 u8 cmd_size;
1142 __le16 flags;
1143 #define CMDQ_CREATE_CQ_FLAGS_DISABLE_CQ_OVERFLOW_DETECTION 0x1UL
1144 #define CMDQ_CREATE_CQ_FLAGS_STEERING_TAG_VALID 0x2UL
1145 #define CMDQ_CREATE_CQ_FLAGS_INFINITE_CQ_MODE 0x4UL
1146 #define CMDQ_CREATE_CQ_FLAGS_COALESCING_VALID 0x8UL
1147 __le16 cookie;
1148 u8 resp_size;
1149 u8 reserved8;
1150 __le64 resp_addr;
1151 __le64 cq_handle;
1152 __le32 pg_size_lvl;
1153 #define CMDQ_CREATE_CQ_LVL_MASK 0x3UL
1154 #define CMDQ_CREATE_CQ_LVL_SFT 0
1155 #define CMDQ_CREATE_CQ_LVL_LVL_0 0x0UL
1156 #define CMDQ_CREATE_CQ_LVL_LVL_1 0x1UL
1157 #define CMDQ_CREATE_CQ_LVL_LVL_2 0x2UL
1158 #define CMDQ_CREATE_CQ_LVL_LAST CMDQ_CREATE_CQ_LVL_LVL_2
1159 #define CMDQ_CREATE_CQ_PG_SIZE_MASK 0x1cUL
1160 #define CMDQ_CREATE_CQ_PG_SIZE_SFT 2
1161 #define CMDQ_CREATE_CQ_PG_SIZE_PG_4K (0x0UL << 2)
1162 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8K (0x1UL << 2)
1163 #define CMDQ_CREATE_CQ_PG_SIZE_PG_64K (0x2UL << 2)
1164 #define CMDQ_CREATE_CQ_PG_SIZE_PG_2M (0x3UL << 2)
1165 #define CMDQ_CREATE_CQ_PG_SIZE_PG_8M (0x4UL << 2)
1166 #define CMDQ_CREATE_CQ_PG_SIZE_PG_1G (0x5UL << 2)
1167 #define CMDQ_CREATE_CQ_PG_SIZE_LAST CMDQ_CREATE_CQ_PG_SIZE_PG_1G
1168 #define CMDQ_CREATE_CQ_UNUSED27_MASK 0xffffffe0UL
1169 #define CMDQ_CREATE_CQ_UNUSED27_SFT 5
1170 __le32 cq_fco_cnq_id;
1171 #define CMDQ_CREATE_CQ_CNQ_ID_MASK 0xfffUL
1172 #define CMDQ_CREATE_CQ_CNQ_ID_SFT 0
1173 #define CMDQ_CREATE_CQ_CQ_FCO_MASK 0xfffff000UL
1174 #define CMDQ_CREATE_CQ_CQ_FCO_SFT 12
1175 __le32 dpi;
1176 __le32 cq_size;
1177 __le64 pbl;
1178 __le16 steering_tag;
1179 u8 reserved48[2];
1180 __le32 coalescing;
1181 #define CMDQ_CREATE_CQ_BUF_MAXTIME_MASK 0x1ffUL
1182 #define CMDQ_CREATE_CQ_BUF_MAXTIME_SFT 0
1183 #define CMDQ_CREATE_CQ_NORMAL_MAXBUF_MASK 0x3e00UL
1184 #define CMDQ_CREATE_CQ_NORMAL_MAXBUF_SFT 9
1185 #define CMDQ_CREATE_CQ_DURING_MAXBUF_MASK 0x7c000UL
1186 #define CMDQ_CREATE_CQ_DURING_MAXBUF_SFT 14
1187 #define CMDQ_CREATE_CQ_ENABLE_RING_IDLE_MODE 0x80000UL
1188 #define CMDQ_CREATE_CQ_UNUSED12_MASK 0xfff00000UL
1189 #define CMDQ_CREATE_CQ_UNUSED12_SFT 20
1190 __le64 reserved64;
1191};
1192
1193/* creq_create_cq_resp (size:128b/16B) */
1194struct creq_create_cq_resp {
1195 u8 type;
1196 #define CREQ_CREATE_CQ_RESP_TYPE_MASK 0x3fUL
1197 #define CREQ_CREATE_CQ_RESP_TYPE_SFT 0
1198 #define CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT 0x38UL
1199 #define CREQ_CREATE_CQ_RESP_TYPE_LAST CREQ_CREATE_CQ_RESP_TYPE_QP_EVENT
1200 u8 status;
1201 __le16 cookie;
1202 __le32 xid;
1203 u8 v;
1204 #define CREQ_CREATE_CQ_RESP_V 0x1UL
1205 u8 event;
1206 #define CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ 0x9UL
1207 #define CREQ_CREATE_CQ_RESP_EVENT_LAST CREQ_CREATE_CQ_RESP_EVENT_CREATE_CQ
1208 u8 reserved48[6];
1209};
1210
1211/* cmdq_destroy_cq (size:192b/24B) */
1212struct cmdq_destroy_cq {
1213 u8 opcode;
1214 #define CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ 0xaUL
1215 #define CMDQ_DESTROY_CQ_OPCODE_LAST CMDQ_DESTROY_CQ_OPCODE_DESTROY_CQ
1216 u8 cmd_size;
1217 __le16 flags;
1218 __le16 cookie;
1219 u8 resp_size;
1220 u8 reserved8;
1221 __le64 resp_addr;
1222 __le32 cq_cid;
1223 __le32 unused_0;
1224};
1225
1226/* creq_destroy_cq_resp (size:128b/16B) */
1227struct creq_destroy_cq_resp {
1228 u8 type;
1229 #define CREQ_DESTROY_CQ_RESP_TYPE_MASK 0x3fUL
1230 #define CREQ_DESTROY_CQ_RESP_TYPE_SFT 0
1231 #define CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT 0x38UL
1232 #define CREQ_DESTROY_CQ_RESP_TYPE_LAST CREQ_DESTROY_CQ_RESP_TYPE_QP_EVENT
1233 u8 status;
1234 __le16 cookie;
1235 __le32 xid;
1236 u8 v;
1237 #define CREQ_DESTROY_CQ_RESP_V 0x1UL
1238 u8 event;
1239 #define CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ 0xaUL
1240 #define CREQ_DESTROY_CQ_RESP_EVENT_LAST CREQ_DESTROY_CQ_RESP_EVENT_DESTROY_CQ
1241 __le16 cq_arm_lvl;
1242 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_MASK 0x3UL
1243 #define CREQ_DESTROY_CQ_RESP_CQ_ARM_LVL_SFT 0
1244 __le16 total_cnq_events;
1245 __le16 reserved16;
1246};
1247
1248/* cmdq_resize_cq (size:320b/40B) */
1249struct cmdq_resize_cq {
1250 u8 opcode;
1251 #define CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ 0xcUL
1252 #define CMDQ_RESIZE_CQ_OPCODE_LAST CMDQ_RESIZE_CQ_OPCODE_RESIZE_CQ
1253 u8 cmd_size;
1254 __le16 flags;
1255 __le16 cookie;
1256 u8 resp_size;
1257 u8 reserved8;
1258 __le64 resp_addr;
1259 __le32 cq_cid;
1260 __le32 new_cq_size_pg_size_lvl;
1261 #define CMDQ_RESIZE_CQ_LVL_MASK 0x3UL
1262 #define CMDQ_RESIZE_CQ_LVL_SFT 0
1263 #define CMDQ_RESIZE_CQ_LVL_LVL_0 0x0UL
1264 #define CMDQ_RESIZE_CQ_LVL_LVL_1 0x1UL
1265 #define CMDQ_RESIZE_CQ_LVL_LVL_2 0x2UL
1266 #define CMDQ_RESIZE_CQ_LVL_LAST CMDQ_RESIZE_CQ_LVL_LVL_2
1267 #define CMDQ_RESIZE_CQ_PG_SIZE_MASK 0x1cUL
1268 #define CMDQ_RESIZE_CQ_PG_SIZE_SFT 2
1269 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_4K (0x0UL << 2)
1270 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8K (0x1UL << 2)
1271 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_64K (0x2UL << 2)
1272 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_2M (0x3UL << 2)
1273 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_8M (0x4UL << 2)
1274 #define CMDQ_RESIZE_CQ_PG_SIZE_PG_1G (0x5UL << 2)
1275 #define CMDQ_RESIZE_CQ_PG_SIZE_LAST CMDQ_RESIZE_CQ_PG_SIZE_PG_1G
1276 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_MASK 0x1fffffe0UL
1277 #define CMDQ_RESIZE_CQ_NEW_CQ_SIZE_SFT 5
1278 __le64 new_pbl;
1279 __le32 new_cq_fco;
1280 __le32 unused_0;
1281};
1282
1283/* creq_resize_cq_resp (size:128b/16B) */
1284struct creq_resize_cq_resp {
1285 u8 type;
1286 #define CREQ_RESIZE_CQ_RESP_TYPE_MASK 0x3fUL
1287 #define CREQ_RESIZE_CQ_RESP_TYPE_SFT 0
1288 #define CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT 0x38UL
1289 #define CREQ_RESIZE_CQ_RESP_TYPE_LAST CREQ_RESIZE_CQ_RESP_TYPE_QP_EVENT
1290 u8 status;
1291 __le16 cookie;
1292 __le32 xid;
1293 u8 v;
1294 #define CREQ_RESIZE_CQ_RESP_V 0x1UL
1295 u8 event;
1296 #define CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ 0xcUL
1297 #define CREQ_RESIZE_CQ_RESP_EVENT_LAST CREQ_RESIZE_CQ_RESP_EVENT_RESIZE_CQ
1298 u8 reserved48[6];
1299};
1300
1301/* cmdq_allocate_mrw (size:256b/32B) */
1302struct cmdq_allocate_mrw {
1303 u8 opcode;
1304 #define CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW 0xdUL
1305 #define CMDQ_ALLOCATE_MRW_OPCODE_LAST CMDQ_ALLOCATE_MRW_OPCODE_ALLOCATE_MRW
1306 u8 cmd_size;
1307 __le16 flags;
1308 __le16 cookie;
1309 u8 resp_size;
1310 u8 reserved8;
1311 __le64 resp_addr;
1312 __le64 mrw_handle;
1313 u8 mrw_flags;
1314 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MASK 0xfUL
1315 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_SFT 0
1316 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR 0x0UL
1317 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR 0x1UL
1318 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 0x2UL
1319 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2A 0x3UL
1320 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B 0x4UL
1321 #define CMDQ_ALLOCATE_MRW_MRW_FLAGS_LAST CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B
1322 #define CMDQ_ALLOCATE_MRW_STEERING_TAG_VALID 0x10UL
1323 #define CMDQ_ALLOCATE_MRW_UNUSED4_MASK 0xe0UL
1324 #define CMDQ_ALLOCATE_MRW_UNUSED4_SFT 5
1325 u8 access;
1326 #define CMDQ_ALLOCATE_MRW_ACCESS_CONSUMER_OWNED_KEY 0x20UL
1327 __le16 steering_tag;
1328 __le32 pd_id;
1329};
1330
1331/* creq_allocate_mrw_resp (size:128b/16B) */
1332struct creq_allocate_mrw_resp {
1333 u8 type;
1334 #define CREQ_ALLOCATE_MRW_RESP_TYPE_MASK 0x3fUL
1335 #define CREQ_ALLOCATE_MRW_RESP_TYPE_SFT 0
1336 #define CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT 0x38UL
1337 #define CREQ_ALLOCATE_MRW_RESP_TYPE_LAST CREQ_ALLOCATE_MRW_RESP_TYPE_QP_EVENT
1338 u8 status;
1339 __le16 cookie;
1340 __le32 xid;
1341 u8 v;
1342 #define CREQ_ALLOCATE_MRW_RESP_V 0x1UL
1343 u8 event;
1344 #define CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW 0xdUL
1345 #define CREQ_ALLOCATE_MRW_RESP_EVENT_LAST CREQ_ALLOCATE_MRW_RESP_EVENT_ALLOCATE_MRW
1346 u8 reserved48[6];
1347};
1348
1349/* cmdq_deallocate_key (size:192b/24B) */
1350struct cmdq_deallocate_key {
1351 u8 opcode;
1352 #define CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY 0xeUL
1353 #define CMDQ_DEALLOCATE_KEY_OPCODE_LAST CMDQ_DEALLOCATE_KEY_OPCODE_DEALLOCATE_KEY
1354 u8 cmd_size;
1355 __le16 flags;
1356 __le16 cookie;
1357 u8 resp_size;
1358 u8 reserved8;
1359 __le64 resp_addr;
1360 u8 mrw_flags;
1361 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MASK 0xfUL
1362 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_SFT 0
1363 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MR 0x0UL
1364 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_PMR 0x1UL
1365 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE1 0x2UL
1366 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2A 0x3UL
1367 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B 0x4UL
1368 #define CMDQ_DEALLOCATE_KEY_MRW_FLAGS_LAST CMDQ_DEALLOCATE_KEY_MRW_FLAGS_MW_TYPE2B
1369 #define CMDQ_DEALLOCATE_KEY_UNUSED4_MASK 0xf0UL
1370 #define CMDQ_DEALLOCATE_KEY_UNUSED4_SFT 4
1371 u8 unused24[3];
1372 __le32 key;
1373};
1374
1375/* creq_deallocate_key_resp (size:128b/16B) */
1376struct creq_deallocate_key_resp {
1377 u8 type;
1378 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_MASK 0x3fUL
1379 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_SFT 0
1380 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT 0x38UL
1381 #define CREQ_DEALLOCATE_KEY_RESP_TYPE_LAST CREQ_DEALLOCATE_KEY_RESP_TYPE_QP_EVENT
1382 u8 status;
1383 __le16 cookie;
1384 __le32 xid;
1385 u8 v;
1386 #define CREQ_DEALLOCATE_KEY_RESP_V 0x1UL
1387 u8 event;
1388 #define CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY 0xeUL
1389 #define CREQ_DEALLOCATE_KEY_RESP_EVENT_LAST CREQ_DEALLOCATE_KEY_RESP_EVENT_DEALLOCATE_KEY
1390 __le16 reserved16;
1391 __le32 bound_window_info;
1392};
1393
1394/* cmdq_register_mr (size:448b/56B) */
1395struct cmdq_register_mr {
1396 u8 opcode;
1397 #define CMDQ_REGISTER_MR_OPCODE_REGISTER_MR 0xfUL
1398 #define CMDQ_REGISTER_MR_OPCODE_LAST CMDQ_REGISTER_MR_OPCODE_REGISTER_MR
1399 u8 cmd_size;
1400 __le16 flags;
1401 #define CMDQ_REGISTER_MR_FLAGS_ALLOC_MR 0x1UL
1402 #define CMDQ_REGISTER_MR_FLAGS_STEERING_TAG_VALID 0x2UL
1403 #define CMDQ_REGISTER_MR_FLAGS_ENABLE_RO 0x4UL
1404 __le16 cookie;
1405 u8 resp_size;
1406 u8 reserved8;
1407 __le64 resp_addr;
1408 u8 log2_pg_size_lvl;
1409 #define CMDQ_REGISTER_MR_LVL_MASK 0x3UL
1410 #define CMDQ_REGISTER_MR_LVL_SFT 0
1411 #define CMDQ_REGISTER_MR_LVL_LVL_0 0x0UL
1412 #define CMDQ_REGISTER_MR_LVL_LVL_1 0x1UL
1413 #define CMDQ_REGISTER_MR_LVL_LVL_2 0x2UL
1414 #define CMDQ_REGISTER_MR_LVL_LAST CMDQ_REGISTER_MR_LVL_LVL_2
1415 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_MASK 0x7cUL
1416 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_SFT 2
1417 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4K (0xcUL << 2)
1418 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_8K (0xdUL << 2)
1419 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_64K (0x10UL << 2)
1420 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_256K (0x12UL << 2)
1421 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1M (0x14UL << 2)
1422 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_2M (0x15UL << 2)
1423 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_4M (0x16UL << 2)
1424 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G (0x1eUL << 2)
1425 #define CMDQ_REGISTER_MR_LOG2_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PG_SIZE_PG_1G
1426 #define CMDQ_REGISTER_MR_UNUSED1 0x80UL
1427 u8 access;
1428 #define CMDQ_REGISTER_MR_ACCESS_LOCAL_WRITE 0x1UL
1429 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_READ 0x2UL
1430 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_WRITE 0x4UL
1431 #define CMDQ_REGISTER_MR_ACCESS_REMOTE_ATOMIC 0x8UL
1432 #define CMDQ_REGISTER_MR_ACCESS_MW_BIND 0x10UL
1433 #define CMDQ_REGISTER_MR_ACCESS_ZERO_BASED 0x20UL
1434 __le16 log2_pbl_pg_size;
1435 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_MASK 0x1fUL
1436 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_SFT 0
1437 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K 0xcUL
1438 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K 0xdUL
1439 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K 0x10UL
1440 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K 0x12UL
1441 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M 0x14UL
1442 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M 0x15UL
1443 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M 0x16UL
1444 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G 0x1eUL
1445 #define CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_LAST CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G
1446 #define CMDQ_REGISTER_MR_UNUSED11_MASK 0xffe0UL
1447 #define CMDQ_REGISTER_MR_UNUSED11_SFT 5
1448 __le32 key;
1449 __le64 pbl;
1450 __le64 va;
1451 __le64 mr_size;
1452 __le16 steering_tag;
1453 u8 reserved48[6];
1454};
1455
1456/* creq_register_mr_resp (size:128b/16B) */
1457struct creq_register_mr_resp {
1458 u8 type;
1459 #define CREQ_REGISTER_MR_RESP_TYPE_MASK 0x3fUL
1460 #define CREQ_REGISTER_MR_RESP_TYPE_SFT 0
1461 #define CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL
1462 #define CREQ_REGISTER_MR_RESP_TYPE_LAST CREQ_REGISTER_MR_RESP_TYPE_QP_EVENT
1463 u8 status;
1464 __le16 cookie;
1465 __le32 xid;
1466 u8 v;
1467 #define CREQ_REGISTER_MR_RESP_V 0x1UL
1468 u8 event;
1469 #define CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR 0xfUL
1470 #define CREQ_REGISTER_MR_RESP_EVENT_LAST CREQ_REGISTER_MR_RESP_EVENT_REGISTER_MR
1471 u8 reserved48[6];
1472};
1473
1474/* cmdq_deregister_mr (size:192b/24B) */
1475struct cmdq_deregister_mr {
1476 u8 opcode;
1477 #define CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR 0x10UL
1478 #define CMDQ_DEREGISTER_MR_OPCODE_LAST CMDQ_DEREGISTER_MR_OPCODE_DEREGISTER_MR
1479 u8 cmd_size;
1480 __le16 flags;
1481 __le16 cookie;
1482 u8 resp_size;
1483 u8 reserved8;
1484 __le64 resp_addr;
1485 __le32 lkey;
1486 __le32 unused_0;
1487};
1488
1489/* creq_deregister_mr_resp (size:128b/16B) */
1490struct creq_deregister_mr_resp {
1491 u8 type;
1492 #define CREQ_DEREGISTER_MR_RESP_TYPE_MASK 0x3fUL
1493 #define CREQ_DEREGISTER_MR_RESP_TYPE_SFT 0
1494 #define CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT 0x38UL
1495 #define CREQ_DEREGISTER_MR_RESP_TYPE_LAST CREQ_DEREGISTER_MR_RESP_TYPE_QP_EVENT
1496 u8 status;
1497 __le16 cookie;
1498 __le32 xid;
1499 u8 v;
1500 #define CREQ_DEREGISTER_MR_RESP_V 0x1UL
1501 u8 event;
1502 #define CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR 0x10UL
1503 #define CREQ_DEREGISTER_MR_RESP_EVENT_LAST CREQ_DEREGISTER_MR_RESP_EVENT_DEREGISTER_MR
1504 __le16 reserved16;
1505 __le32 bound_windows;
1506};
1507
1508/* cmdq_add_gid (size:384b/48B) */
1509struct cmdq_add_gid {
1510 u8 opcode;
1511 #define CMDQ_ADD_GID_OPCODE_ADD_GID 0x11UL
1512 #define CMDQ_ADD_GID_OPCODE_LAST CMDQ_ADD_GID_OPCODE_ADD_GID
1513 u8 cmd_size;
1514 __le16 flags;
1515 __le16 cookie;
1516 u8 resp_size;
1517 u8 reserved8;
1518 __le64 resp_addr;
1519 __be32 gid[4];
1520 __be16 src_mac[3];
1521 __le16 vlan;
1522 #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_MASK 0xffffUL
1523 #define CMDQ_ADD_GID_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0
1524 #define CMDQ_ADD_GID_VLAN_VLAN_ID_MASK 0xfffUL
1525 #define CMDQ_ADD_GID_VLAN_VLAN_ID_SFT 0
1526 #define CMDQ_ADD_GID_VLAN_TPID_MASK 0x7000UL
1527 #define CMDQ_ADD_GID_VLAN_TPID_SFT 12
1528 #define CMDQ_ADD_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12)
1529 #define CMDQ_ADD_GID_VLAN_TPID_TPID_8100 (0x1UL << 12)
1530 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9100 (0x2UL << 12)
1531 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9200 (0x3UL << 12)
1532 #define CMDQ_ADD_GID_VLAN_TPID_TPID_9300 (0x4UL << 12)
1533 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12)
1534 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12)
1535 #define CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12)
1536 #define CMDQ_ADD_GID_VLAN_TPID_LAST CMDQ_ADD_GID_VLAN_TPID_TPID_CFG3
1537 #define CMDQ_ADD_GID_VLAN_VLAN_EN 0x8000UL
1538 __le16 ipid;
1539 __le16 stats_ctx;
1540 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_MASK 0xffffUL
1541 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID_STATS_CTX_ID_SFT 0
1542 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL
1543 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_ID_SFT 0
1544 #define CMDQ_ADD_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL
1545 __le32 unused_0;
1546};
1547
1548/* creq_add_gid_resp (size:128b/16B) */
1549struct creq_add_gid_resp {
1550 u8 type;
1551 #define CREQ_ADD_GID_RESP_TYPE_MASK 0x3fUL
1552 #define CREQ_ADD_GID_RESP_TYPE_SFT 0
1553 #define CREQ_ADD_GID_RESP_TYPE_QP_EVENT 0x38UL
1554 #define CREQ_ADD_GID_RESP_TYPE_LAST CREQ_ADD_GID_RESP_TYPE_QP_EVENT
1555 u8 status;
1556 __le16 cookie;
1557 __le32 xid;
1558 u8 v;
1559 #define CREQ_ADD_GID_RESP_V 0x1UL
1560 u8 event;
1561 #define CREQ_ADD_GID_RESP_EVENT_ADD_GID 0x11UL
1562 #define CREQ_ADD_GID_RESP_EVENT_LAST CREQ_ADD_GID_RESP_EVENT_ADD_GID
1563 u8 reserved48[6];
1564};
1565
1566/* cmdq_delete_gid (size:192b/24B) */
1567struct cmdq_delete_gid {
1568 u8 opcode;
1569 #define CMDQ_DELETE_GID_OPCODE_DELETE_GID 0x12UL
1570 #define CMDQ_DELETE_GID_OPCODE_LAST CMDQ_DELETE_GID_OPCODE_DELETE_GID
1571 u8 cmd_size;
1572 __le16 flags;
1573 __le16 cookie;
1574 u8 resp_size;
1575 u8 reserved8;
1576 __le64 resp_addr;
1577 __le16 gid_index;
1578 u8 unused_0[6];
1579};
1580
1581/* creq_delete_gid_resp (size:128b/16B) */
1582struct creq_delete_gid_resp {
1583 u8 type;
1584 #define CREQ_DELETE_GID_RESP_TYPE_MASK 0x3fUL
1585 #define CREQ_DELETE_GID_RESP_TYPE_SFT 0
1586 #define CREQ_DELETE_GID_RESP_TYPE_QP_EVENT 0x38UL
1587 #define CREQ_DELETE_GID_RESP_TYPE_LAST CREQ_DELETE_GID_RESP_TYPE_QP_EVENT
1588 u8 status;
1589 __le16 cookie;
1590 __le32 xid;
1591 u8 v;
1592 #define CREQ_DELETE_GID_RESP_V 0x1UL
1593 u8 event;
1594 #define CREQ_DELETE_GID_RESP_EVENT_DELETE_GID 0x12UL
1595 #define CREQ_DELETE_GID_RESP_EVENT_LAST CREQ_DELETE_GID_RESP_EVENT_DELETE_GID
1596 u8 reserved48[6];
1597};
1598
1599/* cmdq_modify_gid (size:384b/48B) */
1600struct cmdq_modify_gid {
1601 u8 opcode;
1602 #define CMDQ_MODIFY_GID_OPCODE_MODIFY_GID 0x17UL
1603 #define CMDQ_MODIFY_GID_OPCODE_LAST CMDQ_MODIFY_GID_OPCODE_MODIFY_GID
1604 u8 cmd_size;
1605 __le16 flags;
1606 __le16 cookie;
1607 u8 resp_size;
1608 u8 reserved8;
1609 __le64 resp_addr;
1610 __be32 gid[4];
1611 __be16 src_mac[3];
1612 __le16 vlan;
1613 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_MASK 0xfffUL
1614 #define CMDQ_MODIFY_GID_VLAN_VLAN_ID_SFT 0
1615 #define CMDQ_MODIFY_GID_VLAN_TPID_MASK 0x7000UL
1616 #define CMDQ_MODIFY_GID_VLAN_TPID_SFT 12
1617 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_88A8 (0x0UL << 12)
1618 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_8100 (0x1UL << 12)
1619 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9100 (0x2UL << 12)
1620 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9200 (0x3UL << 12)
1621 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_9300 (0x4UL << 12)
1622 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG1 (0x5UL << 12)
1623 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG2 (0x6UL << 12)
1624 #define CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3 (0x7UL << 12)
1625 #define CMDQ_MODIFY_GID_VLAN_TPID_LAST CMDQ_MODIFY_GID_VLAN_TPID_TPID_CFG3
1626 #define CMDQ_MODIFY_GID_VLAN_VLAN_EN 0x8000UL
1627 __le16 ipid;
1628 __le16 gid_index;
1629 __le16 stats_ctx;
1630 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_MASK 0x7fffUL
1631 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_ID_SFT 0
1632 #define CMDQ_MODIFY_GID_STATS_CTX_STATS_CTX_VALID 0x8000UL
1633 __le16 unused_0;
1634};
1635
1636/* creq_modify_gid_resp (size:128b/16B) */
1637struct creq_modify_gid_resp {
1638 u8 type;
1639 #define CREQ_MODIFY_GID_RESP_TYPE_MASK 0x3fUL
1640 #define CREQ_MODIFY_GID_RESP_TYPE_SFT 0
1641 #define CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT 0x38UL
1642 #define CREQ_MODIFY_GID_RESP_TYPE_LAST CREQ_MODIFY_GID_RESP_TYPE_QP_EVENT
1643 u8 status;
1644 __le16 cookie;
1645 __le32 xid;
1646 u8 v;
1647 #define CREQ_MODIFY_GID_RESP_V 0x1UL
1648 u8 event;
1649 #define CREQ_MODIFY_GID_RESP_EVENT_ADD_GID 0x11UL
1650 #define CREQ_MODIFY_GID_RESP_EVENT_LAST CREQ_MODIFY_GID_RESP_EVENT_ADD_GID
1651 u8 reserved48[6];
1652};
1653
1654/* cmdq_query_gid (size:192b/24B) */
1655struct cmdq_query_gid {
1656 u8 opcode;
1657 #define CMDQ_QUERY_GID_OPCODE_QUERY_GID 0x18UL
1658 #define CMDQ_QUERY_GID_OPCODE_LAST CMDQ_QUERY_GID_OPCODE_QUERY_GID
1659 u8 cmd_size;
1660 __le16 flags;
1661 __le16 cookie;
1662 u8 resp_size;
1663 u8 reserved8;
1664 __le64 resp_addr;
1665 __le16 gid_index;
1666 u8 unused16[6];
1667};
1668
1669/* creq_query_gid_resp (size:128b/16B) */
1670struct creq_query_gid_resp {
1671 u8 type;
1672 #define CREQ_QUERY_GID_RESP_TYPE_MASK 0x3fUL
1673 #define CREQ_QUERY_GID_RESP_TYPE_SFT 0
1674 #define CREQ_QUERY_GID_RESP_TYPE_QP_EVENT 0x38UL
1675 #define CREQ_QUERY_GID_RESP_TYPE_LAST CREQ_QUERY_GID_RESP_TYPE_QP_EVENT
1676 u8 status;
1677 __le16 cookie;
1678 __le32 size;
1679 u8 v;
1680 #define CREQ_QUERY_GID_RESP_V 0x1UL
1681 u8 event;
1682 #define CREQ_QUERY_GID_RESP_EVENT_QUERY_GID 0x18UL
1683 #define CREQ_QUERY_GID_RESP_EVENT_LAST CREQ_QUERY_GID_RESP_EVENT_QUERY_GID
1684 u8 reserved48[6];
1685};
1686
1687/* creq_query_gid_resp_sb (size:320b/40B) */
1688struct creq_query_gid_resp_sb {
1689 u8 opcode;
1690 #define CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID 0x18UL
1691 #define CREQ_QUERY_GID_RESP_SB_OPCODE_LAST CREQ_QUERY_GID_RESP_SB_OPCODE_QUERY_GID
1692 u8 status;
1693 __le16 cookie;
1694 __le16 flags;
1695 u8 resp_size;
1696 u8 reserved8;
1697 __le32 gid[4];
1698 __le16 src_mac[3];
1699 __le16 vlan;
1700 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_MASK 0xffffUL
1701 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN_TPID_VLAN_ID_SFT 0
1702 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_MASK 0xfffUL
1703 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_ID_SFT 0
1704 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_MASK 0x7000UL
1705 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_SFT 12
1706 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_88A8 (0x0UL << 12)
1707 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_8100 (0x1UL << 12)
1708 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9100 (0x2UL << 12)
1709 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9200 (0x3UL << 12)
1710 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_9300 (0x4UL << 12)
1711 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG1 (0x5UL << 12)
1712 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG2 (0x6UL << 12)
1713 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3 (0x7UL << 12)
1714 #define CREQ_QUERY_GID_RESP_SB_VLAN_TPID_LAST CREQ_QUERY_GID_RESP_SB_VLAN_TPID_TPID_CFG3
1715 #define CREQ_QUERY_GID_RESP_SB_VLAN_VLAN_EN 0x8000UL
1716 __le16 ipid;
1717 __le16 gid_index;
1718 __le32 unused_0;
1719};
1720
1721/* cmdq_create_qp1 (size:640b/80B) */
1722struct cmdq_create_qp1 {
1723 u8 opcode;
1724 #define CMDQ_CREATE_QP1_OPCODE_CREATE_QP1 0x13UL
1725 #define CMDQ_CREATE_QP1_OPCODE_LAST CMDQ_CREATE_QP1_OPCODE_CREATE_QP1
1726 u8 cmd_size;
1727 __le16 flags;
1728 __le16 cookie;
1729 u8 resp_size;
1730 u8 reserved8;
1731 __le64 resp_addr;
1732 __le64 qp_handle;
1733 __le32 qp_flags;
1734 #define CMDQ_CREATE_QP1_QP_FLAGS_SRQ_USED 0x1UL
1735 #define CMDQ_CREATE_QP1_QP_FLAGS_FORCE_COMPLETION 0x2UL
1736 #define CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE 0x4UL
1737 #define CMDQ_CREATE_QP1_QP_FLAGS_LAST CMDQ_CREATE_QP1_QP_FLAGS_RESERVED_LKEY_ENABLE
1738 u8 type;
1739 #define CMDQ_CREATE_QP1_TYPE_GSI 0x1UL
1740 #define CMDQ_CREATE_QP1_TYPE_LAST CMDQ_CREATE_QP1_TYPE_GSI
1741 u8 sq_pg_size_sq_lvl;
1742 #define CMDQ_CREATE_QP1_SQ_LVL_MASK 0xfUL
1743 #define CMDQ_CREATE_QP1_SQ_LVL_SFT 0
1744 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_0 0x0UL
1745 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_1 0x1UL
1746 #define CMDQ_CREATE_QP1_SQ_LVL_LVL_2 0x2UL
1747 #define CMDQ_CREATE_QP1_SQ_LVL_LAST CMDQ_CREATE_QP1_SQ_LVL_LVL_2
1748 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_MASK 0xf0UL
1749 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_SFT 4
1750 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_4K (0x0UL << 4)
1751 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8K (0x1UL << 4)
1752 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_64K (0x2UL << 4)
1753 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_2M (0x3UL << 4)
1754 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_8M (0x4UL << 4)
1755 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G (0x5UL << 4)
1756 #define CMDQ_CREATE_QP1_SQ_PG_SIZE_LAST CMDQ_CREATE_QP1_SQ_PG_SIZE_PG_1G
1757 u8 rq_pg_size_rq_lvl;
1758 #define CMDQ_CREATE_QP1_RQ_LVL_MASK 0xfUL
1759 #define CMDQ_CREATE_QP1_RQ_LVL_SFT 0
1760 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_0 0x0UL
1761 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_1 0x1UL
1762 #define CMDQ_CREATE_QP1_RQ_LVL_LVL_2 0x2UL
1763 #define CMDQ_CREATE_QP1_RQ_LVL_LAST CMDQ_CREATE_QP1_RQ_LVL_LVL_2
1764 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_MASK 0xf0UL
1765 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_SFT 4
1766 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_4K (0x0UL << 4)
1767 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8K (0x1UL << 4)
1768 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_64K (0x2UL << 4)
1769 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_2M (0x3UL << 4)
1770 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_8M (0x4UL << 4)
1771 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G (0x5UL << 4)
1772 #define CMDQ_CREATE_QP1_RQ_PG_SIZE_LAST CMDQ_CREATE_QP1_RQ_PG_SIZE_PG_1G
1773 u8 unused_0;
1774 __le32 dpi;
1775 __le32 sq_size;
1776 __le32 rq_size;
1777 __le16 sq_fwo_sq_sge;
1778 #define CMDQ_CREATE_QP1_SQ_SGE_MASK 0xfUL
1779 #define CMDQ_CREATE_QP1_SQ_SGE_SFT 0
1780 #define CMDQ_CREATE_QP1_SQ_FWO_MASK 0xfff0UL
1781 #define CMDQ_CREATE_QP1_SQ_FWO_SFT 4
1782 __le16 rq_fwo_rq_sge;
1783 #define CMDQ_CREATE_QP1_RQ_SGE_MASK 0xfUL
1784 #define CMDQ_CREATE_QP1_RQ_SGE_SFT 0
1785 #define CMDQ_CREATE_QP1_RQ_FWO_MASK 0xfff0UL
1786 #define CMDQ_CREATE_QP1_RQ_FWO_SFT 4
1787 __le32 scq_cid;
1788 __le32 rcq_cid;
1789 __le32 srq_cid;
1790 __le32 pd_id;
1791 __le64 sq_pbl;
1792 __le64 rq_pbl;
1793};
1794
1795/* creq_create_qp1_resp (size:128b/16B) */
1796struct creq_create_qp1_resp {
1797 u8 type;
1798 #define CREQ_CREATE_QP1_RESP_TYPE_MASK 0x3fUL
1799 #define CREQ_CREATE_QP1_RESP_TYPE_SFT 0
1800 #define CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT 0x38UL
1801 #define CREQ_CREATE_QP1_RESP_TYPE_LAST CREQ_CREATE_QP1_RESP_TYPE_QP_EVENT
1802 u8 status;
1803 __le16 cookie;
1804 __le32 xid;
1805 u8 v;
1806 #define CREQ_CREATE_QP1_RESP_V 0x1UL
1807 u8 event;
1808 #define CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1 0x13UL
1809 #define CREQ_CREATE_QP1_RESP_EVENT_LAST CREQ_CREATE_QP1_RESP_EVENT_CREATE_QP1
1810 u8 reserved48[6];
1811};
1812
1813/* cmdq_destroy_qp1 (size:192b/24B) */
1814struct cmdq_destroy_qp1 {
1815 u8 opcode;
1816 #define CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1 0x14UL
1817 #define CMDQ_DESTROY_QP1_OPCODE_LAST CMDQ_DESTROY_QP1_OPCODE_DESTROY_QP1
1818 u8 cmd_size;
1819 __le16 flags;
1820 __le16 cookie;
1821 u8 resp_size;
1822 u8 reserved8;
1823 __le64 resp_addr;
1824 __le32 qp1_cid;
1825 __le32 unused_0;
1826};
1827
1828/* creq_destroy_qp1_resp (size:128b/16B) */
1829struct creq_destroy_qp1_resp {
1830 u8 type;
1831 #define CREQ_DESTROY_QP1_RESP_TYPE_MASK 0x3fUL
1832 #define CREQ_DESTROY_QP1_RESP_TYPE_SFT 0
1833 #define CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT 0x38UL
1834 #define CREQ_DESTROY_QP1_RESP_TYPE_LAST CREQ_DESTROY_QP1_RESP_TYPE_QP_EVENT
1835 u8 status;
1836 __le16 cookie;
1837 __le32 xid;
1838 u8 v;
1839 #define CREQ_DESTROY_QP1_RESP_V 0x1UL
1840 u8 event;
1841 #define CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1 0x14UL
1842 #define CREQ_DESTROY_QP1_RESP_EVENT_LAST CREQ_DESTROY_QP1_RESP_EVENT_DESTROY_QP1
1843 u8 reserved48[6];
1844};
1845
1846/* cmdq_create_ah (size:512b/64B) */
1847struct cmdq_create_ah {
1848 u8 opcode;
1849 #define CMDQ_CREATE_AH_OPCODE_CREATE_AH 0x15UL
1850 #define CMDQ_CREATE_AH_OPCODE_LAST CMDQ_CREATE_AH_OPCODE_CREATE_AH
1851 u8 cmd_size;
1852 __le16 flags;
1853 __le16 cookie;
1854 u8 resp_size;
1855 u8 reserved8;
1856 __le64 resp_addr;
1857 __le64 ah_handle;
1858 __le32 dgid[4];
1859 u8 type;
1860 #define CMDQ_CREATE_AH_TYPE_V1 0x0UL
1861 #define CMDQ_CREATE_AH_TYPE_V2IPV4 0x2UL
1862 #define CMDQ_CREATE_AH_TYPE_V2IPV6 0x3UL
1863 #define CMDQ_CREATE_AH_TYPE_LAST CMDQ_CREATE_AH_TYPE_V2IPV6
1864 u8 hop_limit;
1865 __le16 sgid_index;
1866 __le32 dest_vlan_id_flow_label;
1867 #define CMDQ_CREATE_AH_FLOW_LABEL_MASK 0xfffffUL
1868 #define CMDQ_CREATE_AH_FLOW_LABEL_SFT 0
1869 #define CMDQ_CREATE_AH_DEST_VLAN_ID_MASK 0xfff00000UL
1870 #define CMDQ_CREATE_AH_DEST_VLAN_ID_SFT 20
1871 __le32 pd_id;
1872 __le32 unused_0;
1873 __le16 dest_mac[3];
1874 u8 traffic_class;
1875 u8 enable_cc;
1876 #define CMDQ_CREATE_AH_ENABLE_CC 0x1UL
1877};
1878
1879/* creq_create_ah_resp (size:128b/16B) */
1880struct creq_create_ah_resp {
1881 u8 type;
1882 #define CREQ_CREATE_AH_RESP_TYPE_MASK 0x3fUL
1883 #define CREQ_CREATE_AH_RESP_TYPE_SFT 0
1884 #define CREQ_CREATE_AH_RESP_TYPE_QP_EVENT 0x38UL
1885 #define CREQ_CREATE_AH_RESP_TYPE_LAST CREQ_CREATE_AH_RESP_TYPE_QP_EVENT
1886 u8 status;
1887 __le16 cookie;
1888 __le32 xid;
1889 u8 v;
1890 #define CREQ_CREATE_AH_RESP_V 0x1UL
1891 u8 event;
1892 #define CREQ_CREATE_AH_RESP_EVENT_CREATE_AH 0x15UL
1893 #define CREQ_CREATE_AH_RESP_EVENT_LAST CREQ_CREATE_AH_RESP_EVENT_CREATE_AH
1894 u8 reserved48[6];
1895};
1896
1897/* cmdq_destroy_ah (size:192b/24B) */
1898struct cmdq_destroy_ah {
1899 u8 opcode;
1900 #define CMDQ_DESTROY_AH_OPCODE_DESTROY_AH 0x16UL
1901 #define CMDQ_DESTROY_AH_OPCODE_LAST CMDQ_DESTROY_AH_OPCODE_DESTROY_AH
1902 u8 cmd_size;
1903 __le16 flags;
1904 __le16 cookie;
1905 u8 resp_size;
1906 u8 reserved8;
1907 __le64 resp_addr;
1908 __le32 ah_cid;
1909 __le32 unused_0;
1910};
1911
1912/* creq_destroy_ah_resp (size:128b/16B) */
1913struct creq_destroy_ah_resp {
1914 u8 type;
1915 #define CREQ_DESTROY_AH_RESP_TYPE_MASK 0x3fUL
1916 #define CREQ_DESTROY_AH_RESP_TYPE_SFT 0
1917 #define CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT 0x38UL
1918 #define CREQ_DESTROY_AH_RESP_TYPE_LAST CREQ_DESTROY_AH_RESP_TYPE_QP_EVENT
1919 u8 status;
1920 __le16 cookie;
1921 __le32 xid;
1922 u8 v;
1923 #define CREQ_DESTROY_AH_RESP_V 0x1UL
1924 u8 event;
1925 #define CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH 0x16UL
1926 #define CREQ_DESTROY_AH_RESP_EVENT_LAST CREQ_DESTROY_AH_RESP_EVENT_DESTROY_AH
1927 u8 reserved48[6];
1928};
1929
1930/* cmdq_query_roce_stats (size:192b/24B) */
1931struct cmdq_query_roce_stats {
1932 u8 opcode;
1933 #define CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS 0x8eUL
1934 #define CMDQ_QUERY_ROCE_STATS_OPCODE_LAST CMDQ_QUERY_ROCE_STATS_OPCODE_QUERY_ROCE_STATS
1935 u8 cmd_size;
1936 __le16 flags;
1937 #define CMDQ_QUERY_ROCE_STATS_FLAGS_COLLECTION_ID 0x1UL
1938 #define CMDQ_QUERY_ROCE_STATS_FLAGS_FUNCTION_ID 0x2UL
1939 __le16 cookie;
1940 u8 resp_size;
1941 u8 collection_id;
1942 __le64 resp_addr;
1943 __le32 function_id;
1944 #define CMDQ_QUERY_ROCE_STATS_PF_NUM_MASK 0xffUL
1945 #define CMDQ_QUERY_ROCE_STATS_PF_NUM_SFT 0
1946 #define CMDQ_QUERY_ROCE_STATS_VF_NUM_MASK 0xffff00UL
1947 #define CMDQ_QUERY_ROCE_STATS_VF_NUM_SFT 8
1948 #define CMDQ_QUERY_ROCE_STATS_VF_VALID 0x1000000UL
1949 __le32 reserved32;
1950};
1951
1952/* creq_query_roce_stats_resp (size:128b/16B) */
1953struct creq_query_roce_stats_resp {
1954 u8 type;
1955 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_MASK 0x3fUL
1956 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_SFT 0
1957 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT 0x38UL
1958 #define CREQ_QUERY_ROCE_STATS_RESP_TYPE_LAST CREQ_QUERY_ROCE_STATS_RESP_TYPE_QP_EVENT
1959 u8 status;
1960 __le16 cookie;
1961 __le32 size;
1962 u8 v;
1963 #define CREQ_QUERY_ROCE_STATS_RESP_V 0x1UL
1964 u8 event;
1965 #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS 0x8eUL
1966 #define CREQ_QUERY_ROCE_STATS_RESP_EVENT_LAST \
1967 CREQ_QUERY_ROCE_STATS_RESP_EVENT_QUERY_ROCE_STATS
1968 u8 reserved48[6];
1969};
1970
1971/* creq_query_roce_stats_resp_sb (size:2944b/368B) */
1972struct creq_query_roce_stats_resp_sb {
1973 u8 opcode;
1974 #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS 0x8eUL
1975 #define CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_LAST \
1976 CREQ_QUERY_ROCE_STATS_RESP_SB_OPCODE_QUERY_ROCE_STATS
1977 u8 status;
1978 __le16 cookie;
1979 __le16 flags;
1980 u8 resp_size;
1981 u8 rsvd;
1982 __le32 num_counters;
1983 __le32 rsvd1;
1984 __le64 to_retransmits;
1985 __le64 seq_err_naks_rcvd;
1986 __le64 max_retry_exceeded;
1987 __le64 rnr_naks_rcvd;
1988 __le64 missing_resp;
1989 __le64 unrecoverable_err;
1990 __le64 bad_resp_err;
1991 __le64 local_qp_op_err;
1992 __le64 local_protection_err;
1993 __le64 mem_mgmt_op_err;
1994 __le64 remote_invalid_req_err;
1995 __le64 remote_access_err;
1996 __le64 remote_op_err;
1997 __le64 dup_req;
1998 __le64 res_exceed_max;
1999 __le64 res_length_mismatch;
2000 __le64 res_exceeds_wqe;
2001 __le64 res_opcode_err;
2002 __le64 res_rx_invalid_rkey;
2003 __le64 res_rx_domain_err;
2004 __le64 res_rx_no_perm;
2005 __le64 res_rx_range_err;
2006 __le64 res_tx_invalid_rkey;
2007 __le64 res_tx_domain_err;
2008 __le64 res_tx_no_perm;
2009 __le64 res_tx_range_err;
2010 __le64 res_irrq_oflow;
2011 __le64 res_unsup_opcode;
2012 __le64 res_unaligned_atomic;
2013 __le64 res_rem_inv_err;
2014 __le64 res_mem_error;
2015 __le64 res_srq_err;
2016 __le64 res_cmp_err;
2017 __le64 res_invalid_dup_rkey;
2018 __le64 res_wqe_format_err;
2019 __le64 res_cq_load_err;
2020 __le64 res_srq_load_err;
2021 __le64 res_tx_pci_err;
2022 __le64 res_rx_pci_err;
2023 __le64 res_oos_drop_count;
2024 __le64 active_qp_count_p0;
2025 __le64 active_qp_count_p1;
2026 __le64 active_qp_count_p2;
2027 __le64 active_qp_count_p3;
2028};
2029
2030/* cmdq_query_roce_stats_ext (size:192b/24B) */
2031struct cmdq_query_roce_stats_ext {
2032 u8 opcode;
2033 #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS 0x92UL
2034 #define CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_LAST \
2035 CMDQ_QUERY_ROCE_STATS_EXT_OPCODE_QUERY_ROCE_STATS
2036 u8 cmd_size;
2037 __le16 flags;
2038 #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_COLLECTION_ID 0x1UL
2039 #define CMDQ_QUERY_ROCE_STATS_EXT_FLAGS_FUNCTION_ID 0x2UL
2040 __le16 cookie;
2041 u8 resp_size;
2042 u8 collection_id;
2043 __le64 resp_addr;
2044 __le32 function_id;
2045 #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_MASK 0xffUL
2046 #define CMDQ_QUERY_ROCE_STATS_EXT_PF_NUM_SFT 0
2047 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_MASK 0xffff00UL
2048 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_NUM_SFT 8
2049 #define CMDQ_QUERY_ROCE_STATS_EXT_VF_VALID 0x1000000UL
2050 __le32 reserved32;
2051};
2052
2053/* creq_query_roce_stats_ext_resp (size:128b/16B) */
2054struct creq_query_roce_stats_ext_resp {
2055 u8 type;
2056 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_MASK 0x3fUL
2057 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_SFT 0
2058 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT 0x38UL
2059 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_LAST \
2060 CREQ_QUERY_ROCE_STATS_EXT_RESP_TYPE_QP_EVENT
2061 u8 status;
2062 __le16 cookie;
2063 __le32 size;
2064 u8 v;
2065 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_V 0x1UL
2066 u8 event;
2067 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT 0x92UL
2068 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_LAST \
2069 CREQ_QUERY_ROCE_STATS_EXT_RESP_EVENT_QUERY_ROCE_STATS_EXT
2070 u8 reserved48[6];
2071};
2072
2073/* creq_query_roce_stats_ext_resp_sb (size:1856b/232B) */
2074struct creq_query_roce_stats_ext_resp_sb {
2075 u8 opcode;
2076 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT 0x92UL
2077 #define CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_LAST \
2078 CREQ_QUERY_ROCE_STATS_EXT_RESP_SB_OPCODE_QUERY_ROCE_STATS_EXT
2079 u8 status;
2080 __le16 cookie;
2081 __le16 flags;
2082 u8 resp_size;
2083 u8 rsvd;
2084 __le64 tx_atomic_req_pkts;
2085 __le64 tx_read_req_pkts;
2086 __le64 tx_read_res_pkts;
2087 __le64 tx_write_req_pkts;
2088 __le64 tx_send_req_pkts;
2089 __le64 tx_roce_pkts;
2090 __le64 tx_roce_bytes;
2091 __le64 rx_atomic_req_pkts;
2092 __le64 rx_read_req_pkts;
2093 __le64 rx_read_res_pkts;
2094 __le64 rx_write_req_pkts;
2095 __le64 rx_send_req_pkts;
2096 __le64 rx_roce_pkts;
2097 __le64 rx_roce_bytes;
2098 __le64 rx_roce_good_pkts;
2099 __le64 rx_roce_good_bytes;
2100 __le64 rx_out_of_buffer_pkts;
2101 __le64 rx_out_of_sequence_pkts;
2102 __le64 tx_cnp_pkts;
2103 __le64 rx_cnp_pkts;
2104 __le64 rx_ecn_marked_pkts;
2105 __le64 tx_cnp_bytes;
2106 __le64 rx_cnp_bytes;
2107 __le64 seq_err_naks_rcvd;
2108 __le64 rnr_naks_rcvd;
2109 __le64 missing_resp;
2110 __le64 to_retransmit;
2111 __le64 dup_req;
2112};
2113
2114/* cmdq_roce_mirror_cfg (size:192b/24B) */
2115struct cmdq_roce_mirror_cfg {
2116 u8 opcode;
2117 #define CMDQ_ROCE_MIRROR_CFG_OPCODE_ROCE_MIRROR_CFG 0x99UL
2118 #define CMDQ_ROCE_MIRROR_CFG_OPCODE_LAST \
2119 CMDQ_ROCE_MIRROR_CFG_OPCODE_ROCE_MIRROR_CFG
2120 u8 cmd_size;
2121 __le16 flags;
2122 __le16 cookie;
2123 u8 resp_size;
2124 u8 reserved8;
2125 __le64 resp_addr;
2126 u8 mirror_flags;
2127 #define CMDQ_ROCE_MIRROR_CFG_MIRROR_ENABLE 0x1UL
2128 u8 rsvd[7];
2129};
2130
2131/* creq_roce_mirror_cfg_resp (size:128b/16B) */
2132struct creq_roce_mirror_cfg_resp {
2133 u8 type;
2134 #define CREQ_ROCE_MIRROR_CFG_RESP_TYPE_MASK 0x3fUL
2135 #define CREQ_ROCE_MIRROR_CFG_RESP_TYPE_SFT 0
2136 #define CREQ_ROCE_MIRROR_CFG_RESP_TYPE_QP_EVENT 0x38UL
2137 #define CREQ_ROCE_MIRROR_CFG_RESP_TYPE_LAST \
2138 CREQ_ROCE_MIRROR_CFG_RESP_TYPE_QP_EVENT
2139 u8 status;
2140 __le16 cookie;
2141 __le32 reserved32;
2142 u8 v;
2143 #define CREQ_ROCE_MIRROR_CFG_RESP_V 0x1UL
2144 u8 event;
2145 #define CREQ_ROCE_MIRROR_CFG_RESP_EVENT_ROCE_MIRROR_CFG 0x99UL
2146 #define CREQ_ROCE_MIRROR_CFG_RESP_EVENT_LAST \
2147 CREQ_ROCE_MIRROR_CFG_RESP_EVENT_ROCE_MIRROR_CFG
2148 u8 reserved48[6];
2149};
2150
2151/* cmdq_query_func (size:128b/16B) */
2152struct cmdq_query_func {
2153 u8 opcode;
2154 #define CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC 0x83UL
2155 #define CMDQ_QUERY_FUNC_OPCODE_LAST CMDQ_QUERY_FUNC_OPCODE_QUERY_FUNC
2156 u8 cmd_size;
2157 __le16 flags;
2158 __le16 cookie;
2159 u8 resp_size;
2160 u8 reserved8;
2161 __le64 resp_addr;
2162};
2163
2164/* creq_query_func_resp (size:128b/16B) */
2165struct creq_query_func_resp {
2166 u8 type;
2167 #define CREQ_QUERY_FUNC_RESP_TYPE_MASK 0x3fUL
2168 #define CREQ_QUERY_FUNC_RESP_TYPE_SFT 0
2169 #define CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT 0x38UL
2170 #define CREQ_QUERY_FUNC_RESP_TYPE_LAST CREQ_QUERY_FUNC_RESP_TYPE_QP_EVENT
2171 u8 status;
2172 __le16 cookie;
2173 __le32 size;
2174 u8 v;
2175 #define CREQ_QUERY_FUNC_RESP_V 0x1UL
2176 u8 event;
2177 #define CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC 0x83UL
2178 #define CREQ_QUERY_FUNC_RESP_EVENT_LAST CREQ_QUERY_FUNC_RESP_EVENT_QUERY_FUNC
2179 u8 reserved48[6];
2180};
2181
2182/* creq_query_func_resp_sb (size:1088b/136B) */
2183struct creq_query_func_resp_sb {
2184 u8 opcode;
2185 #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC 0x83UL
2186 #define CREQ_QUERY_FUNC_RESP_SB_OPCODE_LAST CREQ_QUERY_FUNC_RESP_SB_OPCODE_QUERY_FUNC
2187 u8 status;
2188 __le16 cookie;
2189 __le16 flags;
2190 u8 resp_size;
2191 u8 reserved8;
2192 __le64 max_mr_size;
2193 __le32 max_qp;
2194 __le16 max_qp_wr;
2195 __le16 dev_cap_flags;
2196 #define CREQ_QUERY_FUNC_RESP_SB_RESIZE_QP 0x1UL
2197 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_MASK 0xeUL
2198 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_SFT 1
2199 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN0 (0x0UL << 1)
2200 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1 (0x1UL << 1)
2201 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT (0x2UL << 1)
2202 #define CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_LAST \
2203 CREQ_QUERY_FUNC_RESP_SB_CC_GENERATION_CC_GEN1_EXT
2204 #define CREQ_QUERY_FUNC_RESP_SB_EXT_STATS 0x10UL
2205 #define CREQ_QUERY_FUNC_RESP_SB_MR_REGISTER_ALLOC 0x20UL
2206 #define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZED_TRANSMIT_ENABLED 0x40UL
2207 #define CREQ_QUERY_FUNC_RESP_SB_CQE_V2 0x80UL
2208 #define CREQ_QUERY_FUNC_RESP_SB_PINGPONG_PUSH_MODE 0x100UL
2209 #define CREQ_QUERY_FUNC_RESP_SB_HW_REQUESTER_RETX_ENABLED 0x200UL
2210 #define CREQ_QUERY_FUNC_RESP_SB_HW_RESPONDER_RETX_ENABLED 0x400UL
2211 __le32 max_cq;
2212 __le32 max_cqe;
2213 __le32 max_pd;
2214 u8 max_sge;
2215 u8 max_srq_sge;
2216 u8 max_qp_rd_atom;
2217 u8 max_qp_init_rd_atom;
2218 __le32 max_mr;
2219 __le32 max_mw;
2220 __le32 max_raw_eth_qp;
2221 __le32 max_ah;
2222 __le32 max_fmr;
2223 __le32 max_srq_wr;
2224 __le32 max_pkeys;
2225 __le32 max_inline_data;
2226 u8 max_map_per_fmr;
2227 u8 l2_db_space_size;
2228 __le16 max_srq;
2229 __le32 max_gid;
2230 __le32 tqm_alloc_reqs[12];
2231 __le32 max_dpi;
2232 u8 max_sge_var_wqe;
2233 u8 dev_cap_ext_flags;
2234 #define CREQ_QUERY_FUNC_RESP_SB_ATOMIC_OPS_NOT_SUPPORTED 0x1UL
2235 #define CREQ_QUERY_FUNC_RESP_SB_DRV_VERSION_RGTR_SUPPORTED 0x2UL
2236 #define CREQ_QUERY_FUNC_RESP_SB_CREATE_QP_BATCH_SUPPORTED 0x4UL
2237 #define CREQ_QUERY_FUNC_RESP_SB_DESTROY_QP_BATCH_SUPPORTED 0x8UL
2238 #define CREQ_QUERY_FUNC_RESP_SB_ROCE_STATS_EXT_CTX_SUPPORTED 0x10UL
2239 #define CREQ_QUERY_FUNC_RESP_SB_CREATE_SRQ_SGE_SUPPORTED 0x20UL
2240 #define CREQ_QUERY_FUNC_RESP_SB_FIXED_SIZE_WQE_DISABLED 0x40UL
2241 #define CREQ_QUERY_FUNC_RESP_SB_DCN_SUPPORTED 0x80UL
2242 __le16 max_inline_data_var_wqe;
2243 __le32 start_qid;
2244 u8 max_msn_table_size;
2245 u8 reserved8_1;
2246 __le16 dev_cap_ext_flags_2;
2247 #define CREQ_QUERY_FUNC_RESP_SB_OPTIMIZE_MODIFY_QP_SUPPORTED 0x1UL
2248 #define CREQ_QUERY_FUNC_RESP_SB_CHANGE_UDP_SRC_PORT_WQE_SUPPORTED 0x2UL
2249 #define CREQ_QUERY_FUNC_RESP_SB_CQ_COALESCING_SUPPORTED 0x4UL
2250 #define CREQ_QUERY_FUNC_RESP_SB_MEMORY_REGION_RO_SUPPORTED 0x8UL
2251 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_MASK 0x30UL
2252 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_SFT 4
2253 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_PSN_TABLE (0x0UL << 4)
2254 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_HOST_MSN_TABLE (0x1UL << 4)
2255 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE (0x2UL << 4)
2256 #define CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_LAST \
2257 CREQ_QUERY_FUNC_RESP_SB_REQ_RETRANSMISSION_SUPPORT_IQM_MSN_TABLE
2258 #define CREQ_QUERY_FUNC_RESP_SB_MAX_SRQ_EXTENDED 0x40UL
2259 #define CREQ_QUERY_FUNC_RESP_SB_MIN_RNR_RTR_RTS_OPT_SUPPORTED 0x1000UL
2260 __le16 max_xp_qp_size;
2261 __le16 create_qp_batch_size;
2262 __le16 destroy_qp_batch_size;
2263 __le16 max_srq_ext;
2264 __le64 reserved64;
2265};
2266
2267/* cmdq_set_func_resources (size:448b/56B) */
2268struct cmdq_set_func_resources {
2269 u8 opcode;
2270 #define CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES 0x84UL
2271 #define CMDQ_SET_FUNC_RESOURCES_OPCODE_LAST\
2272 CMDQ_SET_FUNC_RESOURCES_OPCODE_SET_FUNC_RESOURCES
2273 u8 cmd_size;
2274 __le16 flags;
2275 #define CMDQ_SET_FUNC_RESOURCES_FLAGS_MRAV_RESERVATION_SPLIT 0x1UL
2276 __le16 cookie;
2277 u8 resp_size;
2278 u8 reserved8;
2279 __le64 resp_addr;
2280 __le32 number_of_qp;
2281 __le32 number_of_mrw;
2282 __le32 number_of_srq;
2283 __le32 number_of_cq;
2284 __le32 max_qp_per_vf;
2285 __le32 max_mrw_per_vf;
2286 __le32 max_srq_per_vf;
2287 __le32 max_cq_per_vf;
2288 __le32 max_gid_per_vf;
2289 __le32 stat_ctx_id;
2290};
2291
2292/* creq_set_func_resources_resp (size:128b/16B) */
2293struct creq_set_func_resources_resp {
2294 u8 type;
2295 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_MASK 0x3fUL
2296 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_SFT 0
2297 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT 0x38UL
2298 #define CREQ_SET_FUNC_RESOURCES_RESP_TYPE_LAST CREQ_SET_FUNC_RESOURCES_RESP_TYPE_QP_EVENT
2299 u8 status;
2300 __le16 cookie;
2301 __le32 reserved32;
2302 u8 v;
2303 #define CREQ_SET_FUNC_RESOURCES_RESP_V 0x1UL
2304 u8 event;
2305 #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES 0x84UL
2306 #define CREQ_SET_FUNC_RESOURCES_RESP_EVENT_LAST \
2307 CREQ_SET_FUNC_RESOURCES_RESP_EVENT_SET_FUNC_RESOURCES
2308 u8 reserved48[6];
2309};
2310
2311/* cmdq_read_context (size:192b/24B) */
2312struct cmdq_read_context {
2313 u8 opcode;
2314 #define CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT 0x85UL
2315 #define CMDQ_READ_CONTEXT_OPCODE_LAST CMDQ_READ_CONTEXT_OPCODE_READ_CONTEXT
2316 u8 cmd_size;
2317 __le16 flags;
2318 __le16 cookie;
2319 u8 resp_size;
2320 u8 reserved8;
2321 __le64 resp_addr;
2322 __le32 xid;
2323 u8 type;
2324 #define CMDQ_READ_CONTEXT_TYPE_QPC 0x0UL
2325 #define CMDQ_READ_CONTEXT_TYPE_CQ 0x1UL
2326 #define CMDQ_READ_CONTEXT_TYPE_MRW 0x2UL
2327 #define CMDQ_READ_CONTEXT_TYPE_SRQ 0x3UL
2328 #define CMDQ_READ_CONTEXT_TYPE_LAST CMDQ_READ_CONTEXT_TYPE_SRQ
2329 u8 unused_0[3];
2330};
2331
2332/* creq_read_context (size:128b/16B) */
2333struct creq_read_context {
2334 u8 type;
2335 #define CREQ_READ_CONTEXT_TYPE_MASK 0x3fUL
2336 #define CREQ_READ_CONTEXT_TYPE_SFT 0
2337 #define CREQ_READ_CONTEXT_TYPE_QP_EVENT 0x38UL
2338 #define CREQ_READ_CONTEXT_TYPE_LAST CREQ_READ_CONTEXT_TYPE_QP_EVENT
2339 u8 status;
2340 __le16 cookie;
2341 __le32 reserved32;
2342 u8 v;
2343 #define CREQ_READ_CONTEXT_V 0x1UL
2344 u8 event;
2345 #define CREQ_READ_CONTEXT_EVENT_READ_CONTEXT 0x85UL
2346 #define CREQ_READ_CONTEXT_EVENT_LAST CREQ_READ_CONTEXT_EVENT_READ_CONTEXT
2347 __le16 reserved16;
2348 __le32 reserved_32;
2349};
2350
2351/* cmdq_map_tc_to_cos (size:192b/24B) */
2352struct cmdq_map_tc_to_cos {
2353 u8 opcode;
2354 #define CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS 0x8aUL
2355 #define CMDQ_MAP_TC_TO_COS_OPCODE_LAST CMDQ_MAP_TC_TO_COS_OPCODE_MAP_TC_TO_COS
2356 u8 cmd_size;
2357 __le16 flags;
2358 __le16 cookie;
2359 u8 resp_size;
2360 u8 reserved8;
2361 __le64 resp_addr;
2362 __le16 cos0;
2363 #define CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE 0xffffUL
2364 #define CMDQ_MAP_TC_TO_COS_COS0_LAST CMDQ_MAP_TC_TO_COS_COS0_NO_CHANGE
2365 __le16 cos1;
2366 #define CMDQ_MAP_TC_TO_COS_COS1_DISABLE 0x8000UL
2367 #define CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE 0xffffUL
2368 #define CMDQ_MAP_TC_TO_COS_COS1_LAST CMDQ_MAP_TC_TO_COS_COS1_NO_CHANGE
2369 __le32 unused_0;
2370};
2371
2372/* creq_map_tc_to_cos_resp (size:128b/16B) */
2373struct creq_map_tc_to_cos_resp {
2374 u8 type;
2375 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_MASK 0x3fUL
2376 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_SFT 0
2377 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT 0x38UL
2378 #define CREQ_MAP_TC_TO_COS_RESP_TYPE_LAST CREQ_MAP_TC_TO_COS_RESP_TYPE_QP_EVENT
2379 u8 status;
2380 __le16 cookie;
2381 __le32 reserved32;
2382 u8 v;
2383 #define CREQ_MAP_TC_TO_COS_RESP_V 0x1UL
2384 u8 event;
2385 #define CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS 0x8aUL
2386 #define CREQ_MAP_TC_TO_COS_RESP_EVENT_LAST CREQ_MAP_TC_TO_COS_RESP_EVENT_MAP_TC_TO_COS
2387 u8 reserved48[6];
2388};
2389
2390/* cmdq_query_roce_cc (size:128b/16B) */
2391struct cmdq_query_roce_cc {
2392 u8 opcode;
2393 #define CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC 0x8dUL
2394 #define CMDQ_QUERY_ROCE_CC_OPCODE_LAST CMDQ_QUERY_ROCE_CC_OPCODE_QUERY_ROCE_CC
2395 u8 cmd_size;
2396 __le16 flags;
2397 __le16 cookie;
2398 u8 resp_size;
2399 u8 reserved8;
2400 __le64 resp_addr;
2401};
2402
2403/* creq_query_roce_cc_resp (size:128b/16B) */
2404struct creq_query_roce_cc_resp {
2405 u8 type;
2406 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_MASK 0x3fUL
2407 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_SFT 0
2408 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT 0x38UL
2409 #define CREQ_QUERY_ROCE_CC_RESP_TYPE_LAST CREQ_QUERY_ROCE_CC_RESP_TYPE_QP_EVENT
2410 u8 status;
2411 __le16 cookie;
2412 __le32 size;
2413 u8 v;
2414 #define CREQ_QUERY_ROCE_CC_RESP_V 0x1UL
2415 u8 event;
2416 #define CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC 0x8dUL
2417 #define CREQ_QUERY_ROCE_CC_RESP_EVENT_LAST CREQ_QUERY_ROCE_CC_RESP_EVENT_QUERY_ROCE_CC
2418 u8 reserved48[6];
2419};
2420
2421/* creq_query_roce_cc_resp_sb (size:256b/32B) */
2422struct creq_query_roce_cc_resp_sb {
2423 u8 opcode;
2424 #define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC 0x8dUL
2425 #define CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_LAST \
2426 CREQ_QUERY_ROCE_CC_RESP_SB_OPCODE_QUERY_ROCE_CC
2427 u8 status;
2428 __le16 cookie;
2429 __le16 flags;
2430 u8 resp_size;
2431 u8 reserved8;
2432 u8 enable_cc;
2433 #define CREQ_QUERY_ROCE_CC_RESP_SB_ENABLE_CC 0x1UL
2434 #define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_MASK 0xfeUL
2435 #define CREQ_QUERY_ROCE_CC_RESP_SB_UNUSED7_SFT 1
2436 u8 tos_dscp_tos_ecn;
2437 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_MASK 0x3UL
2438 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_ECN_SFT 0
2439 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_MASK 0xfcUL
2440 #define CREQ_QUERY_ROCE_CC_RESP_SB_TOS_DSCP_SFT 2
2441 u8 g;
2442 u8 num_phases_per_state;
2443 __le16 init_cr;
2444 __le16 init_tr;
2445 u8 alt_vlan_pcp;
2446 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_MASK 0x7UL
2447 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_VLAN_PCP_SFT 0
2448 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_MASK 0xf8UL
2449 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD1_SFT 3
2450 u8 alt_tos_dscp;
2451 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_MASK 0x3fUL
2452 #define CREQ_QUERY_ROCE_CC_RESP_SB_ALT_TOS_DSCP_SFT 0
2453 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_MASK 0xc0UL
2454 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD4_SFT 6
2455 u8 cc_mode;
2456 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_DCTCP 0x0UL
2457 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC 0x1UL
2458 #define CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_LAST \
2459 CREQ_QUERY_ROCE_CC_RESP_SB_CC_MODE_PROBABILISTIC
2460 u8 tx_queue;
2461 __le16 rtt;
2462 #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_MASK 0x3fffUL
2463 #define CREQ_QUERY_ROCE_CC_RESP_SB_RTT_SFT 0
2464 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_MASK 0xc000UL
2465 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD5_SFT 14
2466 __le16 tcp_cp;
2467 #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_MASK 0x3ffUL
2468 #define CREQ_QUERY_ROCE_CC_RESP_SB_TCP_CP_SFT 0
2469 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_MASK 0xfc00UL
2470 #define CREQ_QUERY_ROCE_CC_RESP_SB_RSVD6_SFT 10
2471 __le16 inactivity_th;
2472 u8 pkts_per_phase;
2473 u8 time_per_phase;
2474 __le32 reserved32;
2475};
2476
2477/* creq_query_roce_cc_resp_sb_tlv (size:384b/48B) */
2478struct creq_query_roce_cc_resp_sb_tlv {
2479 __le16 cmd_discr;
2480 u8 reserved_8b;
2481 u8 tlv_flags;
2482 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL
2483 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL
2484 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
2485 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL
2486 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
2487 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
2488 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \
2489 CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES
2490 __le16 tlv_type;
2491 __le16 length;
2492 u8 total_size;
2493 u8 reserved56[7];
2494 u8 opcode;
2495 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC 0x8dUL
2496 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_LAST \
2497 CREQ_QUERY_ROCE_CC_RESP_SB_TLV_OPCODE_QUERY_ROCE_CC
2498 u8 status;
2499 __le16 cookie;
2500 __le16 flags;
2501 u8 resp_size;
2502 u8 reserved8;
2503 u8 enable_cc;
2504 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ENABLE_CC 0x1UL
2505 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_MASK 0xfeUL
2506 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_UNUSED7_SFT 1
2507 u8 tos_dscp_tos_ecn;
2508 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_MASK 0x3UL
2509 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_ECN_SFT 0
2510 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_MASK 0xfcUL
2511 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TOS_DSCP_SFT 2
2512 u8 g;
2513 u8 num_phases_per_state;
2514 __le16 init_cr;
2515 __le16 init_tr;
2516 u8 alt_vlan_pcp;
2517 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_MASK 0x7UL
2518 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_VLAN_PCP_SFT 0
2519 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_MASK 0xf8UL
2520 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD1_SFT 3
2521 u8 alt_tos_dscp;
2522 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_MASK 0x3fUL
2523 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_ALT_TOS_DSCP_SFT 0
2524 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_MASK 0xc0UL
2525 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD4_SFT 6
2526 u8 cc_mode;
2527 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_DCTCP 0x0UL
2528 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC 0x1UL
2529 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_LAST\
2530 CREQ_QUERY_ROCE_CC_RESP_SB_TLV_CC_MODE_PROBABILISTIC
2531 u8 tx_queue;
2532 __le16 rtt;
2533 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_MASK 0x3fffUL
2534 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RTT_SFT 0
2535 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_MASK 0xc000UL
2536 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD5_SFT 14
2537 __le16 tcp_cp;
2538 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_MASK 0x3ffUL
2539 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_TCP_CP_SFT 0
2540 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_MASK 0xfc00UL
2541 #define CREQ_QUERY_ROCE_CC_RESP_SB_TLV_RSVD6_SFT 10
2542 __le16 inactivity_th;
2543 u8 pkts_per_phase;
2544 u8 time_per_phase;
2545 __le32 reserved32;
2546};
2547
2548/* creq_query_roce_cc_gen1_resp_sb_tlv (size:704b/88B) */
2549struct creq_query_roce_cc_gen1_resp_sb_tlv {
2550 __le16 cmd_discr;
2551 u8 reserved_8b;
2552 u8 tlv_flags;
2553 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE 0x1UL
2554 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_LAST 0x0UL
2555 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
2556 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED 0x2UL
2557 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
2558 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
2559 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_LAST \
2560 CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_TLV_FLAGS_REQUIRED_YES
2561 __le16 tlv_type;
2562 __le16 length;
2563 __le64 reserved64;
2564 __le16 inactivity_th_hi;
2565 __le16 min_time_between_cnps;
2566 __le16 init_cp;
2567 u8 tr_update_mode;
2568 u8 tr_update_cycles;
2569 u8 fr_num_rtts;
2570 u8 ai_rate_increase;
2571 __le16 reduction_relax_rtts_th;
2572 __le16 additional_relax_cr_th;
2573 __le16 cr_min_th;
2574 u8 bw_avg_weight;
2575 u8 actual_cr_factor;
2576 __le16 max_cp_cr_th;
2577 u8 cp_bias_en;
2578 u8 cp_bias;
2579 u8 cnp_ecn;
2580 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_NOT_ECT 0x0UL
2581 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_1 0x1UL
2582 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0 0x2UL
2583 #define CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_LAST \
2584 CREQ_QUERY_ROCE_CC_GEN1_RESP_SB_TLV_CNP_ECN_ECT_0
2585 u8 rtt_jitter_en;
2586 __le16 link_bytes_per_usec;
2587 __le16 reset_cc_cr_th;
2588 u8 cr_width;
2589 u8 quota_period_min;
2590 u8 quota_period_max;
2591 u8 quota_period_abs_max;
2592 __le16 tr_lower_bound;
2593 u8 cr_prob_factor;
2594 u8 tr_prob_factor;
2595 __le16 fairness_cr_th;
2596 u8 red_div;
2597 u8 cnp_ratio_th;
2598 __le16 exp_ai_rtts;
2599 u8 exp_ai_cr_cp_ratio;
2600 u8 use_rate_table;
2601 __le16 cp_exp_update_th;
2602 __le16 high_exp_ai_rtts_th1;
2603 __le16 high_exp_ai_rtts_th2;
2604 __le16 actual_cr_cong_free_rtts_th;
2605 __le16 severe_cong_cr_th1;
2606 __le16 severe_cong_cr_th2;
2607 __le32 link64B_per_rtt;
2608 u8 cc_ack_bytes;
2609 u8 reduce_init_en;
2610 __le16 reduce_init_cong_free_rtts_th;
2611 u8 random_no_red_en;
2612 u8 actual_cr_shift_correction_en;
2613 u8 quota_period_adjust_en;
2614 u8 reserved[5];
2615};
2616
2617/* cmdq_modify_roce_cc (size:448b/56B) */
2618struct cmdq_modify_roce_cc {
2619 u8 opcode;
2620 #define CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC 0x8cUL
2621 #define CMDQ_MODIFY_ROCE_CC_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_OPCODE_MODIFY_ROCE_CC
2622 u8 cmd_size;
2623 __le16 flags;
2624 __le16 cookie;
2625 u8 resp_size;
2626 u8 reserved8;
2627 __le64 resp_addr;
2628 __le32 modify_mask;
2629 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ENABLE_CC 0x1UL
2630 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_G 0x2UL
2631 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_NUMPHASEPERSTATE 0x4UL
2632 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_CR 0x8UL
2633 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INIT_TR 0x10UL
2634 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_ECN 0x20UL
2635 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TOS_DSCP 0x40UL
2636 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_VLAN_PCP 0x80UL
2637 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_ALT_TOS_DSCP 0x100UL
2638 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_RTT 0x200UL
2639 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_CC_MODE 0x400UL
2640 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TCP_CP 0x800UL
2641 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TX_QUEUE 0x1000UL
2642 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_INACTIVITY_CP 0x2000UL
2643 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_TIME_PER_PHASE 0x4000UL
2644 #define CMDQ_MODIFY_ROCE_CC_MODIFY_MASK_PKTS_PER_PHASE 0x8000UL
2645 u8 enable_cc;
2646 #define CMDQ_MODIFY_ROCE_CC_ENABLE_CC 0x1UL
2647 #define CMDQ_MODIFY_ROCE_CC_RSVD1_MASK 0xfeUL
2648 #define CMDQ_MODIFY_ROCE_CC_RSVD1_SFT 1
2649 u8 g;
2650 u8 num_phases_per_state;
2651 u8 pkts_per_phase;
2652 __le16 init_cr;
2653 __le16 init_tr;
2654 u8 tos_dscp_tos_ecn;
2655 #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_MASK 0x3UL
2656 #define CMDQ_MODIFY_ROCE_CC_TOS_ECN_SFT 0
2657 #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_MASK 0xfcUL
2658 #define CMDQ_MODIFY_ROCE_CC_TOS_DSCP_SFT 2
2659 u8 alt_vlan_pcp;
2660 #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_MASK 0x7UL
2661 #define CMDQ_MODIFY_ROCE_CC_ALT_VLAN_PCP_SFT 0
2662 #define CMDQ_MODIFY_ROCE_CC_RSVD3_MASK 0xf8UL
2663 #define CMDQ_MODIFY_ROCE_CC_RSVD3_SFT 3
2664 __le16 alt_tos_dscp;
2665 #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_MASK 0x3fUL
2666 #define CMDQ_MODIFY_ROCE_CC_ALT_TOS_DSCP_SFT 0
2667 #define CMDQ_MODIFY_ROCE_CC_RSVD4_MASK 0xffc0UL
2668 #define CMDQ_MODIFY_ROCE_CC_RSVD4_SFT 6
2669 __le16 rtt;
2670 #define CMDQ_MODIFY_ROCE_CC_RTT_MASK 0x3fffUL
2671 #define CMDQ_MODIFY_ROCE_CC_RTT_SFT 0
2672 #define CMDQ_MODIFY_ROCE_CC_RSVD5_MASK 0xc000UL
2673 #define CMDQ_MODIFY_ROCE_CC_RSVD5_SFT 14
2674 __le16 tcp_cp;
2675 #define CMDQ_MODIFY_ROCE_CC_TCP_CP_MASK 0x3ffUL
2676 #define CMDQ_MODIFY_ROCE_CC_TCP_CP_SFT 0
2677 #define CMDQ_MODIFY_ROCE_CC_RSVD6_MASK 0xfc00UL
2678 #define CMDQ_MODIFY_ROCE_CC_RSVD6_SFT 10
2679 u8 cc_mode;
2680 #define CMDQ_MODIFY_ROCE_CC_CC_MODE_DCTCP_CC_MODE 0x0UL
2681 #define CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE 0x1UL
2682 #define CMDQ_MODIFY_ROCE_CC_CC_MODE_LAST CMDQ_MODIFY_ROCE_CC_CC_MODE_PROBABILISTIC_CC_MODE
2683 u8 tx_queue;
2684 __le16 inactivity_th;
2685 u8 time_per_phase;
2686 u8 reserved8_1;
2687 __le16 reserved16;
2688 __le32 reserved32;
2689 __le64 reserved64;
2690};
2691
2692/* cmdq_modify_roce_cc_tlv (size:640b/80B) */
2693struct cmdq_modify_roce_cc_tlv {
2694 __le16 cmd_discr;
2695 u8 reserved_8b;
2696 u8 tlv_flags;
2697 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE 0x1UL
2698 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_LAST 0x0UL
2699 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
2700 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED 0x2UL
2701 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
2702 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
2703 #define CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_LAST \
2704 CMDQ_MODIFY_ROCE_CC_TLV_TLV_FLAGS_REQUIRED_YES
2705 __le16 tlv_type;
2706 __le16 length;
2707 u8 total_size;
2708 u8 reserved56[7];
2709 u8 opcode;
2710 #define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC 0x8cUL
2711 #define CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_LAST CMDQ_MODIFY_ROCE_CC_TLV_OPCODE_MODIFY_ROCE_CC
2712 u8 cmd_size;
2713 __le16 flags;
2714 __le16 cookie;
2715 u8 resp_size;
2716 u8 reserved8;
2717 __le64 resp_addr;
2718 __le32 modify_mask;
2719 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ENABLE_CC 0x1UL
2720 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_G 0x2UL
2721 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_NUMPHASEPERSTATE 0x4UL
2722 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_CR 0x8UL
2723 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INIT_TR 0x10UL
2724 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_ECN 0x20UL
2725 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TOS_DSCP 0x40UL
2726 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_VLAN_PCP 0x80UL
2727 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_ALT_TOS_DSCP 0x100UL
2728 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_RTT 0x200UL
2729 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_CC_MODE 0x400UL
2730 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TCP_CP 0x800UL
2731 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TX_QUEUE 0x1000UL
2732 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_INACTIVITY_CP 0x2000UL
2733 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_TIME_PER_PHASE 0x4000UL
2734 #define CMDQ_MODIFY_ROCE_CC_TLV_MODIFY_MASK_PKTS_PER_PHASE 0x8000UL
2735 u8 enable_cc;
2736 #define CMDQ_MODIFY_ROCE_CC_TLV_ENABLE_CC 0x1UL
2737 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_MASK 0xfeUL
2738 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD1_SFT 1
2739 u8 g;
2740 u8 num_phases_per_state;
2741 u8 pkts_per_phase;
2742 __le16 init_cr;
2743 __le16 init_tr;
2744 u8 tos_dscp_tos_ecn;
2745 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_MASK 0x3UL
2746 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_ECN_SFT 0
2747 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_MASK 0xfcUL
2748 #define CMDQ_MODIFY_ROCE_CC_TLV_TOS_DSCP_SFT 2
2749 u8 alt_vlan_pcp;
2750 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_MASK 0x7UL
2751 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_VLAN_PCP_SFT 0
2752 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_MASK 0xf8UL
2753 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD3_SFT 3
2754 __le16 alt_tos_dscp;
2755 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_MASK 0x3fUL
2756 #define CMDQ_MODIFY_ROCE_CC_TLV_ALT_TOS_DSCP_SFT 0
2757 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_MASK 0xffc0UL
2758 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD4_SFT 6
2759 __le16 rtt;
2760 #define CMDQ_MODIFY_ROCE_CC_TLV_RTT_MASK 0x3fffUL
2761 #define CMDQ_MODIFY_ROCE_CC_TLV_RTT_SFT 0
2762 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_MASK 0xc000UL
2763 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD5_SFT 14
2764 __le16 tcp_cp;
2765 #define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_MASK 0x3ffUL
2766 #define CMDQ_MODIFY_ROCE_CC_TLV_TCP_CP_SFT 0
2767 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_MASK 0xfc00UL
2768 #define CMDQ_MODIFY_ROCE_CC_TLV_RSVD6_SFT 10
2769 u8 cc_mode;
2770 #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_DCTCP_CC_MODE 0x0UL
2771 #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE 0x1UL
2772 #define CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_LAST\
2773 CMDQ_MODIFY_ROCE_CC_TLV_CC_MODE_PROBABILISTIC_CC_MODE
2774 u8 tx_queue;
2775 __le16 inactivity_th;
2776 u8 time_per_phase;
2777 u8 reserved8_1;
2778 __le16 reserved16;
2779 __le32 reserved32;
2780 __le64 reserved64;
2781 __le64 reservedtlvpad;
2782};
2783
2784/* cmdq_modify_roce_cc_gen1_tlv (size:768b/96B) */
2785struct cmdq_modify_roce_cc_gen1_tlv {
2786 __le16 cmd_discr;
2787 u8 reserved_8b;
2788 u8 tlv_flags;
2789 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE 0x1UL
2790 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_LAST 0x0UL
2791 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_MORE_NOT_LAST 0x1UL
2792 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED 0x2UL
2793 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_NO (0x0UL << 1)
2794 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES (0x1UL << 1)
2795 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_LAST\
2796 CMDQ_MODIFY_ROCE_CC_GEN1_TLV_TLV_FLAGS_REQUIRED_YES
2797 __le16 tlv_type;
2798 __le16 length;
2799 __le64 reserved64;
2800 __le64 modify_mask;
2801 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MIN_TIME_BETWEEN_CNPS 0x1UL
2802 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_INIT_CP 0x2UL
2803 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_MODE 0x4UL
2804 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_UPDATE_CYCLES 0x8UL
2805 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FR_NUM_RTTS 0x10UL
2806 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_AI_RATE_INCREASE 0x20UL
2807 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCTION_RELAX_RTTS_TH 0x40UL
2808 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ADDITIONAL_RELAX_CR_TH 0x80UL
2809 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_MIN_TH 0x100UL
2810 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_BW_AVG_WEIGHT 0x200UL
2811 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_FACTOR 0x400UL
2812 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_MAX_CP_CR_TH 0x800UL
2813 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS_EN 0x1000UL
2814 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_BIAS 0x2000UL
2815 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_ECN 0x4000UL
2816 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RTT_JITTER_EN 0x8000UL
2817 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK_BYTES_PER_USEC 0x10000UL
2818 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RESET_CC_CR_TH 0x20000UL
2819 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_WIDTH 0x40000UL
2820 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MIN 0x80000UL
2821 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_MAX 0x100000UL
2822 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ABS_MAX 0x200000UL
2823 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_LOWER_BOUND 0x400000UL
2824 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CR_PROB_FACTOR 0x800000UL
2825 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_TR_PROB_FACTOR 0x1000000UL
2826 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_FAIRNESS_CR_TH 0x2000000UL
2827 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RED_DIV 0x4000000UL
2828 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CNP_RATIO_TH 0x8000000UL
2829 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_RTTS 0x10000000UL
2830 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_EXP_AI_CR_CP_RATIO 0x20000000UL
2831 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CP_EXP_UPDATE_TH 0x40000000UL
2832 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH1 0x80000000UL
2833 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_HIGH_EXP_AI_RTTS_TH2 0x100000000ULL
2834 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_USE_RATE_TABLE 0x200000000ULL
2835 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_LINK64B_PER_RTT 0x400000000ULL
2836 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_CONG_FREE_RTTS_TH 0x800000000ULL
2837 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH1 0x1000000000ULL
2838 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_SEVERE_CONG_CR_TH2 0x2000000000ULL
2839 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_CC_ACK_BYTES 0x4000000000ULL
2840 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_EN 0x8000000000ULL
2841 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_REDUCE_INIT_CONG_FREE_RTTS_TH \
2842 0x10000000000ULL
2843 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_RANDOM_NO_RED_EN 0x20000000000ULL
2844 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_ACTUAL_CR_SHIFT_CORRECTION_EN \
2845 0x40000000000ULL
2846 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_MODIFY_MASK_QUOTA_PERIOD_ADJUST_EN 0x80000000000ULL
2847 __le16 inactivity_th_hi;
2848 __le16 min_time_between_cnps;
2849 __le16 init_cp;
2850 u8 tr_update_mode;
2851 u8 tr_update_cycles;
2852 u8 fr_num_rtts;
2853 u8 ai_rate_increase;
2854 __le16 reduction_relax_rtts_th;
2855 __le16 additional_relax_cr_th;
2856 __le16 cr_min_th;
2857 u8 bw_avg_weight;
2858 u8 actual_cr_factor;
2859 __le16 max_cp_cr_th;
2860 u8 cp_bias_en;
2861 u8 cp_bias;
2862 u8 cnp_ecn;
2863 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_NOT_ECT 0x0UL
2864 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_1 0x1UL
2865 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0 0x2UL
2866 #define CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_LAST CMDQ_MODIFY_ROCE_CC_GEN1_TLV_CNP_ECN_ECT_0
2867 u8 rtt_jitter_en;
2868 __le16 link_bytes_per_usec;
2869 __le16 reset_cc_cr_th;
2870 u8 cr_width;
2871 u8 quota_period_min;
2872 u8 quota_period_max;
2873 u8 quota_period_abs_max;
2874 __le16 tr_lower_bound;
2875 u8 cr_prob_factor;
2876 u8 tr_prob_factor;
2877 __le16 fairness_cr_th;
2878 u8 red_div;
2879 u8 cnp_ratio_th;
2880 __le16 exp_ai_rtts;
2881 u8 exp_ai_cr_cp_ratio;
2882 u8 use_rate_table;
2883 __le16 cp_exp_update_th;
2884 __le16 high_exp_ai_rtts_th1;
2885 __le16 high_exp_ai_rtts_th2;
2886 __le16 actual_cr_cong_free_rtts_th;
2887 __le16 severe_cong_cr_th1;
2888 __le16 severe_cong_cr_th2;
2889 __le32 link64B_per_rtt;
2890 u8 cc_ack_bytes;
2891 u8 reduce_init_en;
2892 __le16 reduce_init_cong_free_rtts_th;
2893 u8 random_no_red_en;
2894 u8 actual_cr_shift_correction_en;
2895 u8 quota_period_adjust_en;
2896 u8 reserved[5];
2897};
2898
2899/* creq_modify_roce_cc_resp (size:128b/16B) */
2900struct creq_modify_roce_cc_resp {
2901 u8 type;
2902 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_MASK 0x3fUL
2903 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_SFT 0
2904 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT 0x38UL
2905 #define CREQ_MODIFY_ROCE_CC_RESP_TYPE_LAST CREQ_MODIFY_ROCE_CC_RESP_TYPE_QP_EVENT
2906 u8 status;
2907 __le16 cookie;
2908 __le32 reserved32;
2909 u8 v;
2910 #define CREQ_MODIFY_ROCE_CC_RESP_V 0x1UL
2911 u8 event;
2912 #define CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC 0x8cUL
2913 #define CREQ_MODIFY_ROCE_CC_RESP_EVENT_LAST CREQ_MODIFY_ROCE_CC_RESP_EVENT_MODIFY_ROCE_CC
2914 u8 reserved48[6];
2915};
2916
2917/* cmdq_set_link_aggr_mode_cc (size:320b/40B) */
2918struct cmdq_set_link_aggr_mode_cc {
2919 u8 opcode;
2920 #define CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE 0x8fUL
2921 #define CMDQ_SET_LINK_AGGR_MODE_OPCODE_LAST \
2922 CMDQ_SET_LINK_AGGR_MODE_OPCODE_SET_LINK_AGGR_MODE
2923 u8 cmd_size;
2924 __le16 flags;
2925 __le16 cookie;
2926 u8 resp_size;
2927 u8 reserved8;
2928 __le64 resp_addr;
2929 __le32 modify_mask;
2930 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_EN 0x1UL
2931 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_ACTIVE_PORT_MAP 0x2UL
2932 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_MEMBER_PORT_MAP 0x4UL
2933 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_AGGR_MODE 0x8UL
2934 #define CMDQ_SET_LINK_AGGR_MODE_MODIFY_MASK_STAT_CTX_ID 0x10UL
2935 u8 aggr_enable;
2936 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_ENABLE 0x1UL
2937 #define CMDQ_SET_LINK_AGGR_MODE_RSVD1_MASK 0xfeUL
2938 #define CMDQ_SET_LINK_AGGR_MODE_RSVD1_SFT 1
2939 u8 active_port_map;
2940 #define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_MASK 0xfUL
2941 #define CMDQ_SET_LINK_AGGR_MODE_ACTIVE_PORT_MAP_SFT 0
2942 #define CMDQ_SET_LINK_AGGR_MODE_RSVD2_MASK 0xf0UL
2943 #define CMDQ_SET_LINK_AGGR_MODE_RSVD2_SFT 4
2944 u8 member_port_map;
2945 u8 link_aggr_mode;
2946 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_ACTIVE 0x1UL
2947 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_ACTIVE_BACKUP 0x2UL
2948 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_BALANCE_XOR 0x3UL
2949 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD 0x4UL
2950 #define CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_LAST CMDQ_SET_LINK_AGGR_MODE_AGGR_MODE_802_3_AD
2951 __le16 stat_ctx_id[4];
2952 __le64 rsvd1;
2953};
2954
2955/* creq_set_link_aggr_mode_resources_resp (size:128b/16B) */
2956struct creq_set_link_aggr_mode_resources_resp {
2957 u8 type;
2958 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_MASK 0x3fUL
2959 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_SFT 0
2960 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT 0x38UL
2961 #define CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_LAST CREQ_SET_LINK_AGGR_MODE_RESP_TYPE_QP_EVENT
2962 u8 status;
2963 __le16 cookie;
2964 __le32 reserved32;
2965 u8 v;
2966 #define CREQ_SET_LINK_AGGR_MODE_RESP_V 0x1UL
2967 u8 event;
2968 #define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE 0x8fUL
2969 #define CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_LAST\
2970 CREQ_SET_LINK_AGGR_MODE_RESP_EVENT_SET_LINK_AGGR_MODE
2971 u8 reserved48[6];
2972};
2973
2974/* creq_func_event (size:128b/16B) */
2975struct creq_func_event {
2976 u8 type;
2977 #define CREQ_FUNC_EVENT_TYPE_MASK 0x3fUL
2978 #define CREQ_FUNC_EVENT_TYPE_SFT 0
2979 #define CREQ_FUNC_EVENT_TYPE_FUNC_EVENT 0x3aUL
2980 #define CREQ_FUNC_EVENT_TYPE_LAST CREQ_FUNC_EVENT_TYPE_FUNC_EVENT
2981 u8 reserved56[7];
2982 u8 v;
2983 #define CREQ_FUNC_EVENT_V 0x1UL
2984 u8 event;
2985 #define CREQ_FUNC_EVENT_EVENT_TX_WQE_ERROR 0x1UL
2986 #define CREQ_FUNC_EVENT_EVENT_TX_DATA_ERROR 0x2UL
2987 #define CREQ_FUNC_EVENT_EVENT_RX_WQE_ERROR 0x3UL
2988 #define CREQ_FUNC_EVENT_EVENT_RX_DATA_ERROR 0x4UL
2989 #define CREQ_FUNC_EVENT_EVENT_CQ_ERROR 0x5UL
2990 #define CREQ_FUNC_EVENT_EVENT_TQM_ERROR 0x6UL
2991 #define CREQ_FUNC_EVENT_EVENT_CFCQ_ERROR 0x7UL
2992 #define CREQ_FUNC_EVENT_EVENT_CFCS_ERROR 0x8UL
2993 #define CREQ_FUNC_EVENT_EVENT_CFCC_ERROR 0x9UL
2994 #define CREQ_FUNC_EVENT_EVENT_CFCM_ERROR 0xaUL
2995 #define CREQ_FUNC_EVENT_EVENT_TIM_ERROR 0xbUL
2996 #define CREQ_FUNC_EVENT_EVENT_VF_COMM_REQUEST 0x80UL
2997 #define CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED 0x81UL
2998 #define CREQ_FUNC_EVENT_EVENT_LAST CREQ_FUNC_EVENT_EVENT_RESOURCE_EXHAUSTED
2999 u8 reserved48[6];
3000};
3001
3002/* creq_qp_event (size:128b/16B) */
3003struct creq_qp_event {
3004 u8 type;
3005 #define CREQ_QP_EVENT_TYPE_MASK 0x3fUL
3006 #define CREQ_QP_EVENT_TYPE_SFT 0
3007 #define CREQ_QP_EVENT_TYPE_QP_EVENT 0x38UL
3008 #define CREQ_QP_EVENT_TYPE_LAST CREQ_QP_EVENT_TYPE_QP_EVENT
3009 u8 status;
3010 #define CREQ_QP_EVENT_STATUS_SUCCESS 0x0UL
3011 #define CREQ_QP_EVENT_STATUS_FAIL 0x1UL
3012 #define CREQ_QP_EVENT_STATUS_RESOURCES 0x2UL
3013 #define CREQ_QP_EVENT_STATUS_INVALID_CMD 0x3UL
3014 #define CREQ_QP_EVENT_STATUS_NOT_IMPLEMENTED 0x4UL
3015 #define CREQ_QP_EVENT_STATUS_INVALID_PARAMETER 0x5UL
3016 #define CREQ_QP_EVENT_STATUS_HARDWARE_ERROR 0x6UL
3017 #define CREQ_QP_EVENT_STATUS_INTERNAL_ERROR 0x7UL
3018 #define CREQ_QP_EVENT_STATUS_LAST CREQ_QP_EVENT_STATUS_INTERNAL_ERROR
3019 __le16 cookie;
3020 __le32 reserved32;
3021 u8 v;
3022 #define CREQ_QP_EVENT_V 0x1UL
3023 u8 event;
3024 #define CREQ_QP_EVENT_EVENT_CREATE_QP 0x1UL
3025 #define CREQ_QP_EVENT_EVENT_DESTROY_QP 0x2UL
3026 #define CREQ_QP_EVENT_EVENT_MODIFY_QP 0x3UL
3027 #define CREQ_QP_EVENT_EVENT_QUERY_QP 0x4UL
3028 #define CREQ_QP_EVENT_EVENT_CREATE_SRQ 0x5UL
3029 #define CREQ_QP_EVENT_EVENT_DESTROY_SRQ 0x6UL
3030 #define CREQ_QP_EVENT_EVENT_QUERY_SRQ 0x8UL
3031 #define CREQ_QP_EVENT_EVENT_CREATE_CQ 0x9UL
3032 #define CREQ_QP_EVENT_EVENT_DESTROY_CQ 0xaUL
3033 #define CREQ_QP_EVENT_EVENT_RESIZE_CQ 0xcUL
3034 #define CREQ_QP_EVENT_EVENT_ALLOCATE_MRW 0xdUL
3035 #define CREQ_QP_EVENT_EVENT_DEALLOCATE_KEY 0xeUL
3036 #define CREQ_QP_EVENT_EVENT_REGISTER_MR 0xfUL
3037 #define CREQ_QP_EVENT_EVENT_DEREGISTER_MR 0x10UL
3038 #define CREQ_QP_EVENT_EVENT_ADD_GID 0x11UL
3039 #define CREQ_QP_EVENT_EVENT_DELETE_GID 0x12UL
3040 #define CREQ_QP_EVENT_EVENT_MODIFY_GID 0x17UL
3041 #define CREQ_QP_EVENT_EVENT_QUERY_GID 0x18UL
3042 #define CREQ_QP_EVENT_EVENT_CREATE_QP1 0x13UL
3043 #define CREQ_QP_EVENT_EVENT_DESTROY_QP1 0x14UL
3044 #define CREQ_QP_EVENT_EVENT_CREATE_AH 0x15UL
3045 #define CREQ_QP_EVENT_EVENT_DESTROY_AH 0x16UL
3046 #define CREQ_QP_EVENT_EVENT_INITIALIZE_FW 0x80UL
3047 #define CREQ_QP_EVENT_EVENT_DEINITIALIZE_FW 0x81UL
3048 #define CREQ_QP_EVENT_EVENT_STOP_FUNC 0x82UL
3049 #define CREQ_QP_EVENT_EVENT_QUERY_FUNC 0x83UL
3050 #define CREQ_QP_EVENT_EVENT_SET_FUNC_RESOURCES 0x84UL
3051 #define CREQ_QP_EVENT_EVENT_READ_CONTEXT 0x85UL
3052 #define CREQ_QP_EVENT_EVENT_MAP_TC_TO_COS 0x8aUL
3053 #define CREQ_QP_EVENT_EVENT_QUERY_VERSION 0x8bUL
3054 #define CREQ_QP_EVENT_EVENT_MODIFY_CC 0x8cUL
3055 #define CREQ_QP_EVENT_EVENT_QUERY_CC 0x8dUL
3056 #define CREQ_QP_EVENT_EVENT_QUERY_ROCE_STATS 0x8eUL
3057 #define CREQ_QP_EVENT_EVENT_SET_LINK_AGGR_MODE 0x8fUL
3058 #define CREQ_QP_EVENT_EVENT_QUERY_QP_EXTEND 0x91UL
3059 #define CREQ_QP_EVENT_EVENT_QP_ERROR_NOTIFICATION 0xc0UL
3060 #define CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION 0xc1UL
3061 #define CREQ_QP_EVENT_EVENT_LAST CREQ_QP_EVENT_EVENT_CQ_ERROR_NOTIFICATION
3062 u8 reserved48[6];
3063};
3064
3065/* creq_qp_error_notification (size:128b/16B) */
3066struct creq_qp_error_notification {
3067 u8 type;
3068 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_MASK 0x3fUL
3069 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_SFT 0
3070 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT 0x38UL
3071 #define CREQ_QP_ERROR_NOTIFICATION_TYPE_LAST CREQ_QP_ERROR_NOTIFICATION_TYPE_QP_EVENT
3072 u8 status;
3073 u8 req_slow_path_state;
3074 u8 req_err_state_reason;
3075 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_NO_ERROR 0X0UL
3076 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_OPCODE_ERROR 0X1UL
3077 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TIMEOUT_RETRY_LIMIT 0X2UL
3078 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RNR_TIMEOUT_RETRY_LIMIT 0X3UL
3079 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_1 0X4UL
3080 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_2 0X5UL
3081 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_3 0X6UL
3082 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_NAK_ARRIVAL_4 0X7UL
3083 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_MEMORY_ERROR 0X8UL
3084 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_MEMORY_ERROR 0X9UL
3085 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_READ_RESP_LENGTH 0XAUL
3086 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_READ_RESP 0XBUL
3087 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_BIND 0XCUL
3088 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_FAST_REG 0XDUL
3089 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ILLEGAL_INVALIDATE 0XEUL
3090 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CMP_ERROR 0XFUL
3091 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETRAN_LOCAL_ERROR 0X10UL
3092 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_WQE_FORMAT_ERROR 0X11UL
3093 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_ORRQ_FORMAT_ERROR 0X12UL
3094 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_AVID_ERROR 0X13UL
3095 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_AV_DOMAIN_ERROR 0X14UL
3096 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_CQ_LOAD_ERROR 0X15UL
3097 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_SERV_TYPE_ERROR 0X16UL
3098 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_INVALID_OP_ERROR 0X17UL
3099 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_TX_PCI_ERROR 0X18UL
3100 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RX_PCI_ERROR 0X19UL
3101 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PROD_WQE_MSMTCH_ERROR 0X1AUL
3102 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_PSN_RANGE_CHECK_ERROR 0X1BUL
3103 #define CREQ_QP_ERROR_NOTIFICATION_REQ_ERR_STATE_REASON_REQ_RETX_SETUP_ERROR 0X1CUL
3104 __le32 xid;
3105 u8 v;
3106 #define CREQ_QP_ERROR_NOTIFICATION_V 0x1UL
3107 u8 event;
3108 #define CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION 0xc0UL
3109 #define CREQ_QP_ERROR_NOTIFICATION_EVENT_LAST \
3110 CREQ_QP_ERROR_NOTIFICATION_EVENT_QP_ERROR_NOTIFICATION
3111 u8 res_slow_path_state;
3112 u8 res_err_state_reason;
3113 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_NO_ERROR 0x0UL
3114 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEED_MAX 0x1UL
3115 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PAYLOAD_LENGTH_MISMATCH 0x2UL
3116 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_EXCEEDS_WQE 0x3UL
3117 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_OPCODE_ERROR 0x4UL
3118 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_SEQ_ERROR_RETRY_LIMIT 0x5UL
3119 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_INVALID_R_KEY 0x6UL
3120 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_DOMAIN_ERROR 0x7UL
3121 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_NO_PERMISSION 0x8UL
3122 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_RANGE_ERROR 0x9UL
3123 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_INVALID_R_KEY 0xaUL
3124 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_DOMAIN_ERROR 0xbUL
3125 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_NO_PERMISSION 0xcUL
3126 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_RANGE_ERROR 0xdUL
3127 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_OFLOW 0xeUL
3128 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNSUPPORTED_OPCODE 0xfUL
3129 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_UNALIGN_ATOMIC 0x10UL
3130 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_REM_INVALIDATE 0x11UL
3131 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_MEMORY_ERROR 0x12UL
3132 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_ERROR 0x13UL
3133 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CMP_ERROR 0x14UL
3134 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_INVALID_DUP_RKEY 0x15UL
3135 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_WQE_FORMAT_ERROR 0x16UL
3136 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_IRRQ_FORMAT_ERROR 0x17UL
3137 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_CQ_LOAD_ERROR 0x18UL
3138 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_SRQ_LOAD_ERROR 0x19UL
3139 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_TX_PCI_ERROR 0x1bUL
3140 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_RX_PCI_ERROR 0x1cUL
3141 #define CREQ_QP_ERROR_NOTIFICATION_RES_ERR_STATE_REASON_RES_PSN_NOT_FOUND 0x1dUL
3142 __le16 sq_cons_idx;
3143 __le16 rq_cons_idx;
3144};
3145
3146/* creq_cq_error_notification (size:128b/16B) */
3147struct creq_cq_error_notification {
3148 u8 type;
3149 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_MASK 0x3fUL
3150 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_SFT 0
3151 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT 0x38UL
3152 #define CREQ_CQ_ERROR_NOTIFICATION_TYPE_LAST CREQ_CQ_ERROR_NOTIFICATION_TYPE_CQ_EVENT
3153 u8 status;
3154 u8 cq_err_reason;
3155 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_INVALID_ERROR 0x1UL
3156 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_OVERFLOW_ERROR 0x2UL
3157 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_REQ_CQ_LOAD_ERROR 0x3UL
3158 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_INVALID_ERROR 0x4UL
3159 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_OVERFLOW_ERROR 0x5UL
3160 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR 0x6UL
3161 #define CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_LAST \
3162 CREQ_CQ_ERROR_NOTIFICATION_CQ_ERR_REASON_RES_CQ_LOAD_ERROR
3163 u8 reserved8;
3164 __le32 xid;
3165 u8 v;
3166 #define CREQ_CQ_ERROR_NOTIFICATION_V 0x1UL
3167 u8 event;
3168 #define CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION 0xc1UL
3169 #define CREQ_CQ_ERROR_NOTIFICATION_EVENT_LAST \
3170 CREQ_CQ_ERROR_NOTIFICATION_EVENT_CQ_ERROR_NOTIFICATION
3171 u8 reserved48[6];
3172};
3173
3174/* sq_base (size:64b/8B) */
3175struct sq_base {
3176 u8 wqe_type;
3177 #define SQ_BASE_WQE_TYPE_SEND 0x0UL
3178 #define SQ_BASE_WQE_TYPE_SEND_W_IMMEAD 0x1UL
3179 #define SQ_BASE_WQE_TYPE_SEND_W_INVALID 0x2UL
3180 #define SQ_BASE_WQE_TYPE_WRITE_WQE 0x4UL
3181 #define SQ_BASE_WQE_TYPE_WRITE_W_IMMEAD 0x5UL
3182 #define SQ_BASE_WQE_TYPE_READ_WQE 0x6UL
3183 #define SQ_BASE_WQE_TYPE_ATOMIC_CS 0x8UL
3184 #define SQ_BASE_WQE_TYPE_ATOMIC_FA 0xbUL
3185 #define SQ_BASE_WQE_TYPE_LOCAL_INVALID 0xcUL
3186 #define SQ_BASE_WQE_TYPE_FR_PMR 0xdUL
3187 #define SQ_BASE_WQE_TYPE_BIND 0xeUL
3188 #define SQ_BASE_WQE_TYPE_FR_PPMR 0xfUL
3189 #define SQ_BASE_WQE_TYPE_LAST SQ_BASE_WQE_TYPE_FR_PPMR
3190 u8 unused_0[7];
3191};
3192
3193/* sq_sge (size:128b/16B) */
3194struct sq_sge {
3195 __le64 va_or_pa;
3196 __le32 l_key;
3197 __le32 size;
3198};
3199
3200/* sq_psn_search (size:64b/8B) */
3201struct sq_psn_search {
3202 __le32 opcode_start_psn;
3203 #define SQ_PSN_SEARCH_START_PSN_MASK 0xffffffUL
3204 #define SQ_PSN_SEARCH_START_PSN_SFT 0
3205 #define SQ_PSN_SEARCH_OPCODE_MASK 0xff000000UL
3206 #define SQ_PSN_SEARCH_OPCODE_SFT 24
3207 __le32 flags_next_psn;
3208 #define SQ_PSN_SEARCH_NEXT_PSN_MASK 0xffffffUL
3209 #define SQ_PSN_SEARCH_NEXT_PSN_SFT 0
3210 #define SQ_PSN_SEARCH_FLAGS_MASK 0xff000000UL
3211 #define SQ_PSN_SEARCH_FLAGS_SFT 24
3212};
3213
3214/* sq_psn_search_ext (size:128b/16B) */
3215struct sq_psn_search_ext {
3216 __le32 opcode_start_psn;
3217 #define SQ_PSN_SEARCH_EXT_START_PSN_MASK 0xffffffUL
3218 #define SQ_PSN_SEARCH_EXT_START_PSN_SFT 0
3219 #define SQ_PSN_SEARCH_EXT_OPCODE_MASK 0xff000000UL
3220 #define SQ_PSN_SEARCH_EXT_OPCODE_SFT 24
3221 __le32 flags_next_psn;
3222 #define SQ_PSN_SEARCH_EXT_NEXT_PSN_MASK 0xffffffUL
3223 #define SQ_PSN_SEARCH_EXT_NEXT_PSN_SFT 0
3224 #define SQ_PSN_SEARCH_EXT_FLAGS_MASK 0xff000000UL
3225 #define SQ_PSN_SEARCH_EXT_FLAGS_SFT 24
3226 __le16 start_slot_idx;
3227 __le16 reserved16;
3228 __le32 reserved32;
3229};
3230
3231/* sq_msn_search (size:64b/8B) */
3232struct sq_msn_search {
3233 __le64 start_idx_next_psn_start_psn;
3234 #define SQ_MSN_SEARCH_START_PSN_MASK 0xffffffUL
3235 #define SQ_MSN_SEARCH_START_PSN_SFT 0
3236 #define SQ_MSN_SEARCH_NEXT_PSN_MASK 0xffffff000000ULL
3237 #define SQ_MSN_SEARCH_NEXT_PSN_SFT 24
3238 #define SQ_MSN_SEARCH_START_IDX_MASK 0xffff000000000000ULL
3239 #define SQ_MSN_SEARCH_START_IDX_SFT 48
3240};
3241
3242/* sq_send (size:1024b/128B) */
3243struct sq_send {
3244 u8 wqe_type;
3245 #define SQ_SEND_WQE_TYPE_SEND 0x0UL
3246 #define SQ_SEND_WQE_TYPE_SEND_W_IMMEAD 0x1UL
3247 #define SQ_SEND_WQE_TYPE_SEND_W_INVALID 0x2UL
3248 #define SQ_SEND_WQE_TYPE_LAST SQ_SEND_WQE_TYPE_SEND_W_INVALID
3249 u8 flags;
3250 #define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3251 #define SQ_SEND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3252 #define SQ_SEND_FLAGS_SIGNAL_COMP 0x1UL
3253 #define SQ_SEND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3254 #define SQ_SEND_FLAGS_UC_FENCE 0x4UL
3255 #define SQ_SEND_FLAGS_SE 0x8UL
3256 #define SQ_SEND_FLAGS_INLINE 0x10UL
3257 #define SQ_SEND_FLAGS_WQE_TS_EN 0x20UL
3258 #define SQ_SEND_FLAGS_DEBUG_TRACE 0x40UL
3259 u8 wqe_size;
3260 u8 reserved8_1;
3261 __le32 inv_key_or_imm_data;
3262 __le32 length;
3263 __le32 q_key;
3264 __le32 dst_qp;
3265 #define SQ_SEND_DST_QP_MASK 0xffffffUL
3266 #define SQ_SEND_DST_QP_SFT 0
3267 __le32 avid;
3268 #define SQ_SEND_AVID_MASK 0xfffffUL
3269 #define SQ_SEND_AVID_SFT 0
3270 __le32 reserved32;
3271 __le32 timestamp;
3272 #define SQ_SEND_TIMESTAMP_MASK 0xffffffUL
3273 #define SQ_SEND_TIMESTAMP_SFT 0
3274 __le32 data[24];
3275};
3276
3277/* sq_send_hdr (size:256b/32B) */
3278struct sq_send_hdr {
3279 u8 wqe_type;
3280 #define SQ_SEND_HDR_WQE_TYPE_SEND 0x0UL
3281 #define SQ_SEND_HDR_WQE_TYPE_SEND_W_IMMEAD 0x1UL
3282 #define SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID 0x2UL
3283 #define SQ_SEND_HDR_WQE_TYPE_LAST SQ_SEND_HDR_WQE_TYPE_SEND_W_INVALID
3284 u8 flags;
3285 #define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3286 #define SQ_SEND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3287 #define SQ_SEND_HDR_FLAGS_SIGNAL_COMP 0x1UL
3288 #define SQ_SEND_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3289 #define SQ_SEND_HDR_FLAGS_UC_FENCE 0x4UL
3290 #define SQ_SEND_HDR_FLAGS_SE 0x8UL
3291 #define SQ_SEND_HDR_FLAGS_INLINE 0x10UL
3292 #define SQ_SEND_HDR_FLAGS_WQE_TS_EN 0x20UL
3293 #define SQ_SEND_HDR_FLAGS_DEBUG_TRACE 0x40UL
3294 u8 wqe_size;
3295 u8 reserved8_1;
3296 __le32 inv_key_or_imm_data;
3297 __le32 length;
3298 __le32 q_key;
3299 __le32 dst_qp;
3300 #define SQ_SEND_HDR_DST_QP_MASK 0xffffffUL
3301 #define SQ_SEND_HDR_DST_QP_SFT 0
3302 __le32 avid;
3303 #define SQ_SEND_HDR_AVID_MASK 0xfffffUL
3304 #define SQ_SEND_HDR_AVID_SFT 0
3305 __le32 reserved32;
3306 __le32 timestamp;
3307 #define SQ_SEND_HDR_TIMESTAMP_MASK 0xffffffUL
3308 #define SQ_SEND_HDR_TIMESTAMP_SFT 0
3309};
3310
3311/* sq_send_raweth_qp1 (size:1024b/128B) */
3312struct sq_send_raweth_qp1 {
3313 u8 wqe_type;
3314 #define SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND 0x0UL
3315 #define SQ_SEND_RAWETH_QP1_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_WQE_TYPE_SEND
3316 u8 flags;
3317 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK \
3318 0xffUL
3319 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT \
3320 0
3321 #define SQ_SEND_RAWETH_QP1_FLAGS_SIGNAL_COMP 0x1UL
3322 #define SQ_SEND_RAWETH_QP1_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3323 #define SQ_SEND_RAWETH_QP1_FLAGS_UC_FENCE 0x4UL
3324 #define SQ_SEND_RAWETH_QP1_FLAGS_SE 0x8UL
3325 #define SQ_SEND_RAWETH_QP1_FLAGS_INLINE 0x10UL
3326 #define SQ_SEND_RAWETH_QP1_FLAGS_WQE_TS_EN 0x20UL
3327 #define SQ_SEND_RAWETH_QP1_FLAGS_DEBUG_TRACE 0x40UL
3328 u8 wqe_size;
3329 u8 reserved8;
3330 __le16 lflags;
3331 #define SQ_SEND_RAWETH_QP1_LFLAGS_TCP_UDP_CHKSUM 0x1UL
3332 #define SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM 0x2UL
3333 #define SQ_SEND_RAWETH_QP1_LFLAGS_NOCRC 0x4UL
3334 #define SQ_SEND_RAWETH_QP1_LFLAGS_STAMP 0x8UL
3335 #define SQ_SEND_RAWETH_QP1_LFLAGS_T_IP_CHKSUM 0x10UL
3336 #define SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC 0x100UL
3337 #define SQ_SEND_RAWETH_QP1_LFLAGS_FCOE_CRC 0x200UL
3338 __le16 cfa_action;
3339 __le32 length;
3340 __le32 reserved32_1;
3341 __le32 cfa_meta;
3342 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_MASK 0xfffUL
3343 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_VID_SFT 0
3344 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_DE 0x1000UL
3345 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_MASK 0xe000UL
3346 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_PRI_SFT 13
3347 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_MASK 0x70000UL
3348 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_SFT 16
3349 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16)
3350 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16)
3351 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16)
3352 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16)
3353 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16)
3354 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16)
3355 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_LAST\
3356 SQ_SEND_RAWETH_QP1_CFA_META_VLAN_TPID_TPIDCFG
3357 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_MASK 0xff80000UL
3358 #define SQ_SEND_RAWETH_QP1_CFA_META_VLAN_RESERVED_SFT 19
3359 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_MASK 0xf0000000UL
3360 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_SFT 28
3361 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_NONE (0x0UL << 28)
3362 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG (0x1UL << 28)
3363 #define SQ_SEND_RAWETH_QP1_CFA_META_KEY_LAST SQ_SEND_RAWETH_QP1_CFA_META_KEY_VLAN_TAG
3364 __le32 reserved32_2;
3365 __le32 reserved32_3;
3366 __le32 timestamp;
3367 #define SQ_SEND_RAWETH_QP1_TIMESTAMP_MASK 0xffffffUL
3368 #define SQ_SEND_RAWETH_QP1_TIMESTAMP_SFT 0
3369 __le32 data[24];
3370};
3371
3372/* sq_send_raweth_qp1_hdr (size:256b/32B) */
3373struct sq_send_raweth_qp1_hdr {
3374 u8 wqe_type;
3375 #define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND 0x0UL
3376 #define SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_LAST SQ_SEND_RAWETH_QP1_HDR_WQE_TYPE_SEND
3377 u8 flags;
3378 #define \
3379 SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3380 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\
3381 0
3382 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SIGNAL_COMP 0x1UL
3383 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3384 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_UC_FENCE 0x4UL
3385 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_SE 0x8UL
3386 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_INLINE 0x10UL
3387 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_WQE_TS_EN 0x20UL
3388 #define SQ_SEND_RAWETH_QP1_HDR_FLAGS_DEBUG_TRACE 0x40UL
3389 u8 wqe_size;
3390 u8 reserved8;
3391 __le16 lflags;
3392 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_TCP_UDP_CHKSUM 0x1UL
3393 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_IP_CHKSUM 0x2UL
3394 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_NOCRC 0x4UL
3395 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_STAMP 0x8UL
3396 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_T_IP_CHKSUM 0x10UL
3397 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_ROCE_CRC 0x100UL
3398 #define SQ_SEND_RAWETH_QP1_HDR_LFLAGS_FCOE_CRC 0x200UL
3399 __le16 cfa_action;
3400 __le32 length;
3401 __le32 reserved32_1;
3402 __le32 cfa_meta;
3403 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_MASK 0xfffUL
3404 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_VID_SFT 0
3405 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_DE 0x1000UL
3406 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_MASK 0xe000UL
3407 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_PRI_SFT 13
3408 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_MASK 0x70000UL
3409 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_SFT 16
3410 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID88A8 (0x0UL << 16)
3411 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID8100 (0x1UL << 16)
3412 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9100 (0x2UL << 16)
3413 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9200 (0x3UL << 16)
3414 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPID9300 (0x4UL << 16)
3415 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG (0x5UL << 16)
3416 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_LAST\
3417 SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_TPID_TPIDCFG
3418 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_MASK 0xff80000UL
3419 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_VLAN_RESERVED_SFT 19
3420 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_MASK 0xf0000000UL
3421 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_SFT 28
3422 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_NONE (0x0UL << 28)
3423 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG (0x1UL << 28)
3424 #define SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_LAST\
3425 SQ_SEND_RAWETH_QP1_HDR_CFA_META_KEY_VLAN_TAG
3426 __le32 reserved32_2;
3427 __le32 reserved32_3;
3428 __le32 timestamp;
3429 #define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_MASK 0xffffffUL
3430 #define SQ_SEND_RAWETH_QP1_HDR_TIMESTAMP_SFT 0
3431};
3432
3433/* sq_rdma (size:1024b/128B) */
3434struct sq_rdma {
3435 u8 wqe_type;
3436 #define SQ_RDMA_WQE_TYPE_WRITE_WQE 0x4UL
3437 #define SQ_RDMA_WQE_TYPE_WRITE_W_IMMEAD 0x5UL
3438 #define SQ_RDMA_WQE_TYPE_READ_WQE 0x6UL
3439 #define SQ_RDMA_WQE_TYPE_LAST SQ_RDMA_WQE_TYPE_READ_WQE
3440 u8 flags;
3441 #define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3442 #define SQ_RDMA_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3443 #define SQ_RDMA_FLAGS_SIGNAL_COMP 0x1UL
3444 #define SQ_RDMA_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3445 #define SQ_RDMA_FLAGS_UC_FENCE 0x4UL
3446 #define SQ_RDMA_FLAGS_SE 0x8UL
3447 #define SQ_RDMA_FLAGS_INLINE 0x10UL
3448 #define SQ_RDMA_FLAGS_WQE_TS_EN 0x20UL
3449 #define SQ_RDMA_FLAGS_DEBUG_TRACE 0x40UL
3450 u8 wqe_size;
3451 u8 reserved8;
3452 __le32 imm_data;
3453 __le32 length;
3454 __le32 reserved32_1;
3455 __le64 remote_va;
3456 __le32 remote_key;
3457 __le32 timestamp;
3458 #define SQ_RDMA_TIMESTAMP_MASK 0xffffffUL
3459 #define SQ_RDMA_TIMESTAMP_SFT 0
3460 __le32 data[24];
3461};
3462
3463/* sq_rdma_hdr (size:256b/32B) */
3464struct sq_rdma_hdr {
3465 u8 wqe_type;
3466 #define SQ_RDMA_HDR_WQE_TYPE_WRITE_WQE 0x4UL
3467 #define SQ_RDMA_HDR_WQE_TYPE_WRITE_W_IMMEAD 0x5UL
3468 #define SQ_RDMA_HDR_WQE_TYPE_READ_WQE 0x6UL
3469 #define SQ_RDMA_HDR_WQE_TYPE_LAST SQ_RDMA_HDR_WQE_TYPE_READ_WQE
3470 u8 flags;
3471 #define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3472 #define SQ_RDMA_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3473 #define SQ_RDMA_HDR_FLAGS_SIGNAL_COMP 0x1UL
3474 #define SQ_RDMA_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3475 #define SQ_RDMA_HDR_FLAGS_UC_FENCE 0x4UL
3476 #define SQ_RDMA_HDR_FLAGS_SE 0x8UL
3477 #define SQ_RDMA_HDR_FLAGS_INLINE 0x10UL
3478 #define SQ_RDMA_HDR_FLAGS_WQE_TS_EN 0x20UL
3479 #define SQ_RDMA_HDR_FLAGS_DEBUG_TRACE 0x40UL
3480 u8 wqe_size;
3481 u8 reserved8;
3482 __le32 imm_data;
3483 __le32 length;
3484 __le32 reserved32_1;
3485 __le64 remote_va;
3486 __le32 remote_key;
3487 __le32 timestamp;
3488 #define SQ_RDMA_HDR_TIMESTAMP_MASK 0xffffffUL
3489 #define SQ_RDMA_HDR_TIMESTAMP_SFT 0
3490};
3491
3492/* sq_atomic (size:1024b/128B) */
3493struct sq_atomic {
3494 u8 wqe_type;
3495 #define SQ_ATOMIC_WQE_TYPE_ATOMIC_CS 0x8UL
3496 #define SQ_ATOMIC_WQE_TYPE_ATOMIC_FA 0xbUL
3497 #define SQ_ATOMIC_WQE_TYPE_LAST SQ_ATOMIC_WQE_TYPE_ATOMIC_FA
3498 u8 flags;
3499 #define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3500 #define SQ_ATOMIC_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3501 #define SQ_ATOMIC_FLAGS_SIGNAL_COMP 0x1UL
3502 #define SQ_ATOMIC_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3503 #define SQ_ATOMIC_FLAGS_UC_FENCE 0x4UL
3504 #define SQ_ATOMIC_FLAGS_SE 0x8UL
3505 #define SQ_ATOMIC_FLAGS_INLINE 0x10UL
3506 #define SQ_ATOMIC_FLAGS_WQE_TS_EN 0x20UL
3507 #define SQ_ATOMIC_FLAGS_DEBUG_TRACE 0x40UL
3508 __le16 reserved16;
3509 __le32 remote_key;
3510 __le64 remote_va;
3511 __le64 swap_data;
3512 __le64 cmp_data;
3513 __le32 data[24];
3514};
3515
3516/* sq_atomic_hdr (size:256b/32B) */
3517struct sq_atomic_hdr {
3518 u8 wqe_type;
3519 #define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_CS 0x8UL
3520 #define SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA 0xbUL
3521 #define SQ_ATOMIC_HDR_WQE_TYPE_LAST SQ_ATOMIC_HDR_WQE_TYPE_ATOMIC_FA
3522 u8 flags;
3523 #define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3524 #define SQ_ATOMIC_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3525 #define SQ_ATOMIC_HDR_FLAGS_SIGNAL_COMP 0x1UL
3526 #define SQ_ATOMIC_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3527 #define SQ_ATOMIC_HDR_FLAGS_UC_FENCE 0x4UL
3528 #define SQ_ATOMIC_HDR_FLAGS_SE 0x8UL
3529 #define SQ_ATOMIC_HDR_FLAGS_INLINE 0x10UL
3530 #define SQ_ATOMIC_HDR_FLAGS_WQE_TS_EN 0x20UL
3531 #define SQ_ATOMIC_HDR_FLAGS_DEBUG_TRACE 0x40UL
3532 __le16 reserved16;
3533 __le32 remote_key;
3534 __le64 remote_va;
3535 __le64 swap_data;
3536 __le64 cmp_data;
3537};
3538
3539/* sq_localinvalidate (size:1024b/128B) */
3540struct sq_localinvalidate {
3541 u8 wqe_type;
3542 #define SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID 0xcUL
3543 #define SQ_LOCALINVALIDATE_WQE_TYPE_LAST SQ_LOCALINVALIDATE_WQE_TYPE_LOCAL_INVALID
3544 u8 flags;
3545 #define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK\
3546 0xffUL
3547 #define SQ_LOCALINVALIDATE_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\
3548 0
3549 #define SQ_LOCALINVALIDATE_FLAGS_SIGNAL_COMP 0x1UL
3550 #define SQ_LOCALINVALIDATE_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3551 #define SQ_LOCALINVALIDATE_FLAGS_UC_FENCE 0x4UL
3552 #define SQ_LOCALINVALIDATE_FLAGS_SE 0x8UL
3553 #define SQ_LOCALINVALIDATE_FLAGS_INLINE 0x10UL
3554 #define SQ_LOCALINVALIDATE_FLAGS_WQE_TS_EN 0x20UL
3555 #define SQ_LOCALINVALIDATE_FLAGS_DEBUG_TRACE 0x40UL
3556 __le16 reserved16;
3557 __le32 inv_l_key;
3558 __le64 reserved64;
3559 u8 reserved128[16];
3560 __le32 data[24];
3561};
3562
3563/* sq_localinvalidate_hdr (size:256b/32B) */
3564struct sq_localinvalidate_hdr {
3565 u8 wqe_type;
3566 #define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID 0xcUL
3567 #define SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LAST SQ_LOCALINVALIDATE_HDR_WQE_TYPE_LOCAL_INVALID
3568 u8 flags;
3569 #define \
3570 SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3571 #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT\
3572 0
3573 #define SQ_LOCALINVALIDATE_HDR_FLAGS_SIGNAL_COMP 0x1UL
3574 #define SQ_LOCALINVALIDATE_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3575 #define SQ_LOCALINVALIDATE_HDR_FLAGS_UC_FENCE 0x4UL
3576 #define SQ_LOCALINVALIDATE_HDR_FLAGS_SE 0x8UL
3577 #define SQ_LOCALINVALIDATE_HDR_FLAGS_INLINE 0x10UL
3578 #define SQ_LOCALINVALIDATE_HDR_FLAGS_WQE_TS_EN 0x20UL
3579 #define SQ_LOCALINVALIDATE_HDR_FLAGS_DEBUG_TRACE 0x40UL
3580 __le16 reserved16;
3581 __le32 inv_l_key;
3582 __le64 reserved64;
3583 u8 reserved128[16];
3584};
3585
3586/* sq_fr_pmr (size:1024b/128B) */
3587struct sq_fr_pmr {
3588 u8 wqe_type;
3589 #define SQ_FR_PMR_WQE_TYPE_FR_PMR 0xdUL
3590 #define SQ_FR_PMR_WQE_TYPE_LAST SQ_FR_PMR_WQE_TYPE_FR_PMR
3591 u8 flags;
3592 #define SQ_FR_PMR_FLAGS_SIGNAL_COMP 0x1UL
3593 #define SQ_FR_PMR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3594 #define SQ_FR_PMR_FLAGS_UC_FENCE 0x4UL
3595 #define SQ_FR_PMR_FLAGS_SE 0x8UL
3596 #define SQ_FR_PMR_FLAGS_INLINE 0x10UL
3597 #define SQ_FR_PMR_FLAGS_WQE_TS_EN 0x20UL
3598 #define SQ_FR_PMR_FLAGS_DEBUG_TRACE 0x40UL
3599 u8 access_cntl;
3600 #define SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE 0x1UL
3601 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ 0x2UL
3602 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE 0x4UL
3603 #define SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL
3604 #define SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND 0x10UL
3605 u8 zero_based_page_size_log;
3606 #define SQ_FR_PMR_PAGE_SIZE_LOG_MASK 0x1fUL
3607 #define SQ_FR_PMR_PAGE_SIZE_LOG_SFT 0
3608 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4K 0x0UL
3609 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8K 0x1UL
3610 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16K 0x2UL
3611 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32K 0x3UL
3612 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64K 0x4UL
3613 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128K 0x5UL
3614 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256K 0x6UL
3615 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512K 0x7UL
3616 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1M 0x8UL
3617 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2M 0x9UL
3618 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4M 0xaUL
3619 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8M 0xbUL
3620 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16M 0xcUL
3621 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32M 0xdUL
3622 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64M 0xeUL
3623 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128M 0xfUL
3624 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256M 0x10UL
3625 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512M 0x11UL
3626 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1G 0x12UL
3627 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2G 0x13UL
3628 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4G 0x14UL
3629 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8G 0x15UL
3630 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_16G 0x16UL
3631 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_32G 0x17UL
3632 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_64G 0x18UL
3633 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_128G 0x19UL
3634 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL
3635 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL
3636 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL
3637 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL
3638 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL
3639 #define SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL
3640 #define SQ_FR_PMR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PAGE_SIZE_LOG_PGSZ_8T
3641 #define SQ_FR_PMR_ZERO_BASED 0x20UL
3642 __le32 l_key;
3643 u8 length[5];
3644 u8 reserved8_1;
3645 u8 reserved8_2;
3646 u8 numlevels_pbl_page_size_log;
3647 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_MASK 0x1fUL
3648 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_SFT 0
3649 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4K 0x0UL
3650 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8K 0x1UL
3651 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16K 0x2UL
3652 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32K 0x3UL
3653 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64K 0x4UL
3654 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128K 0x5UL
3655 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256K 0x6UL
3656 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512K 0x7UL
3657 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1M 0x8UL
3658 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2M 0x9UL
3659 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4M 0xaUL
3660 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8M 0xbUL
3661 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16M 0xcUL
3662 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32M 0xdUL
3663 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64M 0xeUL
3664 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128M 0xfUL
3665 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256M 0x10UL
3666 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512M 0x11UL
3667 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1G 0x12UL
3668 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2G 0x13UL
3669 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4G 0x14UL
3670 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8G 0x15UL
3671 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_16G 0x16UL
3672 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_32G 0x17UL
3673 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_64G 0x18UL
3674 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_128G 0x19UL
3675 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL
3676 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL
3677 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL
3678 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL
3679 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL
3680 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL
3681 #define SQ_FR_PMR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_PBL_PAGE_SIZE_LOG_PGSZ_8T
3682 #define SQ_FR_PMR_NUMLEVELS_MASK 0xc0UL
3683 #define SQ_FR_PMR_NUMLEVELS_SFT 6
3684 #define SQ_FR_PMR_NUMLEVELS_PHYSICAL (0x0UL << 6)
3685 #define SQ_FR_PMR_NUMLEVELS_LAYER1 (0x1UL << 6)
3686 #define SQ_FR_PMR_NUMLEVELS_LAYER2 (0x2UL << 6)
3687 #define SQ_FR_PMR_NUMLEVELS_LAST SQ_FR_PMR_NUMLEVELS_LAYER2
3688 __le64 pblptr;
3689 __le64 va;
3690 __le32 data[24];
3691};
3692
3693/* sq_fr_pmr_hdr (size:256b/32B) */
3694struct sq_fr_pmr_hdr {
3695 u8 wqe_type;
3696 #define SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR 0xdUL
3697 #define SQ_FR_PMR_HDR_WQE_TYPE_LAST SQ_FR_PMR_HDR_WQE_TYPE_FR_PMR
3698 u8 flags;
3699 #define SQ_FR_PMR_HDR_FLAGS_SIGNAL_COMP 0x1UL
3700 #define SQ_FR_PMR_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3701 #define SQ_FR_PMR_HDR_FLAGS_UC_FENCE 0x4UL
3702 #define SQ_FR_PMR_HDR_FLAGS_SE 0x8UL
3703 #define SQ_FR_PMR_HDR_FLAGS_INLINE 0x10UL
3704 #define SQ_FR_PMR_HDR_FLAGS_WQE_TS_EN 0x20UL
3705 #define SQ_FR_PMR_HDR_FLAGS_DEBUG_TRACE 0x40UL
3706 u8 access_cntl;
3707 #define SQ_FR_PMR_HDR_ACCESS_CNTL_LOCAL_WRITE 0x1UL
3708 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_READ 0x2UL
3709 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_WRITE 0x4UL
3710 #define SQ_FR_PMR_HDR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL
3711 #define SQ_FR_PMR_HDR_ACCESS_CNTL_WINDOW_BIND 0x10UL
3712 u8 zero_based_page_size_log;
3713 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_MASK 0x1fUL
3714 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_SFT 0
3715 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4K 0x0UL
3716 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8K 0x1UL
3717 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16K 0x2UL
3718 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32K 0x3UL
3719 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64K 0x4UL
3720 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128K 0x5UL
3721 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256K 0x6UL
3722 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512K 0x7UL
3723 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1M 0x8UL
3724 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2M 0x9UL
3725 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4M 0xaUL
3726 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8M 0xbUL
3727 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16M 0xcUL
3728 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32M 0xdUL
3729 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64M 0xeUL
3730 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128M 0xfUL
3731 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256M 0x10UL
3732 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512M 0x11UL
3733 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1G 0x12UL
3734 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2G 0x13UL
3735 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4G 0x14UL
3736 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8G 0x15UL
3737 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_16G 0x16UL
3738 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_32G 0x17UL
3739 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_64G 0x18UL
3740 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_128G 0x19UL
3741 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL
3742 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL
3743 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL
3744 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL
3745 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL
3746 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL
3747 #define SQ_FR_PMR_HDR_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PAGE_SIZE_LOG_PGSZ_8T
3748 #define SQ_FR_PMR_HDR_ZERO_BASED 0x20UL
3749 __le32 l_key;
3750 u8 length[5];
3751 u8 reserved8_1;
3752 u8 reserved8_2;
3753 u8 numlevels_pbl_page_size_log;
3754 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_MASK 0x1fUL
3755 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_SFT 0
3756 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4K 0x0UL
3757 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8K 0x1UL
3758 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16K 0x2UL
3759 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32K 0x3UL
3760 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64K 0x4UL
3761 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128K 0x5UL
3762 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256K 0x6UL
3763 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512K 0x7UL
3764 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1M 0x8UL
3765 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2M 0x9UL
3766 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4M 0xaUL
3767 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8M 0xbUL
3768 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16M 0xcUL
3769 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32M 0xdUL
3770 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64M 0xeUL
3771 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128M 0xfUL
3772 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256M 0x10UL
3773 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512M 0x11UL
3774 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1G 0x12UL
3775 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2G 0x13UL
3776 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4G 0x14UL
3777 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8G 0x15UL
3778 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_16G 0x16UL
3779 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_32G 0x17UL
3780 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_64G 0x18UL
3781 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_128G 0x19UL
3782 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_256G 0x1aUL
3783 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_512G 0x1bUL
3784 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_1T 0x1cUL
3785 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_2T 0x1dUL
3786 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_4T 0x1eUL
3787 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T 0x1fUL
3788 #define SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_LAST SQ_FR_PMR_HDR_PBL_PAGE_SIZE_LOG_PGSZ_8T
3789 #define SQ_FR_PMR_HDR_NUMLEVELS_MASK 0xc0UL
3790 #define SQ_FR_PMR_HDR_NUMLEVELS_SFT 6
3791 #define SQ_FR_PMR_HDR_NUMLEVELS_PHYSICAL (0x0UL << 6)
3792 #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER1 (0x1UL << 6)
3793 #define SQ_FR_PMR_HDR_NUMLEVELS_LAYER2 (0x2UL << 6)
3794 #define SQ_FR_PMR_HDR_NUMLEVELS_LAST SQ_FR_PMR_HDR_NUMLEVELS_LAYER2
3795 __le64 pblptr;
3796 __le64 va;
3797};
3798
3799/* sq_bind (size:1024b/128B) */
3800struct sq_bind {
3801 u8 wqe_type;
3802 #define SQ_BIND_WQE_TYPE_BIND 0xeUL
3803 #define SQ_BIND_WQE_TYPE_LAST SQ_BIND_WQE_TYPE_BIND
3804 u8 flags;
3805 #define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3806 #define SQ_BIND_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3807 #define SQ_BIND_FLAGS_SIGNAL_COMP 0x1UL
3808 #define SQ_BIND_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3809 #define SQ_BIND_FLAGS_UC_FENCE 0x4UL
3810 #define SQ_BIND_FLAGS_SE 0x8UL
3811 #define SQ_BIND_FLAGS_INLINE 0x10UL
3812 #define SQ_BIND_FLAGS_WQE_TS_EN 0x20UL
3813 #define SQ_BIND_FLAGS_DEBUG_TRACE 0x40UL
3814 u8 access_cntl;
3815 #define \
3816 SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK\
3817 0xffUL
3818 #define \
3819 SQ_BIND_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT 0
3820 #define SQ_BIND_ACCESS_CNTL_LOCAL_WRITE 0x1UL
3821 #define SQ_BIND_ACCESS_CNTL_REMOTE_READ 0x2UL
3822 #define SQ_BIND_ACCESS_CNTL_REMOTE_WRITE 0x4UL
3823 #define SQ_BIND_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL
3824 #define SQ_BIND_ACCESS_CNTL_WINDOW_BIND 0x10UL
3825 u8 reserved8_1;
3826 u8 mw_type_zero_based;
3827 #define SQ_BIND_ZERO_BASED 0x1UL
3828 #define SQ_BIND_MW_TYPE 0x2UL
3829 #define SQ_BIND_MW_TYPE_TYPE1 (0x0UL << 1)
3830 #define SQ_BIND_MW_TYPE_TYPE2 (0x1UL << 1)
3831 #define SQ_BIND_MW_TYPE_LAST SQ_BIND_MW_TYPE_TYPE2
3832 u8 reserved8_2;
3833 __le16 reserved16;
3834 __le32 parent_l_key;
3835 __le32 l_key;
3836 __le64 va;
3837 u8 length[5];
3838 u8 reserved24[3];
3839 __le32 data[24];
3840};
3841
3842/* sq_bind_hdr (size:256b/32B) */
3843struct sq_bind_hdr {
3844 u8 wqe_type;
3845 #define SQ_BIND_HDR_WQE_TYPE_BIND 0xeUL
3846 #define SQ_BIND_HDR_WQE_TYPE_LAST SQ_BIND_HDR_WQE_TYPE_BIND
3847 u8 flags;
3848 #define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_MASK 0xffUL
3849 #define SQ_BIND_HDR_FLAGS_INLINE_SE_UC_FENCE_RD_OR_ATOMIC_FENCE_SIGNAL_COMP_SFT 0
3850 #define SQ_BIND_HDR_FLAGS_SIGNAL_COMP 0x1UL
3851 #define SQ_BIND_HDR_FLAGS_RD_OR_ATOMIC_FENCE 0x2UL
3852 #define SQ_BIND_HDR_FLAGS_UC_FENCE 0x4UL
3853 #define SQ_BIND_HDR_FLAGS_SE 0x8UL
3854 #define SQ_BIND_HDR_FLAGS_INLINE 0x10UL
3855 #define SQ_BIND_HDR_FLAGS_WQE_TS_EN 0x20UL
3856 #define SQ_BIND_HDR_FLAGS_DEBUG_TRACE 0x40UL
3857 u8 access_cntl;
3858 #define \
3859 SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_MASK\
3860 0xffUL
3861 #define \
3862 SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND_REMOTE_ATOMIC_REMOTE_WRITE_REMOTE_READ_LOCAL_WRITE_SFT \
3863 0
3864 #define SQ_BIND_HDR_ACCESS_CNTL_LOCAL_WRITE 0x1UL
3865 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_READ 0x2UL
3866 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_WRITE 0x4UL
3867 #define SQ_BIND_HDR_ACCESS_CNTL_REMOTE_ATOMIC 0x8UL
3868 #define SQ_BIND_HDR_ACCESS_CNTL_WINDOW_BIND 0x10UL
3869 u8 reserved8_1;
3870 u8 mw_type_zero_based;
3871 #define SQ_BIND_HDR_ZERO_BASED 0x1UL
3872 #define SQ_BIND_HDR_MW_TYPE 0x2UL
3873 #define SQ_BIND_HDR_MW_TYPE_TYPE1 (0x0UL << 1)
3874 #define SQ_BIND_HDR_MW_TYPE_TYPE2 (0x1UL << 1)
3875 #define SQ_BIND_HDR_MW_TYPE_LAST SQ_BIND_HDR_MW_TYPE_TYPE2
3876 u8 reserved8_2;
3877 __le16 reserved16;
3878 __le32 parent_l_key;
3879 __le32 l_key;
3880 __le64 va;
3881 u8 length[5];
3882 u8 reserved24[3];
3883};
3884
3885/* rq_wqe (size:1024b/128B) */
3886struct rq_wqe {
3887 u8 wqe_type;
3888 #define RQ_WQE_WQE_TYPE_RCV 0x80UL
3889 #define RQ_WQE_WQE_TYPE_LAST RQ_WQE_WQE_TYPE_RCV
3890 u8 flags;
3891 u8 wqe_size;
3892 u8 reserved8;
3893 __le32 reserved32;
3894 __le32 wr_id[2];
3895 #define RQ_WQE_WR_ID_MASK 0xfffffUL
3896 #define RQ_WQE_WR_ID_SFT 0
3897 u8 reserved128[16];
3898 __le32 data[24];
3899};
3900
3901/* rq_wqe_hdr (size:256b/32B) */
3902struct rq_wqe_hdr {
3903 u8 wqe_type;
3904 #define RQ_WQE_HDR_WQE_TYPE_RCV 0x80UL
3905 #define RQ_WQE_HDR_WQE_TYPE_LAST RQ_WQE_HDR_WQE_TYPE_RCV
3906 u8 flags;
3907 u8 wqe_size;
3908 u8 reserved8;
3909 __le32 reserved32;
3910 __le32 wr_id[2];
3911 #define RQ_WQE_HDR_WR_ID_MASK 0xfffffUL
3912 #define RQ_WQE_HDR_WR_ID_SFT 0
3913 u8 reserved128[16];
3914};
3915
3916/* cq_base (size:256b/32B) */
3917struct cq_base {
3918 __le64 reserved64_1;
3919 __le64 reserved64_2;
3920 __le64 reserved64_3;
3921 u8 cqe_type_toggle;
3922 #define CQ_BASE_TOGGLE 0x1UL
3923 #define CQ_BASE_CQE_TYPE_MASK 0x1eUL
3924 #define CQ_BASE_CQE_TYPE_SFT 1
3925 #define CQ_BASE_CQE_TYPE_REQ (0x0UL << 1)
3926 #define CQ_BASE_CQE_TYPE_RES_RC (0x1UL << 1)
3927 #define CQ_BASE_CQE_TYPE_RES_UD (0x2UL << 1)
3928 #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1)
3929 #define CQ_BASE_CQE_TYPE_RES_UD_CFA (0x4UL << 1)
3930 #define CQ_BASE_CQE_TYPE_REQ_V3 (0x8UL << 1)
3931 #define CQ_BASE_CQE_TYPE_RES_RC_V3 (0x9UL << 1)
3932 #define CQ_BASE_CQE_TYPE_RES_UD_V3 (0xaUL << 1)
3933 #define CQ_BASE_CQE_TYPE_RES_RAWETH_QP1_V3 (0xbUL << 1)
3934 #define CQ_BASE_CQE_TYPE_RES_UD_CFA_V3 (0xcUL << 1)
3935 #define CQ_BASE_CQE_TYPE_NO_OP (0xdUL << 1)
3936 #define CQ_BASE_CQE_TYPE_TERMINAL (0xeUL << 1)
3937 #define CQ_BASE_CQE_TYPE_CUT_OFF (0xfUL << 1)
3938 #define CQ_BASE_CQE_TYPE_LAST CQ_BASE_CQE_TYPE_CUT_OFF
3939 u8 status;
3940 #define CQ_BASE_STATUS_OK 0x0UL
3941 #define CQ_BASE_STATUS_BAD_RESPONSE_ERR 0x1UL
3942 #define CQ_BASE_STATUS_LOCAL_LENGTH_ERR 0x2UL
3943 #define CQ_BASE_STATUS_HW_LOCAL_LENGTH_ERR 0x3UL
3944 #define CQ_BASE_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
3945 #define CQ_BASE_STATUS_LOCAL_PROTECTION_ERR 0x5UL
3946 #define CQ_BASE_STATUS_LOCAL_ACCESS_ERROR 0x6UL
3947 #define CQ_BASE_STATUS_MEMORY_MGT_OPERATION_ERR 0x7UL
3948 #define CQ_BASE_STATUS_REMOTE_INVALID_REQUEST_ERR 0x8UL
3949 #define CQ_BASE_STATUS_REMOTE_ACCESS_ERR 0x9UL
3950 #define CQ_BASE_STATUS_REMOTE_OPERATION_ERR 0xaUL
3951 #define CQ_BASE_STATUS_RNR_NAK_RETRY_CNT_ERR 0xbUL
3952 #define CQ_BASE_STATUS_TRANSPORT_RETRY_CNT_ERR 0xcUL
3953 #define CQ_BASE_STATUS_WORK_REQUEST_FLUSHED_ERR 0xdUL
3954 #define CQ_BASE_STATUS_HW_FLUSH_ERR 0xeUL
3955 #define CQ_BASE_STATUS_OVERFLOW_ERR 0xfUL
3956 #define CQ_BASE_STATUS_LAST CQ_BASE_STATUS_OVERFLOW_ERR
3957 __le16 reserved16;
3958 __le32 opaque;
3959};
3960
3961/* cq_req (size:256b/32B) */
3962struct cq_req {
3963 __le64 qp_handle;
3964 __le16 sq_cons_idx;
3965 __le16 reserved16_1;
3966 __le32 reserved32_2;
3967 __le64 reserved64;
3968 u8 cqe_type_toggle;
3969 #define CQ_REQ_TOGGLE 0x1UL
3970 #define CQ_REQ_CQE_TYPE_MASK 0x1eUL
3971 #define CQ_REQ_CQE_TYPE_SFT 1
3972 #define CQ_REQ_CQE_TYPE_REQ (0x0UL << 1)
3973 #define CQ_REQ_CQE_TYPE_LAST CQ_REQ_CQE_TYPE_REQ
3974 #define CQ_REQ_PUSH 0x20UL
3975 u8 status;
3976 #define CQ_REQ_STATUS_OK 0x0UL
3977 #define CQ_REQ_STATUS_BAD_RESPONSE_ERR 0x1UL
3978 #define CQ_REQ_STATUS_LOCAL_LENGTH_ERR 0x2UL
3979 #define CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR 0x3UL
3980 #define CQ_REQ_STATUS_LOCAL_PROTECTION_ERR 0x4UL
3981 #define CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
3982 #define CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL
3983 #define CQ_REQ_STATUS_REMOTE_ACCESS_ERR 0x7UL
3984 #define CQ_REQ_STATUS_REMOTE_OPERATION_ERR 0x8UL
3985 #define CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR 0x9UL
3986 #define CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR 0xaUL
3987 #define CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR 0xbUL
3988 #define CQ_REQ_STATUS_LAST CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR
3989 __le16 reserved16_2;
3990 __le32 reserved32_1;
3991};
3992
3993/* cq_res_rc (size:256b/32B) */
3994struct cq_res_rc {
3995 __le32 length;
3996 __le32 imm_data_or_inv_r_key;
3997 __le64 qp_handle;
3998 __le64 mr_handle;
3999 u8 cqe_type_toggle;
4000 #define CQ_RES_RC_TOGGLE 0x1UL
4001 #define CQ_RES_RC_CQE_TYPE_MASK 0x1eUL
4002 #define CQ_RES_RC_CQE_TYPE_SFT 1
4003 #define CQ_RES_RC_CQE_TYPE_RES_RC (0x1UL << 1)
4004 #define CQ_RES_RC_CQE_TYPE_LAST CQ_RES_RC_CQE_TYPE_RES_RC
4005 u8 status;
4006 #define CQ_RES_RC_STATUS_OK 0x0UL
4007 #define CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR 0x1UL
4008 #define CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR 0x2UL
4009 #define CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR 0x3UL
4010 #define CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
4011 #define CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
4012 #define CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR 0x6UL
4013 #define CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
4014 #define CQ_RES_RC_STATUS_HW_FLUSH_ERR 0x8UL
4015 #define CQ_RES_RC_STATUS_LAST CQ_RES_RC_STATUS_HW_FLUSH_ERR
4016 __le16 flags;
4017 #define CQ_RES_RC_FLAGS_SRQ 0x1UL
4018 #define CQ_RES_RC_FLAGS_SRQ_RQ 0x0UL
4019 #define CQ_RES_RC_FLAGS_SRQ_SRQ 0x1UL
4020 #define CQ_RES_RC_FLAGS_SRQ_LAST CQ_RES_RC_FLAGS_SRQ_SRQ
4021 #define CQ_RES_RC_FLAGS_IMM 0x2UL
4022 #define CQ_RES_RC_FLAGS_INV 0x4UL
4023 #define CQ_RES_RC_FLAGS_RDMA 0x8UL
4024 #define CQ_RES_RC_FLAGS_RDMA_SEND (0x0UL << 3)
4025 #define CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE (0x1UL << 3)
4026 #define CQ_RES_RC_FLAGS_RDMA_LAST CQ_RES_RC_FLAGS_RDMA_RDMA_WRITE
4027 __le32 srq_or_rq_wr_id;
4028 #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
4029 #define CQ_RES_RC_SRQ_OR_RQ_WR_ID_SFT 0
4030};
4031
4032/* cq_res_ud (size:256b/32B) */
4033struct cq_res_ud {
4034 __le16 length;
4035 #define CQ_RES_UD_LENGTH_MASK 0x3fffUL
4036 #define CQ_RES_UD_LENGTH_SFT 0
4037 __le16 cfa_metadata;
4038 #define CQ_RES_UD_CFA_METADATA_VID_MASK 0xfffUL
4039 #define CQ_RES_UD_CFA_METADATA_VID_SFT 0
4040 #define CQ_RES_UD_CFA_METADATA_DE 0x1000UL
4041 #define CQ_RES_UD_CFA_METADATA_PRI_MASK 0xe000UL
4042 #define CQ_RES_UD_CFA_METADATA_PRI_SFT 13
4043 __le32 imm_data;
4044 __le64 qp_handle;
4045 __le16 src_mac[3];
4046 __le16 src_qp_low;
4047 u8 cqe_type_toggle;
4048 #define CQ_RES_UD_TOGGLE 0x1UL
4049 #define CQ_RES_UD_CQE_TYPE_MASK 0x1eUL
4050 #define CQ_RES_UD_CQE_TYPE_SFT 1
4051 #define CQ_RES_UD_CQE_TYPE_RES_UD (0x2UL << 1)
4052 #define CQ_RES_UD_CQE_TYPE_LAST CQ_RES_UD_CQE_TYPE_RES_UD
4053 u8 status;
4054 #define CQ_RES_UD_STATUS_OK 0x0UL
4055 #define CQ_RES_UD_STATUS_LOCAL_ACCESS_ERROR 0x1UL
4056 #define CQ_RES_UD_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
4057 #define CQ_RES_UD_STATUS_LOCAL_PROTECTION_ERR 0x3UL
4058 #define CQ_RES_UD_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
4059 #define CQ_RES_UD_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
4060 #define CQ_RES_UD_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
4061 #define CQ_RES_UD_STATUS_HW_FLUSH_ERR 0x8UL
4062 #define CQ_RES_UD_STATUS_LAST CQ_RES_UD_STATUS_HW_FLUSH_ERR
4063 __le16 flags;
4064 #define CQ_RES_UD_FLAGS_SRQ 0x1UL
4065 #define CQ_RES_UD_FLAGS_SRQ_RQ 0x0UL
4066 #define CQ_RES_UD_FLAGS_SRQ_SRQ 0x1UL
4067 #define CQ_RES_UD_FLAGS_SRQ_LAST CQ_RES_UD_FLAGS_SRQ_SRQ
4068 #define CQ_RES_UD_FLAGS_IMM 0x2UL
4069 #define CQ_RES_UD_FLAGS_UNUSED_MASK 0xcUL
4070 #define CQ_RES_UD_FLAGS_UNUSED_SFT 2
4071 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK 0x30UL
4072 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT 4
4073 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4)
4074 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4)
4075 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4)
4076 #define CQ_RES_UD_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_FLAGS_ROCE_IP_VER_V2IPV6
4077 #define CQ_RES_UD_FLAGS_META_FORMAT_MASK 0x3c0UL
4078 #define CQ_RES_UD_FLAGS_META_FORMAT_SFT 6
4079 #define CQ_RES_UD_FLAGS_META_FORMAT_NONE (0x0UL << 6)
4080 #define CQ_RES_UD_FLAGS_META_FORMAT_VLAN (0x1UL << 6)
4081 #define CQ_RES_UD_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6)
4082 #define CQ_RES_UD_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6)
4083 #define CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6)
4084 #define CQ_RES_UD_FLAGS_META_FORMAT_LAST CQ_RES_UD_FLAGS_META_FORMAT_HDR_OFFSET
4085 #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_MASK 0xc00UL
4086 #define CQ_RES_UD_FLAGS_EXT_META_FORMAT_SFT 10
4087 __le32 src_qp_high_srq_or_rq_wr_id;
4088 #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
4089 #define CQ_RES_UD_SRQ_OR_RQ_WR_ID_SFT 0
4090 #define CQ_RES_UD_SRC_QP_HIGH_MASK 0xff000000UL
4091 #define CQ_RES_UD_SRC_QP_HIGH_SFT 24
4092};
4093
4094/* cq_res_ud_v2 (size:256b/32B) */
4095struct cq_res_ud_v2 {
4096 __le16 length;
4097 #define CQ_RES_UD_V2_LENGTH_MASK 0x3fffUL
4098 #define CQ_RES_UD_V2_LENGTH_SFT 0
4099 __le16 cfa_metadata0;
4100 #define CQ_RES_UD_V2_CFA_METADATA0_VID_MASK 0xfffUL
4101 #define CQ_RES_UD_V2_CFA_METADATA0_VID_SFT 0
4102 #define CQ_RES_UD_V2_CFA_METADATA0_DE 0x1000UL
4103 #define CQ_RES_UD_V2_CFA_METADATA0_PRI_MASK 0xe000UL
4104 #define CQ_RES_UD_V2_CFA_METADATA0_PRI_SFT 13
4105 __le32 imm_data;
4106 __le64 qp_handle;
4107 __le16 src_mac[3];
4108 __le16 src_qp_low;
4109 u8 cqe_type_toggle;
4110 #define CQ_RES_UD_V2_TOGGLE 0x1UL
4111 #define CQ_RES_UD_V2_CQE_TYPE_MASK 0x1eUL
4112 #define CQ_RES_UD_V2_CQE_TYPE_SFT 1
4113 #define CQ_RES_UD_V2_CQE_TYPE_RES_UD (0x2UL << 1)
4114 #define CQ_RES_UD_V2_CQE_TYPE_LAST CQ_RES_UD_V2_CQE_TYPE_RES_UD
4115 u8 status;
4116 #define CQ_RES_UD_V2_STATUS_OK 0x0UL
4117 #define CQ_RES_UD_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL
4118 #define CQ_RES_UD_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
4119 #define CQ_RES_UD_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL
4120 #define CQ_RES_UD_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
4121 #define CQ_RES_UD_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
4122 #define CQ_RES_UD_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
4123 #define CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR 0x8UL
4124 #define CQ_RES_UD_V2_STATUS_LAST CQ_RES_UD_V2_STATUS_HW_FLUSH_ERR
4125 __le16 flags;
4126 #define CQ_RES_UD_V2_FLAGS_SRQ 0x1UL
4127 #define CQ_RES_UD_V2_FLAGS_SRQ_RQ 0x0UL
4128 #define CQ_RES_UD_V2_FLAGS_SRQ_SRQ 0x1UL
4129 #define CQ_RES_UD_V2_FLAGS_SRQ_LAST CQ_RES_UD_V2_FLAGS_SRQ_SRQ
4130 #define CQ_RES_UD_V2_FLAGS_IMM 0x2UL
4131 #define CQ_RES_UD_V2_FLAGS_UNUSED_MASK 0xcUL
4132 #define CQ_RES_UD_V2_FLAGS_UNUSED_SFT 2
4133 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_MASK 0x30UL
4134 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_SFT 4
4135 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4)
4136 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4)
4137 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4)
4138 #define CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_V2_FLAGS_ROCE_IP_VER_V2IPV6
4139 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_MASK 0x3c0UL
4140 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_SFT 6
4141 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_NONE (0x0UL << 6)
4142 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_ACT_REC_PTR (0x1UL << 6)
4143 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6)
4144 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6)
4145 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6)
4146 #define CQ_RES_UD_V2_FLAGS_META_FORMAT_LAST CQ_RES_UD_V2_FLAGS_META_FORMAT_HDR_OFFSET
4147 __le32 src_qp_high_srq_or_rq_wr_id;
4148 #define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
4149 #define CQ_RES_UD_V2_SRQ_OR_RQ_WR_ID_SFT 0
4150 #define CQ_RES_UD_V2_CFA_METADATA1_MASK 0xf00000UL
4151 #define CQ_RES_UD_V2_CFA_METADATA1_SFT 20
4152 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL
4153 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_SFT 20
4154 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20)
4155 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20)
4156 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20)
4157 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20)
4158 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20)
4159 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20)
4160 #define CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_LAST CQ_RES_UD_V2_CFA_METADATA1_TPID_SEL_TPIDCFG
4161 #define CQ_RES_UD_V2_CFA_METADATA1_VALID 0x800000UL
4162 #define CQ_RES_UD_V2_SRC_QP_HIGH_MASK 0xff000000UL
4163 #define CQ_RES_UD_V2_SRC_QP_HIGH_SFT 24
4164};
4165
4166/* cq_res_ud_cfa (size:256b/32B) */
4167struct cq_res_ud_cfa {
4168 __le16 length;
4169 #define CQ_RES_UD_CFA_LENGTH_MASK 0x3fffUL
4170 #define CQ_RES_UD_CFA_LENGTH_SFT 0
4171 __le16 cfa_code;
4172 __le32 imm_data;
4173 __le32 qid;
4174 #define CQ_RES_UD_CFA_QID_MASK 0xfffffUL
4175 #define CQ_RES_UD_CFA_QID_SFT 0
4176 __le32 cfa_metadata;
4177 #define CQ_RES_UD_CFA_CFA_METADATA_VID_MASK 0xfffUL
4178 #define CQ_RES_UD_CFA_CFA_METADATA_VID_SFT 0
4179 #define CQ_RES_UD_CFA_CFA_METADATA_DE 0x1000UL
4180 #define CQ_RES_UD_CFA_CFA_METADATA_PRI_MASK 0xe000UL
4181 #define CQ_RES_UD_CFA_CFA_METADATA_PRI_SFT 13
4182 #define CQ_RES_UD_CFA_CFA_METADATA_TPID_MASK 0xffff0000UL
4183 #define CQ_RES_UD_CFA_CFA_METADATA_TPID_SFT 16
4184 __le16 src_mac[3];
4185 __le16 src_qp_low;
4186 u8 cqe_type_toggle;
4187 #define CQ_RES_UD_CFA_TOGGLE 0x1UL
4188 #define CQ_RES_UD_CFA_CQE_TYPE_MASK 0x1eUL
4189 #define CQ_RES_UD_CFA_CQE_TYPE_SFT 1
4190 #define CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA (0x4UL << 1)
4191 #define CQ_RES_UD_CFA_CQE_TYPE_LAST CQ_RES_UD_CFA_CQE_TYPE_RES_UD_CFA
4192 u8 status;
4193 #define CQ_RES_UD_CFA_STATUS_OK 0x0UL
4194 #define CQ_RES_UD_CFA_STATUS_LOCAL_ACCESS_ERROR 0x1UL
4195 #define CQ_RES_UD_CFA_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
4196 #define CQ_RES_UD_CFA_STATUS_LOCAL_PROTECTION_ERR 0x3UL
4197 #define CQ_RES_UD_CFA_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
4198 #define CQ_RES_UD_CFA_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
4199 #define CQ_RES_UD_CFA_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
4200 #define CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR 0x8UL
4201 #define CQ_RES_UD_CFA_STATUS_LAST CQ_RES_UD_CFA_STATUS_HW_FLUSH_ERR
4202 __le16 flags;
4203 #define CQ_RES_UD_CFA_FLAGS_SRQ 0x1UL
4204 #define CQ_RES_UD_CFA_FLAGS_SRQ_RQ 0x0UL
4205 #define CQ_RES_UD_CFA_FLAGS_SRQ_SRQ 0x1UL
4206 #define CQ_RES_UD_CFA_FLAGS_SRQ_LAST CQ_RES_UD_CFA_FLAGS_SRQ_SRQ
4207 #define CQ_RES_UD_CFA_FLAGS_IMM 0x2UL
4208 #define CQ_RES_UD_CFA_FLAGS_UNUSED_MASK 0xcUL
4209 #define CQ_RES_UD_CFA_FLAGS_UNUSED_SFT 2
4210 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_MASK 0x30UL
4211 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_SFT 4
4212 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4)
4213 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4)
4214 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4)
4215 #define CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_FLAGS_ROCE_IP_VER_V2IPV6
4216 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_MASK 0x3c0UL
4217 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_SFT 6
4218 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_NONE (0x0UL << 6)
4219 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_VLAN (0x1UL << 6)
4220 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6)
4221 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6)
4222 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6)
4223 #define CQ_RES_UD_CFA_FLAGS_META_FORMAT_LAST CQ_RES_UD_CFA_FLAGS_META_FORMAT_HDR_OFFSET
4224 #define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_MASK 0xc00UL
4225 #define CQ_RES_UD_CFA_FLAGS_EXT_META_FORMAT_SFT 10
4226 __le32 src_qp_high_srq_or_rq_wr_id;
4227 #define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
4228 #define CQ_RES_UD_CFA_SRQ_OR_RQ_WR_ID_SFT 0
4229 #define CQ_RES_UD_CFA_SRC_QP_HIGH_MASK 0xff000000UL
4230 #define CQ_RES_UD_CFA_SRC_QP_HIGH_SFT 24
4231};
4232
4233/* cq_res_ud_cfa_v2 (size:256b/32B) */
4234struct cq_res_ud_cfa_v2 {
4235 __le16 length;
4236 #define CQ_RES_UD_CFA_V2_LENGTH_MASK 0x3fffUL
4237 #define CQ_RES_UD_CFA_V2_LENGTH_SFT 0
4238 __le16 cfa_metadata0;
4239 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_MASK 0xfffUL
4240 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_VID_SFT 0
4241 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_DE 0x1000UL
4242 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_MASK 0xe000UL
4243 #define CQ_RES_UD_CFA_V2_CFA_METADATA0_PRI_SFT 13
4244 __le32 imm_data;
4245 __le32 qid;
4246 #define CQ_RES_UD_CFA_V2_QID_MASK 0xfffffUL
4247 #define CQ_RES_UD_CFA_V2_QID_SFT 0
4248 __le32 cfa_metadata2;
4249 __le16 src_mac[3];
4250 __le16 src_qp_low;
4251 u8 cqe_type_toggle;
4252 #define CQ_RES_UD_CFA_V2_TOGGLE 0x1UL
4253 #define CQ_RES_UD_CFA_V2_CQE_TYPE_MASK 0x1eUL
4254 #define CQ_RES_UD_CFA_V2_CQE_TYPE_SFT 1
4255 #define CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA (0x4UL << 1)
4256 #define CQ_RES_UD_CFA_V2_CQE_TYPE_LAST CQ_RES_UD_CFA_V2_CQE_TYPE_RES_UD_CFA
4257 u8 status;
4258 #define CQ_RES_UD_CFA_V2_STATUS_OK 0x0UL
4259 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL
4260 #define CQ_RES_UD_CFA_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
4261 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL
4262 #define CQ_RES_UD_CFA_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
4263 #define CQ_RES_UD_CFA_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
4264 #define CQ_RES_UD_CFA_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
4265 #define CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR 0x8UL
4266 #define CQ_RES_UD_CFA_V2_STATUS_LAST CQ_RES_UD_CFA_V2_STATUS_HW_FLUSH_ERR
4267 __le16 flags;
4268 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ 0x1UL
4269 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_RQ 0x0UL
4270 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ 0x1UL
4271 #define CQ_RES_UD_CFA_V2_FLAGS_SRQ_LAST CQ_RES_UD_CFA_V2_FLAGS_SRQ_SRQ
4272 #define CQ_RES_UD_CFA_V2_FLAGS_IMM 0x2UL
4273 #define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_MASK 0xcUL
4274 #define CQ_RES_UD_CFA_V2_FLAGS_UNUSED_SFT 2
4275 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_MASK 0x30UL
4276 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_SFT 4
4277 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V1 (0x0UL << 4)
4278 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV4 (0x2UL << 4)
4279 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6 (0x3UL << 4)
4280 #define CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_LAST CQ_RES_UD_CFA_V2_FLAGS_ROCE_IP_VER_V2IPV6
4281 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_MASK 0x3c0UL
4282 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_SFT 6
4283 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_NONE (0x0UL << 6)
4284 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_ACT_REC_PTR (0x1UL << 6)
4285 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_TUNNEL_ID (0x2UL << 6)
4286 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_CHDR_DATA (0x3UL << 6)
4287 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET (0x4UL << 6)
4288 #define CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_LAST \
4289 CQ_RES_UD_CFA_V2_FLAGS_META_FORMAT_HDR_OFFSET
4290 __le32 src_qp_high_srq_or_rq_wr_id;
4291 #define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
4292 #define CQ_RES_UD_CFA_V2_SRQ_OR_RQ_WR_ID_SFT 0
4293 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_MASK 0xf00000UL
4294 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_SFT 20
4295 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL
4296 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_SFT 20
4297 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20)
4298 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20)
4299 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20)
4300 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20)
4301 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20)
4302 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20)
4303 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_LAST \
4304 CQ_RES_UD_CFA_V2_CFA_METADATA1_TPID_SEL_TPIDCFG
4305 #define CQ_RES_UD_CFA_V2_CFA_METADATA1_VALID 0x800000UL
4306 #define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_MASK 0xff000000UL
4307 #define CQ_RES_UD_CFA_V2_SRC_QP_HIGH_SFT 24
4308};
4309
4310/* cq_res_raweth_qp1 (size:256b/32B) */
4311struct cq_res_raweth_qp1 {
4312 __le16 length;
4313 #define CQ_RES_RAWETH_QP1_LENGTH_MASK 0x3fffUL
4314 #define CQ_RES_RAWETH_QP1_LENGTH_SFT 0
4315 __le16 raweth_qp1_flags;
4316 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_MASK 0x3ffUL
4317 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_SFT 0
4318 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ERROR 0x1UL
4319 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_MASK 0x3c0UL
4320 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_SFT 6
4321 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6)
4322 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_IP (0x1UL << 6)
4323 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_TCP (0x2UL << 6)
4324 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_UDP (0x3UL << 6)
4325 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_FCOE (0x4UL << 6)
4326 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE (0x5UL << 6)
4327 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ICMP (0x7UL << 6)
4328 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 6)
4329 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 6)
4330 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_LAST \
4331 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP
4332 __le16 raweth_qp1_errors;
4333 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL
4334 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL
4335 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL
4336 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL
4337 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL
4338 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL
4339 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9
4340 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9)
4341 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9)
4342 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9)
4343 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3UL << 9)
4344 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4UL << 9)
4345 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5UL << 9)
4346 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6UL << 9)
4347 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST \
4348 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
4349 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL
4350 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12
4351 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12)
4352 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12)
4353 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12)
4354 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12)
4355 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12)
4356 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12)
4357 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12)
4358 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7UL << 12)
4359 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8UL << 12)
4360 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_LAST \
4361 CQ_RES_RAWETH_QP1_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
4362 __le16 raweth_qp1_cfa_code;
4363 __le64 qp_handle;
4364 __le32 raweth_qp1_flags2;
4365 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC 0x1UL
4366 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC 0x2UL
4367 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_IP_CS_CALC 0x4UL
4368 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_T_L4_CS_CALC 0x8UL
4369 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL
4370 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4
4371 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (0x0UL << 4)
4372 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN (0x1UL << 4)
4373 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4)
4374 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4)
4375 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4)
4376 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_LAST \
4377 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET
4378 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL
4379 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL
4380 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_MASK 0xc00UL
4381 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_EXT_META_FORMAT_SFT 10
4382 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL
4383 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16
4384 __le32 raweth_qp1_metadata;
4385 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_MASK 0xffffUL
4386 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_DE_VID_SFT 0
4387 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK 0xfffUL
4388 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_SFT 0
4389 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_DE 0x1000UL
4390 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK 0xe000UL
4391 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT 13
4392 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK 0xffff0000UL
4393 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT 16
4394 u8 cqe_type_toggle;
4395 #define CQ_RES_RAWETH_QP1_TOGGLE 0x1UL
4396 #define CQ_RES_RAWETH_QP1_CQE_TYPE_MASK 0x1eUL
4397 #define CQ_RES_RAWETH_QP1_CQE_TYPE_SFT 1
4398 #define CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1)
4399 #define CQ_RES_RAWETH_QP1_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_CQE_TYPE_RES_RAWETH_QP1
4400 u8 status;
4401 #define CQ_RES_RAWETH_QP1_STATUS_OK 0x0UL
4402 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR 0x1UL
4403 #define CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
4404 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR 0x3UL
4405 #define CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
4406 #define CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
4407 #define CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
4408 #define CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR 0x8UL
4409 #define CQ_RES_RAWETH_QP1_STATUS_LAST CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR
4410 __le16 flags;
4411 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ 0x1UL
4412 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_RQ 0x0UL
4413 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ 0x1UL
4414 #define CQ_RES_RAWETH_QP1_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_FLAGS_SRQ_SRQ
4415 __le32 raweth_qp1_payload_offset_srq_or_rq_wr_id;
4416 #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
4417 #define CQ_RES_RAWETH_QP1_SRQ_OR_RQ_WR_ID_SFT 0
4418 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_MASK 0xff000000UL
4419 #define CQ_RES_RAWETH_QP1_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24
4420};
4421
4422/* cq_res_raweth_qp1_v2 (size:256b/32B) */
4423struct cq_res_raweth_qp1_v2 {
4424 __le16 length;
4425 #define CQ_RES_RAWETH_QP1_V2_LENGTH_MASK 0x3fffUL
4426 #define CQ_RES_RAWETH_QP1_V2_LENGTH_SFT 0
4427 __le16 raweth_qp1_flags;
4428 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_MASK 0x3ffUL
4429 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_SFT 0
4430 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ERROR 0x1UL
4431 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_MASK 0x3c0UL
4432 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_SFT 6
4433 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_NOT_KNOWN (0x0UL << 6)
4434 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_IP (0x1UL << 6)
4435 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_TCP (0x2UL << 6)
4436 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_UDP (0x3UL << 6)
4437 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_FCOE (0x4UL << 6)
4438 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ROCE (0x5UL << 6)
4439 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_ICMP (0x7UL << 6)
4440 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_WO_TIMESTAMP (0x8UL << 6)
4441 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP (0x9UL << 6)
4442 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_LAST \
4443 CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS_ITYPE_PTP_W_TIMESTAMP
4444 __le16 raweth_qp1_errors;
4445 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_IP_CS_ERROR 0x10UL
4446 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_L4_CS_ERROR 0x20UL
4447 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_IP_CS_ERROR 0x40UL
4448 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_L4_CS_ERROR 0x80UL
4449 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_CRC_ERROR 0x100UL
4450 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_MASK 0xe00UL
4451 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_SFT 9
4452 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_NO_ERROR (0x0UL << 9)
4453 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1UL << 9)
4454 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2UL << 9)
4455 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3UL << 9)
4456 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4UL << 9)
4457 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5UL << 9)
4458 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6UL << 9)
4459 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_LAST \
4460 CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL
4461 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_MASK 0xf000UL
4462 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_SFT 12
4463 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_NO_ERROR (0x0UL << 12)
4464 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1UL << 12)
4465 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2UL << 12)
4466 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3UL << 12)
4467 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4UL << 12)
4468 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5UL << 12)
4469 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6UL << 12)
4470 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL \
4471 (0x7UL << 12)
4472 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN \
4473 (0x8UL << 12)
4474 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_LAST \
4475 CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN
4476 __le16 cfa_metadata0;
4477 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_MASK 0xfffUL
4478 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_VID_SFT 0
4479 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_DE 0x1000UL
4480 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_MASK 0xe000UL
4481 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA0_PRI_SFT 13
4482 __le64 qp_handle;
4483 __le32 raweth_qp1_flags2;
4484 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_ALL_OK_MODE 0x8UL
4485 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_MASK 0xf0UL
4486 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_SFT 4
4487 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_NONE (0x0UL << 4)
4488 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_ACT_REC_PTR (0x1UL << 4)
4489 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_TUNNEL_ID (0x2UL << 4)
4490 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_CHDR_DATA (0x3UL << 4)
4491 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET (0x4UL << 4)
4492 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_LAST \
4493 CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_META_FORMAT_HDR_OFFSET
4494 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_IP_TYPE 0x100UL
4495 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_CALC 0x200UL
4496 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_MASK 0xfc00UL
4497 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_CS_OK_SFT 10
4498 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_MASK 0xffff0000UL
4499 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_FLAGS2_COMPLETE_CHECKSUM_SFT 16
4500 __le32 cfa_metadata2;
4501 u8 cqe_type_toggle;
4502 #define CQ_RES_RAWETH_QP1_V2_TOGGLE 0x1UL
4503 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_MASK 0x1eUL
4504 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_SFT 1
4505 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1 (0x3UL << 1)
4506 #define CQ_RES_RAWETH_QP1_V2_CQE_TYPE_LAST CQ_RES_RAWETH_QP1_V2_CQE_TYPE_RES_RAWETH_QP1
4507 u8 status;
4508 #define CQ_RES_RAWETH_QP1_V2_STATUS_OK 0x0UL
4509 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_ACCESS_ERROR 0x1UL
4510 #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_LOCAL_LENGTH_ERR 0x2UL
4511 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_PROTECTION_ERR 0x3UL
4512 #define CQ_RES_RAWETH_QP1_V2_STATUS_LOCAL_QP_OPERATION_ERR 0x4UL
4513 #define CQ_RES_RAWETH_QP1_V2_STATUS_MEMORY_MGT_OPERATION_ERR 0x5UL
4514 #define CQ_RES_RAWETH_QP1_V2_STATUS_WORK_REQUEST_FLUSHED_ERR 0x7UL
4515 #define CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR 0x8UL
4516 #define CQ_RES_RAWETH_QP1_V2_STATUS_LAST CQ_RES_RAWETH_QP1_V2_STATUS_HW_FLUSH_ERR
4517 __le16 flags;
4518 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ 0x1UL
4519 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_RQ 0x0UL
4520 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ 0x1UL
4521 #define CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_LAST CQ_RES_RAWETH_QP1_V2_FLAGS_SRQ_SRQ
4522 __le32 raweth_qp1_payload_offset_srq_or_rq_wr_id;
4523 #define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_MASK 0xfffffUL
4524 #define CQ_RES_RAWETH_QP1_V2_SRQ_OR_RQ_WR_ID_SFT 0
4525 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_MASK 0xf00000UL
4526 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_SFT 20
4527 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_MASK 0x700000UL
4528 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_SFT 20
4529 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID88A8 (0x0UL << 20)
4530 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID8100 (0x1UL << 20)
4531 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9100 (0x2UL << 20)
4532 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9200 (0x3UL << 20)
4533 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPID9300 (0x4UL << 20)
4534 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG (0x5UL << 20)
4535 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_LAST \
4536 CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_TPID_SEL_TPIDCFG
4537 #define CQ_RES_RAWETH_QP1_V2_CFA_METADATA1_VALID 0x800000UL
4538 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_MASK 0xff000000UL
4539 #define CQ_RES_RAWETH_QP1_V2_RAWETH_QP1_PAYLOAD_OFFSET_SFT 24
4540};
4541
4542/* cq_terminal (size:256b/32B) */
4543struct cq_terminal {
4544 __le64 qp_handle;
4545 __le16 sq_cons_idx;
4546 __le16 rq_cons_idx;
4547 __le32 reserved32_1;
4548 __le64 reserved64_3;
4549 u8 cqe_type_toggle;
4550 #define CQ_TERMINAL_TOGGLE 0x1UL
4551 #define CQ_TERMINAL_CQE_TYPE_MASK 0x1eUL
4552 #define CQ_TERMINAL_CQE_TYPE_SFT 1
4553 #define CQ_TERMINAL_CQE_TYPE_TERMINAL (0xeUL << 1)
4554 #define CQ_TERMINAL_CQE_TYPE_LAST CQ_TERMINAL_CQE_TYPE_TERMINAL
4555 u8 status;
4556 #define CQ_TERMINAL_STATUS_OK 0x0UL
4557 #define CQ_TERMINAL_STATUS_LAST CQ_TERMINAL_STATUS_OK
4558 __le16 reserved16;
4559 __le32 reserved32_2;
4560};
4561
4562/* cq_cutoff (size:256b/32B) */
4563struct cq_cutoff {
4564 __le64 reserved64_1;
4565 __le64 reserved64_2;
4566 __le64 reserved64_3;
4567 u8 cqe_type_toggle;
4568 #define CQ_CUTOFF_TOGGLE 0x1UL
4569 #define CQ_CUTOFF_CQE_TYPE_MASK 0x1eUL
4570 #define CQ_CUTOFF_CQE_TYPE_SFT 1
4571 #define CQ_CUTOFF_CQE_TYPE_CUT_OFF (0xfUL << 1)
4572 #define CQ_CUTOFF_CQE_TYPE_LAST CQ_CUTOFF_CQE_TYPE_CUT_OFF
4573 #define CQ_CUTOFF_RESIZE_TOGGLE_MASK 0x60UL
4574 #define CQ_CUTOFF_RESIZE_TOGGLE_SFT 5
4575 u8 status;
4576 #define CQ_CUTOFF_STATUS_OK 0x0UL
4577 #define CQ_CUTOFF_STATUS_LAST CQ_CUTOFF_STATUS_OK
4578 __le16 reserved16;
4579 __le32 reserved32;
4580};
4581
4582/* nq_base (size:128b/16B) */
4583struct nq_base {
4584 __le16 info10_type;
4585 #define NQ_BASE_TYPE_MASK 0x3fUL
4586 #define NQ_BASE_TYPE_SFT 0
4587 #define NQ_BASE_TYPE_CQ_NOTIFICATION 0x30UL
4588 #define NQ_BASE_TYPE_SRQ_EVENT 0x32UL
4589 #define NQ_BASE_TYPE_DBQ_EVENT 0x34UL
4590 #define NQ_BASE_TYPE_QP_EVENT 0x38UL
4591 #define NQ_BASE_TYPE_FUNC_EVENT 0x3aUL
4592 #define NQ_BASE_TYPE_LAST NQ_BASE_TYPE_FUNC_EVENT
4593 #define NQ_BASE_INFO10_MASK 0xffc0UL
4594 #define NQ_BASE_INFO10_SFT 6
4595 __le16 info16;
4596 __le32 info32;
4597 __le32 info63_v[2];
4598 #define NQ_BASE_V 0x1UL
4599 #define NQ_BASE_INFO63_MASK 0xfffffffeUL
4600 #define NQ_BASE_INFO63_SFT 1
4601};
4602
4603/* nq_cn (size:128b/16B) */
4604struct nq_cn {
4605 __le16 type;
4606 #define NQ_CN_TYPE_MASK 0x3fUL
4607 #define NQ_CN_TYPE_SFT 0
4608 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
4609 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
4610 #define NQ_CN_TOGGLE_MASK 0xc0UL
4611 #define NQ_CN_TOGGLE_SFT 6
4612 __le16 reserved16;
4613 __le32 cq_handle_low;
4614 __le32 v;
4615 #define NQ_CN_V 0x1UL
4616 __le32 cq_handle_high;
4617};
4618
4619/* nq_srq_event (size:128b/16B) */
4620struct nq_srq_event {
4621 u8 type;
4622 #define NQ_SRQ_EVENT_TYPE_MASK 0x3fUL
4623 #define NQ_SRQ_EVENT_TYPE_SFT 0
4624 #define NQ_SRQ_EVENT_TYPE_SRQ_EVENT 0x32UL
4625 #define NQ_SRQ_EVENT_TYPE_LAST NQ_SRQ_EVENT_TYPE_SRQ_EVENT
4626 #define NQ_SRQ_EVENT_TOGGLE_MASK 0xc0UL
4627 #define NQ_SRQ_EVENT_TOGGLE_SFT 6
4628 u8 event;
4629 #define NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT 0x1UL
4630 #define NQ_SRQ_EVENT_EVENT_LAST NQ_SRQ_EVENT_EVENT_SRQ_THRESHOLD_EVENT
4631 __le16 reserved16;
4632 __le32 srq_handle_low;
4633 __le32 v;
4634 #define NQ_SRQ_EVENT_V 0x1UL
4635 __le32 srq_handle_high;
4636};
4637
4638/* nq_dbq_event (size:128b/16B) */
4639struct nq_dbq_event {
4640 u8 type;
4641 #define NQ_DBQ_EVENT_TYPE_MASK 0x3fUL
4642 #define NQ_DBQ_EVENT_TYPE_SFT 0
4643 #define NQ_DBQ_EVENT_TYPE_DBQ_EVENT 0x34UL
4644 #define NQ_DBQ_EVENT_TYPE_LAST NQ_DBQ_EVENT_TYPE_DBQ_EVENT
4645 u8 event;
4646 #define NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT 0x1UL
4647 #define NQ_DBQ_EVENT_EVENT_LAST NQ_DBQ_EVENT_EVENT_DBQ_THRESHOLD_EVENT
4648 __le16 db_pfid;
4649 #define NQ_DBQ_EVENT_DB_PFID_MASK 0xfUL
4650 #define NQ_DBQ_EVENT_DB_PFID_SFT 0
4651 __le32 db_dpi;
4652 #define NQ_DBQ_EVENT_DB_DPI_MASK 0xfffffUL
4653 #define NQ_DBQ_EVENT_DB_DPI_SFT 0
4654 __le32 v;
4655 #define NQ_DBQ_EVENT_V 0x1UL
4656 __le32 db_type_db_xid;
4657 #define NQ_DBQ_EVENT_DB_XID_MASK 0xfffffUL
4658 #define NQ_DBQ_EVENT_DB_XID_SFT 0
4659 #define NQ_DBQ_EVENT_DB_TYPE_MASK 0xf0000000UL
4660 #define NQ_DBQ_EVENT_DB_TYPE_SFT 28
4661};
4662
4663/* xrrq_irrq (size:256b/32B) */
4664struct xrrq_irrq {
4665 __le16 credits_type;
4666 #define XRRQ_IRRQ_TYPE 0x1UL
4667 #define XRRQ_IRRQ_TYPE_READ_REQ 0x0UL
4668 #define XRRQ_IRRQ_TYPE_ATOMIC_REQ 0x1UL
4669 #define XRRQ_IRRQ_TYPE_LAST XRRQ_IRRQ_TYPE_ATOMIC_REQ
4670 #define XRRQ_IRRQ_CREDITS_MASK 0xf800UL
4671 #define XRRQ_IRRQ_CREDITS_SFT 11
4672 __le16 reserved16;
4673 __le32 reserved32;
4674 __le32 psn;
4675 #define XRRQ_IRRQ_PSN_MASK 0xffffffUL
4676 #define XRRQ_IRRQ_PSN_SFT 0
4677 __le32 msn;
4678 #define XRRQ_IRRQ_MSN_MASK 0xffffffUL
4679 #define XRRQ_IRRQ_MSN_SFT 0
4680 __le64 va_or_atomic_result;
4681 __le32 rdma_r_key;
4682 __le32 length;
4683};
4684
4685/* xrrq_orrq (size:256b/32B) */
4686struct xrrq_orrq {
4687 __le16 num_sges_type;
4688 #define XRRQ_ORRQ_TYPE 0x1UL
4689 #define XRRQ_ORRQ_TYPE_READ_REQ 0x0UL
4690 #define XRRQ_ORRQ_TYPE_ATOMIC_REQ 0x1UL
4691 #define XRRQ_ORRQ_TYPE_LAST XRRQ_ORRQ_TYPE_ATOMIC_REQ
4692 #define XRRQ_ORRQ_NUM_SGES_MASK 0xf800UL
4693 #define XRRQ_ORRQ_NUM_SGES_SFT 11
4694 __le16 reserved16;
4695 __le32 length;
4696 __le32 psn;
4697 #define XRRQ_ORRQ_PSN_MASK 0xffffffUL
4698 #define XRRQ_ORRQ_PSN_SFT 0
4699 __le32 end_psn;
4700 #define XRRQ_ORRQ_END_PSN_MASK 0xffffffUL
4701 #define XRRQ_ORRQ_END_PSN_SFT 0
4702 __le64 first_sge_phy_or_sing_sge_va;
4703 __le32 single_sge_l_key;
4704 __le32 single_sge_size;
4705};
4706
4707/* ptu_pte (size:64b/8B) */
4708struct ptu_pte {
4709 __le32 page_next_to_last_last_valid[2];
4710 #define PTU_PTE_VALID 0x1UL
4711 #define PTU_PTE_LAST 0x2UL
4712 #define PTU_PTE_NEXT_TO_LAST 0x4UL
4713 #define PTU_PTE_UNUSED_MASK 0xff8UL
4714 #define PTU_PTE_UNUSED_SFT 3
4715 #define PTU_PTE_PAGE_MASK 0xfffff000UL
4716 #define PTU_PTE_PAGE_SFT 12
4717};
4718
4719/* ptu_pde (size:64b/8B) */
4720struct ptu_pde {
4721 __le32 page_valid[2];
4722 #define PTU_PDE_VALID 0x1UL
4723 #define PTU_PDE_UNUSED_MASK 0xffeUL
4724 #define PTU_PDE_UNUSED_SFT 1
4725 #define PTU_PDE_PAGE_MASK 0xfffff000UL
4726 #define PTU_PDE_PAGE_SFT 12
4727};
4728
4729#endif /* ___BNXT_RE_HSI_H__ */
4730

source code of linux/drivers/infiniband/hw/bnxt_re/roce_hsi.h