1/*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 * SOFTWARE.
30 */
31#ifndef _T4FW_RI_API_H_
32#define _T4FW_RI_API_H_
33
34#include "t4fw_api.h"
35
36enum fw_ri_wr_opcode {
37 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */
38 FW_RI_READ_REQ = 0x1,
39 FW_RI_READ_RESP = 0x2,
40 FW_RI_SEND = 0x3,
41 FW_RI_SEND_WITH_INV = 0x4,
42 FW_RI_SEND_WITH_SE = 0x5,
43 FW_RI_SEND_WITH_SE_INV = 0x6,
44 FW_RI_TERMINATE = 0x7,
45 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */
46 FW_RI_BIND_MW = 0x9,
47 FW_RI_FAST_REGISTER = 0xa,
48 FW_RI_LOCAL_INV = 0xb,
49 FW_RI_QP_MODIFY = 0xc,
50 FW_RI_BYPASS = 0xd,
51 FW_RI_RECEIVE = 0xe,
52
53 FW_RI_SGE_EC_CR_RETURN = 0xf,
54 FW_RI_WRITE_IMMEDIATE = FW_RI_RDMA_INIT
55};
56
57enum fw_ri_wr_flags {
58 FW_RI_COMPLETION_FLAG = 0x01,
59 FW_RI_NOTIFICATION_FLAG = 0x02,
60 FW_RI_SOLICITED_EVENT_FLAG = 0x04,
61 FW_RI_READ_FENCE_FLAG = 0x08,
62 FW_RI_LOCAL_FENCE_FLAG = 0x10,
63 FW_RI_RDMA_READ_INVALIDATE = 0x20,
64 FW_RI_RDMA_WRITE_WITH_IMMEDIATE = 0x40
65};
66
67enum fw_ri_mpa_attrs {
68 FW_RI_MPA_RX_MARKER_ENABLE = 0x01,
69 FW_RI_MPA_TX_MARKER_ENABLE = 0x02,
70 FW_RI_MPA_CRC_ENABLE = 0x04,
71 FW_RI_MPA_IETF_ENABLE = 0x08
72};
73
74enum fw_ri_qp_caps {
75 FW_RI_QP_RDMA_READ_ENABLE = 0x01,
76 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02,
77 FW_RI_QP_BIND_ENABLE = 0x04,
78 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08,
79 FW_RI_QP_STAG0_ENABLE = 0x10
80};
81
82enum fw_ri_addr_type {
83 FW_RI_ZERO_BASED_TO = 0x00,
84 FW_RI_VA_BASED_TO = 0x01
85};
86
87enum fw_ri_mem_perms {
88 FW_RI_MEM_ACCESS_REM_WRITE = 0x01,
89 FW_RI_MEM_ACCESS_REM_READ = 0x02,
90 FW_RI_MEM_ACCESS_REM = 0x03,
91 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04,
92 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08,
93 FW_RI_MEM_ACCESS_LOCAL = 0x0C
94};
95
96enum fw_ri_stag_type {
97 FW_RI_STAG_NSMR = 0x00,
98 FW_RI_STAG_SMR = 0x01,
99 FW_RI_STAG_MW = 0x02,
100 FW_RI_STAG_MW_RELAXED = 0x03
101};
102
103enum fw_ri_data_op {
104 FW_RI_DATA_IMMD = 0x81,
105 FW_RI_DATA_DSGL = 0x82,
106 FW_RI_DATA_ISGL = 0x83
107};
108
109enum fw_ri_sgl_depth {
110 FW_RI_SGL_DEPTH_MAX_SQ = 16,
111 FW_RI_SGL_DEPTH_MAX_RQ = 4
112};
113
114struct fw_ri_dsge_pair {
115 __be32 len[2];
116 __be64 addr[2];
117};
118
119struct fw_ri_dsgl {
120 __u8 op;
121 __u8 r1;
122 __be16 nsge;
123 __be32 len0;
124 __be64 addr0;
125 struct fw_ri_dsge_pair sge[];
126};
127
128struct fw_ri_sge {
129 __be32 stag;
130 __be32 len;
131 __be64 to;
132};
133
134struct fw_ri_isgl {
135 __u8 op;
136 __u8 r1;
137 __be16 nsge;
138 __be32 r2;
139 struct fw_ri_sge sge[];
140};
141
142struct fw_ri_immd {
143 __u8 op;
144 __u8 r1;
145 __be16 r2;
146 __be32 immdlen;
147 __u8 data[];
148};
149
150struct fw_ri_tpte {
151 __be32 valid_to_pdid;
152 __be32 locread_to_qpid;
153 __be32 nosnoop_pbladdr;
154 __be32 len_lo;
155 __be32 va_hi;
156 __be32 va_lo_fbo;
157 __be32 dca_mwbcnt_pstag;
158 __be32 len_hi;
159};
160
161#define FW_RI_TPTE_VALID_S 31
162#define FW_RI_TPTE_VALID_M 0x1
163#define FW_RI_TPTE_VALID_V(x) ((x) << FW_RI_TPTE_VALID_S)
164#define FW_RI_TPTE_VALID_G(x) \
165 (((x) >> FW_RI_TPTE_VALID_S) & FW_RI_TPTE_VALID_M)
166#define FW_RI_TPTE_VALID_F FW_RI_TPTE_VALID_V(1U)
167
168#define FW_RI_TPTE_STAGKEY_S 23
169#define FW_RI_TPTE_STAGKEY_M 0xff
170#define FW_RI_TPTE_STAGKEY_V(x) ((x) << FW_RI_TPTE_STAGKEY_S)
171#define FW_RI_TPTE_STAGKEY_G(x) \
172 (((x) >> FW_RI_TPTE_STAGKEY_S) & FW_RI_TPTE_STAGKEY_M)
173
174#define FW_RI_TPTE_STAGSTATE_S 22
175#define FW_RI_TPTE_STAGSTATE_M 0x1
176#define FW_RI_TPTE_STAGSTATE_V(x) ((x) << FW_RI_TPTE_STAGSTATE_S)
177#define FW_RI_TPTE_STAGSTATE_G(x) \
178 (((x) >> FW_RI_TPTE_STAGSTATE_S) & FW_RI_TPTE_STAGSTATE_M)
179#define FW_RI_TPTE_STAGSTATE_F FW_RI_TPTE_STAGSTATE_V(1U)
180
181#define FW_RI_TPTE_STAGTYPE_S 20
182#define FW_RI_TPTE_STAGTYPE_M 0x3
183#define FW_RI_TPTE_STAGTYPE_V(x) ((x) << FW_RI_TPTE_STAGTYPE_S)
184#define FW_RI_TPTE_STAGTYPE_G(x) \
185 (((x) >> FW_RI_TPTE_STAGTYPE_S) & FW_RI_TPTE_STAGTYPE_M)
186
187#define FW_RI_TPTE_PDID_S 0
188#define FW_RI_TPTE_PDID_M 0xfffff
189#define FW_RI_TPTE_PDID_V(x) ((x) << FW_RI_TPTE_PDID_S)
190#define FW_RI_TPTE_PDID_G(x) \
191 (((x) >> FW_RI_TPTE_PDID_S) & FW_RI_TPTE_PDID_M)
192
193#define FW_RI_TPTE_PERM_S 28
194#define FW_RI_TPTE_PERM_M 0xf
195#define FW_RI_TPTE_PERM_V(x) ((x) << FW_RI_TPTE_PERM_S)
196#define FW_RI_TPTE_PERM_G(x) \
197 (((x) >> FW_RI_TPTE_PERM_S) & FW_RI_TPTE_PERM_M)
198
199#define FW_RI_TPTE_REMINVDIS_S 27
200#define FW_RI_TPTE_REMINVDIS_M 0x1
201#define FW_RI_TPTE_REMINVDIS_V(x) ((x) << FW_RI_TPTE_REMINVDIS_S)
202#define FW_RI_TPTE_REMINVDIS_G(x) \
203 (((x) >> FW_RI_TPTE_REMINVDIS_S) & FW_RI_TPTE_REMINVDIS_M)
204#define FW_RI_TPTE_REMINVDIS_F FW_RI_TPTE_REMINVDIS_V(1U)
205
206#define FW_RI_TPTE_ADDRTYPE_S 26
207#define FW_RI_TPTE_ADDRTYPE_M 1
208#define FW_RI_TPTE_ADDRTYPE_V(x) ((x) << FW_RI_TPTE_ADDRTYPE_S)
209#define FW_RI_TPTE_ADDRTYPE_G(x) \
210 (((x) >> FW_RI_TPTE_ADDRTYPE_S) & FW_RI_TPTE_ADDRTYPE_M)
211#define FW_RI_TPTE_ADDRTYPE_F FW_RI_TPTE_ADDRTYPE_V(1U)
212
213#define FW_RI_TPTE_MWBINDEN_S 25
214#define FW_RI_TPTE_MWBINDEN_M 0x1
215#define FW_RI_TPTE_MWBINDEN_V(x) ((x) << FW_RI_TPTE_MWBINDEN_S)
216#define FW_RI_TPTE_MWBINDEN_G(x) \
217 (((x) >> FW_RI_TPTE_MWBINDEN_S) & FW_RI_TPTE_MWBINDEN_M)
218#define FW_RI_TPTE_MWBINDEN_F FW_RI_TPTE_MWBINDEN_V(1U)
219
220#define FW_RI_TPTE_PS_S 20
221#define FW_RI_TPTE_PS_M 0x1f
222#define FW_RI_TPTE_PS_V(x) ((x) << FW_RI_TPTE_PS_S)
223#define FW_RI_TPTE_PS_G(x) \
224 (((x) >> FW_RI_TPTE_PS_S) & FW_RI_TPTE_PS_M)
225
226#define FW_RI_TPTE_QPID_S 0
227#define FW_RI_TPTE_QPID_M 0xfffff
228#define FW_RI_TPTE_QPID_V(x) ((x) << FW_RI_TPTE_QPID_S)
229#define FW_RI_TPTE_QPID_G(x) \
230 (((x) >> FW_RI_TPTE_QPID_S) & FW_RI_TPTE_QPID_M)
231
232#define FW_RI_TPTE_NOSNOOP_S 30
233#define FW_RI_TPTE_NOSNOOP_M 0x1
234#define FW_RI_TPTE_NOSNOOP_V(x) ((x) << FW_RI_TPTE_NOSNOOP_S)
235#define FW_RI_TPTE_NOSNOOP_G(x) \
236 (((x) >> FW_RI_TPTE_NOSNOOP_S) & FW_RI_TPTE_NOSNOOP_M)
237#define FW_RI_TPTE_NOSNOOP_F FW_RI_TPTE_NOSNOOP_V(1U)
238
239#define FW_RI_TPTE_PBLADDR_S 0
240#define FW_RI_TPTE_PBLADDR_M 0x1fffffff
241#define FW_RI_TPTE_PBLADDR_V(x) ((x) << FW_RI_TPTE_PBLADDR_S)
242#define FW_RI_TPTE_PBLADDR_G(x) \
243 (((x) >> FW_RI_TPTE_PBLADDR_S) & FW_RI_TPTE_PBLADDR_M)
244
245#define FW_RI_TPTE_DCA_S 24
246#define FW_RI_TPTE_DCA_M 0x1f
247#define FW_RI_TPTE_DCA_V(x) ((x) << FW_RI_TPTE_DCA_S)
248#define FW_RI_TPTE_DCA_G(x) \
249 (((x) >> FW_RI_TPTE_DCA_S) & FW_RI_TPTE_DCA_M)
250
251#define FW_RI_TPTE_MWBCNT_PSTAG_S 0
252#define FW_RI_TPTE_MWBCNT_PSTAG_M 0xffffff
253#define FW_RI_TPTE_MWBCNT_PSTAT_V(x) \
254 ((x) << FW_RI_TPTE_MWBCNT_PSTAG_S)
255#define FW_RI_TPTE_MWBCNT_PSTAG_G(x) \
256 (((x) >> FW_RI_TPTE_MWBCNT_PSTAG_S) & FW_RI_TPTE_MWBCNT_PSTAG_M)
257
258enum fw_ri_res_type {
259 FW_RI_RES_TYPE_SQ,
260 FW_RI_RES_TYPE_RQ,
261 FW_RI_RES_TYPE_CQ,
262 FW_RI_RES_TYPE_SRQ,
263};
264
265enum fw_ri_res_op {
266 FW_RI_RES_OP_WRITE,
267 FW_RI_RES_OP_RESET,
268};
269
270struct fw_ri_res {
271 union fw_ri_restype {
272 struct fw_ri_res_sqrq {
273 __u8 restype;
274 __u8 op;
275 __be16 r3;
276 __be32 eqid;
277 __be32 r4[2];
278 __be32 fetchszm_to_iqid;
279 __be32 dcaen_to_eqsize;
280 __be64 eqaddr;
281 } sqrq;
282 struct fw_ri_res_cq {
283 __u8 restype;
284 __u8 op;
285 __be16 r3;
286 __be32 iqid;
287 __be32 r4[2];
288 __be32 iqandst_to_iqandstindex;
289 __be16 iqdroprss_to_iqesize;
290 __be16 iqsize;
291 __be64 iqaddr;
292 __be32 iqns_iqro;
293 __be32 r6_lo;
294 __be64 r7;
295 } cq;
296 struct fw_ri_res_srq {
297 __u8 restype;
298 __u8 op;
299 __be16 r3;
300 __be32 eqid;
301 __be32 r4[2];
302 __be32 fetchszm_to_iqid;
303 __be32 dcaen_to_eqsize;
304 __be64 eqaddr;
305 __be32 srqid;
306 __be32 pdid;
307 __be32 hwsrqsize;
308 __be32 hwsrqaddr;
309 } srq;
310 } u;
311};
312
313struct fw_ri_res_wr {
314 __be32 op_nres;
315 __be32 len16_pkd;
316 __u64 cookie;
317 struct fw_ri_res res[];
318};
319
320#define FW_RI_RES_WR_NRES_S 0
321#define FW_RI_RES_WR_NRES_M 0xff
322#define FW_RI_RES_WR_NRES_V(x) ((x) << FW_RI_RES_WR_NRES_S)
323#define FW_RI_RES_WR_NRES_G(x) \
324 (((x) >> FW_RI_RES_WR_NRES_S) & FW_RI_RES_WR_NRES_M)
325
326#define FW_RI_RES_WR_FETCHSZM_S 26
327#define FW_RI_RES_WR_FETCHSZM_M 0x1
328#define FW_RI_RES_WR_FETCHSZM_V(x) ((x) << FW_RI_RES_WR_FETCHSZM_S)
329#define FW_RI_RES_WR_FETCHSZM_G(x) \
330 (((x) >> FW_RI_RES_WR_FETCHSZM_S) & FW_RI_RES_WR_FETCHSZM_M)
331#define FW_RI_RES_WR_FETCHSZM_F FW_RI_RES_WR_FETCHSZM_V(1U)
332
333#define FW_RI_RES_WR_STATUSPGNS_S 25
334#define FW_RI_RES_WR_STATUSPGNS_M 0x1
335#define FW_RI_RES_WR_STATUSPGNS_V(x) ((x) << FW_RI_RES_WR_STATUSPGNS_S)
336#define FW_RI_RES_WR_STATUSPGNS_G(x) \
337 (((x) >> FW_RI_RES_WR_STATUSPGNS_S) & FW_RI_RES_WR_STATUSPGNS_M)
338#define FW_RI_RES_WR_STATUSPGNS_F FW_RI_RES_WR_STATUSPGNS_V(1U)
339
340#define FW_RI_RES_WR_STATUSPGRO_S 24
341#define FW_RI_RES_WR_STATUSPGRO_M 0x1
342#define FW_RI_RES_WR_STATUSPGRO_V(x) ((x) << FW_RI_RES_WR_STATUSPGRO_S)
343#define FW_RI_RES_WR_STATUSPGRO_G(x) \
344 (((x) >> FW_RI_RES_WR_STATUSPGRO_S) & FW_RI_RES_WR_STATUSPGRO_M)
345#define FW_RI_RES_WR_STATUSPGRO_F FW_RI_RES_WR_STATUSPGRO_V(1U)
346
347#define FW_RI_RES_WR_FETCHNS_S 23
348#define FW_RI_RES_WR_FETCHNS_M 0x1
349#define FW_RI_RES_WR_FETCHNS_V(x) ((x) << FW_RI_RES_WR_FETCHNS_S)
350#define FW_RI_RES_WR_FETCHNS_G(x) \
351 (((x) >> FW_RI_RES_WR_FETCHNS_S) & FW_RI_RES_WR_FETCHNS_M)
352#define FW_RI_RES_WR_FETCHNS_F FW_RI_RES_WR_FETCHNS_V(1U)
353
354#define FW_RI_RES_WR_FETCHRO_S 22
355#define FW_RI_RES_WR_FETCHRO_M 0x1
356#define FW_RI_RES_WR_FETCHRO_V(x) ((x) << FW_RI_RES_WR_FETCHRO_S)
357#define FW_RI_RES_WR_FETCHRO_G(x) \
358 (((x) >> FW_RI_RES_WR_FETCHRO_S) & FW_RI_RES_WR_FETCHRO_M)
359#define FW_RI_RES_WR_FETCHRO_F FW_RI_RES_WR_FETCHRO_V(1U)
360
361#define FW_RI_RES_WR_HOSTFCMODE_S 20
362#define FW_RI_RES_WR_HOSTFCMODE_M 0x3
363#define FW_RI_RES_WR_HOSTFCMODE_V(x) ((x) << FW_RI_RES_WR_HOSTFCMODE_S)
364#define FW_RI_RES_WR_HOSTFCMODE_G(x) \
365 (((x) >> FW_RI_RES_WR_HOSTFCMODE_S) & FW_RI_RES_WR_HOSTFCMODE_M)
366
367#define FW_RI_RES_WR_CPRIO_S 19
368#define FW_RI_RES_WR_CPRIO_M 0x1
369#define FW_RI_RES_WR_CPRIO_V(x) ((x) << FW_RI_RES_WR_CPRIO_S)
370#define FW_RI_RES_WR_CPRIO_G(x) \
371 (((x) >> FW_RI_RES_WR_CPRIO_S) & FW_RI_RES_WR_CPRIO_M)
372#define FW_RI_RES_WR_CPRIO_F FW_RI_RES_WR_CPRIO_V(1U)
373
374#define FW_RI_RES_WR_ONCHIP_S 18
375#define FW_RI_RES_WR_ONCHIP_M 0x1
376#define FW_RI_RES_WR_ONCHIP_V(x) ((x) << FW_RI_RES_WR_ONCHIP_S)
377#define FW_RI_RES_WR_ONCHIP_G(x) \
378 (((x) >> FW_RI_RES_WR_ONCHIP_S) & FW_RI_RES_WR_ONCHIP_M)
379#define FW_RI_RES_WR_ONCHIP_F FW_RI_RES_WR_ONCHIP_V(1U)
380
381#define FW_RI_RES_WR_PCIECHN_S 16
382#define FW_RI_RES_WR_PCIECHN_M 0x3
383#define FW_RI_RES_WR_PCIECHN_V(x) ((x) << FW_RI_RES_WR_PCIECHN_S)
384#define FW_RI_RES_WR_PCIECHN_G(x) \
385 (((x) >> FW_RI_RES_WR_PCIECHN_S) & FW_RI_RES_WR_PCIECHN_M)
386
387#define FW_RI_RES_WR_IQID_S 0
388#define FW_RI_RES_WR_IQID_M 0xffff
389#define FW_RI_RES_WR_IQID_V(x) ((x) << FW_RI_RES_WR_IQID_S)
390#define FW_RI_RES_WR_IQID_G(x) \
391 (((x) >> FW_RI_RES_WR_IQID_S) & FW_RI_RES_WR_IQID_M)
392
393#define FW_RI_RES_WR_DCAEN_S 31
394#define FW_RI_RES_WR_DCAEN_M 0x1
395#define FW_RI_RES_WR_DCAEN_V(x) ((x) << FW_RI_RES_WR_DCAEN_S)
396#define FW_RI_RES_WR_DCAEN_G(x) \
397 (((x) >> FW_RI_RES_WR_DCAEN_S) & FW_RI_RES_WR_DCAEN_M)
398#define FW_RI_RES_WR_DCAEN_F FW_RI_RES_WR_DCAEN_V(1U)
399
400#define FW_RI_RES_WR_DCACPU_S 26
401#define FW_RI_RES_WR_DCACPU_M 0x1f
402#define FW_RI_RES_WR_DCACPU_V(x) ((x) << FW_RI_RES_WR_DCACPU_S)
403#define FW_RI_RES_WR_DCACPU_G(x) \
404 (((x) >> FW_RI_RES_WR_DCACPU_S) & FW_RI_RES_WR_DCACPU_M)
405
406#define FW_RI_RES_WR_FBMIN_S 23
407#define FW_RI_RES_WR_FBMIN_M 0x7
408#define FW_RI_RES_WR_FBMIN_V(x) ((x) << FW_RI_RES_WR_FBMIN_S)
409#define FW_RI_RES_WR_FBMIN_G(x) \
410 (((x) >> FW_RI_RES_WR_FBMIN_S) & FW_RI_RES_WR_FBMIN_M)
411
412#define FW_RI_RES_WR_FBMAX_S 20
413#define FW_RI_RES_WR_FBMAX_M 0x7
414#define FW_RI_RES_WR_FBMAX_V(x) ((x) << FW_RI_RES_WR_FBMAX_S)
415#define FW_RI_RES_WR_FBMAX_G(x) \
416 (((x) >> FW_RI_RES_WR_FBMAX_S) & FW_RI_RES_WR_FBMAX_M)
417
418#define FW_RI_RES_WR_CIDXFTHRESHO_S 19
419#define FW_RI_RES_WR_CIDXFTHRESHO_M 0x1
420#define FW_RI_RES_WR_CIDXFTHRESHO_V(x) ((x) << FW_RI_RES_WR_CIDXFTHRESHO_S)
421#define FW_RI_RES_WR_CIDXFTHRESHO_G(x) \
422 (((x) >> FW_RI_RES_WR_CIDXFTHRESHO_S) & FW_RI_RES_WR_CIDXFTHRESHO_M)
423#define FW_RI_RES_WR_CIDXFTHRESHO_F FW_RI_RES_WR_CIDXFTHRESHO_V(1U)
424
425#define FW_RI_RES_WR_CIDXFTHRESH_S 16
426#define FW_RI_RES_WR_CIDXFTHRESH_M 0x7
427#define FW_RI_RES_WR_CIDXFTHRESH_V(x) ((x) << FW_RI_RES_WR_CIDXFTHRESH_S)
428#define FW_RI_RES_WR_CIDXFTHRESH_G(x) \
429 (((x) >> FW_RI_RES_WR_CIDXFTHRESH_S) & FW_RI_RES_WR_CIDXFTHRESH_M)
430
431#define FW_RI_RES_WR_EQSIZE_S 0
432#define FW_RI_RES_WR_EQSIZE_M 0xffff
433#define FW_RI_RES_WR_EQSIZE_V(x) ((x) << FW_RI_RES_WR_EQSIZE_S)
434#define FW_RI_RES_WR_EQSIZE_G(x) \
435 (((x) >> FW_RI_RES_WR_EQSIZE_S) & FW_RI_RES_WR_EQSIZE_M)
436
437#define FW_RI_RES_WR_IQANDST_S 15
438#define FW_RI_RES_WR_IQANDST_M 0x1
439#define FW_RI_RES_WR_IQANDST_V(x) ((x) << FW_RI_RES_WR_IQANDST_S)
440#define FW_RI_RES_WR_IQANDST_G(x) \
441 (((x) >> FW_RI_RES_WR_IQANDST_S) & FW_RI_RES_WR_IQANDST_M)
442#define FW_RI_RES_WR_IQANDST_F FW_RI_RES_WR_IQANDST_V(1U)
443
444#define FW_RI_RES_WR_IQANUS_S 14
445#define FW_RI_RES_WR_IQANUS_M 0x1
446#define FW_RI_RES_WR_IQANUS_V(x) ((x) << FW_RI_RES_WR_IQANUS_S)
447#define FW_RI_RES_WR_IQANUS_G(x) \
448 (((x) >> FW_RI_RES_WR_IQANUS_S) & FW_RI_RES_WR_IQANUS_M)
449#define FW_RI_RES_WR_IQANUS_F FW_RI_RES_WR_IQANUS_V(1U)
450
451#define FW_RI_RES_WR_IQANUD_S 12
452#define FW_RI_RES_WR_IQANUD_M 0x3
453#define FW_RI_RES_WR_IQANUD_V(x) ((x) << FW_RI_RES_WR_IQANUD_S)
454#define FW_RI_RES_WR_IQANUD_G(x) \
455 (((x) >> FW_RI_RES_WR_IQANUD_S) & FW_RI_RES_WR_IQANUD_M)
456
457#define FW_RI_RES_WR_IQANDSTINDEX_S 0
458#define FW_RI_RES_WR_IQANDSTINDEX_M 0xfff
459#define FW_RI_RES_WR_IQANDSTINDEX_V(x) ((x) << FW_RI_RES_WR_IQANDSTINDEX_S)
460#define FW_RI_RES_WR_IQANDSTINDEX_G(x) \
461 (((x) >> FW_RI_RES_WR_IQANDSTINDEX_S) & FW_RI_RES_WR_IQANDSTINDEX_M)
462
463#define FW_RI_RES_WR_IQDROPRSS_S 15
464#define FW_RI_RES_WR_IQDROPRSS_M 0x1
465#define FW_RI_RES_WR_IQDROPRSS_V(x) ((x) << FW_RI_RES_WR_IQDROPRSS_S)
466#define FW_RI_RES_WR_IQDROPRSS_G(x) \
467 (((x) >> FW_RI_RES_WR_IQDROPRSS_S) & FW_RI_RES_WR_IQDROPRSS_M)
468#define FW_RI_RES_WR_IQDROPRSS_F FW_RI_RES_WR_IQDROPRSS_V(1U)
469
470#define FW_RI_RES_WR_IQGTSMODE_S 14
471#define FW_RI_RES_WR_IQGTSMODE_M 0x1
472#define FW_RI_RES_WR_IQGTSMODE_V(x) ((x) << FW_RI_RES_WR_IQGTSMODE_S)
473#define FW_RI_RES_WR_IQGTSMODE_G(x) \
474 (((x) >> FW_RI_RES_WR_IQGTSMODE_S) & FW_RI_RES_WR_IQGTSMODE_M)
475#define FW_RI_RES_WR_IQGTSMODE_F FW_RI_RES_WR_IQGTSMODE_V(1U)
476
477#define FW_RI_RES_WR_IQPCIECH_S 12
478#define FW_RI_RES_WR_IQPCIECH_M 0x3
479#define FW_RI_RES_WR_IQPCIECH_V(x) ((x) << FW_RI_RES_WR_IQPCIECH_S)
480#define FW_RI_RES_WR_IQPCIECH_G(x) \
481 (((x) >> FW_RI_RES_WR_IQPCIECH_S) & FW_RI_RES_WR_IQPCIECH_M)
482
483#define FW_RI_RES_WR_IQDCAEN_S 11
484#define FW_RI_RES_WR_IQDCAEN_M 0x1
485#define FW_RI_RES_WR_IQDCAEN_V(x) ((x) << FW_RI_RES_WR_IQDCAEN_S)
486#define FW_RI_RES_WR_IQDCAEN_G(x) \
487 (((x) >> FW_RI_RES_WR_IQDCAEN_S) & FW_RI_RES_WR_IQDCAEN_M)
488#define FW_RI_RES_WR_IQDCAEN_F FW_RI_RES_WR_IQDCAEN_V(1U)
489
490#define FW_RI_RES_WR_IQDCACPU_S 6
491#define FW_RI_RES_WR_IQDCACPU_M 0x1f
492#define FW_RI_RES_WR_IQDCACPU_V(x) ((x) << FW_RI_RES_WR_IQDCACPU_S)
493#define FW_RI_RES_WR_IQDCACPU_G(x) \
494 (((x) >> FW_RI_RES_WR_IQDCACPU_S) & FW_RI_RES_WR_IQDCACPU_M)
495
496#define FW_RI_RES_WR_IQINTCNTTHRESH_S 4
497#define FW_RI_RES_WR_IQINTCNTTHRESH_M 0x3
498#define FW_RI_RES_WR_IQINTCNTTHRESH_V(x) \
499 ((x) << FW_RI_RES_WR_IQINTCNTTHRESH_S)
500#define FW_RI_RES_WR_IQINTCNTTHRESH_G(x) \
501 (((x) >> FW_RI_RES_WR_IQINTCNTTHRESH_S) & FW_RI_RES_WR_IQINTCNTTHRESH_M)
502
503#define FW_RI_RES_WR_IQO_S 3
504#define FW_RI_RES_WR_IQO_M 0x1
505#define FW_RI_RES_WR_IQO_V(x) ((x) << FW_RI_RES_WR_IQO_S)
506#define FW_RI_RES_WR_IQO_G(x) \
507 (((x) >> FW_RI_RES_WR_IQO_S) & FW_RI_RES_WR_IQO_M)
508#define FW_RI_RES_WR_IQO_F FW_RI_RES_WR_IQO_V(1U)
509
510#define FW_RI_RES_WR_IQCPRIO_S 2
511#define FW_RI_RES_WR_IQCPRIO_M 0x1
512#define FW_RI_RES_WR_IQCPRIO_V(x) ((x) << FW_RI_RES_WR_IQCPRIO_S)
513#define FW_RI_RES_WR_IQCPRIO_G(x) \
514 (((x) >> FW_RI_RES_WR_IQCPRIO_S) & FW_RI_RES_WR_IQCPRIO_M)
515#define FW_RI_RES_WR_IQCPRIO_F FW_RI_RES_WR_IQCPRIO_V(1U)
516
517#define FW_RI_RES_WR_IQESIZE_S 0
518#define FW_RI_RES_WR_IQESIZE_M 0x3
519#define FW_RI_RES_WR_IQESIZE_V(x) ((x) << FW_RI_RES_WR_IQESIZE_S)
520#define FW_RI_RES_WR_IQESIZE_G(x) \
521 (((x) >> FW_RI_RES_WR_IQESIZE_S) & FW_RI_RES_WR_IQESIZE_M)
522
523#define FW_RI_RES_WR_IQNS_S 31
524#define FW_RI_RES_WR_IQNS_M 0x1
525#define FW_RI_RES_WR_IQNS_V(x) ((x) << FW_RI_RES_WR_IQNS_S)
526#define FW_RI_RES_WR_IQNS_G(x) \
527 (((x) >> FW_RI_RES_WR_IQNS_S) & FW_RI_RES_WR_IQNS_M)
528#define FW_RI_RES_WR_IQNS_F FW_RI_RES_WR_IQNS_V(1U)
529
530#define FW_RI_RES_WR_IQRO_S 30
531#define FW_RI_RES_WR_IQRO_M 0x1
532#define FW_RI_RES_WR_IQRO_V(x) ((x) << FW_RI_RES_WR_IQRO_S)
533#define FW_RI_RES_WR_IQRO_G(x) \
534 (((x) >> FW_RI_RES_WR_IQRO_S) & FW_RI_RES_WR_IQRO_M)
535#define FW_RI_RES_WR_IQRO_F FW_RI_RES_WR_IQRO_V(1U)
536
537struct fw_ri_rdma_write_wr {
538 __u8 opcode;
539 __u8 flags;
540 __u16 wrid;
541 __u8 r1[3];
542 __u8 len16;
543 /*
544 * Use union for immediate data to be consistent with stack's 32 bit
545 * data and iWARP spec's 64 bit data.
546 */
547 union {
548 struct {
549 __be32 imm_data32;
550 u32 reserved;
551 } ib_imm_data;
552 __be64 imm_data64;
553 } iw_imm_data;
554 __be32 plen;
555 __be32 stag_sink;
556 __be64 to_sink;
557 union {
558 DECLARE_FLEX_ARRAY(struct fw_ri_immd, immd_src);
559 DECLARE_FLEX_ARRAY(struct fw_ri_isgl, isgl_src);
560 } u;
561};
562
563struct fw_ri_send_wr {
564 __u8 opcode;
565 __u8 flags;
566 __u16 wrid;
567 __u8 r1[3];
568 __u8 len16;
569 __be32 sendop_pkd;
570 __be32 stag_inv;
571 __be32 plen;
572 __be32 r3;
573 __be64 r4;
574 union {
575 DECLARE_FLEX_ARRAY(struct fw_ri_immd, immd_src);
576 DECLARE_FLEX_ARRAY(struct fw_ri_isgl, isgl_src);
577 } u;
578};
579
580#define FW_RI_SEND_WR_SENDOP_S 0
581#define FW_RI_SEND_WR_SENDOP_M 0xf
582#define FW_RI_SEND_WR_SENDOP_V(x) ((x) << FW_RI_SEND_WR_SENDOP_S)
583#define FW_RI_SEND_WR_SENDOP_G(x) \
584 (((x) >> FW_RI_SEND_WR_SENDOP_S) & FW_RI_SEND_WR_SENDOP_M)
585
586struct fw_ri_rdma_write_cmpl_wr {
587 __u8 opcode;
588 __u8 flags;
589 __u16 wrid;
590 __u8 r1[3];
591 __u8 len16;
592 __u8 r2;
593 __u8 flags_send;
594 __u16 wrid_send;
595 __be32 stag_inv;
596 __be32 plen;
597 __be32 stag_sink;
598 __be64 to_sink;
599 union fw_ri_cmpl {
600 struct fw_ri_immd_cmpl {
601 __u8 op;
602 __u8 r1[6];
603 __u8 immdlen;
604 __u8 data[16];
605 } immd_src;
606 struct fw_ri_isgl isgl_src;
607 } u_cmpl;
608 __be64 r3;
609 union fw_ri_write {
610 DECLARE_FLEX_ARRAY(struct fw_ri_immd, immd_src);
611 DECLARE_FLEX_ARRAY(struct fw_ri_isgl, isgl_src);
612 } u;
613};
614
615struct fw_ri_rdma_read_wr {
616 __u8 opcode;
617 __u8 flags;
618 __u16 wrid;
619 __u8 r1[3];
620 __u8 len16;
621 __be64 r2;
622 __be32 stag_sink;
623 __be32 to_sink_hi;
624 __be32 to_sink_lo;
625 __be32 plen;
626 __be32 stag_src;
627 __be32 to_src_hi;
628 __be32 to_src_lo;
629 __be32 r5;
630};
631
632struct fw_ri_recv_wr {
633 __u8 opcode;
634 __u8 r1;
635 __u16 wrid;
636 __u8 r2[3];
637 __u8 len16;
638 struct fw_ri_isgl isgl;
639};
640
641struct fw_ri_bind_mw_wr {
642 __u8 opcode;
643 __u8 flags;
644 __u16 wrid;
645 __u8 r1[3];
646 __u8 len16;
647 __u8 qpbinde_to_dcacpu;
648 __u8 pgsz_shift;
649 __u8 addr_type;
650 __u8 mem_perms;
651 __be32 stag_mr;
652 __be32 stag_mw;
653 __be32 r3;
654 __be64 len_mw;
655 __be64 va_fbo;
656 __be64 r4;
657};
658
659#define FW_RI_BIND_MW_WR_QPBINDE_S 6
660#define FW_RI_BIND_MW_WR_QPBINDE_M 0x1
661#define FW_RI_BIND_MW_WR_QPBINDE_V(x) ((x) << FW_RI_BIND_MW_WR_QPBINDE_S)
662#define FW_RI_BIND_MW_WR_QPBINDE_G(x) \
663 (((x) >> FW_RI_BIND_MW_WR_QPBINDE_S) & FW_RI_BIND_MW_WR_QPBINDE_M)
664#define FW_RI_BIND_MW_WR_QPBINDE_F FW_RI_BIND_MW_WR_QPBINDE_V(1U)
665
666#define FW_RI_BIND_MW_WR_NS_S 5
667#define FW_RI_BIND_MW_WR_NS_M 0x1
668#define FW_RI_BIND_MW_WR_NS_V(x) ((x) << FW_RI_BIND_MW_WR_NS_S)
669#define FW_RI_BIND_MW_WR_NS_G(x) \
670 (((x) >> FW_RI_BIND_MW_WR_NS_S) & FW_RI_BIND_MW_WR_NS_M)
671#define FW_RI_BIND_MW_WR_NS_F FW_RI_BIND_MW_WR_NS_V(1U)
672
673#define FW_RI_BIND_MW_WR_DCACPU_S 0
674#define FW_RI_BIND_MW_WR_DCACPU_M 0x1f
675#define FW_RI_BIND_MW_WR_DCACPU_V(x) ((x) << FW_RI_BIND_MW_WR_DCACPU_S)
676#define FW_RI_BIND_MW_WR_DCACPU_G(x) \
677 (((x) >> FW_RI_BIND_MW_WR_DCACPU_S) & FW_RI_BIND_MW_WR_DCACPU_M)
678
679struct fw_ri_fr_nsmr_wr {
680 __u8 opcode;
681 __u8 flags;
682 __u16 wrid;
683 __u8 r1[3];
684 __u8 len16;
685 __u8 qpbinde_to_dcacpu;
686 __u8 pgsz_shift;
687 __u8 addr_type;
688 __u8 mem_perms;
689 __be32 stag;
690 __be32 len_hi;
691 __be32 len_lo;
692 __be32 va_hi;
693 __be32 va_lo_fbo;
694};
695
696#define FW_RI_FR_NSMR_WR_QPBINDE_S 6
697#define FW_RI_FR_NSMR_WR_QPBINDE_M 0x1
698#define FW_RI_FR_NSMR_WR_QPBINDE_V(x) ((x) << FW_RI_FR_NSMR_WR_QPBINDE_S)
699#define FW_RI_FR_NSMR_WR_QPBINDE_G(x) \
700 (((x) >> FW_RI_FR_NSMR_WR_QPBINDE_S) & FW_RI_FR_NSMR_WR_QPBINDE_M)
701#define FW_RI_FR_NSMR_WR_QPBINDE_F FW_RI_FR_NSMR_WR_QPBINDE_V(1U)
702
703#define FW_RI_FR_NSMR_WR_NS_S 5
704#define FW_RI_FR_NSMR_WR_NS_M 0x1
705#define FW_RI_FR_NSMR_WR_NS_V(x) ((x) << FW_RI_FR_NSMR_WR_NS_S)
706#define FW_RI_FR_NSMR_WR_NS_G(x) \
707 (((x) >> FW_RI_FR_NSMR_WR_NS_S) & FW_RI_FR_NSMR_WR_NS_M)
708#define FW_RI_FR_NSMR_WR_NS_F FW_RI_FR_NSMR_WR_NS_V(1U)
709
710#define FW_RI_FR_NSMR_WR_DCACPU_S 0
711#define FW_RI_FR_NSMR_WR_DCACPU_M 0x1f
712#define FW_RI_FR_NSMR_WR_DCACPU_V(x) ((x) << FW_RI_FR_NSMR_WR_DCACPU_S)
713#define FW_RI_FR_NSMR_WR_DCACPU_G(x) \
714 (((x) >> FW_RI_FR_NSMR_WR_DCACPU_S) & FW_RI_FR_NSMR_WR_DCACPU_M)
715
716struct fw_ri_fr_nsmr_tpte_wr {
717 __u8 opcode;
718 __u8 flags;
719 __u16 wrid;
720 __u8 r1[3];
721 __u8 len16;
722 __be32 r2;
723 __be32 stag;
724 struct fw_ri_tpte tpte;
725 __u64 pbl[2];
726};
727
728struct fw_ri_inv_lstag_wr {
729 __u8 opcode;
730 __u8 flags;
731 __u16 wrid;
732 __u8 r1[3];
733 __u8 len16;
734 __be32 r2;
735 __be32 stag_inv;
736};
737
738enum fw_ri_type {
739 FW_RI_TYPE_INIT,
740 FW_RI_TYPE_FINI,
741 FW_RI_TYPE_TERMINATE
742};
743
744enum fw_ri_init_p2ptype {
745 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE,
746 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ,
747 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND,
748 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV,
749 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE,
750 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV,
751 FW_RI_INIT_P2PTYPE_DISABLED = 0xf,
752};
753
754enum fw_ri_init_rqeqid_srq {
755 FW_RI_INIT_RQEQID_SRQ = 1 << 31,
756};
757
758struct fw_ri_wr {
759 __be32 op_compl;
760 __be32 flowid_len16;
761 __u64 cookie;
762 union fw_ri {
763 struct fw_ri_init {
764 __u8 type;
765 __u8 mpareqbit_p2ptype;
766 __u8 r4[2];
767 __u8 mpa_attrs;
768 __u8 qp_caps;
769 __be16 nrqe;
770 __be32 pdid;
771 __be32 qpid;
772 __be32 sq_eqid;
773 __be32 rq_eqid;
774 __be32 scqid;
775 __be32 rcqid;
776 __be32 ord_max;
777 __be32 ird_max;
778 __be32 iss;
779 __be32 irs;
780 __be32 hwrqsize;
781 __be32 hwrqaddr;
782 __be64 r5;
783 union fw_ri_init_p2p {
784 struct fw_ri_rdma_write_wr write;
785 struct fw_ri_rdma_read_wr read;
786 struct fw_ri_send_wr send;
787 } u;
788 } init;
789 struct fw_ri_fini {
790 __u8 type;
791 __u8 r3[7];
792 __be64 r4;
793 } fini;
794 struct fw_ri_terminate {
795 __u8 type;
796 __u8 r3[3];
797 __be32 immdlen;
798 __u8 termmsg[40];
799 } terminate;
800 } u;
801};
802
803#define FW_RI_WR_MPAREQBIT_S 7
804#define FW_RI_WR_MPAREQBIT_M 0x1
805#define FW_RI_WR_MPAREQBIT_V(x) ((x) << FW_RI_WR_MPAREQBIT_S)
806#define FW_RI_WR_MPAREQBIT_G(x) \
807 (((x) >> FW_RI_WR_MPAREQBIT_S) & FW_RI_WR_MPAREQBIT_M)
808#define FW_RI_WR_MPAREQBIT_F FW_RI_WR_MPAREQBIT_V(1U)
809
810#define FW_RI_WR_P2PTYPE_S 0
811#define FW_RI_WR_P2PTYPE_M 0xf
812#define FW_RI_WR_P2PTYPE_V(x) ((x) << FW_RI_WR_P2PTYPE_S)
813#define FW_RI_WR_P2PTYPE_G(x) \
814 (((x) >> FW_RI_WR_P2PTYPE_S) & FW_RI_WR_P2PTYPE_M)
815
816#endif /* _T4FW_RI_API_H_ */
817

source code of linux/drivers/infiniband/hw/cxgb4/t4fw_ri_api.h